B4 Assignment 4

RS232 UART Group: B4 (GTU)

Assignment#4

Command Descriptions:

• IC Compiler Commands:

create_mw_lib

This command used for create milkyway library. For generate this library

file require minimum technology library (.tf) file.

import_designs

This command used to import our netlist file into IC compiler which is in

.ddc or verilog format.

initialize_floorplan

This command initializes the floorplan. This command has may option

which is describe below.

-core_utilization

These options define the core utilization inside the chip.

-core_aspect_ratio

These options define core aspect ratio of the chip.

-left_io2core

These options indicate space from I/O pins and core from left side.

-bottom_io2core

These options indicate space from I/O pins and core from bottom

side.

-right_io2core

These options indicate space from I/O pins and core from right

side.


-top_io2core

These options indicate space from I/O pins and core from top side.

derive_pg_connection

This command used to define power and ground net name manually.

create_rectangular_rings

This command used for creates rectangular power and ground ring

around the core area for applied VDD and VSS to the standard cells. It has

many options which are explain below.

-nets

These options define which net we want to draw ring for that.

-offset options

These options define offset from all the sides top, bottom, right and

left. According to this offset rectangular ring create around core

area.

-segment_layer

This option defines which type of metal used to define rings.

-segment_width

This option defines width of the rings.

create_power_straps

This command used for creates power straps in core.

preroute_standard_cells

This command used for preroute the standard cells and provide power

and ground rails to the standard cells. There are many options in this

command which is describe below:

-connect horizontal

Connects power and ground in the horizontal direction. This option is selected by default.


-fill_empty_rows

Fills rows without cells with power and ground rails.

set_tlu_plus_files

This command used for configure TLUplus file in IC compiler. There are

three files are defined which are TLU max, TLU min and Map or ITF files.

place_opt

This command does placement and optimization in current design. This

command performs simultaneous placement, routing, and optimization on the

current design. The output of this command is a legally placed netlist.

clock_opt

The clock_opt command performs clock tree synthesis, routing of clock

nets, extraction, optimization, and optionally hold-time violation fixing on the

current design. If clock tree synthesis fails, or the routing of clock nets fail, the

command returns with a value of 0.

route_opt

This command performs simultaneous routing and postroute

optimization on the current design. The output of this command is a postroute

optimized design.

save_mw_cel

This command used for save current cell in milkyway library.

report_congestion

This command used for generate congestion report.


Tetramax Commands:

read_netlist

This command does read the netlist files or read library.

run_build_model

This command builds the in-memory simulation model from the design

modules that have been read in. You can use the set_build command to control

the build process. After the build process is completed, TetraMAX performs a

learning process, which you can control with the set_learning command. If a

simulation model already exists, it is automatically deleted before the new

model is built.

run_drc

You use this command to perform design rule checking, which is

required to enter the TEST command mode, where test generation and fault

simulation may be performed.

add_faults

Use this command to create a list of faults for fault simulation or test

generation. Allowed fault sites include top-level ports and input and output

pins of cells, which have a netlist defined pin name. The nofault attribute can

be used to prevent selected faults from being placed in the fault list.

set_atpg

You use this command to generate ATPG patterns for current set of

faults using the pattern source set by the set_patterns command.

run_atpg

You use this command to generate ATPG patterns for current set of

faults using the pattern source set by the set_patterns command.

analyze_faults

This command helps determine why faults are not detected.


report_patterns

Use this command to report pattern data from the internal or external

pattern buffer.

write_patterns

Use this command to write ATPG patterns to a file in one of the

supported formats: FTDL, STIL, TDL91, TSTL2, WGL, WGL_FLAT, and the

ATPG tool's proprietary binary.

Scripts:

Create Library:

#Create Milkyway Library

create_mw_lib -technology ../ref/tech/saed90nm.tf -mw_reference_library

{../ref/saed90nm_fr} -bus_naming_style {[%d]} -open ./assign_f1

#Import Design

import_designs -format ddc -top cuart -cel cuart

{../source/scanstitched_uart.ddc}

# Set TLUPlus Files

set_tlu_plus_files -max_tluplus

../ref/tluplus/saed90nm_1p9m_1t_Cmax.tluplus -min_tluplus

../ref/tluplus/saed90nm_1p9m_1t_Cmin.tluplus -tech2itf_map

../ref/tluplus/saed90nm.map

Floorplanning:

#initialize Floorplan

initialize_floorplan -core_utilization 0.79 \

-core_aspect_ratio 0.89 \

-start_first_row \

-flip_first_row \

-left_io2core 10.0 -bottom_io2core 10.0

-right_io2core 10.0 -top_io2core 10.0


#Define PG Connection names by Manually

derive_pg_connection -power_net {VDD} \

-ground_net {VSS} \

-power_pin {VDD} \

-ground_pin {VSS}

#Create Power reactangular Ring for VDD

create_rectangular_rings -nets {VDD} \

-left_offset 0 \

-left_segment_layer M4 \

-left_segment_width 2 \

-right_offset 0 \

-right_segment_layer M4 \

-right_segment_width 2 \

-bottom_offset 0 \

-bottom_segment_layer M4 \

-bottom_segment_width 2 \

-top_offset 0 \

-top_segment_layer M4 \

-top_segment_width 2

#Create Power reactangular Ring for VSS

create_rectangular_rings -nets {VSS} \

-left_offset 3 \

-left_segment_layer M5 \

-left_segment_width 2 \

-right_offset 3 \

-right_segment_layer M5 \

-right_segment_width 2 \

-bottom_offset 3 \

-bottom_segment_layer M5 \

-bottom_segment_width 2 \

-top_offset 3 \

-top_segment_layer M5 \

-top_segment_width 2


#Create Power Straps

create_power_straps -direction vertical -start_at 53.309 -nets {VDD} -layer M4

-width 2

create_power_straps -direction vertical -start_at 50.375 -nets {VSS} -layer M5 -

width 2

report_congestion > congestion_f1.rpt

report_area > fp_area.rpt

report_qor > fp_qor.prt

report_timing > fp_timing.rpt

report_power > fp_power.rpt

#write FP netlist

write_verilog floorplan_netlist.v

Placement:

#Prerote Standard Cells

preroute_standard_cells -connect horizontal \

-remove_floating_pieces \

-fill_empty_rows \

-port_filter_mode off \

-cell_master_filter_mode off \

-cell_instance_filter_mode off \

-voltage_area_filter_mode off

#set tluplus file as Max TLUplus file

set_tlu_plus_files -max_tluplus

../ref/tluplus/saed90nm_1p9m_1t_Cmax.tluplus

#Placement

place_opt

# Generate Congestion Report & Power,Area,Timing,Qor

report_congestion > placed_congestion_f1.rpt

report_area > report_placed_area.rpt

report_qor > report_placed_qor.rpt

report_timing > report_placed_timing.rpt


report_power > report_placed_pwer.rpt

#write Placed netlist

write_verilog uart_placednetlist_f1.v

#CTS & Optimization

clock_opt

#write CTS netlist

write_verilog cts_netlist_f1.v


report_area > report_cts_area.rpt

report_qor > report_cts_qor.rpt

report_timing > report_cts_timing.rpt

report_power > report_cts_pwer.rpt

Routing:

route_opt

save_mw_cel -design "cuart.CEL;1"


report_area > report_routed_area.rpt

report_qor > report_routed_qor.rpt

report_timing > report_routed_timing.rpt

report_power > report_routed_pwer.rpt

# Write Verilog for routed

write_verilog routed_netlist_f1.v


Netlist Files:

Scan Stitched: module cuart ( sys_clk, sys_rst, csr_a, csr_we, csr_di, csr_do, rx_irq, tx_irq, uart_rx, uart_tx, Scan_Enable, Test_Mode ); input [13:0] csr_a; input [31:0] csr_di; output [31:0] csr_do; input sys_clk, sys_rst, csr_we, uart_rx, Scan_Enable, Test_Mode; output rx_irq, tx_irq, uart_tx; wire csr_a_1, csr_a_0, n460, uart_tx_transceiver, thru, N80, N81, N82, N83, N84, N85, N86, N87, N88, N89, N90, N91, N92, N93, N94, N95, \transceiver/N190 , \transceiver/tx_busy , \transceiver/tx_reg[7] , \transceiver/tx_reg[6] , \transceiver/tx_reg[5] , \transceiver/tx_reg[4] , \transceiver/tx_reg[3] , \transceiver/tx_reg[2] , \transceiver/tx_reg[1] , \transceiver/tx_reg[0] , \transceiver/tx_bitcount[0] , \transceiver/tx_bitcount[1] , \transceiver/tx_bitcount[2] , \transceiver/tx_count16[0] , \transceiver/tx_count16[2] , \transceiver/tx_count16[3] , \transceiver/N137 , \transceiver/rx_reg[0] , \transceiver/rx_reg[1] , \transceiver/rx_reg[2] , \transceiver/rx_reg[3] , \transceiver/rx_reg[4] , \transceiver/rx_reg[5] , \transceiver/rx_reg[6] , \transceiver/rx_reg[7] , \transceiver/rx_bitcount[1] , \transceiver/rx_bitcount[2] , \transceiver/rx_count16[0] , \transceiver/rx_count16[1] , \transceiver/rx_count16[2] , \transceiver/rx_count16[3] , \transceiver/rx_busy , \transceiver/uart_rx2 , \transceiver/N100 , \transceiver/N99 , \transceiver/N98 , \transceiver/N97 , \transceiver/N96 , \transceiver/N95 , \transceiver/N94 , \transceiver/N93 , \transceiver/N92 , \transceiver/N91 , \transceiver/N90 , \transceiver/N89 , \transceiver/N88 , \transceiver/N87 , \transceiver/N86 , \transceiver/enable16_counter[0] , \transceiver/enable16_counter[1] , \transceiver/enable16_counter[2] , \transceiver/enable16_counter[3] , \transceiver/enable16_counter[4] , \transceiver/enable16_counter[5] , \transceiver/enable16_counter[6] , \transceiver/enable16_counter[7] , \transceiver/enable16_counter[8] , \transceiver/enable16_counter[9] , \transceiver/enable16_counter[10] , \transceiver/enable16_counter[11] , \transceiver/enable16_counter[12] , \transceiver/enable16_counter[13] , \transceiver/enable16_counter[14] , \transceiver/enable16_counter[15] , n72, n109, n110, n114, n115, n193,


n194, n195, n196, n197, n198, n199, n200, n201, n202, n204, n205, n206, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n226, n227, n229, n230, n234, n235, n236, n238, n240, n242, n244, n246, n248, n250, n251, n252, n253, n254, n257, n259, n263, n265, n267, n269, n271, n273, n275, n277, n279, n281, n283, n285, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n462, n463, n464, n465, n466, n467, n468; wire [15:0] divisor; wire [7:0] rx_data; assign csr_a_1 = csr_a[1]; assign csr_a_0 = csr_a[0]; assign csr_do[16] = 1'b0; assign csr_do[17] = 1'b0; assign csr_do[18] = 1'b0; assign csr_do[19] = 1'b0; assign csr_do[20] = 1'b0; assign csr_do[21] = 1'b0; assign csr_do[22] = 1'b0; assign csr_do[23] = 1'b0; assign csr_do[24] = 1'b0; assign csr_do[25] = 1'b0; assign csr_do[26] = 1'b0; assign csr_do[27] = 1'b0; assign csr_do[28] = 1'b0; assign csr_do[29] = 1'b0; assign csr_do[30] = 1'b0; assign csr_do[31] = 1'b0; SDFFX1 thru_reg ( .D(n250), .SI(divisor[15]), .SE(Scan_Enable), .CLK(sys_clk), .Q(thru) );


SDFFX1 \divisor_reg[14] ( .D(n248), .SI(divisor[13]), .SE(Scan_Enable), .CLK(sys_clk), .Q(divisor[14]) ); SDFFX1 \divisor_reg[12] ( .D(n246), .SI(divisor[11]), .SE(Scan_Enable), .CLK(sys_clk), .Q(divisor[12]) ); SDFFX1 \divisor_reg[10] ( .D(n244), .SI(divisor[9]), .SE(Scan_Enable), .CLK(sys_clk), .Q(divisor[10]) ); SDFFX1 \divisor_reg[8] ( .D(n242), .SI(divisor[7]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[8]) ); SDFFX1 \divisor_reg[6] ( .D(n240), .SI(divisor[5]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[6]) ); SDFFX1 \divisor_reg[4] ( .D(n238), .SI(divisor[3]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[4]) ); SDFFX1 \divisor_reg[2] ( .D(n236), .SI(divisor[1]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[2]) ); SDFFX1 \divisor_reg[1] ( .D(n235), .SI(divisor[0]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[1]) ); SDFFX1 \divisor_reg[0] ( .D(n234), .SI(csr_do[15]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[0]) ); SDFFX1 \csr_do_reg[15] ( .D(N95), .SI(csr_do[14]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[15]) ); SDFFX1 \csr_do_reg[14] ( .D(N94), .SI(csr_do[13]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[14]) ); SDFFX1 \csr_do_reg[13] ( .D(N93), .SI(csr_do[12]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[13]) ); SDFFX1 \csr_do_reg[12] ( .D(N92), .SI(csr_do[11]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[12]) ); SDFFX1 \csr_do_reg[11] ( .D(N91), .SI(csr_do[10]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[11]) ); SDFFX1 \csr_do_reg[10] ( .D(N90), .SI(csr_do[9]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[10]) ); SDFFX1 \csr_do_reg[9] ( .D(N89), .SI(csr_do[8]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[9]) ); SDFFX1 \csr_do_reg[8] ( .D(N88), .SI(csr_do[7]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[8]) ); SDFFX1 \transceiver/enable16_counter_reg[15] ( .D(\transceiver/N100 ), .SI( \transceiver/enable16_counter[14] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[15] ) ); SDFFX1 \transceiver/rx_done_reg ( .D(\transceiver/N137 ), .SI(rx_data[7]), .SE(Scan_Enable), .CLK(sys_clk), .Q(rx_irq) ); SDFFX1 \transceiver/rx_bitcount_reg[1] ( .D(n230), .SI(n293), .SE( Scan_Enable), .CLK(sys_clk), .Q(\transceiver/rx_bitcount[1] ) ); SDFFX1 \transceiver/rx_bitcount_reg[2] ( .D(n229), .SI( \transceiver/rx_bitcount[1] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( \transceiver/rx_bitcount[2] ) ); SDFFX1 \csr_do_reg[0] ( .D(N80), .SI(\transceiver/tx_reg[0] ), .SE(


Scan_Enable), .CLK(sys_clk), .Q(csr_do[0]) ); SDFFX1 \transceiver/rx_count16_reg[1] ( .D(n227), .SI( \transceiver/rx_count16[0] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( \transceiver/rx_count16[1] ) ); SDFFX1 \transceiver/rx_count16_reg[2] ( .D(n226), .SI( \transceiver/rx_count16[1] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( \transceiver/rx_count16[2] ) ); SDFFX1 \transceiver/tx_count16_reg[0] ( .D(n208), .SI(\transceiver/tx_busy ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/tx_count16[0] ) ); SDFFX1 \transceiver/tx_count16_reg[3] ( .D(n206), .SI( \transceiver/tx_count16[2] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( \transceiver/tx_count16[3] ) ); SDFFX1 \transceiver/tx_bitcount_reg[0] ( .D(n205), .SI(rx_irq), .SE( Scan_Enable), .CLK(sys_clk), .Q(\transceiver/tx_bitcount[0] ) ); SDFFX1 \transceiver/tx_bitcount_reg[2] ( .D(n204), .SI(n464), .SE( Scan_Enable), .CLK(sys_clk), .Q(\transceiver/tx_bitcount[2] ) ); SDFFX1 \transceiver/tx_reg_reg[7] ( .D(n201), .SI(\transceiver/rx_reg[0] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/tx_reg[7] ) ); SDFFX1 \transceiver/tx_done_reg ( .D(\transceiver/N190 ), .SI( uart_tx_transceiver), .SE(Scan_Enable), .CLK(sys_clk), .Q(tx_irq) ); SDFFX1 \transceiver/tx_busy_reg ( .D(n202), .SI(n463), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/tx_busy ) ); SDFFX1 \transceiver/uart_tx_reg ( .D(n199), .SI(\transceiver/tx_count16[3] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(uart_tx_transceiver) ); SDFFX1 \transceiver/enable16_counter_reg[14] ( .D(\transceiver/N99 ), .SI( \transceiver/enable16_counter[13] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[14] ) ); SDFFX1 \transceiver/enable16_counter_reg[13] ( .D(\transceiver/N98 ), .SI( \transceiver/enable16_counter[12] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[13] ) ); SDFFX1 \transceiver/enable16_counter_reg[12] ( .D(\transceiver/N97 ), .SI( \transceiver/enable16_counter[11] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[12] ) ); SDFFX1 \transceiver/enable16_counter_reg[11] ( .D(\transceiver/N96 ), .SI( \transceiver/enable16_counter[10] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[11] ) ); SDFFX1 \transceiver/enable16_counter_reg[10] ( .D(\transceiver/N95 ), .SI( \transceiver/enable16_counter[9] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[10] ) ); SDFFX1 \transceiver/enable16_counter_reg[9] ( .D(\transceiver/N94 ), .SI( \transceiver/enable16_counter[8] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[9] ) ); SDFFX1 \transceiver/enable16_counter_reg[8] ( .D(\transceiver/N93 ), .SI( \transceiver/enable16_counter[7] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[8] ) );


SDFFX1 \transceiver/enable16_counter_reg[7] ( .D(\transceiver/N92 ), .SI( \transceiver/enable16_counter[6] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[7] ) ); SDFFX1 \transceiver/enable16_counter_reg[6] ( .D(\transceiver/N91 ), .SI( \transceiver/enable16_counter[5] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[6] ) ); SDFFX1 \transceiver/enable16_counter_reg[5] ( .D(\transceiver/N90 ), .SI( \transceiver/enable16_counter[4] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[5] ) ); SDFFX1 \transceiver/enable16_counter_reg[4] ( .D(\transceiver/N89 ), .SI( \transceiver/enable16_counter[3] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[4] ) ); SDFFX1 \transceiver/enable16_counter_reg[2] ( .D(\transceiver/N87 ), .SI( \transceiver/enable16_counter[1] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[2] ) ); SDFFX1 \transceiver/enable16_counter_reg[1] ( .D(\transceiver/N86 ), .SI( n306), .SE(Scan_Enable), .CLK(sys_clk), .Q( \transceiver/enable16_counter[1] ) ); DFFX1 \transceiver/tx_reg_reg[6] ( .D(n193), .CLK(sys_clk), .Q( \transceiver/tx_reg[6] ) ); DFFX1 \transceiver/tx_reg_reg[5] ( .D(n194), .CLK(sys_clk), .Q( \transceiver/tx_reg[5] ) ); DFFX1 \transceiver/tx_reg_reg[4] ( .D(n195), .CLK(sys_clk), .Q( \transceiver/tx_reg[4] ) ); DFFX1 \transceiver/tx_reg_reg[3] ( .D(n196), .CLK(sys_clk), .Q( \transceiver/tx_reg[3] ) ); DFFX1 \transceiver/tx_reg_reg[2] ( .D(n197), .CLK(sys_clk), .Q( \transceiver/tx_reg[2] ) ); DFFX1 \transceiver/tx_reg_reg[1] ( .D(n198), .CLK(sys_clk), .Q( \transceiver/tx_reg[1] ) ); DFFX1 \transceiver/tx_reg_reg[0] ( .D(n200), .CLK(sys_clk), .Q( \transceiver/tx_reg[0] ) ); DFFX1 \transceiver/uart_rx2_reg ( .D(n72), .CLK(sys_clk), .Q(n303), .QN( \transceiver/uart_rx2 ) ); SDFFX1 \transceiver/rx_busy_reg ( .D(n289), .SI(n304), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/rx_busy ), .QN(n292) ); SDFFX1 \transceiver/enable16_counter_reg[0] ( .D(n387), .SI(thru), .SE( Scan_Enable), .CLK(sys_clk), .Q(n306), .QN( \transceiver/enable16_counter[0] ) ); SDFFX1 \transceiver/enable16_counter_reg[3] ( .D(\transceiver/N88 ), .SI( \transceiver/enable16_counter[2] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/enable16_counter[3] ), .QN(n305) ); SDFFX1 \transceiver/rx_bitcount_reg[0] ( .D(n285), .SI( \transceiver/enable16_counter[15] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(n293), .QN(n114) );


SDFFX1 \transceiver/rx_count16_reg[3] ( .D(n283), .SI( \transceiver/rx_count16[2] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( \transceiver/rx_count16[3] ), .QN(n307) ); SDFFX1 \transceiver/rx_bitcount_reg[3] ( .D(n281), .SI( \transceiver/rx_bitcount[2] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( n304), .QN(n115) ); SDFFX1 \divisor_reg[15] ( .D(n279), .SI(divisor[14]), .SE(Scan_Enable), .CLK(sys_clk), .Q(divisor[15]), .QN(n301) ); SDFFX1 \divisor_reg[13] ( .D(n277), .SI(divisor[12]), .SE(Scan_Enable), .CLK(sys_clk), .Q(divisor[13]), .QN(n300) ); SDFFX1 \divisor_reg[11] ( .D(n275), .SI(divisor[10]), .SE(Scan_Enable), .CLK(sys_clk), .Q(divisor[11]), .QN(n299) ); SDFFX1 \divisor_reg[9] ( .D(n273), .SI(divisor[8]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[9]), .QN(n298) ); SDFFX1 \transceiver/rx_count16_reg[0] ( .D(n271), .SI(\transceiver/rx_busy ), .SE(Scan_Enable), .CLK(sys_clk), .Q(\transceiver/rx_count16[0] ), .QN(n296) ); SDFFX1 \divisor_reg[5] ( .D(n269), .SI(divisor[4]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[5]), .QN(n295) ); SDFFX1 \divisor_reg[7] ( .D(n267), .SI(divisor[6]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[7]), .QN(n302) ); SDFFX1 \divisor_reg[3] ( .D(n265), .SI(divisor[2]), .SE(Scan_Enable), .CLK( sys_clk), .Q(divisor[3]), .QN(n294) ); SDFFX1 \transceiver/tx_count16_reg[2] ( .D(n263), .SI(n109), .SE( Scan_Enable), .CLK(sys_clk), .Q(\transceiver/tx_count16[2] ), .QN(n297) ); SDFFX1 \transceiver/uart_rx1_reg ( .D(uart_rx), .SI(uart_rx), .SE( Scan_Enable), .CLK(sys_clk), .QN(n72) ); SDFFX1 \transceiver/tx_count16_reg[1] ( .D(n459), .SI( \transceiver/tx_count16[0] ), .SE(Scan_Enable), .CLK(sys_clk), .Q(n109) ); SDFFX1 \transceiver/tx_bitcount_reg[3] ( .D(n259), .SI( \transceiver/tx_bitcount[2] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( n463), .QN(n110) ); SDFFX1 \transceiver/tx_bitcount_reg[1] ( .D(n257), .SI( \transceiver/tx_bitcount[0] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( n464), .QN(\transceiver/tx_bitcount[1] ) ); NAND2X0 U296 ( .IN1(n377), .IN2(n109), .QN(n360) ); NAND2X0 U297 ( .IN1(\transceiver/rx_busy ), .IN2(n371), .QN(n344) ); NAND2X0 U298 ( .IN1(n378), .IN2(n374), .QN(n251) ); NAND2X0 U299 ( .IN1(n375), .IN2(n251), .QN(n384) ); NOR2X0 U300 ( .IN1(n293), .IN2(n325), .QN(n252) ); NOR2X0 U301 ( .IN1(n252), .IN2(n326), .QN(n285) ); MUX21X1 U302 ( .IN1(rx_data[0]), .IN2(thru), .S(csr_a_1), .Q(n253) ); AO22X1 U303 ( .IN1(n309), .IN2(divisor[0]), .IN3(n312), .IN4(n253), .Q(N80) ); INVX0 U304 ( .IN(n462), .QN(n254) );


INVX8 U305 ( .IN(n254), .QN(uart_tx) ); NAND2X0 U325 ( .IN1(n369), .IN2(n368), .QN(n259) ); NAND2X0 U326 ( .IN1(n322), .IN2(n321), .QN(n281) ); NAND2X0 U327 ( .IN1(n373), .IN2(n372), .QN(n202) ); NAND2X0 U328 ( .IN1(n377), .IN2(n375), .QN(n363) ); NAND2X0 U329 ( .IN1(n458), .IN2(n360), .QN(n358) ); NAND2X0 U330 ( .IN1(n399), .IN2(n398), .QN(\transceiver/N88 ) ); NAND2X0 U331 ( .IN1(n373), .IN2(n353), .QN(n355) ); NOR4X1 U332 ( .IN1(n348), .IN2(n346), .IN3(n345), .IN4(n344), .QN(n347) ); NAND2X0 U333 ( .IN1(n377), .IN2(n371), .QN(n353) ); NAND2X0 U334 ( .IN1(n352), .IN2(n296), .QN(n319) ); NAND2X0 U335 ( .IN1(n452), .IN2(n451), .QN(n456) ); NAND2X0 U336 ( .IN1(n447), .IN2(n300), .QN(n454) ); NAND2X0 U337 ( .IN1(n450), .IN2(n446), .QN(n449) ); NAND2X0 U338 ( .IN1(\transceiver/enable16_counter[14] ), .IN2(n450), .QN( n451) ); NAND2X0 U339 ( .IN1(n445), .IN2(n441), .QN(n444) ); NAND2X0 U340 ( .IN1(n437), .IN2(n299), .QN(n442) ); NAND2X0 U341 ( .IN1(\transceiver/enable16_counter[13] ), .IN2(n445), .QN( n446) ); NAND2X0 U342 ( .IN1(\transceiver/enable16_counter[12] ), .IN2(n440), .QN( n441) ); NAND2X0 U343 ( .IN1(n440), .IN2(n436), .QN(n439) ); NAND2X0 U344 ( .IN1(\transceiver/enable16_counter[11] ), .IN2(n435), .QN( n436) ); NAND2X0 U345 ( .IN1(n435), .IN2(n431), .QN(n434) ); NAND2X0 U346 ( .IN1(n427), .IN2(n298), .QN(n432) ); NAND2X0 U347 ( .IN1(n430), .IN2(n426), .QN(n429) ); NAND2X0 U348 ( .IN1(\transceiver/enable16_counter[10] ), .IN2(n430), .QN( n431) ); NAND2X0 U349 ( .IN1(\transceiver/enable16_counter[9] ), .IN2(n425), .QN(n426) ); NAND2X0 U350 ( .IN1(n425), .IN2(n421), .QN(n424) ); NAND2X0 U351 ( .IN1(n417), .IN2(n302), .QN(n422) ); NAND2X0 U352 ( .IN1(\transceiver/enable16_counter[8] ), .IN2(n420), .QN(n421) ); NAND2X0 U353 ( .IN1(n420), .IN2(n416), .QN(n419) ); NAND2X0 U354 ( .IN1(n407), .IN2(n295), .QN(n412) ); NAND2X0 U355 ( .IN1(\transceiver/enable16_counter[7] ), .IN2(n415), .QN(n416) ); NAND2X0 U356 ( .IN1(n415), .IN2(n411), .QN(n414) ); NAND2X0 U357 ( .IN1(n410), .IN2(n406), .QN(n409) ); NAND2X0 U358 ( .IN1(\transceiver/enable16_counter[6] ), .IN2(n410), .QN(n411) ); NAND2X0 U359 ( .IN1(n371), .IN2(n361), .QN(n373) );


NAND2X0 U360 ( .IN1(\transceiver/rx_count16[2] ), .IN2(n339), .QN(n340) ); NAND2X0 U361 ( .IN1(n396), .IN2(n294), .QN(n402) ); NAND2X0 U362 ( .IN1(n405), .IN2(n401), .QN(n404) ); NAND2X0 U363 ( .IN1(\transceiver/enable16_counter[5] ), .IN2(n405), .QN(n406) ); NAND2X0 U364 ( .IN1(\transceiver/enable16_counter[4] ), .IN2(n400), .QN(n401) ); NAND2X0 U365 ( .IN1(n392), .IN2(n388), .QN(n389) ); NAND2X0 U366 ( .IN1(\transceiver/rx_count16[0] ), .IN2( \transceiver/rx_count16[1] ), .QN(n338) ); INVX0 U367 ( .IN(n395), .QN(n290) ); INVX0 U368 ( .IN(n395), .QN(n291) ); NAND2X0 U369 ( .IN1(n332), .IN2(n290), .QN(n343) ); NAND2X0 U370 ( .IN1(n374), .IN2(\transceiver/tx_count16[0] ), .QN(n354) ); NOR2X0 U371 ( .IN1(csr_a_0), .IN2(n351), .QN(n361) ); NOR2X0 U372 ( .IN1(sys_rst), .IN2(n317), .QN(n318) ); NOR2X0 U373 ( .IN1(n352), .IN2(sys_rst), .QN(n395) ); INVX0 U374 ( .IN(sys_rst), .QN(n371) ); OA21X1 U375 ( .IN1(n315), .IN2(n351), .IN3(n371), .Q(n317) ); NOR2X0 U376 ( .IN1(sys_rst), .IN2(n381), .QN(n375) ); NOR2X0 U377 ( .IN1(\transceiver/enable16_counter[15] ), .IN2(n452), .QN(n352) ); NOR2X0 U378 ( .IN1(csr_a_1), .IN2(n308), .QN(n314) ); NOR2X0 U379 ( .IN1(sys_rst), .IN2(n343), .QN(n337) ); NAND2X0 U380 ( .IN1(\transceiver/tx_bitcount[1] ), .IN2( \transceiver/tx_bitcount[0] ), .QN(n364) ); AND4X1 U381 ( .IN1(n350), .IN2(n349), .IN3(\transceiver/uart_rx2 ), .IN4( n348), .Q(\transceiver/N137 ) ); NOR2X0 U382 ( .IN1(n376), .IN2(n384), .QN(n382) ); NAND2X0 U383 ( .IN1(divisor[0]), .IN2(divisor[1]), .QN(n388) ); ISOLANDX1 U384 ( .D(n312), .ISO(csr_a_1), .Q(n310) ); INVX0 U385 ( .IN(n344), .QN(n350) ); AO22X1 U386 ( .IN1(csr_di[6]), .IN2(n318), .IN3(divisor[6]), .IN4(n317), .Q( n240) ); AO22X1 U387 ( .IN1(csr_di[0]), .IN2(n318), .IN3(divisor[0]), .IN4(n317), .Q( n234) ); AO22X1 U388 ( .IN1(csr_di[7]), .IN2(n318), .IN3(divisor[7]), .IN4(n317), .Q( n267) ); AO22X1 U389 ( .IN1(csr_di[3]), .IN2(n318), .IN3(divisor[3]), .IN4(n317), .Q( n265) ); INVX0 U390 ( .IN(n373), .QN(n383) ); INVX0 U391 ( .IN(n361), .QN(n374) ); NAND2X1 U392 ( .IN1(csr_we), .IN2(n314), .QN(n351) ); MUX21X1 U393 ( .IN1(uart_tx_transceiver), .IN2(uart_rx), .S(thru), .Q(n460) );


OR4X1 U395 ( .IN1(csr_a[10]), .IN2(csr_a[11]), .IN3(csr_a[12]), .IN4( csr_a[13]), .Q(n308) ); NAND3X0 U396 ( .IN1(n314), .IN2(csr_a_0), .IN3(n371), .QN(n311) ); INVX0 U397 ( .IN(n311), .QN(n309) ); NOR3X0 U398 ( .IN1(csr_a_0), .IN2(sys_rst), .IN3(n308), .QN(n312) ); AO22X1 U399 ( .IN1(rx_data[1]), .IN2(n310), .IN3(divisor[1]), .IN4(n309), .Q(N81) ); AO22X1 U400 ( .IN1(rx_data[2]), .IN2(n310), .IN3(divisor[2]), .IN4(n309), .Q(N82) ); AO22X1 U401 ( .IN1(rx_data[3]), .IN2(n310), .IN3(divisor[3]), .IN4(n309), .Q(N83) ); AO22X1 U402 ( .IN1(rx_data[4]), .IN2(n310), .IN3(divisor[4]), .IN4(n309), .Q(N84) ); AO22X1 U403 ( .IN1(rx_data[5]), .IN2(n310), .IN3(divisor[5]), .IN4(n309), .Q(N85) ); AO22X1 U404 ( .IN1(rx_data[6]), .IN2(n310), .IN3(divisor[6]), .IN4(n309), .Q(N86) ); AO22X1 U405 ( .IN1(rx_data[7]), .IN2(n310), .IN3(divisor[7]), .IN4(n309), .Q(N87) ); ISOLANDX1 U406 ( .D(divisor[8]), .ISO(n311), .Q(N88) ); NOR2X0 U407 ( .IN1(n298), .IN2(n311), .QN(N89) ); ISOLANDX1 U408 ( .D(divisor[10]), .ISO(n311), .Q(N90) ); NOR2X0 U409 ( .IN1(n299), .IN2(n311), .QN(N91) ); ISOLANDX1 U410 ( .D(divisor[12]), .ISO(n311), .Q(N92) ); NOR2X0 U411 ( .IN1(n300), .IN2(n311), .QN(N93) ); ISOLANDX1 U412 ( .D(divisor[14]), .ISO(n311), .Q(N94) ); NOR2X0 U413 ( .IN1(n301), .IN2(n311), .QN(N95) ); NAND3X0 U414 ( .IN1(csr_a_1), .IN2(csr_we), .IN3(n312), .QN(n313) ); MUX21X1 U415 ( .IN1(csr_di[0]), .IN2(thru), .S(n313), .Q(n250) ); INVX0 U416 ( .IN(csr_a_0), .QN(n315) ); AO22X1 U417 ( .IN1(divisor[15]), .IN2(n317), .IN3(n318), .IN4(csr_di[15]), .Q(n279) ); AO22X1 U418 ( .IN1(divisor[14]), .IN2(n317), .IN3(n318), .IN4(csr_di[14]), .Q(n248) ); AO22X1 U419 ( .IN1(divisor[13]), .IN2(n317), .IN3(n318), .IN4(csr_di[13]), .Q(n277) ); AO22X1 U420 ( .IN1(divisor[12]), .IN2(n317), .IN3(n318), .IN4(csr_di[12]), .Q(n246) ); AO22X1 U421 ( .IN1(divisor[11]), .IN2(n317), .IN3(n318), .IN4(csr_di[11]), .Q(n275) ); AO22X1 U422 ( .IN1(divisor[10]), .IN2(n317), .IN3(n318), .IN4(csr_di[10]), .Q(n244) ); AO22X1 U423 ( .IN1(divisor[9]), .IN2(n317), .IN3(n318), .IN4(csr_di[9]), .Q( n273) ); AO22X1 U424 ( .IN1(divisor[8]), .IN2(n317), .IN3(n318), .IN4(csr_di[8]), .Q(


n242) ); INVX0 U425 ( .IN(n317), .QN(n316) ); AO221X1 U426 ( .IN1(n316), .IN2(csr_di[5]), .IN3(n317), .IN4(divisor[5]), .IN5(sys_rst), .Q(n269) ); AO221X1 U427 ( .IN1(n316), .IN2(csr_di[4]), .IN3(n317), .IN4(divisor[4]), .IN5(sys_rst), .Q(n238) ); AO221X1 U428 ( .IN1(n316), .IN2(csr_di[2]), .IN3(n317), .IN4(divisor[2]), .IN5(sys_rst), .Q(n236) ); AO221X1 U429 ( .IN1(n316), .IN2(csr_di[1]), .IN3(n317), .IN4(divisor[1]), .IN5(sys_rst), .Q(n235) ); OR4X1 U430 ( .IN1(\transceiver/enable16_counter[3] ), .IN2( \transceiver/enable16_counter[2] ), .IN3( \transceiver/enable16_counter[0] ), .IN4( \transceiver/enable16_counter[1] ), .Q(n400) ); OR2X1 U431 ( .IN1(\transceiver/enable16_counter[4] ), .IN2(n400), .Q(n405) ); OR2X1 U432 ( .IN1(\transceiver/enable16_counter[5] ), .IN2(n405), .Q(n410) ); OR2X1 U433 ( .IN1(\transceiver/enable16_counter[6] ), .IN2(n410), .Q(n415) ); OR2X1 U434 ( .IN1(\transceiver/enable16_counter[7] ), .IN2(n415), .Q(n420) ); OR2X1 U435 ( .IN1(\transceiver/enable16_counter[8] ), .IN2(n420), .Q(n425) ); OR2X1 U436 ( .IN1(\transceiver/enable16_counter[9] ), .IN2(n425), .Q(n430) ); OR2X1 U437 ( .IN1(\transceiver/enable16_counter[10] ), .IN2(n430), .Q(n435) ); OR2X1 U438 ( .IN1(\transceiver/enable16_counter[11] ), .IN2(n435), .Q(n440) ); OR2X1 U439 ( .IN1(\transceiver/enable16_counter[12] ), .IN2(n440), .Q(n445) ); OR2X1 U440 ( .IN1(\transceiver/enable16_counter[13] ), .IN2(n445), .Q(n450) ); OR2X1 U441 ( .IN1(\transceiver/enable16_counter[14] ), .IN2(n450), .Q(n452) ); NOR4X0 U442 ( .IN1(\transceiver/rx_count16[2] ), .IN2( \transceiver/rx_count16[1] ), .IN3(\transceiver/rx_count16[3] ), .IN4( n319), .QN(n349) ); NAND4X0 U443 ( .IN1(\transceiver/rx_busy ), .IN2(n349), .IN3(n371), .IN4( n293), .QN(n327) ); ISOLANDX1 U444 ( .D(\transceiver/rx_bitcount[1] ), .ISO(n327), .Q(n331) ); NAND3X0 U445 ( .IN1(n331), .IN2(\transceiver/rx_bitcount[2] ), .IN3(n115), .QN(n322) ); NAND3X0 U446 ( .IN1(n352), .IN2(n292), .IN3(n303), .QN(n324) );


NAND2X0 U447 ( .IN1(n349), .IN2(\transceiver/rx_busy ), .QN(n320) ); NAND3X0 U448 ( .IN1(n371), .IN2(n324), .IN3(n320), .QN(n325) ); OA21X1 U449 ( .IN1(n293), .IN2(n344), .IN3(n325), .Q(n326) ); OA21X1 U450 ( .IN1(\transceiver/rx_bitcount[1] ), .IN2(n344), .IN3(n326), .Q(n329) ); AO221X1 U451 ( .IN1(n329), .IN2(\transceiver/rx_bitcount[2] ), .IN3(n329), .IN4(n344), .IN5(n115), .Q(n321) ); NOR4X0 U452 ( .IN1(n115), .IN2(\transceiver/rx_bitcount[2] ), .IN3( \transceiver/rx_bitcount[1] ), .IN4(n114), .QN(n348) ); NOR4X0 U453 ( .IN1(\transceiver/rx_bitcount[1] ), .IN2( \transceiver/rx_bitcount[2] ), .IN3(n304), .IN4(n293), .QN(n346) ); OA221X1 U454 ( .IN1(n348), .IN2(n346), .IN3(n348), .IN4( \transceiver/uart_rx2 ), .IN5(n349), .Q(n323) ); OAI22X1 U455 ( .IN1(sys_rst), .IN2(n324), .IN3(n323), .IN4(n344), .QN(n289) ); MUX21X1 U456 ( .IN1(n327), .IN2(n326), .S(\transceiver/rx_bitcount[1] ), .Q( n328) ); INVX0 U457 ( .IN(n328), .QN(n230) ); INVX0 U458 ( .IN(n329), .QN(n330) ); MUX21X1 U459 ( .IN1(n331), .IN2(n330), .S(\transceiver/rx_bitcount[2] ), .Q( n229) ); NAND3X0 U460 ( .IN1(\transceiver/uart_rx2 ), .IN2(n292), .IN3(n371), .QN( n332) ); AO222X1 U461 ( .IN1(n337), .IN2(n296), .IN3(n337), .IN4(n292), .IN5( \transceiver/rx_count16[0] ), .IN6(n343), .Q(n271) ); NOR2X0 U462 ( .IN1(\transceiver/rx_count16[1] ), .IN2(n296), .QN(n334) ); OA221X1 U463 ( .IN1(n343), .IN2(n371), .IN3(n343), .IN4(n296), .IN5( \transceiver/rx_count16[1] ), .Q(n333) ); AO221X1 U464 ( .IN1(n337), .IN2(n334), .IN3(n337), .IN4(n292), .IN5(n333), .Q(n227) ); NOR2X0 U465 ( .IN1(\transceiver/rx_count16[2] ), .IN2(n338), .QN(n336) ); OA221X1 U466 ( .IN1(n343), .IN2(n371), .IN3(n343), .IN4(n338), .IN5( \transceiver/rx_count16[2] ), .Q(n335) ); AO221X1 U467 ( .IN1(n337), .IN2(n336), .IN3(n337), .IN4(n292), .IN5(n335), .Q(n226) ); INVX0 U468 ( .IN(n338), .QN(n339) ); OA21X1 U469 ( .IN1(n340), .IN2(n307), .IN3(n350), .Q(n342) ); NOR2X0 U470 ( .IN1(n343), .IN2(n340), .QN(n341) ); OA22X1 U471 ( .IN1(n343), .IN2(n342), .IN3(\transceiver/rx_count16[3] ), .IN4(n341), .Q(n283) ); INVX0 U472 ( .IN(n349), .QN(n345) ); MUX21X1 U473 ( .IN1(\transceiver/rx_reg[7] ), .IN2(\transceiver/uart_rx2 ), .S(n468), .Q(n224) ); MUX21X1 U474 ( .IN1(\transceiver/rx_reg[6] ), .IN2(\transceiver/rx_reg[7] ), .S(n468), .Q(n223) );


MUX21X1 U475 ( .IN1(\transceiver/rx_reg[5] ), .IN2(\transceiver/rx_reg[6] ), .S(n468), .Q(n222) ); MUX21X1 U476 ( .IN1(\transceiver/rx_reg[4] ), .IN2(\transceiver/rx_reg[5] ), .S(n468), .Q(n221) ); MUX21X1 U477 ( .IN1(\transceiver/rx_reg[3] ), .IN2(\transceiver/rx_reg[4] ), .S(n468), .Q(n220) ); MUX21X1 U478 ( .IN1(\transceiver/rx_reg[2] ), .IN2(\transceiver/rx_reg[3] ), .S(n468), .Q(n219) ); MUX21X1 U479 ( .IN1(\transceiver/rx_reg[1] ), .IN2(\transceiver/rx_reg[2] ), .S(n468), .Q(n218) ); MUX21X1 U480 ( .IN1(\transceiver/rx_reg[0] ), .IN2(\transceiver/rx_reg[1] ), .S(n468), .Q(n217) ); MUX21X1 U481 ( .IN1(rx_data[0]), .IN2(\transceiver/rx_reg[0] ), .S( \transceiver/N137 ), .Q(n216) ); MUX21X1 U482 ( .IN1(rx_data[1]), .IN2(\transceiver/rx_reg[1] ), .S( \transceiver/N137 ), .Q(n215) ); MUX21X1 U483 ( .IN1(rx_data[2]), .IN2(\transceiver/rx_reg[2] ), .S( \transceiver/N137 ), .Q(n214) ); MUX21X1 U484 ( .IN1(rx_data[3]), .IN2(\transceiver/rx_reg[3] ), .S( \transceiver/N137 ), .Q(n213) ); MUX21X1 U485 ( .IN1(rx_data[4]), .IN2(\transceiver/rx_reg[4] ), .S( \transceiver/N137 ), .Q(n212) ); MUX21X1 U486 ( .IN1(rx_data[5]), .IN2(\transceiver/rx_reg[5] ), .S( \transceiver/N137 ), .Q(n211) ); MUX21X1 U487 ( .IN1(rx_data[6]), .IN2(\transceiver/rx_reg[6] ), .S( \transceiver/N137 ), .Q(n210) ); MUX21X1 U488 ( .IN1(rx_data[7]), .IN2(\transceiver/rx_reg[7] ), .S( \transceiver/N137 ), .Q(n209) ); NAND3X0 U489 ( .IN1(n352), .IN2(\transceiver/tx_busy ), .IN3(n374), .QN(n376) ); INVX0 U490 ( .IN(n376), .QN(n377) ); MUX21X1 U491 ( .IN1(\transceiver/tx_count16[0] ), .IN2(n354), .S(n355), .Q( n208) ); OA21X1 U492 ( .IN1(\transceiver/tx_count16[0] ), .IN2(n376), .IN3(n355), .Q( n458) ); NAND3X0 U493 ( .IN1(n377), .IN2(\transceiver/tx_count16[0] ), .IN3(n371), .QN(n457) ); NOR2X0 U494 ( .IN1(n109), .IN2(n457), .QN(n356) ); MUX21X1 U495 ( .IN1(n358), .IN2(n356), .S(n297), .Q(n263) ); NOR2X0 U496 ( .IN1(\transceiver/tx_count16[2] ), .IN2(n376), .QN(n359) ); NOR4X0 U497 ( .IN1(n109), .IN2(\transceiver/tx_count16[3] ), .IN3(n297), .IN4(n457), .QN(n357) ); AO221X1 U498 ( .IN1(\transceiver/tx_count16[3] ), .IN2(n359), .IN3( \transceiver/tx_count16[3] ), .IN4(n358), .IN5(n357), .Q(n206) ); NOR4X0 U499 ( .IN1(\transceiver/tx_count16[0] ), .IN2(


\transceiver/tx_count16[3] ), .IN3(\transceiver/tx_count16[2] ), .IN4( n360), .QN(n370) ); NOR2X0 U500 ( .IN1(n361), .IN2(n370), .QN(n381) ); MUX21X1 U501 ( .IN1(n363), .IN2(n375), .S(\transceiver/tx_bitcount[0] ), .Q( n362) ); INVX0 U502 ( .IN(n362), .QN(n205) ); OA221X1 U503 ( .IN1(n376), .IN2(\transceiver/tx_bitcount[1] ), .IN3(n376), .IN4(\transceiver/tx_bitcount[0] ), .IN5(n375), .Q(n367) ); INVX0 U504 ( .IN(n367), .QN(n365) ); OAI221X1 U505 ( .IN1(\transceiver/tx_bitcount[1] ), .IN2(n375), .IN3( \transceiver/tx_bitcount[1] ), .IN4(\transceiver/tx_bitcount[0] ), .IN5(n365), .QN(n257) ); NOR2X0 U506 ( .IN1(n364), .IN2(n363), .QN(n366) ); MUX21X1 U507 ( .IN1(n366), .IN2(n365), .S(\transceiver/tx_bitcount[2] ), .Q( n204) ); NAND3X0 U508 ( .IN1(n366), .IN2(n110), .IN3(\transceiver/tx_bitcount[2] ), .QN(n369) ); AO221X1 U509 ( .IN1(n367), .IN2(\transceiver/tx_bitcount[2] ), .IN3(n367), .IN4(n376), .IN5(n110), .Q(n368) ); NOR3X0 U510 ( .IN1(\transceiver/tx_bitcount[2] ), .IN2(n110), .IN3( \transceiver/tx_bitcount[1] ), .QN(n378) ); NAND3X0 U511 ( .IN1(n370), .IN2(\transceiver/tx_bitcount[0] ), .IN3(n378), .QN(n386) ); NAND3X0 U512 ( .IN1(\transceiver/tx_busy ), .IN2(n371), .IN3(n386), .QN(n372) ); AO22X1 U513 ( .IN1(csr_di[7]), .IN2(n383), .IN3(\transceiver/tx_reg[7] ), .IN4(n384), .Q(n201) ); AO222X1 U514 ( .IN1(n467), .IN2(\transceiver/tx_reg[0] ), .IN3(n465), .IN4( \transceiver/tx_reg[1] ), .IN5(n466), .IN6(csr_di[0]), .Q(n200) ); INVX0 U515 ( .IN(n381), .QN(n380) ); OA21X1 U516 ( .IN1(n378), .IN2(\transceiver/tx_reg[0] ), .IN3(n377), .Q(n379) ); AO221X1 U517 ( .IN1(n381), .IN2(uart_tx_transceiver), .IN3(n380), .IN4(n379), .IN5(sys_rst), .Q(n199) ); AO222X1 U518 ( .IN1(n467), .IN2(\transceiver/tx_reg[1] ), .IN3(n466), .IN4( csr_di[1]), .IN5(\transceiver/tx_reg[2] ), .IN6(n465), .Q(n198) ); AO222X1 U519 ( .IN1(n467), .IN2(\transceiver/tx_reg[2] ), .IN3(n466), .IN4( csr_di[2]), .IN5(\transceiver/tx_reg[3] ), .IN6(n465), .Q(n197) ); AO222X1 U520 ( .IN1(n467), .IN2(\transceiver/tx_reg[3] ), .IN3(n466), .IN4( csr_di[3]), .IN5(\transceiver/tx_reg[4] ), .IN6(n465), .Q(n196) ); AO222X1 U521 ( .IN1(n467), .IN2(\transceiver/tx_reg[4] ), .IN3(n466), .IN4( csr_di[4]), .IN5(\transceiver/tx_reg[5] ), .IN6(n465), .Q(n195) ); AO222X1 U522 ( .IN1(n467), .IN2(\transceiver/tx_reg[5] ), .IN3(n466), .IN4( csr_di[5]), .IN5(\transceiver/tx_reg[6] ), .IN6(n465), .Q(n194) ); AO222X1 U523 ( .IN1(n467), .IN2(\transceiver/tx_reg[6] ), .IN3(n466), .IN4(


csr_di[6]), .IN5(\transceiver/tx_reg[7] ), .IN6(n465), .Q(n193) ); OR2X1 U524 ( .IN1(divisor[0]), .IN2(divisor[1]), .Q(n392) ); NOR2X0 U525 ( .IN1(divisor[2]), .IN2(n392), .QN(n396) ); NOR2X0 U526 ( .IN1(divisor[4]), .IN2(n402), .QN(n407) ); NOR2X0 U527 ( .IN1(divisor[6]), .IN2(n412), .QN(n417) ); NOR2X0 U528 ( .IN1(divisor[8]), .IN2(n422), .QN(n427) ); NOR2X0 U529 ( .IN1(divisor[10]), .IN2(n432), .QN(n437) ); NOR2X0 U530 ( .IN1(divisor[12]), .IN2(n442), .QN(n447) ); NOR2X0 U531 ( .IN1(divisor[14]), .IN2(n454), .QN(n453) ); MUX21X1 U532 ( .IN1(divisor[15]), .IN2(n301), .S(n453), .Q(n385) ); OA222X1 U533 ( .IN1(n291), .IN2(\transceiver/enable16_counter[15] ), .IN3( n290), .IN4(n452), .IN5(n385), .IN6(n395), .Q(\transceiver/N100 ) ); NOR2X0 U534 ( .IN1(sys_rst), .IN2(n386), .QN(\transceiver/N190 ) ); MUX21X1 U535 ( .IN1(\transceiver/enable16_counter[0] ), .IN2(divisor[0]), .S(n290), .Q(n387) ); MUX21X1 U536 ( .IN1(n306), .IN2(\transceiver/enable16_counter[0] ), .S( \transceiver/enable16_counter[1] ), .Q(n390) ); MUX21X1 U537 ( .IN1(n390), .IN2(n389), .S(n291), .Q(\transceiver/N86 ) ); OR2X1 U538 ( .IN1(\transceiver/enable16_counter[0] ), .IN2( \transceiver/enable16_counter[1] ), .Q(n391) ); NOR2X0 U539 ( .IN1(\transceiver/enable16_counter[2] ), .IN2(n391), .QN(n397) ); AO21X1 U540 ( .IN1(\transceiver/enable16_counter[2] ), .IN2(n391), .IN3(n397), .Q(n394) ); AO21X1 U541 ( .IN1(divisor[2]), .IN2(n392), .IN3(n396), .Q(n393) ); MUX21X1 U542 ( .IN1(n394), .IN2(n393), .S(n290), .Q(\transceiver/N87 ) ); AO221X1 U543 ( .IN1(n402), .IN2(n396), .IN3(n402), .IN4(n294), .IN5(n395), .Q(n399) ); AO221X1 U544 ( .IN1(n400), .IN2(n397), .IN3(n400), .IN4(n305), .IN5(n291), .Q(n398) ); AO21X1 U545 ( .IN1(divisor[4]), .IN2(n402), .IN3(n407), .Q(n403) ); MUX21X1 U546 ( .IN1(n404), .IN2(n403), .S(n291), .Q(\transceiver/N89 ) ); MUX21X1 U547 ( .IN1(divisor[5]), .IN2(n295), .S(n407), .Q(n408) ); MUX21X1 U548 ( .IN1(n409), .IN2(n408), .S(n290), .Q(\transceiver/N90 ) ); AO21X1 U549 ( .IN1(divisor[6]), .IN2(n412), .IN3(n417), .Q(n413) ); MUX21X1 U550 ( .IN1(n414), .IN2(n413), .S(n291), .Q(\transceiver/N91 ) ); MUX21X1 U551 ( .IN1(divisor[7]), .IN2(n302), .S(n417), .Q(n418) ); MUX21X1 U552 ( .IN1(n419), .IN2(n418), .S(n290), .Q(\transceiver/N92 ) ); AO21X1 U553 ( .IN1(divisor[8]), .IN2(n422), .IN3(n427), .Q(n423) ); MUX21X1 U554 ( .IN1(n424), .IN2(n423), .S(n291), .Q(\transceiver/N93 ) ); MUX21X1 U555 ( .IN1(divisor[9]), .IN2(n298), .S(n427), .Q(n428) ); MUX21X1 U556 ( .IN1(n429), .IN2(n428), .S(n290), .Q(\transceiver/N94 ) ); AO21X1 U557 ( .IN1(divisor[10]), .IN2(n432), .IN3(n437), .Q(n433) ); MUX21X1 U558 ( .IN1(n434), .IN2(n433), .S(n291), .Q(\transceiver/N95 ) );


MUX21X1 U559 ( .IN1(divisor[11]), .IN2(n299), .S(n437), .Q(n438) ); MUX21X1 U560 ( .IN1(n439), .IN2(n438), .S(n290), .Q(\transceiver/N96 ) ); AO21X1 U561 ( .IN1(divisor[12]), .IN2(n442), .IN3(n447), .Q(n443) ); MUX21X1 U562 ( .IN1(n444), .IN2(n443), .S(n291), .Q(\transceiver/N97 ) ); MUX21X1 U563 ( .IN1(divisor[13]), .IN2(n300), .S(n447), .Q(n448) ); MUX21X1 U564 ( .IN1(n449), .IN2(n448), .S(n290), .Q(\transceiver/N98 ) ); AO21X1 U565 ( .IN1(divisor[14]), .IN2(n454), .IN3(n453), .Q(n455) ); MUX21X1 U566 ( .IN1(n456), .IN2(n455), .S(n291), .Q(\transceiver/N99 ) ); MUX21X1 U567 ( .IN1(n458), .IN2(n457), .S(n109), .Q(n459) ); SDFFX1 \transceiver/rx_data_reg[1] ( .D(n215), .SI(rx_data[0]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[1]) ); SDFFX1 \csr_do_reg[1] ( .D(N81), .SI(csr_do[0]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[1]) ); SDFFX1 \transceiver/rx_data_reg[2] ( .D(n214), .SI(rx_data[1]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[2]) ); SDFFX1 \csr_do_reg[2] ( .D(N82), .SI(csr_do[1]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[2]) ); SDFFX1 \transceiver/rx_data_reg[3] ( .D(n213), .SI(rx_data[2]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[3]) ); SDFFX1 \csr_do_reg[3] ( .D(N83), .SI(csr_do[2]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[3]) ); SDFFX1 \transceiver/rx_data_reg[4] ( .D(n212), .SI(rx_data[3]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[4]) ); SDFFX1 \csr_do_reg[4] ( .D(N84), .SI(csr_do[3]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[4]) ); SDFFX1 \transceiver/rx_data_reg[5] ( .D(n211), .SI(rx_data[4]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[5]) ); SDFFX1 \csr_do_reg[5] ( .D(N85), .SI(csr_do[4]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[5]) ); SDFFX1 \transceiver/rx_data_reg[6] ( .D(n210), .SI(rx_data[5]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[6]) ); SDFFX1 \csr_do_reg[6] ( .D(N86), .SI(csr_do[5]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[6]) ); SDFFX1 \transceiver/rx_data_reg[7] ( .D(n209), .SI(rx_data[6]), .SE( Scan_Enable), .CLK(sys_clk), .Q(rx_data[7]) ); SDFFX1 \csr_do_reg[7] ( .D(N87), .SI(csr_do[6]), .SE(Scan_Enable), .CLK( sys_clk), .Q(csr_do[7]) ); SDFFX1 \transceiver/rx_data_reg[0] ( .D(n216), .SI( \transceiver/rx_count16[3] ), .SE(Scan_Enable), .CLK(sys_clk), .Q( rx_data[0]) ); DFFX1 \transceiver/rx_reg_reg[7] ( .D(n224), .CLK(sys_clk), .Q( \transceiver/rx_reg[7] ) ); DFFX1 \transceiver/rx_reg_reg[6] ( .D(n223), .CLK(sys_clk), .Q( \transceiver/rx_reg[6] ) ); DFFX1 \transceiver/rx_reg_reg[5] ( .D(n222), .CLK(sys_clk), .Q(


\transceiver/rx_reg[5] ) ); DFFX1 \transceiver/rx_reg_reg[4] ( .D(n221), .CLK(sys_clk), .Q( \transceiver/rx_reg[4] ) ); DFFX1 \transceiver/rx_reg_reg[3] ( .D(n220), .CLK(sys_clk), .Q( \transceiver/rx_reg[3] ) ); DFFX1 \transceiver/rx_reg_reg[2] ( .D(n219), .CLK(sys_clk), .Q( \transceiver/rx_reg[2] ) ); DFFX1 \transceiver/rx_reg_reg[1] ( .D(n218), .CLK(sys_clk), .Q( \transceiver/rx_reg[1] ) ); DFFX1 \transceiver/rx_reg_reg[0] ( .D(n217), .CLK(sys_clk), .Q( \transceiver/rx_reg[0] ) ); MUX21X1 U568 ( .IN1(n460), .IN2(tx_irq), .S(Scan_Enable), .Q(n462) ); OR2X1 U569 ( .IN1(n382), .IN2(Scan_Enable), .Q(n465) ); OR2X1 U570 ( .IN1(Scan_Enable), .IN2(n347), .Q(n468) ); NOR2X0 U571 ( .IN1(Scan_Enable), .IN2(n373), .QN(n466) ); ISOLANDX1 U572 ( .D(n384), .ISO(Scan_Enable), .Q(n467) ); endmodule Placed Netlist: // // Milkyway Hierarchical Verilog Dump: // Generated on 04/20/2012 at 17:18:37 // Design Generated by Cell Based Verilog Reader // File produced by Consolidated Verilog Writer // Library Name :assign_3_f1 // Cell Name :cuart // Hierarchy delimiter:'/' // module cuart (sys_clk , sys_rst , csr_a , csr_we , csr_di , csr_do , rx_irq , tx_irq , uart_rx , uart_tx , Scan_Enable , Test_Mode ); input sys_clk ; input sys_rst ; input [13:0] csr_a ; input csr_we ; input [31:0] csr_di ; output [31:0] csr_do ; output rx_irq ; output tx_irq ; input uart_rx ; output uart_tx ; input Scan_Enable ; input Test_Mode ;


wire [15:0] divisor ; wire [7:0] rx_data ; wire [7:0] \transceiver/tx_reg ; assign csr_do[30] = csr_do[16] ; assign csr_do[29] = csr_do[16] ; assign csr_do[28] = csr_do[16] ; assign csr_do[27] = csr_do[16] ; assign csr_do[26] = csr_do[16] ; assign csr_do[25] = csr_do[16] ; assign csr_do[24] = csr_do[16] ; assign csr_do[23] = csr_do[16] ; assign csr_do[22] = csr_do[16] ; assign csr_do[21] = csr_do[16] ; assign csr_do[20] = csr_do[16] ; assign csr_do[19] = csr_do[16] ; assign csr_do[18] = csr_do[16] ; assign csr_do[17] = csr_do[16] ; assign csr_do[31] = csr_do[16] ; INVX32 U319 (.IN ( n486 ) , .QN ( uart_tx ) ) ; INVX16 U318 (.IN ( n487 ) , .QN ( n486 ) ) ; INVX2 U312 (.IN ( n479 ) , .QN ( n487 ) ) ; INVX0 U313 (.QN ( n479 ) , .IN ( n462 ) ) ; MUX21X1 U568 (.S ( n483 ) , .IN2 ( tx_irq ) , .IN1 ( n460 ) , .Q ( n462 ) ) ; NOR4X1 U452 (.IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n115 ) , .IN3 ( \transceiver/rx_bitcount[1] ) , .IN4 ( n114 ) , .QN ( n348 ) ) ; INVX0 U317 (.QN ( n484 ) , .IN ( n395 ) ) ; NBUFFX2 U316 (.IN ( Scan_Enable ) , .Q ( n482 ) ) ; NBUFFX2 U315 (.IN ( Scan_Enable ) , .Q ( n481 ) ) ; LSDNX1 U314 (.D ( Scan_Enable ) , .Q ( n480 ) ) ; NBUFFX2 U304 (.IN ( Scan_Enable ) , .Q ( n483 ) ) ; NAND2X0 U392 (.IN2 ( n314 ) , .IN1 ( csr_we ) , .QN ( n351 ) ) ; INVX0 U306 (.QN ( n472 ) , .IN ( sys_rst ) ) ; NOR4X0 U332 (.IN2 ( n346 ) , .IN1 ( n348 ) , .IN3 ( n477 ) , .IN4 ( n344 ) , .QN ( n347 ) ) ; NAND2X0 U369 (.IN1 ( n332 ) , .IN2 ( n476 ) , .QN ( n343 ) ) ; NBUFFX2 U305 (.IN ( Scan_Enable ) , .Q ( n471 ) ) ; INVX0 U311 (.QN ( n477 ) , .IN ( n349 ) ) ; INVX2 U310 (.IN ( n395 ) , .QN ( n476 ) ) ; INVX0 U309 (.QN ( n475 ) , .IN ( n376 ) ) ; INVX0 U308 (.QN ( n474 ) , .IN ( n317 ) ) ; INVX0 U307 (.QN ( n473 ) , .IN ( n311 ) ) ; NOR2X1 U372 (.QN ( n318 ) , .IN1 ( sys_rst ) , .IN2 ( n317 ) ) ; NOR4X1 U442 (.IN2 ( \transceiver/rx_count16[1] )


, .IN1 ( \transceiver/rx_count16[2] ) , .IN3 ( \transceiver/rx_count16[3] ) , .IN4 ( n319 ) , .QN ( n349 ) ) ; NAND2X0 U334 (.IN1 ( n352 ) , .IN2 ( n296 ) , .QN ( n319 ) ) ; NAND2X0 U333 (.IN1 ( n475 ) , .IN2 ( n472 ) , .QN ( n353 ) ) ; NAND2X0 U331 (.IN1 ( n373 ) , .IN2 ( n353 ) , .QN ( n355 ) ) ; NAND2X0 U330 (.IN1 ( n399 ) , .IN2 ( n398 ) , .QN ( \transceiver/N88 ) ) ; NAND2X0 U329 (.IN1 ( n458 ) , .IN2 ( n360 ) , .QN ( n358 ) ) ; NAND2X0 U328 (.IN1 ( n475 ) , .IN2 ( n375 ) , .QN ( n363 ) ) ; NAND2X0 U327 (.IN1 ( n373 ) , .IN2 ( n372 ) , .QN ( n202 ) ) ; NAND2X0 U326 (.IN1 ( n322 ) , .IN2 ( n321 ) , .QN ( n281 ) ) ; NAND2X0 U325 (.IN1 ( n369 ) , .IN2 ( n368 ) , .QN ( n259 ) ) ; AO22X1 U303 (.IN1 ( n473 ) , .IN3 ( n312 ) , .IN2 ( divisor[0] ) , .Q ( N80 ) , .IN4 ( n253 ) ) ; MUX21X1 U302 (.S ( csr_a[1] ) , .IN2 ( thru ) , .IN1 ( rx_data[0] ) , .Q ( n253 ) ) ; NOR2X0 U301 (.QN ( n285 ) , .IN1 ( n252 ) , .IN2 ( n326 ) ) ; NOR2X0 U300 (.QN ( n252 ) , .IN1 ( n293 ) , .IN2 ( n325 ) ) ; NAND2X0 U299 (.IN1 ( n375 ) , .IN2 ( n251 ) , .QN ( n384 ) ) ; NAND2X0 U298 (.IN1 ( n378 ) , .IN2 ( n374 ) , .QN ( n251 ) ) ; NAND2X0 U297 (.IN1 ( \transceiver/rx_busy ) , .IN2 ( n472 ) , .QN ( n344 ) ) ; NAND2X0 U296 (.IN1 ( n475 ) , .IN2 ( n109 ) , .QN ( n360 ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[1] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/tx_bitcount[0] ) , .D ( n257 ) , .QN ( \transceiver/tx_bitcount[1] ) , .Q ( n464 ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[3] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/tx_bitcount[2] ) , .D ( n259 ) , .QN ( n110 ) , .Q ( n463 ) ) ; SDFFX1 \transceiver/tx_count16_reg[1] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/tx_count16[0] ) , .D ( n459 ) , .Q ( n109 ) ) ; SDFFX1 \transceiver/uart_rx1_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( uart_rx ) , .D ( uart_rx ) , .QN ( n72 ) ) ; SDFFX1 \transceiver/tx_count16_reg[2] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( n109 ) , .D ( n263 ) , .QN ( n297 ) , .Q ( \transceiver/tx_count16[2] ) ) ; SDFFX1 \divisor_reg[3] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[2] ) , .D ( n265 ) , .QN ( n294 ) , .Q ( divisor[3] ) ) ; SDFFX1 \divisor_reg[7] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[6] ) , .D ( n267 ) , .QN ( n302 ) , .Q ( divisor[7] ) ) ; SDFFX1 \divisor_reg[5] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[4] ) , .D ( n269 ) , .QN ( n295 ) , .Q ( divisor[5] ) ) ; SDFFX1 \transceiver/rx_count16_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_busy ) , .D ( n271 ) , .QN ( n296 ) , .Q ( \transceiver/rx_count16[0] ) ) ; SDFFX1 \divisor_reg[9] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[8] ) , .D ( n273 ) , .QN ( n298 ) , .Q ( divisor[9] ) ) ; SDFFX1 \divisor_reg[11] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[10] ) , .D ( n275 ) , .QN ( n299 ) , .Q ( divisor[11] ) ) ;


SDFFX1 \divisor_reg[13] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[12] ) , .D ( n277 ) , .QN ( n300 ) , .Q ( divisor[13] ) ) ; SDFFX1 \divisor_reg[15] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[14] ) , .D ( n279 ) , .QN ( n301 ) , .Q ( divisor[15] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[3] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_bitcount[2] ) , .D ( n281 ) , .QN ( n115 ) , .Q ( n304 ) ) ; SDFFX1 \transceiver/rx_count16_reg[3] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[2] ) , .D ( n283 ) , .QN ( n307 ) , .Q ( \transceiver/rx_count16[3] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/enable16_counter[15] ) , .D ( n285 ) , .QN ( n114 ) , .Q ( n293 ) ) ; SDFFX1 \transceiver/enable16_counter_reg[3] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[2] ) , .D ( \transceiver/N88 ) , .QN ( n305 ) , .Q ( \transceiver/enable16_counter[3] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[0] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( thru ) , .D ( n387 ) , .QN ( \transceiver/enable16_counter[0] ) , .Q ( n306 ) ) ; SDFFX1 \transceiver/rx_busy_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( n304 ) , .D ( n289 ) , .QN ( n292 ) , .Q ( \transceiver/rx_busy ) ) ; DFFX1 \transceiver/uart_rx2_reg (.CLK ( sys_clk ) , .QN ( \transceiver/uart_rx2 ) , .Q ( n303 ) , .D ( n72 ) ) ; DFFX1 \transceiver/tx_reg_reg[0] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [0] ) , .D ( n200 ) ) ; DFFX1 \transceiver/tx_reg_reg[1] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [1] ) , .D ( n198 ) ) ; DFFX1 \transceiver/tx_reg_reg[2] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [2] ) , .D ( n197 ) ) ; DFFX1 \transceiver/tx_reg_reg[3] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [3] ) , .D ( n196 ) ) ; DFFX1 \transceiver/tx_reg_reg[4] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [4] ) , .D ( n195 ) ) ; DFFX1 \transceiver/tx_reg_reg[5] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [5] ) , .D ( n194 ) ) ; DFFX1 \transceiver/tx_reg_reg[6] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [6] ) , .D ( n193 ) ) ; SDFFX1 \transceiver/enable16_counter_reg[1] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( n306 ) , .D ( \transceiver/N86 ) , .Q ( \transceiver/enable16_counter[1] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[2] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[1] ) , .D ( \transceiver/N87 ) , .Q ( \transceiver/enable16_counter[2] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[4] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[3] ) , .D ( \transceiver/N89 ) , .Q ( \transceiver/enable16_counter[4] ) ) ;


SDFFX1 \transceiver/enable16_counter_reg[5] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[4] ) , .D ( \transceiver/N90 ) , .Q ( \transceiver/enable16_counter[5] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[6] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[5] ) , .D ( \transceiver/N91 ) , .Q ( \transceiver/enable16_counter[6] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[7] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[6] ) , .D ( \transceiver/N92 ) , .Q ( \transceiver/enable16_counter[7] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[8] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[7] ) , .D ( \transceiver/N93 ) , .Q ( \transceiver/enable16_counter[8] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[9] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[8] ) , .D ( \transceiver/N94 ) , .Q ( \transceiver/enable16_counter[9] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[10] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[9] ) , .D ( \transceiver/N95 ) , .Q ( \transceiver/enable16_counter[10] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[11] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[10] ) , .D ( \transceiver/N96 ) , .Q ( \transceiver/enable16_counter[11] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[12] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[11] ) , .D ( \transceiver/N97 ) , .Q ( \transceiver/enable16_counter[12] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[13] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[12] ) , .D ( \transceiver/N98 ) , .Q ( \transceiver/enable16_counter[13] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[14] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[13] ) , .D ( \transceiver/N99 ) , .Q ( \transceiver/enable16_counter[14] ) ) ; SDFFX1 \transceiver/uart_tx_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_count16[3] ) , .D ( n199 ) , .Q ( uart_tx_transceiver ) ) ; SDFFX1 \transceiver/tx_busy_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( n463 ) , .D ( n202 ) , .Q ( \transceiver/tx_busy ) ) ; SDFFX1 \transceiver/tx_done_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( uart_tx_transceiver ) , .D ( \transceiver/N190 ) , .Q ( tx_irq ) ) ; SDFFX1 \transceiver/tx_reg_reg[7] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/rx_reg[0] ) , .D ( n201 ) , .Q ( \transceiver/tx_reg [7] ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[2] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( n464 ) , .D ( n204 ) , .Q ( \transceiver/tx_bitcount[2] ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( rx_irq ) , .D ( n205 ) , .Q ( \transceiver/tx_bitcount[0] ) ) ; SDFFX1 \transceiver/tx_count16_reg[3] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_count16[2] ) , .D ( n206 ) , .Q ( \transceiver/tx_count16[3] ) ) ;


SDFFX1 \transceiver/tx_count16_reg[0] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_busy ) , .D ( n208 ) , .Q ( \transceiver/tx_count16[0] ) ) ; SDFFX1 \transceiver/rx_count16_reg[2] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[1] ) , .D ( n226 ) , .Q ( \transceiver/rx_count16[2] ) ) ; SDFFX1 \transceiver/rx_count16_reg[1] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[0] ) , .D ( n227 ) , .Q ( \transceiver/rx_count16[1] ) ) ; SDFFX1 \csr_do_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/tx_reg [0] ) , .D ( N80 ) , .Q ( csr_do[0] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[2] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/rx_bitcount[1] ) , .D ( n229 ) , .Q ( \transceiver/rx_bitcount[2] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[1] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( n293 ) , .D ( n230 ) , .Q ( \transceiver/rx_bitcount[1] ) ) ; SDFFX1 \transceiver/rx_done_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( rx_data[7] ) , .D ( \transceiver/N137 ) , .Q ( rx_irq ) ) ; SDFFX1 \transceiver/enable16_counter_reg[15] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[14] ) , .D ( \transceiver/N100 ) , .Q ( \transceiver/enable16_counter[15] ) ) ; SDFFX1 \csr_do_reg[8] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[7] ) , .D ( N88 ) , .Q ( csr_do[8] ) ) ; SDFFX1 \csr_do_reg[9] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[8] ) , .D ( N89 ) , .Q ( csr_do[9] ) ) ; SDFFX1 \csr_do_reg[10] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[9] ) , .D ( N90 ) , .Q ( csr_do[10] ) ) ; SDFFX1 \csr_do_reg[11] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[10] ) , .D ( N91 ) , .Q ( csr_do[11] ) ) ; SDFFX1 \csr_do_reg[12] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[11] ) , .D ( N92 ) , .Q ( csr_do[12] ) ) ; SDFFX1 \csr_do_reg[13] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[12] ) , .D ( N93 ) , .Q ( csr_do[13] ) ) ; SDFFX1 \csr_do_reg[14] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[13] ) , .D ( N94 ) , .Q ( csr_do[14] ) ) ; SDFFX1 \csr_do_reg[15] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( csr_do[14] ) , .D ( N95 ) , .Q ( csr_do[15] ) ) ; SDFFX1 \divisor_reg[0] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[15] ) , .D ( n234 ) , .Q ( divisor[0] ) ) ; SDFFX1 \divisor_reg[1] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[0] ) , .D ( n235 ) , .Q ( divisor[1] ) ) ; SDFFX1 \divisor_reg[2] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[1] ) , .D ( n236 ) , .Q ( divisor[2] ) ) ; SDFFX1 \divisor_reg[4] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[3] ) , .D ( n238 ) , .Q ( divisor[4] ) ) ;


SDFFX1 \divisor_reg[6] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[5] ) , .D ( n240 ) , .Q ( divisor[6] ) ) ; SDFFX1 \divisor_reg[8] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[7] ) , .D ( n242 ) , .Q ( divisor[8] ) ) ; SDFFX1 \divisor_reg[10] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[9] ) , .D ( n244 ) , .Q ( divisor[10] ) ) ; SDFFX1 \divisor_reg[12] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[11] ) , .D ( n246 ) , .Q ( divisor[12] ) ) ; SDFFX1 \divisor_reg[14] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( divisor[13] ) , .D ( n248 ) , .Q ( divisor[14] ) ) ; SDFFX1 thru_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( divisor[15] ) , .D ( n250 ) , .Q ( thru ) ) ; AO221X1 U428 (.IN5 ( sys_rst ) , .Q ( n236 ) , .IN2 ( csr_di[2] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[2] ) ) ; AO221X1 U427 (.IN5 ( sys_rst ) , .Q ( n238 ) , .IN2 ( csr_di[4] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[4] ) ) ; AO221X1 U426 (.IN5 ( sys_rst ) , .Q ( n269 ) , .IN2 ( csr_di[5] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[5] ) ) ; AO22X1 U424 (.IN1 ( divisor[8] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n242 ) , .IN4 ( csr_di[8] ) ) ; AO22X1 U423 (.IN1 ( divisor[9] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n273 ) , .IN4 ( csr_di[9] ) ) ; AO22X1 U422 (.IN1 ( divisor[10] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n244 ) , .IN4 ( csr_di[10] ) ) ; AO22X1 U421 (.IN1 ( divisor[11] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n275 ) , .IN4 ( csr_di[11] ) ) ; AO22X1 U420 (.IN1 ( divisor[12] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n246 ) , .IN4 ( csr_di[12] ) ) ; AO22X1 U419 (.IN1 ( divisor[13] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n277 ) , .IN4 ( csr_di[13] ) ) ; AO22X1 U418 (.IN1 ( divisor[14] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n248 ) , .IN4 ( csr_di[14] ) ) ; AO22X1 U417 (.IN1 ( divisor[15] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n279 ) , .IN4 ( csr_di[15] ) ) ; INVX0 U416 (.QN ( n315 ) , .IN ( csr_a[0] ) ) ; MUX21X1 U415 (.S ( n313 ) , .IN2 ( thru ) , .IN1 ( csr_di[0] ) , .Q ( n250 ) ) ; NAND3X0 U414 (.QN ( n313 ) , .IN3 ( n312 ) , .IN2 ( csr_we ) , .IN1 ( csr_a[1] ) ) ; NOR2X0 U413 (.QN ( N95 ) , .IN1 ( n301 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U412 (.ISO ( n311 ) , .D ( divisor[14] ) , .Q ( N94 ) ) ; NOR2X0 U411 (.QN ( N93 ) , .IN1 ( n300 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U410 (.ISO ( n311 ) , .D ( divisor[12] ) , .Q ( N92 ) ) ; NOR2X0 U409 (.QN ( N91 ) , .IN1 ( n299 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U408 (.ISO ( n311 ) , .D ( divisor[10] ) , .Q ( N90 ) ) ; NOR2X0 U407 (.QN ( N89 ) , .IN1 ( n298 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U406 (.ISO ( n311 ) , .D ( divisor[8] ) , .Q ( N88 ) ) ;


AO22X1 U405 (.IN1 ( rx_data[7] ) , .IN3 ( divisor[7] ) , .IN2 ( n310 ) , .Q ( N87 ) , .IN4 ( n473 ) ) ; AO22X1 U404 (.IN1 ( rx_data[6] ) , .IN3 ( divisor[6] ) , .IN2 ( n310 ) , .Q ( N86 ) , .IN4 ( n473 ) ) ; AO22X1 U403 (.IN1 ( rx_data[5] ) , .IN3 ( divisor[5] ) , .IN2 ( n310 ) , .Q ( N85 ) , .IN4 ( n473 ) ) ; AO22X1 U402 (.IN1 ( rx_data[4] ) , .IN3 ( divisor[4] ) , .IN2 ( n310 ) , .Q ( N84 ) , .IN4 ( n473 ) ) ; AO22X1 U401 (.IN1 ( rx_data[3] ) , .IN3 ( divisor[3] ) , .IN2 ( n310 ) , .Q ( N83 ) , .IN4 ( n473 ) ) ; AO22X1 U400 (.IN1 ( rx_data[2] ) , .IN3 ( divisor[2] ) , .IN2 ( n310 ) , .Q ( N82 ) , .IN4 ( n473 ) ) ; AO22X1 U399 (.IN1 ( rx_data[1] ) , .IN3 ( divisor[1] ) , .IN2 ( n310 ) , .Q ( N81 ) , .IN4 ( n473 ) ) ; NOR3X0 U398 (.IN2 ( sys_rst ) , .QN ( n312 ) , .IN1 ( csr_a[0] ) , .IN3 ( n308 ) ) ; NAND3X0 U396 (.QN ( n311 ) , .IN3 ( n472 ) , .IN2 ( csr_a[0] ) , .IN1 ( n314 ) ) ; OR4X1 U395 (.IN4 ( csr_a[13] ) , .IN2 ( csr_a[11] ) , .Q ( n308 ) , .IN1 ( csr_a[10] ) , .IN3 ( csr_a[12] ) ) ; MUX21X1 U393 (.S ( thru ) , .IN2 ( uart_rx ) , .IN1 ( uart_tx_transceiver ) , .Q ( n460 ) ) ; INVX0 U391 (.QN ( n374 ) , .IN ( n361 ) ) ; INVX0 U390 (.QN ( n383 ) , .IN ( n373 ) ) ; AO22X1 U389 (.IN1 ( csr_di[3] ) , .IN3 ( divisor[3] ) , .IN2 ( n318 ) , .Q ( n265 ) , .IN4 ( n317 ) ) ; AO22X1 U388 (.IN1 ( csr_di[7] ) , .IN3 ( divisor[7] ) , .IN2 ( n318 ) , .Q ( n267 ) , .IN4 ( n317 ) ) ; AO22X1 U387 (.IN1 ( csr_di[0] ) , .IN3 ( divisor[0] ) , .IN2 ( n318 ) , .Q ( n234 ) , .IN4 ( n317 ) ) ; AO22X1 U386 (.IN1 ( csr_di[6] ) , .IN3 ( divisor[6] ) , .IN2 ( n318 ) , .Q ( n240 ) , .IN4 ( n317 ) ) ; INVX0 U385 (.QN ( n350 ) , .IN ( n344 ) ) ; ISOLANDX1 U384 (.ISO ( csr_a[1] ) , .D ( n312 ) , .Q ( n310 ) ) ; NAND2X0 U383 (.IN1 ( divisor[0] ) , .IN2 ( divisor[1] ) , .QN ( n388 ) ) ; NOR2X0 U382 (.QN ( n382 ) , .IN1 ( n376 ) , .IN2 ( n384 ) ) ; AND4X1 U381 (.IN1 ( n350 ) , .IN2 ( n349 ) , .IN3 ( \transceiver/uart_rx2 ) , .IN4 ( n348 ) , .Q ( \transceiver/N137 ) ) ; NAND2X0 U380 (.IN1 ( \transceiver/tx_bitcount[1] ) , .IN2 ( \transceiver/tx_bitcount[0] ) , .QN ( n364 ) ) ; NOR2X0 U379 (.QN ( n337 ) , .IN1 ( sys_rst ) , .IN2 ( n343 ) ) ; NOR2X0 U378 (.QN ( n314 ) , .IN1 ( csr_a[1] ) , .IN2 ( n308 ) ) ; NOR2X0 U377 (.QN ( n352 ) , .IN1 ( \transceiver/enable16_counter[15] ) , .IN2 ( n452 ) ) ; NOR2X0 U376 (.QN ( n375 ) , .IN1 ( sys_rst ) , .IN2 ( n381 ) ) ; OA21X1 U375 (.IN2 ( n351 ) , .IN3 ( n472 ) , .IN1 ( n315 ) , .Q ( n317 ) ) ; NOR2X0 U373 (.QN ( n395 ) , .IN1 ( n352 ) , .IN2 ( sys_rst ) ) ;


NOR2X0 U371 (.QN ( n361 ) , .IN1 ( csr_a[0] ) , .IN2 ( n351 ) ) ; NAND2X0 U370 (.IN1 ( n374 ) , .IN2 ( \transceiver/tx_count16[0] ) , .QN ( n354 ) ) ; NAND2X0 U366 (.IN1 ( \transceiver/rx_count16[0] ) , .IN2 ( \transceiver/rx_count16[1] ) , .QN ( n338 ) ) ; NAND2X0 U365 (.IN1 ( n392 ) , .IN2 ( n388 ) , .QN ( n389 ) ) ; NAND2X0 U364 (.IN1 ( \transceiver/enable16_counter[4] ) , .IN2 ( n400 ) , .QN ( n401 ) ) ; NAND2X0 U363 (.IN1 ( \transceiver/enable16_counter[5] ) , .IN2 ( n405 ) , .QN ( n406 ) ) ; NAND2X0 U362 (.IN1 ( n405 ) , .IN2 ( n401 ) , .QN ( n404 ) ) ; NAND2X0 U361 (.IN1 ( n396 ) , .IN2 ( n294 ) , .QN ( n402 ) ) ; NAND2X0 U360 (.IN1 ( \transceiver/rx_count16[2] ) , .IN2 ( n339 ) , .QN ( n340 ) ) ; NAND2X0 U359 (.IN1 ( n472 ) , .IN2 ( n361 ) , .QN ( n373 ) ) ; NAND2X0 U358 (.IN1 ( \transceiver/enable16_counter[6] ) , .IN2 ( n410 ) , .QN ( n411 ) ) ; NAND2X0 U357 (.IN1 ( n410 ) , .IN2 ( n406 ) , .QN ( n409 ) ) ; NAND2X0 U356 (.IN1 ( n415 ) , .IN2 ( n411 ) , .QN ( n414 ) ) ; NAND2X0 U355 (.IN1 ( \transceiver/enable16_counter[7] ) , .IN2 ( n415 ) , .QN ( n416 ) ) ; NAND2X0 U354 (.IN1 ( n407 ) , .IN2 ( n295 ) , .QN ( n412 ) ) ; NAND2X0 U353 (.IN1 ( n420 ) , .IN2 ( n416 ) , .QN ( n419 ) ) ; NAND2X0 U352 (.IN1 ( \transceiver/enable16_counter[8] ) , .IN2 ( n420 ) , .QN ( n421 ) ) ; NAND2X0 U351 (.IN1 ( n417 ) , .IN2 ( n302 ) , .QN ( n422 ) ) ; NAND2X0 U350 (.IN1 ( n425 ) , .IN2 ( n421 ) , .QN ( n424 ) ) ; NAND2X0 U349 (.IN1 ( \transceiver/enable16_counter[9] ) , .IN2 ( n425 ) , .QN ( n426 ) ) ; NAND2X0 U348 (.IN1 ( \transceiver/enable16_counter[10] ) , .IN2 ( n430 ) , .QN ( n431 ) ) ; NAND2X0 U347 (.IN1 ( n430 ) , .IN2 ( n426 ) , .QN ( n429 ) ) ; NAND2X0 U346 (.IN1 ( n427 ) , .IN2 ( n298 ) , .QN ( n432 ) ) ; NAND2X0 U345 (.IN1 ( n435 ) , .IN2 ( n431 ) , .QN ( n434 ) ) ; NAND2X0 U344 (.IN1 ( \transceiver/enable16_counter[11] ) , .IN2 ( n435 ) , .QN ( n436 ) ) ; NAND2X0 U343 (.IN1 ( n440 ) , .IN2 ( n436 ) , .QN ( n439 ) ) ; NAND2X0 U342 (.IN1 ( \transceiver/enable16_counter[12] ) , .IN2 ( n440 ) , .QN ( n441 ) ) ; NAND2X0 U341 (.IN1 ( \transceiver/enable16_counter[13] ) , .IN2 ( n445 ) , .QN ( n446 ) ) ; NAND2X0 U340 (.IN1 ( n437 ) , .IN2 ( n299 ) , .QN ( n442 ) ) ; NAND2X0 U339 (.IN1 ( n445 ) , .IN2 ( n441 ) , .QN ( n444 ) ) ; NAND2X0 U338 (.IN1 ( \transceiver/enable16_counter[14] ) , .IN2 ( n450 ) , .QN ( n451 ) ) ;


NAND2X0 U337 (.IN1 ( n450 ) , .IN2 ( n446 ) , .QN ( n449 ) ) ; NAND2X0 U336 (.IN1 ( n447 ) , .IN2 ( n300 ) , .QN ( n454 ) ) ; NAND2X0 U335 (.IN1 ( n452 ) , .IN2 ( n451 ) , .QN ( n456 ) ) ; AO222X1 U521 (.Q ( n195 ) , .IN2 ( \transceiver/tx_reg [4] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[4] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [5] ) ) ; AO222X1 U520 (.Q ( n196 ) , .IN2 ( \transceiver/tx_reg [3] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[3] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [4] ) ) ; AO222X1 U519 (.Q ( n197 ) , .IN2 ( \transceiver/tx_reg [2] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[2] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [3] ) ) ; AO222X1 U518 (.Q ( n198 ) , .IN2 ( \transceiver/tx_reg [1] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[1] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [2] ) ) ; AO221X1 U517 (.IN5 ( sys_rst ) , .Q ( n199 ) , .IN2 ( uart_tx_transceiver ) , .IN1 ( n381 ) , .IN3 ( n380 ) , .IN4 ( n379 ) ) ; OA21X1 U516 (.IN2 ( \transceiver/tx_reg [0] ) , .IN3 ( n475 ) , .IN1 ( n378 ) , .Q ( n379 ) ) ; INVX0 U515 (.QN ( n380 ) , .IN ( n381 ) ) ; AO222X1 U514 (.Q ( n200 ) , .IN2 ( \transceiver/tx_reg [0] ) , .IN1 ( n467 ) , .IN3 ( n465 ) , .IN4 ( \transceiver/tx_reg [1] ) , .IN6 ( csr_di[0] ) , .IN5 ( n466 ) ) ; AO22X1 U513 (.IN1 ( csr_di[7] ) , .IN3 ( \transceiver/tx_reg [7] ) , .IN2 ( n383 ) , .Q ( n201 ) , .IN4 ( n384 ) ) ; NAND3X0 U512 (.QN ( n372 ) , .IN3 ( n386 ) , .IN2 ( n472 ) , .IN1 ( \transceiver/tx_busy ) ) ; NAND3X0 U511 (.QN ( n386 ) , .IN3 ( n378 ) , .IN2 ( \transceiver/tx_bitcount[0] ) , .IN1 ( n370 ) ) ; NOR3X0 U510 (.IN2 ( n110 ) , .QN ( n378 ) , .IN1 ( \transceiver/tx_bitcount[2] ) , .IN3 ( \transceiver/tx_bitcount[1] ) ) ; AO221X1 U509 (.IN5 ( n110 ) , .Q ( n368 ) , .IN2 ( \transceiver/tx_bitcount[2] ) , .IN1 ( n367 ) , .IN3 ( n367 ) , .IN4 ( n376 ) ) ; NAND3X0 U508 (.QN ( n369 ) , .IN3 ( \transceiver/tx_bitcount[2] ) , .IN2 ( n110 ) , .IN1 ( n366 ) ) ; MUX21X1 U507 (.S ( \transceiver/tx_bitcount[2] ) , .IN2 ( n365 ) , .IN1 ( n366 ) , .Q ( n204 ) ) ; NOR2X0 U506 (.QN ( n366 ) , .IN1 ( n364 ) , .IN2 ( n363 ) ) ; OAI221X1 U505 (.IN2 ( n375 ) , .QN ( n257 ) , .IN5 ( n365 ) , .IN4 ( \transceiver/tx_bitcount[0] ) , .IN3 ( \transceiver/tx_bitcount[1] ) , .IN1 ( \transceiver/tx_bitcount[1] ) ) ; INVX0 U504 (.QN ( n365 ) , .IN ( n367 ) ) ; OA221X1 U503 (.IN2 ( \transceiver/tx_bitcount[1] ) , .IN4 ( \transceiver/tx_bitcount[0] ) , .Q ( n367 ) , .IN5 ( n375 ) , .IN1 ( n376 ) , .IN3 ( n376 ) ) ;


INVX0 U502 (.QN ( n205 ) , .IN ( n362 ) ) ; MUX21X1 U501 (.S ( \transceiver/tx_bitcount[0] ) , .IN2 ( n375 ) , .IN1 ( n363 ) , .Q ( n362 ) ) ; NOR2X0 U500 (.QN ( n381 ) , .IN1 ( n361 ) , .IN2 ( n370 ) ) ; NOR4X0 U499 (.IN2 ( \transceiver/tx_count16[3] ) , .IN1 ( \transceiver/tx_count16[0] ) , .IN3 ( \transceiver/tx_count16[2] ) , .IN4 ( n360 ) , .QN ( n370 ) ) ; AO221X1 U498 (.IN5 ( n357 ) , .Q ( n206 ) , .IN2 ( n359 ) , .IN1 ( \transceiver/tx_count16[3] ) , .IN3 ( \transceiver/tx_count16[3] ) , .IN4 ( n358 ) ) ; NOR4X0 U497 (.IN2 ( \transceiver/tx_count16[3] ) , .IN1 ( n109 ) , .IN3 ( n297 ) , .IN4 ( n457 ) , .QN ( n357 ) ) ; NOR2X0 U496 (.QN ( n359 ) , .IN1 ( \transceiver/tx_count16[2] ) , .IN2 ( n376 ) ) ; MUX21X1 U495 (.S ( n297 ) , .IN2 ( n356 ) , .IN1 ( n358 ) , .Q ( n263 ) ) ; NOR2X0 U494 (.QN ( n356 ) , .IN1 ( n109 ) , .IN2 ( n457 ) ) ; NAND3X0 U493 (.QN ( n457 ) , .IN3 ( n472 ) , .IN2 ( \transceiver/tx_count16[0] ) , .IN1 ( n475 ) ) ; OA21X1 U492 (.IN2 ( n376 ) , .IN3 ( n355 ) , .IN1 ( \transceiver/tx_count16[0] ) , .Q ( n458 ) ) ; MUX21X1 U491 (.S ( n355 ) , .IN2 ( n354 ) , .IN1 ( \transceiver/tx_count16[0] ) , .Q ( n208 ) ) ; NAND3X0 U489 (.QN ( n376 ) , .IN3 ( n374 ) , .IN2 ( \transceiver/tx_busy ) , .IN1 ( n352 ) ) ; MUX21X1 U488 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[7] ) , .IN1 ( rx_data[7] ) , .Q ( n209 ) ) ; MUX21X1 U487 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[6] ) , .IN1 ( rx_data[6] ) , .Q ( n210 ) ) ; MUX21X1 U486 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[5] ) , .IN1 ( rx_data[5] ) , .Q ( n211 ) ) ; MUX21X1 U485 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[4] ) , .IN1 ( rx_data[4] ) , .Q ( n212 ) ) ; MUX21X1 U484 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[3] ) , .IN1 ( rx_data[3] ) , .Q ( n213 ) ) ; MUX21X1 U483 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[2] ) , .IN1 ( rx_data[2] ) , .Q ( n214 ) ) ; MUX21X1 U482 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[1] ) , .IN1 ( rx_data[1] ) , .Q ( n215 ) ) ; MUX21X1 U481 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[0] ) , .IN1 ( rx_data[0] ) , .Q ( n216 ) ) ; MUX21X1 U480 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[1] ) , .IN1 ( \transceiver/rx_reg[0] ) , .Q ( n217 ) ) ; MUX21X1 U479 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[2] ) , .IN1 ( \transceiver/rx_reg[1] ) , .Q ( n218 ) ) ;


MUX21X1 U478 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[3] ) , .IN1 ( \transceiver/rx_reg[2] ) , .Q ( n219 ) ) ; MUX21X1 U477 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[4] ) , .IN1 ( \transceiver/rx_reg[3] ) , .Q ( n220 ) ) ; MUX21X1 U476 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[5] ) , .IN1 ( \transceiver/rx_reg[4] ) , .Q ( n221 ) ) ; MUX21X1 U475 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[6] ) , .IN1 ( \transceiver/rx_reg[5] ) , .Q ( n222 ) ) ; MUX21X1 U474 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[7] ) , .IN1 ( \transceiver/rx_reg[6] ) , .Q ( n223 ) ) ; MUX21X1 U473 (.S ( n468 ) , .IN2 ( \transceiver/uart_rx2 ) , .IN1 ( \transceiver/rx_reg[7] ) , .Q ( n224 ) ) ; OA22X1 U471 (.IN2 ( n342 ) , .IN4 ( n341 ) , .IN1 ( n343 ) , .IN3 ( \transceiver/rx_count16[3] ) , .Q ( n283 ) ) ; NOR2X0 U470 (.QN ( n341 ) , .IN1 ( n343 ) , .IN2 ( n340 ) ) ; OA21X1 U469 (.IN2 ( n307 ) , .IN3 ( n350 ) , .IN1 ( n340 ) , .Q ( n342 ) ) ; INVX0 U468 (.QN ( n339 ) , .IN ( n338 ) ) ; AO221X1 U467 (.IN5 ( n335 ) , .Q ( n226 ) , .IN2 ( n336 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) ) ; OA221X1 U466 (.IN2 ( n472 ) , .IN4 ( n338 ) , .Q ( n335 ) , .IN5 ( \transceiver/rx_count16[2] ) , .IN1 ( n343 ) , .IN3 ( n343 ) ) ; NOR2X0 U465 (.QN ( n336 ) , .IN1 ( \transceiver/rx_count16[2] ) , .IN2 ( n338 ) ) ; AO221X1 U464 (.IN5 ( n333 ) , .Q ( n227 ) , .IN2 ( n334 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) ) ; OA221X1 U463 (.IN2 ( n472 ) , .IN4 ( n296 ) , .Q ( n333 ) , .IN5 ( \transceiver/rx_count16[1] ) , .IN1 ( n343 ) , .IN3 ( n343 ) ) ; NOR2X0 U462 (.QN ( n334 ) , .IN1 ( \transceiver/rx_count16[1] ) , .IN2 ( n296 ) ) ; AO222X1 U461 (.Q ( n271 ) , .IN2 ( n296 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) , .IN6 ( n343 ) , .IN5 ( \transceiver/rx_count16[0] ) ) ; NAND3X0 U460 (.QN ( n332 ) , .IN3 ( n472 ) , .IN2 ( n292 ) , .IN1 ( \transceiver/uart_rx2 ) ) ; MUX21X1 U459 (.S ( \transceiver/rx_bitcount[2] ) , .IN2 ( n330 ) , .IN1 ( n331 ) , .Q ( n229 ) ) ; INVX0 U458 (.QN ( n330 ) , .IN ( n329 ) ) ; INVX0 U457 (.QN ( n230 ) , .IN ( n328 ) ) ; MUX21X1 U456 (.S ( \transceiver/rx_bitcount[1] ) , .IN2 ( n326 ) , .IN1 ( n327 ) , .Q ( n328 ) ) ; OAI22X1 U455 (.IN3 ( n323 ) , .QN ( n289 ) , .IN1 ( sys_rst ) , .IN4 ( n344 ) , .IN2 ( n324 ) ) ; OA221X1 U454 (.IN2 ( n346 ) , .IN4 ( \transceiver/uart_rx2 ) , .Q ( n323 ) , .IN5 ( n349 ) , .IN1 ( n348 ) , .IN3 ( n348 ) ) ; NOR4X0 U453 (.IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( \transceiver/rx_bitcount[1] ) , .IN3 ( n304 ) , .IN4 ( n293 )


, .QN ( n346 ) ) ; AO221X1 U451 (.IN5 ( n115 ) , .Q ( n321 ) , .IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n329 ) , .IN3 ( n329 ) , .IN4 ( n344 ) ) ; OA21X1 U450 (.IN2 ( n344 ) , .IN3 ( n326 ) , .IN1 ( \transceiver/rx_bitcount[1] ) , .Q ( n329 ) ) ; OA21X1 U449 (.IN2 ( n344 ) , .IN3 ( n325 ) , .IN1 ( n293 ) , .Q ( n326 ) ) ; NAND3X0 U448 (.QN ( n325 ) , .IN3 ( n320 ) , .IN2 ( n324 ) , .IN1 ( n472 ) ) ; NAND2X0 U447 (.IN1 ( n349 ) , .IN2 ( \transceiver/rx_busy ) , .QN ( n320 ) ) ; NAND3X0 U446 (.QN ( n324 ) , .IN3 ( n303 ) , .IN2 ( n292 ) , .IN1 ( n352 ) ) ; NAND3X0 U445 (.QN ( n322 ) , .IN3 ( n115 ) , .IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n331 ) ) ; ISOLANDX1 U444 (.ISO ( n327 ) , .D ( \transceiver/rx_bitcount[1] ) , .Q ( n331 ) ) ; NAND4X0 U443 (.IN1 ( \transceiver/rx_busy ) , .QN ( n327 ) , .IN2 ( n349 ) , .IN3 ( n472 ) , .IN4 ( n293 ) ) ; OR2X1 U441 (.IN2 ( n450 ) , .IN1 ( \transceiver/enable16_counter[14] ) , .Q ( n452 ) ) ; OR2X1 U440 (.IN2 ( n445 ) , .IN1 ( \transceiver/enable16_counter[13] ) , .Q ( n450 ) ) ; OR2X1 U439 (.IN2 ( n440 ) , .IN1 ( \transceiver/enable16_counter[12] ) , .Q ( n445 ) ) ; OR2X1 U438 (.IN2 ( n435 ) , .IN1 ( \transceiver/enable16_counter[11] ) , .Q ( n440 ) ) ; OR2X1 U437 (.IN2 ( n430 ) , .IN1 ( \transceiver/enable16_counter[10] ) , .Q ( n435 ) ) ; OR2X1 U436 (.IN2 ( n425 ) , .IN1 ( \transceiver/enable16_counter[9] ) , .Q ( n430 ) ) ; OR2X1 U435 (.IN2 ( n420 ) , .IN1 ( \transceiver/enable16_counter[8] ) , .Q ( n425 ) ) ; OR2X1 U434 (.IN2 ( n415 ) , .IN1 ( \transceiver/enable16_counter[7] ) , .Q ( n420 ) ) ; OR2X1 U433 (.IN2 ( n410 ) , .IN1 ( \transceiver/enable16_counter[6] ) , .Q ( n415 ) ) ; OR2X1 U432 (.IN2 ( n405 ) , .IN1 ( \transceiver/enable16_counter[5] ) , .Q ( n410 ) ) ; OR2X1 U431 (.IN2 ( n400 ) , .IN1 ( \transceiver/enable16_counter[4] ) , .Q ( n405 ) ) ; OR4X1 U430 (.IN4 ( \transceiver/enable16_counter[1] ) , .IN2 ( \transceiver/enable16_counter[2] ) , .Q ( n400 ) , .IN1 ( \transceiver/enable16_counter[3] ) , .IN3 ( \transceiver/enable16_counter[0] ) ) ; AO221X1 U429 (.IN5 ( sys_rst ) , .Q ( n235 ) , .IN2 ( csr_di[1] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[1] ) ) ; ISOLANDX1 U572 (.ISO ( n471 ) , .D ( n384 ) , .Q ( n467 ) ) ; NOR2X0 U571 (.QN ( n466 ) , .IN1 ( n471 ) , .IN2 ( n373 ) ) ;


OR2X1 U570 (.IN2 ( n347 ) , .IN1 ( n471 ) , .Q ( n468 ) ) ; OR2X1 U569 (.IN2 ( n471 ) , .IN1 ( n382 ) , .Q ( n465 ) ) ; DFFX1 \transceiver/rx_reg_reg[0] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[0] ) , .D ( n217 ) ) ; DFFX1 \transceiver/rx_reg_reg[1] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[1] ) , .D ( n218 ) ) ; DFFX1 \transceiver/rx_reg_reg[2] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[2] ) , .D ( n219 ) ) ; DFFX1 \transceiver/rx_reg_reg[3] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[3] ) , .D ( n220 ) ) ; DFFX1 \transceiver/rx_reg_reg[4] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[4] ) , .D ( n221 ) ) ; DFFX1 \transceiver/rx_reg_reg[5] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[5] ) , .D ( n222 ) ) ; DFFX1 \transceiver/rx_reg_reg[6] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[6] ) , .D ( n223 ) ) ; DFFX1 \transceiver/rx_reg_reg[7] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[7] ) , .D ( n224 ) ) ; SDFFX1 \transceiver/rx_data_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[3] ) , .D ( n216 ) , .Q ( rx_data[0] ) ) ; SDFFX1 \csr_do_reg[7] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[6] ) , .D ( N87 ) , .Q ( csr_do[7] ) ) ; SDFFX1 \transceiver/rx_data_reg[7] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( rx_data[6] ) , .D ( n209 ) , .Q ( rx_data[7] ) ) ; SDFFX1 \csr_do_reg[6] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[5] ) , .D ( N86 ) , .Q ( csr_do[6] ) ) ; SDFFX1 \transceiver/rx_data_reg[6] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( rx_data[5] ) , .D ( n210 ) , .Q ( rx_data[6] ) ) ; SDFFX1 \csr_do_reg[5] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[4] ) , .D ( N85 ) , .Q ( csr_do[5] ) ) ; SDFFX1 \transceiver/rx_data_reg[5] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[4] ) , .D ( n211 ) , .Q ( rx_data[5] ) ) ; SDFFX1 \csr_do_reg[4] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[3] ) , .D ( N84 ) , .Q ( csr_do[4] ) ) ; SDFFX1 \transceiver/rx_data_reg[4] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[3] ) , .D ( n212 ) , .Q ( rx_data[4] ) ) ; SDFFX1 \csr_do_reg[3] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[2] ) , .D ( N83 ) , .Q ( csr_do[3] ) ) ; SDFFX1 \transceiver/rx_data_reg[3] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[2] ) , .D ( n213 ) , .Q ( rx_data[3] ) ) ; SDFFX1 \csr_do_reg[2] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( csr_do[1] ) , .D ( N82 ) , .Q ( csr_do[2] ) ) ; SDFFX1 \transceiver/rx_data_reg[2] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[1] ) , .D ( n214 ) , .Q ( rx_data[2] ) ) ; SDFFX1 \csr_do_reg[1] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( csr_do[0] )


, .D ( N81 ) , .Q ( csr_do[1] ) ) ; SDFFX1 \transceiver/rx_data_reg[1] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[0] ) , .D ( n215 ) , .Q ( rx_data[1] ) ) ; MUX21X1 U567 (.S ( n109 ) , .IN2 ( n457 ) , .IN1 ( n458 ) , .Q ( n459 ) ) ; MUX21X1 U566 (.S ( n476 ) , .IN2 ( n455 ) , .IN1 ( n456 ) , .Q ( \transceiver/N99 ) ) ; AO21X1 U565 (.IN2 ( n454 ) , .IN1 ( divisor[14] ) , .IN3 ( n453 ) , .Q ( n455 ) ) ; MUX21X1 U564 (.S ( n476 ) , .IN2 ( n448 ) , .IN1 ( n449 ) , .Q ( \transceiver/N98 ) ) ; MUX21X1 U563 (.S ( n447 ) , .IN2 ( n300 ) , .IN1 ( divisor[13] ) , .Q ( n448 ) ) ; MUX21X1 U562 (.S ( n476 ) , .IN2 ( n443 ) , .IN1 ( n444 ) , .Q ( \transceiver/N97 ) ) ; AO21X1 U561 (.IN2 ( n442 ) , .IN1 ( divisor[12] ) , .IN3 ( n447 ) , .Q ( n443 ) ) ; MUX21X1 U560 (.S ( n476 ) , .IN2 ( n438 ) , .IN1 ( n439 ) , .Q ( \transceiver/N96 ) ) ; MUX21X1 U559 (.S ( n437 ) , .IN2 ( n299 ) , .IN1 ( divisor[11] ) , .Q ( n438 ) ) ; MUX21X1 U558 (.S ( n484 ) , .IN2 ( n433 ) , .IN1 ( n434 ) , .Q ( \transceiver/N95 ) ) ; AO21X1 U557 (.IN2 ( n432 ) , .IN1 ( divisor[10] ) , .IN3 ( n437 ) , .Q ( n433 ) ) ; MUX21X1 U556 (.S ( n484 ) , .IN2 ( n428 ) , .IN1 ( n429 ) , .Q ( \transceiver/N94 ) ) ; MUX21X1 U555 (.S ( n427 ) , .IN2 ( n298 ) , .IN1 ( divisor[9] ) , .Q ( n428 ) ) ; MUX21X1 U554 (.S ( n484 ) , .IN2 ( n423 ) , .IN1 ( n424 ) , .Q ( \transceiver/N93 ) ) ; AO21X1 U553 (.IN2 ( n422 ) , .IN1 ( divisor[8] ) , .IN3 ( n427 ) , .Q ( n423 ) ) ; MUX21X1 U552 (.S ( n484 ) , .IN2 ( n418 ) , .IN1 ( n419 ) , .Q ( \transceiver/N92 ) ) ; MUX21X1 U551 (.S ( n417 ) , .IN2 ( n302 ) , .IN1 ( divisor[7] ) , .Q ( n418 ) ) ; MUX21X1 U550 (.S ( n476 ) , .IN2 ( n413 ) , .IN1 ( n414 ) , .Q ( \transceiver/N91 ) ) ; AO21X1 U549 (.IN2 ( n412 ) , .IN1 ( divisor[6] ) , .IN3 ( n417 ) , .Q ( n413 ) ) ; MUX21X1 U548 (.S ( n476 ) , .IN2 ( n408 ) , .IN1 ( n409 ) , .Q ( \transceiver/N90 ) ) ; MUX21X1 U547 (.S ( n407 ) , .IN2 ( n295 ) , .IN1 ( divisor[5] ) , .Q ( n408 ) ) ; MUX21X1 U546 (.S ( n476 ) , .IN2 ( n403 ) , .IN1 ( n404 ) , .Q ( \transceiver/N89 ) ) ; AO21X1 U545 (.IN2 ( n402 ) , .IN1 ( divisor[4] ) , .IN3 ( n407 ) , .Q ( n403 ) ) ; AO221X1 U544 (.IN5 ( n476 ) , .Q ( n398 ) , .IN2 ( n397 ) , .IN1 ( n400 ) , .IN3 ( n400 ) , .IN4 ( n305 ) ) ; AO221X1 U543 (.IN5 ( n395 ) , .Q ( n399 ) , .IN2 ( n396 ) , .IN1 ( n402 ) , .IN3 ( n402 ) , .IN4 ( n294 ) ) ; MUX21X1 U542 (.S ( n476 ) , .IN2 ( n393 ) , .IN1 ( n394 ) , .Q ( \transceiver/N87 ) ) ; AO21X1 U541 (.IN2 ( n392 ) , .IN1 ( divisor[2] ) , .IN3 ( n396 ) , .Q ( n393 ) ) ; AO21X1 U540 (.IN2 ( n391 ) , .IN1 ( \transceiver/enable16_counter[2] )


, .IN3 ( n397 ) , .Q ( n394 ) ) ; NOR2X0 U539 (.QN ( n397 ) , .IN1 ( \transceiver/enable16_counter[2] ) , .IN2 ( n391 ) ) ; OR2X1 U538 (.IN2 ( \transceiver/enable16_counter[1] ) , .IN1 ( \transceiver/enable16_counter[0] ) , .Q ( n391 ) ) ; MUX21X1 U537 (.S ( n476 ) , .IN2 ( n389 ) , .IN1 ( n390 ) , .Q ( \transceiver/N86 ) ) ; MUX21X1 U536 (.S ( \transceiver/enable16_counter[1] ) , .IN2 ( \transceiver/enable16_counter[0] ) , .IN1 ( n306 ) , .Q ( n390 ) ) ; MUX21X1 U535 (.S ( n476 ) , .IN2 ( divisor[0] ) , .IN1 ( \transceiver/enable16_counter[0] ) , .Q ( n387 ) ) ; NOR2X0 U534 (.QN ( \transceiver/N190 ) , .IN1 ( sys_rst ) , .IN2 ( n386 ) ) ; OA222X1 U533 (.IN1 ( n476 ) , .IN5 ( n385 ) , .IN3 ( n476 ) , .IN2 ( \transceiver/enable16_counter[15] ) , .IN4 ( n452 ) , .IN6 ( n395 ) , .Q ( \transceiver/N100 ) ) ; MUX21X1 U532 (.S ( n453 ) , .IN2 ( n301 ) , .IN1 ( divisor[15] ) , .Q ( n385 ) ) ; NOR2X0 U531 (.QN ( n453 ) , .IN1 ( divisor[14] ) , .IN2 ( n454 ) ) ; NOR2X0 U530 (.QN ( n447 ) , .IN1 ( divisor[12] ) , .IN2 ( n442 ) ) ; NOR2X0 U529 (.QN ( n437 ) , .IN1 ( divisor[10] ) , .IN2 ( n432 ) ) ; NOR2X0 U528 (.QN ( n427 ) , .IN1 ( divisor[8] ) , .IN2 ( n422 ) ) ; NOR2X0 U527 (.QN ( n417 ) , .IN1 ( divisor[6] ) , .IN2 ( n412 ) ) ; NOR2X0 U526 (.QN ( n407 ) , .IN1 ( divisor[4] ) , .IN2 ( n402 ) ) ; NOR2X0 U525 (.QN ( n396 ) , .IN1 ( divisor[2] ) , .IN2 ( n392 ) ) ; OR2X1 U524 (.IN2 ( divisor[1] ) , .IN1 ( divisor[0] ) , .Q ( n392 ) ) ; AO222X1 U523 (.Q ( n193 ) , .IN2 ( \transceiver/tx_reg [6] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[6] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [7] ) ) ; AO222X1 U522 (.Q ( n194 ) , .IN2 ( \transceiver/tx_reg [5] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[5] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [6] ) ) ; assign csr_do[16] = 1'b0; endmodule Netlist after Synthesis: // // Milkyway Hierarchical Verilog Dump: // Generated on 04/23/2012 at 11:05:21 // Design Generated by Cell Based Verilog Reader // File produced by Consolidated Verilog Writer // Library Name :assign_3_f1 // Cell Name :cuart // Hierarchy delimiter:'/' //


module cuart (sys_clk , sys_rst , csr_a , csr_we , csr_di , csr_do , rx_irq , tx_irq , uart_rx , uart_tx , Scan_Enable , Test_Mode ); input sys_clk ; input sys_rst ; input [13:0] csr_a ; input csr_we ; input [31:0] csr_di ; output [31:0] csr_do ; output rx_irq ; output tx_irq ; input uart_rx ; output uart_tx ; input Scan_Enable ; input Test_Mode ; wire [15:0] divisor ; wire [7:0] rx_data ; wire [7:0] \transceiver/tx_reg ; assign csr_do[30] = csr_do[16] ; assign csr_do[29] = csr_do[16] ; assign csr_do[28] = csr_do[16] ; assign csr_do[27] = csr_do[16] ; assign csr_do[26] = csr_do[16] ; assign csr_do[25] = csr_do[16] ; assign csr_do[24] = csr_do[16] ; assign csr_do[23] = csr_do[16] ; assign csr_do[22] = csr_do[16] ; assign csr_do[21] = csr_do[16] ; assign csr_do[20] = csr_do[16] ; assign csr_do[19] = csr_do[16] ; assign csr_do[18] = csr_do[16] ; assign csr_do[17] = csr_do[16] ; assign csr_do[31] = csr_do[16] ; INVX32 U323 (.IN ( n496 ) , .QN ( n495 ) ) ; INVX32 U322 (.IN ( n495 ) , .QN ( n494 ) ) ; INVX32 U321 (.IN ( n494 ) , .QN ( n493 ) ) ; INVX32 U320 (.IN ( n493 ) , .QN ( uart_tx ) ) ; NOR4X0 U452 (.IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n115 ) , .IN3 ( \transceiver/rx_bitcount[1] ) , .IN4 ( n114 ) , .QN ( n348 ) ) ; NOR4X0 U442 (.IN2 ( \transceiver/rx_count16[1] ) , .IN1 ( \transceiver/rx_count16[2] ) , .IN3 ( \transceiver/rx_count16[3] ) , .IN4 ( n319 ) , .QN ( n349 ) ) ; INVX2 U318 (.IN ( n487 ) , .QN ( n486 ) ) ;


NAND2X0 U334 (.IN1 ( n352 ) , .IN2 ( n296 ) , .QN ( n319 ) ) ; NAND2X0 U333 (.IN1 ( n475 ) , .IN2 ( n472 ) , .QN ( n353 ) ) ; NOR4X0 U332 (.IN2 ( n346 ) , .IN1 ( n348 ) , .IN3 ( n477 ) , .IN4 ( n344 ) , .QN ( n347 ) ) ; NAND2X0 U331 (.IN1 ( n373 ) , .IN2 ( n353 ) , .QN ( n355 ) ) ; NAND2X0 U330 (.IN1 ( n399 ) , .IN2 ( n398 ) , .QN ( \transceiver/N88 ) ) ; NAND2X0 U329 (.IN1 ( n458 ) , .IN2 ( n360 ) , .QN ( n358 ) ) ; NAND2X0 U328 (.IN1 ( n475 ) , .IN2 ( n375 ) , .QN ( n363 ) ) ; NAND2X0 U327 (.IN1 ( n373 ) , .IN2 ( n372 ) , .QN ( n202 ) ) ; NAND2X0 U326 (.IN1 ( n322 ) , .IN2 ( n321 ) , .QN ( n281 ) ) ; NAND2X0 U325 (.IN1 ( n369 ) , .IN2 ( n368 ) , .QN ( n259 ) ) ; AO22X1 U303 (.IN1 ( n473 ) , .IN3 ( n312 ) , .IN2 ( divisor[0] ) , .Q ( N80 ) , .IN4 ( n253 ) ) ; MUX21X1 U302 (.S ( csr_a[1] ) , .IN2 ( thru ) , .IN1 ( rx_data[0] ) , .Q ( n253 ) ) ; NOR2X0 U301 (.QN ( n285 ) , .IN1 ( n252 ) , .IN2 ( n326 ) ) ; NOR2X0 U300 (.QN ( n252 ) , .IN1 ( n293 ) , .IN2 ( n325 ) ) ; NAND2X0 U299 (.IN1 ( n375 ) , .IN2 ( n251 ) , .QN ( n384 ) ) ; NAND2X0 U298 (.IN1 ( n378 ) , .IN2 ( n374 ) , .QN ( n251 ) ) ; NAND2X0 U297 (.IN1 ( \transceiver/rx_busy ) , .IN2 ( n472 ) , .QN ( n344 ) ) ; NAND2X0 U296 (.IN1 ( n475 ) , .IN2 ( n109 ) , .QN ( n360 ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[1] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/tx_bitcount[0] ) , .D ( n257 ) , .QN ( \transceiver/tx_bitcount[1] ) , .Q ( n464 ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[3] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/tx_bitcount[2] ) , .D ( n259 ) , .QN ( n110 ) , .Q ( n463 ) ) ; SDFFX1 \transceiver/tx_count16_reg[1] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/tx_count16[0] ) , .D ( n459 ) , .Q ( n109 ) ) ; SDFFX1 \transceiver/uart_rx1_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( uart_rx ) , .D ( uart_rx ) , .QN ( n72 ) ) ; SDFFX1 \transceiver/tx_count16_reg[2] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( n109 ) , .D ( n263 ) , .QN ( n297 ) , .Q ( \transceiver/tx_count16[2] ) ) ; SDFFX1 \divisor_reg[3] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[2] ) , .D ( n265 ) , .QN ( n294 ) , .Q ( divisor[3] ) ) ; SDFFX1 \divisor_reg[7] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[6] ) , .D ( n267 ) , .QN ( n302 ) , .Q ( divisor[7] ) ) ; SDFFX1 \divisor_reg[5] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[4] ) , .D ( n269 ) , .QN ( n295 ) , .Q ( divisor[5] ) ) ; SDFFX1 \transceiver/rx_count16_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_busy ) , .D ( n271 ) , .QN ( n296 ) , .Q ( \transceiver/rx_count16[0] ) ) ; SDFFX1 \divisor_reg[9] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[8] ) , .D ( n273 ) , .QN ( n298 ) , .Q ( divisor[9] ) ) ; SDFFX1 \divisor_reg[11] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[10] ) , .D ( n275 ) , .QN ( n299 ) , .Q ( divisor[11] ) ) ;


SDFFX1 \divisor_reg[13] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[12] ) , .D ( n277 ) , .QN ( n300 ) , .Q ( divisor[13] ) ) ; SDFFX1 \divisor_reg[15] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[14] ) , .D ( n279 ) , .QN ( n301 ) , .Q ( divisor[15] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[3] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_bitcount[2] ) , .D ( n281 ) , .QN ( n115 ) , .Q ( n304 ) ) ; SDFFX1 \transceiver/rx_count16_reg[3] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[2] ) , .D ( n283 ) , .QN ( n307 ) , .Q ( \transceiver/rx_count16[3] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/enable16_counter[15] ) , .D ( n285 ) , .QN ( n114 ) , .Q ( n293 ) ) ; SDFFX1 \transceiver/enable16_counter_reg[3] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[2] ) , .D ( \transceiver/N88 ) , .QN ( n305 ) , .Q ( \transceiver/enable16_counter[3] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[0] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( thru ) , .D ( n387 ) , .QN ( \transceiver/enable16_counter[0] ) , .Q ( n306 ) ) ; SDFFX1 \transceiver/rx_busy_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( n304 ) , .D ( n289 ) , .QN ( n292 ) , .Q ( \transceiver/rx_busy ) ) ; DFFX1 \transceiver/uart_rx2_reg (.CLK ( sys_clk ) , .QN ( \transceiver/uart_rx2 ) , .Q ( n303 ) , .D ( n72 ) ) ; DFFX1 \transceiver/tx_reg_reg[0] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [0] ) , .D ( n200 ) ) ; DFFX1 \transceiver/tx_reg_reg[1] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [1] ) , .D ( n198 ) ) ; DFFX1 \transceiver/tx_reg_reg[2] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [2] ) , .D ( n197 ) ) ; DFFX1 \transceiver/tx_reg_reg[3] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [3] ) , .D ( n196 ) ) ; DFFX1 \transceiver/tx_reg_reg[4] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [4] ) , .D ( n195 ) ) ; DFFX1 \transceiver/tx_reg_reg[5] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [5] ) , .D ( n194 ) ) ; DFFX1 \transceiver/tx_reg_reg[6] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [6] ) , .D ( n193 ) ) ; SDFFX1 \transceiver/enable16_counter_reg[1] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( n306 ) , .D ( \transceiver/N86 ) , .Q ( \transceiver/enable16_counter[1] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[2] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[1] ) , .D ( \transceiver/N87 ) , .Q ( \transceiver/enable16_counter[2] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[4] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[3] ) , .D ( \transceiver/N89 ) , .Q ( \transceiver/enable16_counter[4] ) ) ;


SDFFX1 \transceiver/enable16_counter_reg[5] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[4] ) , .D ( \transceiver/N90 ) , .Q ( \transceiver/enable16_counter[5] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[6] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[5] ) , .D ( \transceiver/N91 ) , .Q ( \transceiver/enable16_counter[6] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[7] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[6] ) , .D ( \transceiver/N92 ) , .Q ( \transceiver/enable16_counter[7] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[8] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[7] ) , .D ( \transceiver/N93 ) , .Q ( \transceiver/enable16_counter[8] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[9] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[8] ) , .D ( \transceiver/N94 ) , .Q ( \transceiver/enable16_counter[9] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[10] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[9] ) , .D ( \transceiver/N95 ) , .Q ( \transceiver/enable16_counter[10] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[11] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[10] ) , .D ( \transceiver/N96 ) , .Q ( \transceiver/enable16_counter[11] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[12] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[11] ) , .D ( \transceiver/N97 ) , .Q ( \transceiver/enable16_counter[12] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[13] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[12] ) , .D ( \transceiver/N98 ) , .Q ( \transceiver/enable16_counter[13] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[14] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[13] ) , .D ( \transceiver/N99 ) , .Q ( \transceiver/enable16_counter[14] ) ) ; SDFFX1 \transceiver/uart_tx_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_count16[3] ) , .D ( n199 ) , .Q ( uart_tx_transceiver ) ) ; SDFFX1 \transceiver/tx_busy_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( n463 ) , .D ( n202 ) , .Q ( \transceiver/tx_busy ) ) ; SDFFX1 \transceiver/tx_done_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( uart_tx_transceiver ) , .D ( \transceiver/N190 ) , .Q ( tx_irq ) ) ; SDFFX1 \transceiver/tx_reg_reg[7] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/rx_reg[0] ) , .D ( n201 ) , .Q ( \transceiver/tx_reg [7] ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[2] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( n464 ) , .D ( n204 ) , .Q ( \transceiver/tx_bitcount[2] ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( rx_irq ) , .D ( n205 ) , .Q ( \transceiver/tx_bitcount[0] ) ) ; SDFFX1 \transceiver/tx_count16_reg[3] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_count16[2] ) , .D ( n206 ) , .Q ( \transceiver/tx_count16[3] ) ) ;


SDFFX1 \transceiver/tx_count16_reg[0] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_busy ) , .D ( n208 ) , .Q ( \transceiver/tx_count16[0] ) ) ; SDFFX1 \transceiver/rx_count16_reg[2] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[1] ) , .D ( n226 ) , .Q ( \transceiver/rx_count16[2] ) ) ; SDFFX1 \transceiver/rx_count16_reg[1] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[0] ) , .D ( n227 ) , .Q ( \transceiver/rx_count16[1] ) ) ; SDFFX1 \csr_do_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/tx_reg [0] ) , .D ( N80 ) , .Q ( csr_do[0] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[2] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/rx_bitcount[1] ) , .D ( n229 ) , .Q ( \transceiver/rx_bitcount[2] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[1] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( n293 ) , .D ( n230 ) , .Q ( \transceiver/rx_bitcount[1] ) ) ; SDFFX1 \transceiver/rx_done_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( rx_data[7] ) , .D ( \transceiver/N137 ) , .Q ( rx_irq ) ) ; SDFFX1 \transceiver/enable16_counter_reg[15] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[14] ) , .D ( \transceiver/N100 ) , .Q ( \transceiver/enable16_counter[15] ) ) ; SDFFX1 \csr_do_reg[8] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[7] ) , .D ( N88 ) , .Q ( csr_do[8] ) ) ; SDFFX1 \csr_do_reg[9] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[8] ) , .D ( N89 ) , .Q ( csr_do[9] ) ) ; SDFFX1 \csr_do_reg[10] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[9] ) , .D ( N90 ) , .Q ( csr_do[10] ) ) ; SDFFX1 \csr_do_reg[11] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[10] ) , .D ( N91 ) , .Q ( csr_do[11] ) ) ; SDFFX1 \csr_do_reg[12] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[11] ) , .D ( N92 ) , .Q ( csr_do[12] ) ) ; SDFFX1 \csr_do_reg[13] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[12] ) , .D ( N93 ) , .Q ( csr_do[13] ) ) ; SDFFX1 \csr_do_reg[14] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[13] ) , .D ( N94 ) , .Q ( csr_do[14] ) ) ; SDFFX1 \csr_do_reg[15] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( csr_do[14] ) , .D ( N95 ) , .Q ( csr_do[15] ) ) ; SDFFX1 \divisor_reg[0] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[15] ) , .D ( n234 ) , .Q ( divisor[0] ) ) ; SDFFX1 \divisor_reg[1] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[0] ) , .D ( n235 ) , .Q ( divisor[1] ) ) ; SDFFX1 \divisor_reg[2] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[1] ) , .D ( n236 ) , .Q ( divisor[2] ) ) ; SDFFX1 \divisor_reg[4] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[3] ) , .D ( n238 ) , .Q ( divisor[4] ) ) ;


SDFFX1 \divisor_reg[6] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[5] ) , .D ( n240 ) , .Q ( divisor[6] ) ) ; SDFFX1 \divisor_reg[8] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[7] ) , .D ( n242 ) , .Q ( divisor[8] ) ) ; SDFFX1 \divisor_reg[10] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[9] ) , .D ( n244 ) , .Q ( divisor[10] ) ) ; SDFFX1 \divisor_reg[12] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[11] ) , .D ( n246 ) , .Q ( divisor[12] ) ) ; SDFFX1 \divisor_reg[14] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( divisor[13] ) , .D ( n248 ) , .Q ( divisor[14] ) ) ; SDFFX1 thru_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( divisor[15] ) , .D ( n250 ) , .Q ( thru ) ) ; AO221X1 U428 (.IN5 ( sys_rst ) , .Q ( n236 ) , .IN2 ( csr_di[2] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[2] ) ) ; AO221X1 U427 (.IN5 ( sys_rst ) , .Q ( n238 ) , .IN2 ( csr_di[4] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[4] ) ) ; AO221X1 U426 (.IN5 ( sys_rst ) , .Q ( n269 ) , .IN2 ( csr_di[5] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[5] ) ) ; AO22X1 U424 (.IN1 ( divisor[8] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n242 ) , .IN4 ( csr_di[8] ) ) ; AO22X1 U423 (.IN1 ( divisor[9] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n273 ) , .IN4 ( csr_di[9] ) ) ; AO22X1 U422 (.IN1 ( divisor[10] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n244 ) , .IN4 ( csr_di[10] ) ) ; AO22X1 U421 (.IN1 ( divisor[11] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n275 ) , .IN4 ( csr_di[11] ) ) ; AO22X1 U420 (.IN1 ( divisor[12] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n246 ) , .IN4 ( csr_di[12] ) ) ; AO22X1 U419 (.IN1 ( divisor[13] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n277 ) , .IN4 ( csr_di[13] ) ) ; AO22X1 U418 (.IN1 ( divisor[14] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n248 ) , .IN4 ( csr_di[14] ) ) ; AO22X1 U417 (.IN1 ( divisor[15] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n279 ) , .IN4 ( csr_di[15] ) ) ; INVX0 U416 (.QN ( n315 ) , .IN ( csr_a[0] ) ) ; MUX21X1 U415 (.S ( n313 ) , .IN2 ( thru ) , .IN1 ( csr_di[0] ) , .Q ( n250 ) ) ; NAND3X0 U414 (.QN ( n313 ) , .IN3 ( n312 ) , .IN2 ( csr_we ) , .IN1 ( csr_a[1] ) ) ; NOR2X0 U413 (.QN ( N95 ) , .IN1 ( n301 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U412 (.ISO ( n311 ) , .D ( divisor[14] ) , .Q ( N94 ) ) ; NOR2X0 U411 (.QN ( N93 ) , .IN1 ( n300 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U410 (.ISO ( n311 ) , .D ( divisor[12] ) , .Q ( N92 ) ) ; NOR2X0 U409 (.QN ( N91 ) , .IN1 ( n299 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U408 (.ISO ( n311 ) , .D ( divisor[10] ) , .Q ( N90 ) ) ; NOR2X0 U407 (.QN ( N89 ) , .IN1 ( n298 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U406 (.ISO ( n311 ) , .D ( divisor[8] ) , .Q ( N88 ) ) ;


AO22X1 U405 (.IN1 ( rx_data[7] ) , .IN3 ( divisor[7] ) , .IN2 ( n310 ) , .Q ( N87 ) , .IN4 ( n473 ) ) ; AO22X1 U404 (.IN1 ( rx_data[6] ) , .IN3 ( divisor[6] ) , .IN2 ( n310 ) , .Q ( N86 ) , .IN4 ( n473 ) ) ; AO22X1 U403 (.IN1 ( rx_data[5] ) , .IN3 ( divisor[5] ) , .IN2 ( n310 ) , .Q ( N85 ) , .IN4 ( n473 ) ) ; AO22X1 U402 (.IN1 ( rx_data[4] ) , .IN3 ( divisor[4] ) , .IN2 ( n310 ) , .Q ( N84 ) , .IN4 ( n473 ) ) ; AO22X1 U401 (.IN1 ( rx_data[3] ) , .IN3 ( divisor[3] ) , .IN2 ( n310 ) , .Q ( N83 ) , .IN4 ( n473 ) ) ; AO22X1 U400 (.IN1 ( rx_data[2] ) , .IN3 ( divisor[2] ) , .IN2 ( n310 ) , .Q ( N82 ) , .IN4 ( n473 ) ) ; AO22X1 U399 (.IN1 ( rx_data[1] ) , .IN3 ( divisor[1] ) , .IN2 ( n310 ) , .Q ( N81 ) , .IN4 ( n473 ) ) ; NOR3X0 U398 (.IN2 ( sys_rst ) , .QN ( n312 ) , .IN1 ( csr_a[0] ) , .IN3 ( n308 ) ) ; NAND3X0 U396 (.QN ( n311 ) , .IN3 ( n472 ) , .IN2 ( csr_a[0] ) , .IN1 ( n314 ) ) ; OR4X1 U395 (.IN4 ( csr_a[13] ) , .IN2 ( csr_a[11] ) , .Q ( n308 ) , .IN1 ( csr_a[10] ) , .IN3 ( csr_a[12] ) ) ; MUX21X1 U393 (.S ( thru ) , .IN2 ( uart_rx ) , .IN1 ( uart_tx_transceiver ) , .Q ( n460 ) ) ; NAND2X0 U392 (.IN2 ( n314 ) , .IN1 ( csr_we ) , .QN ( n351 ) ) ; INVX0 U391 (.QN ( n374 ) , .IN ( n361 ) ) ; INVX0 U390 (.QN ( n383 ) , .IN ( n373 ) ) ; AO22X1 U389 (.IN1 ( csr_di[3] ) , .IN3 ( divisor[3] ) , .IN2 ( n318 ) , .Q ( n265 ) , .IN4 ( n317 ) ) ; AO22X1 U388 (.IN1 ( csr_di[7] ) , .IN3 ( divisor[7] ) , .IN2 ( n318 ) , .Q ( n267 ) , .IN4 ( n317 ) ) ; AO22X1 U387 (.IN1 ( csr_di[0] ) , .IN3 ( divisor[0] ) , .IN2 ( n318 ) , .Q ( n234 ) , .IN4 ( n317 ) ) ; AO22X1 U386 (.IN1 ( csr_di[6] ) , .IN3 ( divisor[6] ) , .IN2 ( n318 ) , .Q ( n240 ) , .IN4 ( n317 ) ) ; INVX0 U385 (.QN ( n350 ) , .IN ( n344 ) ) ; ISOLANDX1 U384 (.ISO ( csr_a[1] ) , .D ( n312 ) , .Q ( n310 ) ) ; NAND2X0 U383 (.IN1 ( divisor[0] ) , .IN2 ( divisor[1] ) , .QN ( n388 ) ) ; NOR2X0 U382 (.QN ( n382 ) , .IN1 ( n376 ) , .IN2 ( n384 ) ) ; AND4X1 U381 (.IN1 ( n350 ) , .IN2 ( n349 ) , .IN3 ( \transceiver/uart_rx2 ) , .IN4 ( n348 ) , .Q ( \transceiver/N137 ) ) ; NAND2X0 U380 (.IN1 ( \transceiver/tx_bitcount[1] ) , .IN2 ( \transceiver/tx_bitcount[0] ) , .QN ( n364 ) ) ; NOR2X0 U379 (.QN ( n337 ) , .IN1 ( sys_rst ) , .IN2 ( n343 ) ) ; NOR2X0 U378 (.QN ( n314 ) , .IN1 ( csr_a[1] ) , .IN2 ( n308 ) ) ; NOR2X0 U377 (.QN ( n352 ) , .IN1 ( \transceiver/enable16_counter[15] ) , .IN2 ( n452 ) ) ; NOR2X0 U376 (.QN ( n375 ) , .IN1 ( sys_rst ) , .IN2 ( n381 ) ) ;


OA21X1 U375 (.IN2 ( n351 ) , .IN3 ( n472 ) , .IN1 ( n315 ) , .Q ( n317 ) ) ; NOR2X0 U373 (.QN ( n395 ) , .IN1 ( n352 ) , .IN2 ( sys_rst ) ) ; NOR2X1 U372 (.QN ( n318 ) , .IN1 ( sys_rst ) , .IN2 ( n317 ) ) ; NOR2X0 U371 (.QN ( n361 ) , .IN1 ( csr_a[0] ) , .IN2 ( n351 ) ) ; NAND2X0 U370 (.IN1 ( n374 ) , .IN2 ( \transceiver/tx_count16[0] ) , .QN ( n354 ) ) ; NAND2X0 U369 (.IN1 ( n332 ) , .IN2 ( n476 ) , .QN ( n343 ) ) ; NAND2X0 U366 (.IN1 ( \transceiver/rx_count16[0] ) , .IN2 ( \transceiver/rx_count16[1] ) , .QN ( n338 ) ) ; NAND2X0 U365 (.IN1 ( n392 ) , .IN2 ( n388 ) , .QN ( n389 ) ) ; NAND2X0 U364 (.IN1 ( \transceiver/enable16_counter[4] ) , .IN2 ( n400 ) , .QN ( n401 ) ) ; NAND2X0 U363 (.IN1 ( \transceiver/enable16_counter[5] ) , .IN2 ( n405 ) , .QN ( n406 ) ) ; NAND2X0 U362 (.IN1 ( n405 ) , .IN2 ( n401 ) , .QN ( n404 ) ) ; NAND2X0 U361 (.IN1 ( n396 ) , .IN2 ( n294 ) , .QN ( n402 ) ) ; NAND2X0 U360 (.IN1 ( \transceiver/rx_count16[2] ) , .IN2 ( n339 ) , .QN ( n340 ) ) ; NAND2X0 U359 (.IN1 ( n472 ) , .IN2 ( n361 ) , .QN ( n373 ) ) ; NAND2X0 U358 (.IN1 ( \transceiver/enable16_counter[6] ) , .IN2 ( n410 ) , .QN ( n411 ) ) ; NAND2X0 U357 (.IN1 ( n410 ) , .IN2 ( n406 ) , .QN ( n409 ) ) ; NAND2X0 U356 (.IN1 ( n415 ) , .IN2 ( n411 ) , .QN ( n414 ) ) ; NAND2X0 U355 (.IN1 ( \transceiver/enable16_counter[7] ) , .IN2 ( n415 ) , .QN ( n416 ) ) ; NAND2X0 U354 (.IN1 ( n407 ) , .IN2 ( n295 ) , .QN ( n412 ) ) ; NAND2X0 U353 (.IN1 ( n420 ) , .IN2 ( n416 ) , .QN ( n419 ) ) ; NAND2X0 U352 (.IN1 ( \transceiver/enable16_counter[8] ) , .IN2 ( n420 ) , .QN ( n421 ) ) ; NAND2X0 U351 (.IN1 ( n417 ) , .IN2 ( n302 ) , .QN ( n422 ) ) ; NAND2X0 U350 (.IN1 ( n425 ) , .IN2 ( n421 ) , .QN ( n424 ) ) ; NAND2X0 U349 (.IN1 ( \transceiver/enable16_counter[9] ) , .IN2 ( n425 ) , .QN ( n426 ) ) ; NAND2X0 U348 (.IN1 ( \transceiver/enable16_counter[10] ) , .IN2 ( n430 ) , .QN ( n431 ) ) ; NAND2X0 U347 (.IN1 ( n430 ) , .IN2 ( n426 ) , .QN ( n429 ) ) ; NAND2X0 U346 (.IN1 ( n427 ) , .IN2 ( n298 ) , .QN ( n432 ) ) ; NAND2X0 U345 (.IN1 ( n435 ) , .IN2 ( n431 ) , .QN ( n434 ) ) ; NAND2X0 U344 (.IN1 ( \transceiver/enable16_counter[11] ) , .IN2 ( n435 ) , .QN ( n436 ) ) ; NAND2X0 U343 (.IN1 ( n440 ) , .IN2 ( n436 ) , .QN ( n439 ) ) ; NAND2X0 U342 (.IN1 ( \transceiver/enable16_counter[12] ) , .IN2 ( n440 ) , .QN ( n441 ) ) ;


NAND2X0 U341 (.IN1 ( \transceiver/enable16_counter[13] ) , .IN2 ( n445 ) , .QN ( n446 ) ) ; NAND2X0 U340 (.IN1 ( n437 ) , .IN2 ( n299 ) , .QN ( n442 ) ) ; NAND2X0 U339 (.IN1 ( n445 ) , .IN2 ( n441 ) , .QN ( n444 ) ) ; NAND2X0 U338 (.IN1 ( \transceiver/enable16_counter[14] ) , .IN2 ( n450 ) , .QN ( n451 ) ) ; NAND2X0 U337 (.IN1 ( n450 ) , .IN2 ( n446 ) , .QN ( n449 ) ) ; NAND2X0 U336 (.IN1 ( n447 ) , .IN2 ( n300 ) , .QN ( n454 ) ) ; NAND2X0 U335 (.IN1 ( n452 ) , .IN2 ( n451 ) , .QN ( n456 ) ) ; AO222X1 U521 (.Q ( n195 ) , .IN2 ( \transceiver/tx_reg [4] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[4] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [5] ) ) ; AO222X1 U520 (.Q ( n196 ) , .IN2 ( \transceiver/tx_reg [3] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[3] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [4] ) ) ; AO222X1 U519 (.Q ( n197 ) , .IN2 ( \transceiver/tx_reg [2] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[2] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [3] ) ) ; AO222X1 U518 (.Q ( n198 ) , .IN2 ( \transceiver/tx_reg [1] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[1] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [2] ) ) ; AO221X1 U517 (.IN5 ( sys_rst ) , .Q ( n199 ) , .IN2 ( uart_tx_transceiver ) , .IN1 ( n381 ) , .IN3 ( n380 ) , .IN4 ( n379 ) ) ; OA21X1 U516 (.IN2 ( \transceiver/tx_reg [0] ) , .IN3 ( n475 ) , .IN1 ( n378 ) , .Q ( n379 ) ) ; INVX0 U515 (.QN ( n380 ) , .IN ( n381 ) ) ; AO222X1 U514 (.Q ( n200 ) , .IN2 ( \transceiver/tx_reg [0] ) , .IN1 ( n467 ) , .IN3 ( n465 ) , .IN4 ( \transceiver/tx_reg [1] ) , .IN6 ( csr_di[0] ) , .IN5 ( n466 ) ) ; AO22X1 U513 (.IN1 ( csr_di[7] ) , .IN3 ( \transceiver/tx_reg [7] ) , .IN2 ( n383 ) , .Q ( n201 ) , .IN4 ( n384 ) ) ; NAND3X0 U512 (.QN ( n372 ) , .IN3 ( n386 ) , .IN2 ( n472 ) , .IN1 ( \transceiver/tx_busy ) ) ; NAND3X0 U511 (.QN ( n386 ) , .IN3 ( n378 ) , .IN2 ( \transceiver/tx_bitcount[0] ) , .IN1 ( n370 ) ) ; NOR3X0 U510 (.IN2 ( n110 ) , .QN ( n378 ) , .IN1 ( \transceiver/tx_bitcount[2] ) , .IN3 ( \transceiver/tx_bitcount[1] ) ) ; AO221X1 U509 (.IN5 ( n110 ) , .Q ( n368 ) , .IN2 ( \transceiver/tx_bitcount[2] ) , .IN1 ( n367 ) , .IN3 ( n367 ) , .IN4 ( n376 ) ) ; NAND3X0 U508 (.QN ( n369 ) , .IN3 ( \transceiver/tx_bitcount[2] ) , .IN2 ( n110 ) , .IN1 ( n366 ) ) ; MUX21X1 U507 (.S ( \transceiver/tx_bitcount[2] ) , .IN2 ( n365 ) , .IN1 ( n366 ) , .Q ( n204 ) ) ;


NOR2X0 U506 (.QN ( n366 ) , .IN1 ( n364 ) , .IN2 ( n363 ) ) ; OAI221X1 U505 (.IN2 ( n375 ) , .QN ( n257 ) , .IN5 ( n365 ) , .IN4 ( \transceiver/tx_bitcount[0] ) , .IN3 ( \transceiver/tx_bitcount[1] ) , .IN1 ( \transceiver/tx_bitcount[1] ) ) ; INVX0 U504 (.QN ( n365 ) , .IN ( n367 ) ) ; OA221X1 U503 (.IN2 ( \transceiver/tx_bitcount[1] ) , .IN4 ( \transceiver/tx_bitcount[0] ) , .Q ( n367 ) , .IN5 ( n375 ) , .IN1 ( n376 ) , .IN3 ( n376 ) ) ; INVX0 U502 (.QN ( n205 ) , .IN ( n362 ) ) ; MUX21X1 U501 (.S ( \transceiver/tx_bitcount[0] ) , .IN2 ( n375 ) , .IN1 ( n363 ) , .Q ( n362 ) ) ; NOR2X0 U500 (.QN ( n381 ) , .IN1 ( n361 ) , .IN2 ( n370 ) ) ; NOR4X0 U499 (.IN2 ( \transceiver/tx_count16[3] ) , .IN1 ( \transceiver/tx_count16[0] ) , .IN3 ( \transceiver/tx_count16[2] ) , .IN4 ( n360 ) , .QN ( n370 ) ) ; AO221X1 U498 (.IN5 ( n357 ) , .Q ( n206 ) , .IN2 ( n359 ) , .IN1 ( \transceiver/tx_count16[3] ) , .IN3 ( \transceiver/tx_count16[3] ) , .IN4 ( n358 ) ) ; NOR4X0 U497 (.IN2 ( \transceiver/tx_count16[3] ) , .IN1 ( n109 ) , .IN3 ( n297 ) , .IN4 ( n457 ) , .QN ( n357 ) ) ; NOR2X0 U496 (.QN ( n359 ) , .IN1 ( \transceiver/tx_count16[2] ) , .IN2 ( n376 ) ) ; MUX21X1 U495 (.S ( n297 ) , .IN2 ( n356 ) , .IN1 ( n358 ) , .Q ( n263 ) ) ; NOR2X0 U494 (.QN ( n356 ) , .IN1 ( n109 ) , .IN2 ( n457 ) ) ; NAND3X0 U493 (.QN ( n457 ) , .IN3 ( n472 ) , .IN2 ( \transceiver/tx_count16[0] ) , .IN1 ( n475 ) ) ; OA21X1 U492 (.IN2 ( n376 ) , .IN3 ( n355 ) , .IN1 ( \transceiver/tx_count16[0] ) , .Q ( n458 ) ) ; MUX21X1 U491 (.S ( n355 ) , .IN2 ( n354 ) , .IN1 ( \transceiver/tx_count16[0] ) , .Q ( n208 ) ) ; NAND3X0 U489 (.QN ( n376 ) , .IN3 ( n374 ) , .IN2 ( \transceiver/tx_busy ) , .IN1 ( n352 ) ) ; MUX21X1 U488 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[7] ) , .IN1 ( rx_data[7] ) , .Q ( n209 ) ) ; MUX21X1 U487 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[6] ) , .IN1 ( rx_data[6] ) , .Q ( n210 ) ) ; MUX21X1 U486 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[5] ) , .IN1 ( rx_data[5] ) , .Q ( n211 ) ) ; MUX21X1 U485 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[4] ) , .IN1 ( rx_data[4] ) , .Q ( n212 ) ) ; MUX21X1 U484 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[3] ) , .IN1 ( rx_data[3] ) , .Q ( n213 ) ) ; MUX21X1 U483 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[2] )


, .IN1 ( rx_data[2] ) , .Q ( n214 ) ) ; MUX21X1 U482 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[1] ) , .IN1 ( rx_data[1] ) , .Q ( n215 ) ) ; MUX21X1 U481 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[0] ) , .IN1 ( rx_data[0] ) , .Q ( n216 ) ) ; MUX21X1 U480 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[1] ) , .IN1 ( \transceiver/rx_reg[0] ) , .Q ( n217 ) ) ; MUX21X1 U479 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[2] ) , .IN1 ( \transceiver/rx_reg[1] ) , .Q ( n218 ) ) ; MUX21X1 U478 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[3] ) , .IN1 ( \transceiver/rx_reg[2] ) , .Q ( n219 ) ) ; MUX21X1 U477 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[4] ) , .IN1 ( \transceiver/rx_reg[3] ) , .Q ( n220 ) ) ; MUX21X1 U476 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[5] ) , .IN1 ( \transceiver/rx_reg[4] ) , .Q ( n221 ) ) ; MUX21X1 U475 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[6] ) , .IN1 ( \transceiver/rx_reg[5] ) , .Q ( n222 ) ) ; MUX21X1 U474 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[7] ) , .IN1 ( \transceiver/rx_reg[6] ) , .Q ( n223 ) ) ; MUX21X1 U473 (.S ( n468 ) , .IN2 ( \transceiver/uart_rx2 ) , .IN1 ( \transceiver/rx_reg[7] ) , .Q ( n224 ) ) ; OA22X1 U471 (.IN2 ( n342 ) , .IN4 ( n341 ) , .IN1 ( n343 ) , .IN3 ( \transceiver/rx_count16[3] ) , .Q ( n283 ) ) ; NOR2X0 U470 (.QN ( n341 ) , .IN1 ( n343 ) , .IN2 ( n340 ) ) ; OA21X1 U469 (.IN2 ( n307 ) , .IN3 ( n350 ) , .IN1 ( n340 ) , .Q ( n342 ) ) ; INVX0 U468 (.QN ( n339 ) , .IN ( n338 ) ) ; AO221X1 U467 (.IN5 ( n335 ) , .Q ( n226 ) , .IN2 ( n336 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) ) ; OA221X1 U466 (.IN2 ( n472 ) , .IN4 ( n338 ) , .Q ( n335 ) , .IN5 ( \transceiver/rx_count16[2] ) , .IN1 ( n343 ) , .IN3 ( n343 ) ) ; NOR2X0 U465 (.QN ( n336 ) , .IN1 ( \transceiver/rx_count16[2] ) , .IN2 ( n338 ) ) ; AO221X1 U464 (.IN5 ( n333 ) , .Q ( n227 ) , .IN2 ( n334 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) ) ; OA221X1 U463 (.IN2 ( n472 ) , .IN4 ( n296 ) , .Q ( n333 ) , .IN5 ( \transceiver/rx_count16[1] ) , .IN1 ( n343 ) , .IN3 ( n343 ) ) ; NOR2X0 U462 (.QN ( n334 ) , .IN1 ( \transceiver/rx_count16[1] ) , .IN2 ( n296 ) ) ; AO222X1 U461 (.Q ( n271 ) , .IN2 ( n296 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) , .IN6 ( n343 ) , .IN5 ( \transceiver/rx_count16[0] ) ) ; NAND3X0 U460 (.QN ( n332 ) , .IN3 ( n472 ) , .IN2 ( n292 ) , .IN1 ( \transceiver/uart_rx2 ) ) ; MUX21X1 U459 (.S ( \transceiver/rx_bitcount[2] ) , .IN2 ( n330 ) , .IN1 ( n331 ) , .Q ( n229 ) ) ;


INVX0 U458 (.QN ( n330 ) , .IN ( n329 ) ) ; INVX0 U457 (.QN ( n230 ) , .IN ( n328 ) ) ; MUX21X1 U456 (.S ( \transceiver/rx_bitcount[1] ) , .IN2 ( n326 ) , .IN1 ( n327 ) , .Q ( n328 ) ) ; OAI22X1 U455 (.IN3 ( n323 ) , .QN ( n289 ) , .IN1 ( sys_rst ) , .IN4 ( n344 ) , .IN2 ( n324 ) ) ; OA221X1 U454 (.IN2 ( n346 ) , .IN4 ( \transceiver/uart_rx2 ) , .Q ( n323 ) , .IN5 ( n349 ) , .IN1 ( n348 ) , .IN3 ( n348 ) ) ; NOR4X0 U453 (.IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( \transceiver/rx_bitcount[1] ) , .IN3 ( n304 ) , .IN4 ( n293 ) , .QN ( n346 ) ) ; AO221X1 U451 (.IN5 ( n115 ) , .Q ( n321 ) , .IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n329 ) , .IN3 ( n329 ) , .IN4 ( n344 ) ) ; OA21X1 U450 (.IN2 ( n344 ) , .IN3 ( n326 ) , .IN1 ( \transceiver/rx_bitcount[1] ) , .Q ( n329 ) ) ; OA21X1 U449 (.IN2 ( n344 ) , .IN3 ( n325 ) , .IN1 ( n293 ) , .Q ( n326 ) ) ; NAND3X0 U448 (.QN ( n325 ) , .IN3 ( n320 ) , .IN2 ( n324 ) , .IN1 ( n472 ) ) ; NAND2X0 U447 (.IN1 ( n349 ) , .IN2 ( \transceiver/rx_busy ) , .QN ( n320 ) ) ; NAND3X0 U446 (.QN ( n324 ) , .IN3 ( n303 ) , .IN2 ( n292 ) , .IN1 ( n352 ) ) ; NAND3X0 U445 (.QN ( n322 ) , .IN3 ( n115 ) , .IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n331 ) ) ; ISOLANDX1 U444 (.ISO ( n327 ) , .D ( \transceiver/rx_bitcount[1] ) , .Q ( n331 ) ) ; NAND4X0 U443 (.IN1 ( \transceiver/rx_busy ) , .QN ( n327 ) , .IN2 ( n349 ) , .IN3 ( n472 ) , .IN4 ( n293 ) ) ; OR2X1 U441 (.IN2 ( n450 ) , .IN1 ( \transceiver/enable16_counter[14] ) , .Q ( n452 ) ) ; OR2X1 U440 (.IN2 ( n445 ) , .IN1 ( \transceiver/enable16_counter[13] ) , .Q ( n450 ) ) ; OR2X1 U439 (.IN2 ( n440 ) , .IN1 ( \transceiver/enable16_counter[12] ) , .Q ( n445 ) ) ; OR2X1 U438 (.IN2 ( n435 ) , .IN1 ( \transceiver/enable16_counter[11] ) , .Q ( n440 ) ) ; OR2X1 U437 (.IN2 ( n430 ) , .IN1 ( \transceiver/enable16_counter[10] ) , .Q ( n435 ) ) ; OR2X1 U436 (.IN2 ( n425 ) , .IN1 ( \transceiver/enable16_counter[9] ) , .Q ( n430 ) ) ; OR2X1 U435 (.IN2 ( n420 ) , .IN1 ( \transceiver/enable16_counter[8] ) , .Q ( n425 ) ) ; OR2X1 U434 (.IN2 ( n415 ) , .IN1 ( \transceiver/enable16_counter[7] ) , .Q ( n420 ) ) ; OR2X1 U433 (.IN2 ( n410 ) , .IN1 ( \transceiver/enable16_counter[6] ) , .Q ( n415 ) ) ; OR2X1 U432 (.IN2 ( n405 ) , .IN1 ( \transceiver/enable16_counter[5] )


, .Q ( n410 ) ) ; OR2X1 U431 (.IN2 ( n400 ) , .IN1 ( \transceiver/enable16_counter[4] ) , .Q ( n405 ) ) ; OR4X1 U430 (.IN4 ( \transceiver/enable16_counter[1] ) , .IN2 ( \transceiver/enable16_counter[2] ) , .Q ( n400 ) , .IN1 ( \transceiver/enable16_counter[3] ) , .IN3 ( \transceiver/enable16_counter[0] ) ) ; AO221X1 U429 (.IN5 ( sys_rst ) , .Q ( n235 ) , .IN2 ( csr_di[1] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[1] ) ) ; INVX0 U307 (.QN ( n473 ) , .IN ( n311 ) ) ; INVX0 U308 (.QN ( n474 ) , .IN ( n317 ) ) ; INVX0 U309 (.QN ( n475 ) , .IN ( n376 ) ) ; INVX2 U310 (.IN ( n395 ) , .QN ( n476 ) ) ; INVX0 U311 (.QN ( n477 ) , .IN ( n349 ) ) ; NBUFFX2 U305 (.IN ( Scan_Enable ) , .Q ( n471 ) ) ; INVX0 U306 (.QN ( n472 ) , .IN ( sys_rst ) ) ; NBUFFX2 U304 (.IN ( Scan_Enable ) , .Q ( n483 ) ) ; LSDNX1 U314 (.D ( Scan_Enable ) , .Q ( n480 ) ) ; NBUFFX2 U315 (.IN ( Scan_Enable ) , .Q ( n481 ) ) ; NBUFFX2 U316 (.IN ( Scan_Enable ) , .Q ( n482 ) ) ; INVX0 U317 (.QN ( n484 ) , .IN ( n395 ) ) ; INVX0 U313 (.QN ( n479 ) , .IN ( n462 ) ) ; INVX2 U312 (.IN ( n479 ) , .QN ( n487 ) ) ; INVX32 U319 (.IN ( n486 ) , .QN ( n496 ) ) ; ISOLANDX1 U572 (.ISO ( n471 ) , .D ( n384 ) , .Q ( n467 ) ) ; NOR2X0 U571 (.QN ( n466 ) , .IN1 ( n471 ) , .IN2 ( n373 ) ) ; OR2X1 U570 (.IN2 ( n347 ) , .IN1 ( n471 ) , .Q ( n468 ) ) ; OR2X1 U569 (.IN2 ( n471 ) , .IN1 ( n382 ) , .Q ( n465 ) ) ; MUX21X1 U568 (.S ( n483 ) , .IN2 ( tx_irq ) , .IN1 ( n460 ) , .Q ( n462 ) ) ; DFFX1 \transceiver/rx_reg_reg[0] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[0] ) , .D ( n217 ) ) ; DFFX1 \transceiver/rx_reg_reg[1] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[1] ) , .D ( n218 ) ) ; DFFX1 \transceiver/rx_reg_reg[2] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[2] ) , .D ( n219 ) ) ; DFFX1 \transceiver/rx_reg_reg[3] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[3] ) , .D ( n220 ) ) ; DFFX1 \transceiver/rx_reg_reg[4] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[4] ) , .D ( n221 ) ) ; DFFX1 \transceiver/rx_reg_reg[5] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[5] ) , .D ( n222 ) ) ; DFFX1 \transceiver/rx_reg_reg[6] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[6] ) , .D ( n223 ) ) ; DFFX1 \transceiver/rx_reg_reg[7] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[7] ) , .D ( n224 ) ) ;


SDFFX1 \transceiver/rx_data_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[3] ) , .D ( n216 ) , .Q ( rx_data[0] ) ) ; SDFFX1 \csr_do_reg[7] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[6] ) , .D ( N87 ) , .Q ( csr_do[7] ) ) ; SDFFX1 \transceiver/rx_data_reg[7] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( rx_data[6] ) , .D ( n209 ) , .Q ( rx_data[7] ) ) ; SDFFX1 \csr_do_reg[6] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[5] ) , .D ( N86 ) , .Q ( csr_do[6] ) ) ; SDFFX1 \transceiver/rx_data_reg[6] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( rx_data[5] ) , .D ( n210 ) , .Q ( rx_data[6] ) ) ; SDFFX1 \csr_do_reg[5] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[4] ) , .D ( N85 ) , .Q ( csr_do[5] ) ) ; SDFFX1 \transceiver/rx_data_reg[5] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[4] ) , .D ( n211 ) , .Q ( rx_data[5] ) ) ; SDFFX1 \csr_do_reg[4] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[3] ) , .D ( N84 ) , .Q ( csr_do[4] ) ) ; SDFFX1 \transceiver/rx_data_reg[4] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[3] ) , .D ( n212 ) , .Q ( rx_data[4] ) ) ; SDFFX1 \csr_do_reg[3] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[2] ) , .D ( N83 ) , .Q ( csr_do[3] ) ) ; SDFFX1 \transceiver/rx_data_reg[3] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[2] ) , .D ( n213 ) , .Q ( rx_data[3] ) ) ; SDFFX1 \csr_do_reg[2] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( csr_do[1] ) , .D ( N82 ) , .Q ( csr_do[2] ) ) ; SDFFX1 \transceiver/rx_data_reg[2] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[1] ) , .D ( n214 ) , .Q ( rx_data[2] ) ) ; SDFFX1 \csr_do_reg[1] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( csr_do[0] ) , .D ( N81 ) , .Q ( csr_do[1] ) ) ; SDFFX1 \transceiver/rx_data_reg[1] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[0] ) , .D ( n215 ) , .Q ( rx_data[1] ) ) ; MUX21X1 U567 (.S ( n109 ) , .IN2 ( n457 ) , .IN1 ( n458 ) , .Q ( n459 ) ) ; MUX21X1 U566 (.S ( n476 ) , .IN2 ( n455 ) , .IN1 ( n456 ) , .Q ( \transceiver/N99 ) ) ; AO21X1 U565 (.IN2 ( n454 ) , .IN1 ( divisor[14] ) , .IN3 ( n453 ) , .Q ( n455 ) ) ; MUX21X1 U564 (.S ( n476 ) , .IN2 ( n448 ) , .IN1 ( n449 ) , .Q ( \transceiver/N98 ) ) ; MUX21X1 U563 (.S ( n447 ) , .IN2 ( n300 ) , .IN1 ( divisor[13] ) , .Q ( n448 ) ) ; MUX21X1 U562 (.S ( n476 ) , .IN2 ( n443 ) , .IN1 ( n444 ) , .Q ( \transceiver/N97 ) ) ; AO21X1 U561 (.IN2 ( n442 ) , .IN1 ( divisor[12] ) , .IN3 ( n447 ) , .Q ( n443 ) ) ; MUX21X1 U560 (.S ( n476 ) , .IN2 ( n438 ) , .IN1 ( n439 ) , .Q ( \transceiver/N96 ) ) ; MUX21X1 U559 (.S ( n437 ) , .IN2 ( n299 ) , .IN1 ( divisor[11] ) , .Q ( n438 ) ) ; MUX21X1 U558 (.S ( n484 ) , .IN2 ( n433 ) , .IN1 ( n434 ) , .Q ( \transceiver/N95 ) ) ;


AO21X1 U557 (.IN2 ( n432 ) , .IN1 ( divisor[10] ) , .IN3 ( n437 ) , .Q ( n433 ) ) ; MUX21X1 U556 (.S ( n484 ) , .IN2 ( n428 ) , .IN1 ( n429 ) , .Q ( \transceiver/N94 ) ) ; MUX21X1 U555 (.S ( n427 ) , .IN2 ( n298 ) , .IN1 ( divisor[9] ) , .Q ( n428 ) ) ; MUX21X1 U554 (.S ( n484 ) , .IN2 ( n423 ) , .IN1 ( n424 ) , .Q ( \transceiver/N93 ) ) ; AO21X1 U553 (.IN2 ( n422 ) , .IN1 ( divisor[8] ) , .IN3 ( n427 ) , .Q ( n423 ) ) ; MUX21X1 U552 (.S ( n484 ) , .IN2 ( n418 ) , .IN1 ( n419 ) , .Q ( \transceiver/N92 ) ) ; MUX21X1 U551 (.S ( n417 ) , .IN2 ( n302 ) , .IN1 ( divisor[7] ) , .Q ( n418 ) ) ; MUX21X1 U550 (.S ( n476 ) , .IN2 ( n413 ) , .IN1 ( n414 ) , .Q ( \transceiver/N91 ) ) ; AO21X1 U549 (.IN2 ( n412 ) , .IN1 ( divisor[6] ) , .IN3 ( n417 ) , .Q ( n413 ) ) ; MUX21X1 U548 (.S ( n476 ) , .IN2 ( n408 ) , .IN1 ( n409 ) , .Q ( \transceiver/N90 ) ) ; MUX21X1 U547 (.S ( n407 ) , .IN2 ( n295 ) , .IN1 ( divisor[5] ) , .Q ( n408 ) ) ; MUX21X1 U546 (.S ( n476 ) , .IN2 ( n403 ) , .IN1 ( n404 ) , .Q ( \transceiver/N89 ) ) ; AO21X1 U545 (.IN2 ( n402 ) , .IN1 ( divisor[4] ) , .IN3 ( n407 ) , .Q ( n403 ) ) ; AO221X1 U544 (.IN5 ( n476 ) , .Q ( n398 ) , .IN2 ( n397 ) , .IN1 ( n400 ) , .IN3 ( n400 ) , .IN4 ( n305 ) ) ; AO221X1 U543 (.IN5 ( n395 ) , .Q ( n399 ) , .IN2 ( n396 ) , .IN1 ( n402 ) , .IN3 ( n402 ) , .IN4 ( n294 ) ) ; MUX21X1 U542 (.S ( n476 ) , .IN2 ( n393 ) , .IN1 ( n394 ) , .Q ( \transceiver/N87 ) ) ; AO21X1 U541 (.IN2 ( n392 ) , .IN1 ( divisor[2] ) , .IN3 ( n396 ) , .Q ( n393 ) ) ; AO21X1 U540 (.IN2 ( n391 ) , .IN1 ( \transceiver/enable16_counter[2] ) , .IN3 ( n397 ) , .Q ( n394 ) ) ; NOR2X0 U539 (.QN ( n397 ) , .IN1 ( \transceiver/enable16_counter[2] ) , .IN2 ( n391 ) ) ; OR2X1 U538 (.IN2 ( \transceiver/enable16_counter[1] ) , .IN1 ( \transceiver/enable16_counter[0] ) , .Q ( n391 ) ) ; MUX21X1 U537 (.S ( n476 ) , .IN2 ( n389 ) , .IN1 ( n390 ) , .Q ( \transceiver/N86 ) ) ; MUX21X1 U536 (.S ( \transceiver/enable16_counter[1] ) , .IN2 ( \transceiver/enable16_counter[0] ) , .IN1 ( n306 ) , .Q ( n390 ) ) ; MUX21X1 U535 (.S ( n476 ) , .IN2 ( divisor[0] ) , .IN1 ( \transceiver/enable16_counter[0] ) , .Q ( n387 ) ) ; NOR2X0 U534 (.QN ( \transceiver/N190 ) , .IN1 ( sys_rst ) , .IN2 ( n386 ) ) ; OA222X1 U533 (.IN1 ( n476 ) , .IN5 ( n385 ) , .IN3 ( n476 ) , .IN2 ( \transceiver/enable16_counter[15] ) , .IN4 ( n452 ) , .IN6 ( n395 ) , .Q ( \transceiver/N100 ) ) ; MUX21X1 U532 (.S ( n453 ) , .IN2 ( n301 ) , .IN1 ( divisor[15] ) , .Q ( n385 ) ) ; NOR2X0 U531 (.QN ( n453 ) , .IN1 ( divisor[14] ) , .IN2 ( n454 ) ) ;


NOR2X0 U530 (.QN ( n447 ) , .IN1 ( divisor[12] ) , .IN2 ( n442 ) ) ; NOR2X0 U529 (.QN ( n437 ) , .IN1 ( divisor[10] ) , .IN2 ( n432 ) ) ; NOR2X0 U528 (.QN ( n427 ) , .IN1 ( divisor[8] ) , .IN2 ( n422 ) ) ; NOR2X0 U527 (.QN ( n417 ) , .IN1 ( divisor[6] ) , .IN2 ( n412 ) ) ; NOR2X0 U526 (.QN ( n407 ) , .IN1 ( divisor[4] ) , .IN2 ( n402 ) ) ; NOR2X0 U525 (.QN ( n396 ) , .IN1 ( divisor[2] ) , .IN2 ( n392 ) ) ; OR2X1 U524 (.IN2 ( divisor[1] ) , .IN1 ( divisor[0] ) , .Q ( n392 ) ) ; AO222X1 U523 (.Q ( n193 ) , .IN2 ( \transceiver/tx_reg [6] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[6] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [7] ) ) ; AO222X1 U522 (.Q ( n194 ) , .IN2 ( \transceiver/tx_reg [5] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[5] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [6] ) ) ; assign csr_do[16] = 1'b0; endmodule Routed Netlist: // // Milkyway Hierarchical Verilog Dump: // Generated on 04/23/2012 at 11:06:30 // Design Generated by Cell Based Verilog Reader // File produced by Consolidated Verilog Writer // Library Name :assign_3_f1 // Cell Name :cuart // Hierarchy delimiter:'/' // module cuart (sys_clk , sys_rst , csr_a , csr_we , csr_di , csr_do , rx_irq , tx_irq , uart_rx , uart_tx , Scan_Enable , Test_Mode ); input sys_clk ; input sys_rst ; input [13:0] csr_a ; input csr_we ; input [31:0] csr_di ; output [31:0] csr_do ; output rx_irq ; output tx_irq ; input uart_rx ; output uart_tx ; input Scan_Enable ; input Test_Mode ;


wire [15:0] divisor ; wire [7:0] rx_data ; wire [7:0] \transceiver/tx_reg ; assign csr_do[30] = csr_do[16] ; assign csr_do[29] = csr_do[16] ; assign csr_do[28] = csr_do[16] ; assign csr_do[27] = csr_do[16] ; assign csr_do[26] = csr_do[16] ; assign csr_do[25] = csr_do[16] ; assign csr_do[24] = csr_do[16] ; assign csr_do[23] = csr_do[16] ; assign csr_do[22] = csr_do[16] ; assign csr_do[21] = csr_do[16] ; assign csr_do[20] = csr_do[16] ; assign csr_do[19] = csr_do[16] ; assign csr_do[18] = csr_do[16] ; assign csr_do[17] = csr_do[16] ; assign csr_do[31] = csr_do[16] ; NBUFFX2 U314 (.IN ( Scan_Enable ) , .Q ( n480 ) ) ; INVX32 U323 (.IN ( n496 ) , .QN ( n495 ) ) ; INVX32 U322 (.IN ( n495 ) , .QN ( n494 ) ) ; INVX32 U321 (.IN ( n494 ) , .QN ( n493 ) ) ; INVX32 U320 (.IN ( n493 ) , .QN ( uart_tx ) ) ; NOR4X0 U452 (.IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n115 ) , .IN3 ( \transceiver/rx_bitcount[1] ) , .IN4 ( n114 ) , .QN ( n348 ) ) ; NOR4X0 U442 (.IN2 ( \transceiver/rx_count16[1] ) , .IN1 ( \transceiver/rx_count16[2] ) , .IN3 ( \transceiver/rx_count16[3] ) , .IN4 ( n319 ) , .QN ( n349 ) ) ; INVX2 U318 (.IN ( n487 ) , .QN ( n486 ) ) ; NAND2X0 U334 (.IN1 ( n352 ) , .IN2 ( n296 ) , .QN ( n319 ) ) ; NAND2X0 U333 (.IN1 ( n475 ) , .IN2 ( n472 ) , .QN ( n353 ) ) ; NOR4X0 U332 (.IN2 ( n346 ) , .IN1 ( n348 ) , .IN3 ( n477 ) , .IN4 ( n344 ) , .QN ( n347 ) ) ; NAND2X0 U331 (.IN1 ( n373 ) , .IN2 ( n353 ) , .QN ( n355 ) ) ; NAND2X0 U330 (.IN1 ( n399 ) , .IN2 ( n398 ) , .QN ( \transceiver/N88 ) ) ; NAND2X0 U329 (.IN1 ( n458 ) , .IN2 ( n360 ) , .QN ( n358 ) ) ; NAND2X0 U328 (.IN1 ( n475 ) , .IN2 ( n375 ) , .QN ( n363 ) ) ; NAND2X0 U327 (.IN1 ( n373 ) , .IN2 ( n372 ) , .QN ( n202 ) ) ; NAND2X0 U326 (.IN1 ( n322 ) , .IN2 ( n321 ) , .QN ( n281 ) ) ; NAND2X0 U325 (.IN1 ( n369 ) , .IN2 ( n368 ) , .QN ( n259 ) ) ; AO22X1 U303 (.IN1 ( n473 ) , .IN3 ( n312 ) , .IN2 ( divisor[0] ) , .Q ( N80 ) , .IN4 ( n253 ) ) ; MUX21X1 U302 (.S ( csr_a[1] ) , .IN2 ( thru ) , .IN1 ( rx_data[0] ) , .Q ( n253 ) ) ;


NOR2X0 U301 (.QN ( n285 ) , .IN1 ( n252 ) , .IN2 ( n326 ) ) ; NOR2X0 U300 (.QN ( n252 ) , .IN1 ( n293 ) , .IN2 ( n325 ) ) ; NAND2X0 U299 (.IN1 ( n375 ) , .IN2 ( n251 ) , .QN ( n384 ) ) ; NAND2X0 U298 (.IN1 ( n378 ) , .IN2 ( n374 ) , .QN ( n251 ) ) ; NAND2X0 U297 (.IN1 ( \transceiver/rx_busy ) , .IN2 ( n472 ) , .QN ( n344 ) ) ; NAND2X0 U296 (.IN1 ( n475 ) , .IN2 ( n109 ) , .QN ( n360 ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[1] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/tx_bitcount[0] ) , .D ( n257 ) , .QN ( \transceiver/tx_bitcount[1] ) , .Q ( n464 ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[3] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/tx_bitcount[2] ) , .D ( n259 ) , .QN ( n110 ) , .Q ( n463 ) ) ; SDFFX1 \transceiver/tx_count16_reg[1] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/tx_count16[0] ) , .D ( n459 ) , .Q ( n109 ) ) ; SDFFX1 \transceiver/uart_rx1_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( uart_rx ) , .D ( uart_rx ) , .QN ( n72 ) ) ; SDFFX1 \transceiver/tx_count16_reg[2] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( n109 ) , .D ( n263 ) , .QN ( n297 ) , .Q ( \transceiver/tx_count16[2] ) ) ; SDFFX1 \divisor_reg[3] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[2] ) , .D ( n265 ) , .QN ( n294 ) , .Q ( divisor[3] ) ) ; SDFFX1 \divisor_reg[7] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[6] ) , .D ( n267 ) , .QN ( n302 ) , .Q ( divisor[7] ) ) ; SDFFX1 \divisor_reg[5] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[4] ) , .D ( n269 ) , .QN ( n295 ) , .Q ( divisor[5] ) ) ; SDFFX1 \transceiver/rx_count16_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_busy ) , .D ( n271 ) , .QN ( n296 ) , .Q ( \transceiver/rx_count16[0] ) ) ; SDFFX1 \divisor_reg[9] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[8] ) , .D ( n273 ) , .QN ( n298 ) , .Q ( divisor[9] ) ) ; SDFFX1 \divisor_reg[11] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[10] ) , .D ( n275 ) , .QN ( n299 ) , .Q ( divisor[11] ) ) ; SDFFX1 \divisor_reg[13] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[12] ) , .D ( n277 ) , .QN ( n300 ) , .Q ( divisor[13] ) ) ; SDFFX1 \divisor_reg[15] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[14] ) , .D ( n279 ) , .QN ( n301 ) , .Q ( divisor[15] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[3] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_bitcount[2] ) , .D ( n281 ) , .QN ( n115 ) , .Q ( n304 ) ) ; SDFFX1 \transceiver/rx_count16_reg[3] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[2] ) , .D ( n283 ) , .QN ( n307 ) , .Q ( \transceiver/rx_count16[3] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/enable16_counter[15] ) , .D ( n285 ) , .QN ( n114 ) , .Q ( n293 ) ) ; SDFFX1 \transceiver/enable16_counter_reg[3] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[2] ) , .D ( \transceiver/N88 ) , .QN ( n305 ) , .Q ( \transceiver/enable16_counter[3] ) ) ;


SDFFX1 \transceiver/enable16_counter_reg[0] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( thru ) , .D ( n387 ) , .QN ( \transceiver/enable16_counter[0] ) , .Q ( n306 ) ) ; SDFFX1 \transceiver/rx_busy_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( n304 ) , .D ( n289 ) , .QN ( n292 ) , .Q ( \transceiver/rx_busy ) ) ; DFFX1 \transceiver/uart_rx2_reg (.CLK ( sys_clk ) , .QN ( \transceiver/uart_rx2 ) , .Q ( n303 ) , .D ( n72 ) ) ; DFFX1 \transceiver/tx_reg_reg[0] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [0] ) , .D ( n200 ) ) ; DFFX1 \transceiver/tx_reg_reg[1] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [1] ) , .D ( n198 ) ) ; DFFX1 \transceiver/tx_reg_reg[2] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [2] ) , .D ( n197 ) ) ; DFFX1 \transceiver/tx_reg_reg[3] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [3] ) , .D ( n196 ) ) ; DFFX1 \transceiver/tx_reg_reg[4] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [4] ) , .D ( n195 ) ) ; DFFX1 \transceiver/tx_reg_reg[5] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [5] ) , .D ( n194 ) ) ; DFFX1 \transceiver/tx_reg_reg[6] (.CLK ( sys_clk ) , .Q ( \transceiver/tx_reg [6] ) , .D ( n193 ) ) ; SDFFX1 \transceiver/enable16_counter_reg[1] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( n306 ) , .D ( \transceiver/N86 ) , .Q ( \transceiver/enable16_counter[1] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[2] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[1] ) , .D ( \transceiver/N87 ) , .Q ( \transceiver/enable16_counter[2] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[4] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[3] ) , .D ( \transceiver/N89 ) , .Q ( \transceiver/enable16_counter[4] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[5] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[4] ) , .D ( \transceiver/N90 ) , .Q ( \transceiver/enable16_counter[5] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[6] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[5] ) , .D ( \transceiver/N91 ) , .Q ( \transceiver/enable16_counter[6] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[7] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[6] ) , .D ( \transceiver/N92 ) , .Q ( \transceiver/enable16_counter[7] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[8] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[7] ) , .D ( \transceiver/N93 ) , .Q ( \transceiver/enable16_counter[8] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[9] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[8] ) , .D ( \transceiver/N94 )


, .Q ( \transceiver/enable16_counter[9] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[10] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[9] ) , .D ( \transceiver/N95 ) , .Q ( \transceiver/enable16_counter[10] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[11] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[10] ) , .D ( \transceiver/N96 ) , .Q ( \transceiver/enable16_counter[11] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[12] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[11] ) , .D ( \transceiver/N97 ) , .Q ( \transceiver/enable16_counter[12] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[13] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[12] ) , .D ( \transceiver/N98 ) , .Q ( \transceiver/enable16_counter[13] ) ) ; SDFFX1 \transceiver/enable16_counter_reg[14] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( \transceiver/enable16_counter[13] ) , .D ( \transceiver/N99 ) , .Q ( \transceiver/enable16_counter[14] ) ) ; SDFFX1 \transceiver/uart_tx_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_count16[3] ) , .D ( n199 ) , .Q ( uart_tx_transceiver ) ) ; SDFFX1 \transceiver/tx_busy_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( n463 ) , .D ( n202 ) , .Q ( \transceiver/tx_busy ) ) ; SDFFX1 \transceiver/tx_done_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( uart_tx_transceiver ) , .D ( \transceiver/N190 ) , .Q ( tx_irq ) ) ; SDFFX1 \transceiver/tx_reg_reg[7] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/rx_reg[0] ) , .D ( n201 ) , .Q ( \transceiver/tx_reg [7] ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[2] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( n464 ) , .D ( n204 ) , .Q ( \transceiver/tx_bitcount[2] ) ) ; SDFFX1 \transceiver/tx_bitcount_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( rx_irq ) , .D ( n205 ) , .Q ( \transceiver/tx_bitcount[0] ) ) ; SDFFX1 \transceiver/tx_count16_reg[3] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_count16[2] ) , .D ( n206 ) , .Q ( \transceiver/tx_count16[3] ) ) ; SDFFX1 \transceiver/tx_count16_reg[0] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( \transceiver/tx_busy ) , .D ( n208 ) , .Q ( \transceiver/tx_count16[0] ) ) ; SDFFX1 \transceiver/rx_count16_reg[2] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[1] ) , .D ( n226 ) , .Q ( \transceiver/rx_count16[2] ) ) ; SDFFX1 \transceiver/rx_count16_reg[1] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[0] ) , .D ( n227 ) , .Q ( \transceiver/rx_count16[1] ) ) ; SDFFX1 \csr_do_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/tx_reg [0] ) , .D ( N80 ) , .Q ( csr_do[0] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[2] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( \transceiver/rx_bitcount[1] ) , .D ( n229 )


, .Q ( \transceiver/rx_bitcount[2] ) ) ; SDFFX1 \transceiver/rx_bitcount_reg[1] (.CLK ( sys_clk ) , .SE ( Scan_Enable ) , .SI ( n293 ) , .D ( n230 ) , .Q ( \transceiver/rx_bitcount[1] ) ) ; SDFFX1 \transceiver/rx_done_reg (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( rx_data[7] ) , .D ( \transceiver/N137 ) , .Q ( rx_irq ) ) ; SDFFX1 \transceiver/enable16_counter_reg[15] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( \transceiver/enable16_counter[14] ) , .D ( \transceiver/N100 ) , .Q ( \transceiver/enable16_counter[15] ) ) ; SDFFX1 \csr_do_reg[8] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[7] ) , .D ( N88 ) , .Q ( csr_do[8] ) ) ; SDFFX1 \csr_do_reg[9] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[8] ) , .D ( N89 ) , .Q ( csr_do[9] ) ) ; SDFFX1 \csr_do_reg[10] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[9] ) , .D ( N90 ) , .Q ( csr_do[10] ) ) ; SDFFX1 \csr_do_reg[11] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[10] ) , .D ( N91 ) , .Q ( csr_do[11] ) ) ; SDFFX1 \csr_do_reg[12] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[11] ) , .D ( N92 ) , .Q ( csr_do[12] ) ) ; SDFFX1 \csr_do_reg[13] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[12] ) , .D ( N93 ) , .Q ( csr_do[13] ) ) ; SDFFX1 \csr_do_reg[14] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[13] ) , .D ( N94 ) , .Q ( csr_do[14] ) ) ; SDFFX1 \csr_do_reg[15] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( csr_do[14] ) , .D ( N95 ) , .Q ( csr_do[15] ) ) ; SDFFX1 \divisor_reg[0] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[15] ) , .D ( n234 ) , .Q ( divisor[0] ) ) ; SDFFX1 \divisor_reg[1] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[0] ) , .D ( n235 ) , .Q ( divisor[1] ) ) ; SDFFX1 \divisor_reg[2] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[1] ) , .D ( n236 ) , .Q ( divisor[2] ) ) ; SDFFX1 \divisor_reg[4] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[3] ) , .D ( n238 ) , .Q ( divisor[4] ) ) ; SDFFX1 \divisor_reg[6] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( divisor[5] ) , .D ( n240 ) , .Q ( divisor[6] ) ) ; SDFFX1 \divisor_reg[8] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[7] ) , .D ( n242 ) , .Q ( divisor[8] ) ) ; SDFFX1 \divisor_reg[10] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[9] ) , .D ( n244 ) , .Q ( divisor[10] ) ) ; SDFFX1 \divisor_reg[12] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( divisor[11] ) , .D ( n246 ) , .Q ( divisor[12] ) ) ; SDFFX1 \divisor_reg[14] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( divisor[13] ) , .D ( n248 ) , .Q ( divisor[14] ) ) ; SDFFX1 thru_reg (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( divisor[15] ) , .D ( n250 ) , .Q ( thru ) ) ;


AO221X1 U428 (.IN5 ( sys_rst ) , .Q ( n236 ) , .IN2 ( csr_di[2] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[2] ) ) ; AO221X1 U427 (.IN5 ( sys_rst ) , .Q ( n238 ) , .IN2 ( csr_di[4] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[4] ) ) ; AO221X1 U426 (.IN5 ( sys_rst ) , .Q ( n269 ) , .IN2 ( csr_di[5] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[5] ) ) ; AO22X1 U424 (.IN1 ( divisor[8] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n242 ) , .IN4 ( csr_di[8] ) ) ; AO22X1 U423 (.IN1 ( divisor[9] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n273 ) , .IN4 ( csr_di[9] ) ) ; AO22X1 U422 (.IN1 ( divisor[10] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n244 ) , .IN4 ( csr_di[10] ) ) ; AO22X1 U421 (.IN1 ( divisor[11] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n275 ) , .IN4 ( csr_di[11] ) ) ; AO22X1 U420 (.IN1 ( divisor[12] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n246 ) , .IN4 ( csr_di[12] ) ) ; AO22X1 U419 (.IN1 ( divisor[13] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n277 ) , .IN4 ( csr_di[13] ) ) ; AO22X1 U418 (.IN1 ( divisor[14] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n248 ) , .IN4 ( csr_di[14] ) ) ; AO22X1 U417 (.IN1 ( divisor[15] ) , .IN3 ( n318 ) , .IN2 ( n317 ) , .Q ( n279 ) , .IN4 ( csr_di[15] ) ) ; INVX0 U416 (.QN ( n315 ) , .IN ( csr_a[0] ) ) ; MUX21X1 U415 (.S ( n313 ) , .IN2 ( thru ) , .IN1 ( csr_di[0] ) , .Q ( n250 ) ) ; NAND3X0 U414 (.QN ( n313 ) , .IN3 ( n312 ) , .IN2 ( csr_we ) , .IN1 ( csr_a[1] ) ) ; NOR2X0 U413 (.QN ( N95 ) , .IN1 ( n301 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U412 (.ISO ( n311 ) , .D ( divisor[14] ) , .Q ( N94 ) ) ; NOR2X0 U411 (.QN ( N93 ) , .IN1 ( n300 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U410 (.ISO ( n311 ) , .D ( divisor[12] ) , .Q ( N92 ) ) ; NOR2X0 U409 (.QN ( N91 ) , .IN1 ( n299 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U408 (.ISO ( n311 ) , .D ( divisor[10] ) , .Q ( N90 ) ) ; NOR2X0 U407 (.QN ( N89 ) , .IN1 ( n298 ) , .IN2 ( n311 ) ) ; ISOLANDX1 U406 (.ISO ( n311 ) , .D ( divisor[8] ) , .Q ( N88 ) ) ; AO22X1 U405 (.IN1 ( rx_data[7] ) , .IN3 ( divisor[7] ) , .IN2 ( n310 ) , .Q ( N87 ) , .IN4 ( n473 ) ) ; AO22X1 U404 (.IN1 ( rx_data[6] ) , .IN3 ( divisor[6] ) , .IN2 ( n310 ) , .Q ( N86 ) , .IN4 ( n473 ) ) ; AO22X1 U403 (.IN1 ( rx_data[5] ) , .IN3 ( divisor[5] ) , .IN2 ( n310 ) , .Q ( N85 ) , .IN4 ( n473 ) ) ; AO22X1 U402 (.IN1 ( rx_data[4] ) , .IN3 ( divisor[4] ) , .IN2 ( n310 ) , .Q ( N84 ) , .IN4 ( n473 ) ) ; AO22X1 U401 (.IN1 ( rx_data[3] ) , .IN3 ( divisor[3] ) , .IN2 ( n310 ) , .Q ( N83 ) , .IN4 ( n473 ) ) ; AO22X1 U400 (.IN1 ( rx_data[2] ) , .IN3 ( divisor[2] ) , .IN2 ( n310 )


, .Q ( N82 ) , .IN4 ( n473 ) ) ; AO22X1 U399 (.IN1 ( rx_data[1] ) , .IN3 ( divisor[1] ) , .IN2 ( n310 ) , .Q ( N81 ) , .IN4 ( n473 ) ) ; NOR3X0 U398 (.IN2 ( sys_rst ) , .QN ( n312 ) , .IN1 ( csr_a[0] ) , .IN3 ( n308 ) ) ; NAND3X0 U396 (.QN ( n311 ) , .IN3 ( n472 ) , .IN2 ( csr_a[0] ) , .IN1 ( n314 ) ) ; OR4X1 U395 (.IN4 ( csr_a[13] ) , .IN2 ( csr_a[11] ) , .Q ( n308 ) , .IN1 ( csr_a[10] ) , .IN3 ( csr_a[12] ) ) ; MUX21X1 U393 (.S ( thru ) , .IN2 ( uart_rx ) , .IN1 ( uart_tx_transceiver ) , .Q ( n460 ) ) ; NAND2X0 U392 (.IN2 ( n314 ) , .IN1 ( csr_we ) , .QN ( n351 ) ) ; INVX0 U391 (.QN ( n374 ) , .IN ( n361 ) ) ; INVX0 U390 (.QN ( n383 ) , .IN ( n373 ) ) ; AO22X1 U389 (.IN1 ( csr_di[3] ) , .IN3 ( divisor[3] ) , .IN2 ( n318 ) , .Q ( n265 ) , .IN4 ( n317 ) ) ; AO22X1 U388 (.IN1 ( csr_di[7] ) , .IN3 ( divisor[7] ) , .IN2 ( n318 ) , .Q ( n267 ) , .IN4 ( n317 ) ) ; AO22X1 U387 (.IN1 ( csr_di[0] ) , .IN3 ( divisor[0] ) , .IN2 ( n318 ) , .Q ( n234 ) , .IN4 ( n317 ) ) ; AO22X1 U386 (.IN1 ( csr_di[6] ) , .IN3 ( divisor[6] ) , .IN2 ( n318 ) , .Q ( n240 ) , .IN4 ( n317 ) ) ; INVX0 U385 (.QN ( n350 ) , .IN ( n344 ) ) ; ISOLANDX1 U384 (.ISO ( csr_a[1] ) , .D ( n312 ) , .Q ( n310 ) ) ; NAND2X0 U383 (.IN1 ( divisor[0] ) , .IN2 ( divisor[1] ) , .QN ( n388 ) ) ; NOR2X0 U382 (.QN ( n382 ) , .IN1 ( n376 ) , .IN2 ( n384 ) ) ; AND4X1 U381 (.IN1 ( n350 ) , .IN2 ( n349 ) , .IN3 ( \transceiver/uart_rx2 ) , .IN4 ( n348 ) , .Q ( \transceiver/N137 ) ) ; NAND2X0 U380 (.IN1 ( \transceiver/tx_bitcount[1] ) , .IN2 ( \transceiver/tx_bitcount[0] ) , .QN ( n364 ) ) ; NOR2X0 U379 (.QN ( n337 ) , .IN1 ( sys_rst ) , .IN2 ( n343 ) ) ; NOR2X0 U378 (.QN ( n314 ) , .IN1 ( csr_a[1] ) , .IN2 ( n308 ) ) ; NOR2X0 U377 (.QN ( n352 ) , .IN1 ( \transceiver/enable16_counter[15] ) , .IN2 ( n452 ) ) ; NOR2X0 U376 (.QN ( n375 ) , .IN1 ( sys_rst ) , .IN2 ( n381 ) ) ; OA21X1 U375 (.IN2 ( n351 ) , .IN3 ( n472 ) , .IN1 ( n315 ) , .Q ( n317 ) ) ; NOR2X0 U373 (.QN ( n395 ) , .IN1 ( n352 ) , .IN2 ( sys_rst ) ) ; NOR2X1 U372 (.QN ( n318 ) , .IN1 ( sys_rst ) , .IN2 ( n317 ) ) ; NOR2X0 U371 (.QN ( n361 ) , .IN1 ( csr_a[0] ) , .IN2 ( n351 ) ) ; NAND2X0 U370 (.IN1 ( n374 ) , .IN2 ( \transceiver/tx_count16[0] ) , .QN ( n354 ) ) ; NAND2X0 U369 (.IN1 ( n332 ) , .IN2 ( n476 ) , .QN ( n343 ) ) ; NAND2X0 U366 (.IN1 ( \transceiver/rx_count16[0] ) , .IN2 ( \transceiver/rx_count16[1] ) , .QN ( n338 ) ) ; NAND2X0 U365 (.IN1 ( n392 ) , .IN2 ( n388 ) , .QN ( n389 ) ) ; NAND2X0 U364 (.IN1 ( \transceiver/enable16_counter[4] ) , .IN2 ( n400 ) , .QN ( n401 ) ) ;


NAND2X0 U363 (.IN1 ( \transceiver/enable16_counter[5] ) , .IN2 ( n405 ) , .QN ( n406 ) ) ; NAND2X0 U362 (.IN1 ( n405 ) , .IN2 ( n401 ) , .QN ( n404 ) ) ; NAND2X0 U361 (.IN1 ( n396 ) , .IN2 ( n294 ) , .QN ( n402 ) ) ; NAND2X0 U360 (.IN1 ( \transceiver/rx_count16[2] ) , .IN2 ( n339 ) , .QN ( n340 ) ) ; NAND2X0 U359 (.IN1 ( n472 ) , .IN2 ( n361 ) , .QN ( n373 ) ) ; NAND2X0 U358 (.IN1 ( \transceiver/enable16_counter[6] ) , .IN2 ( n410 ) , .QN ( n411 ) ) ; NAND2X0 U357 (.IN1 ( n410 ) , .IN2 ( n406 ) , .QN ( n409 ) ) ; NAND2X0 U356 (.IN1 ( n415 ) , .IN2 ( n411 ) , .QN ( n414 ) ) ; NAND2X0 U355 (.IN1 ( \transceiver/enable16_counter[7] ) , .IN2 ( n415 ) , .QN ( n416 ) ) ; NAND2X0 U354 (.IN1 ( n407 ) , .IN2 ( n295 ) , .QN ( n412 ) ) ; NAND2X0 U353 (.IN1 ( n420 ) , .IN2 ( n416 ) , .QN ( n419 ) ) ; NAND2X0 U352 (.IN1 ( \transceiver/enable16_counter[8] ) , .IN2 ( n420 ) , .QN ( n421 ) ) ; NAND2X0 U351 (.IN1 ( n417 ) , .IN2 ( n302 ) , .QN ( n422 ) ) ; NAND2X0 U350 (.IN1 ( n425 ) , .IN2 ( n421 ) , .QN ( n424 ) ) ; NAND2X0 U349 (.IN1 ( \transceiver/enable16_counter[9] ) , .IN2 ( n425 ) , .QN ( n426 ) ) ; NAND2X0 U348 (.IN1 ( \transceiver/enable16_counter[10] ) , .IN2 ( n430 ) , .QN ( n431 ) ) ; NAND2X0 U347 (.IN1 ( n430 ) , .IN2 ( n426 ) , .QN ( n429 ) ) ; NAND2X0 U346 (.IN1 ( n427 ) , .IN2 ( n298 ) , .QN ( n432 ) ) ; NAND2X0 U345 (.IN1 ( n435 ) , .IN2 ( n431 ) , .QN ( n434 ) ) ; NAND2X0 U344 (.IN1 ( \transceiver/enable16_counter[11] ) , .IN2 ( n435 ) , .QN ( n436 ) ) ; NAND2X0 U343 (.IN1 ( n440 ) , .IN2 ( n436 ) , .QN ( n439 ) ) ; NAND2X0 U342 (.IN1 ( \transceiver/enable16_counter[12] ) , .IN2 ( n440 ) , .QN ( n441 ) ) ; NAND2X0 U341 (.IN1 ( \transceiver/enable16_counter[13] ) , .IN2 ( n445 ) , .QN ( n446 ) ) ; NAND2X0 U340 (.IN1 ( n437 ) , .IN2 ( n299 ) , .QN ( n442 ) ) ; NAND2X0 U339 (.IN1 ( n445 ) , .IN2 ( n441 ) , .QN ( n444 ) ) ; NAND2X0 U338 (.IN1 ( \transceiver/enable16_counter[14] ) , .IN2 ( n450 ) , .QN ( n451 ) ) ; NAND2X0 U337 (.IN1 ( n450 ) , .IN2 ( n446 ) , .QN ( n449 ) ) ; NAND2X0 U336 (.IN1 ( n447 ) , .IN2 ( n300 ) , .QN ( n454 ) ) ; NAND2X0 U335 (.IN1 ( n452 ) , .IN2 ( n451 ) , .QN ( n456 ) ) ; AO222X1 U521 (.Q ( n195 ) , .IN2 ( \transceiver/tx_reg [4] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[4] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [5] ) ) ; AO222X1 U520 (.Q ( n196 ) , .IN2 ( \transceiver/tx_reg [3] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[3] ) , .IN6 ( n465 )


, .IN5 ( \transceiver/tx_reg [4] ) ) ; AO222X1 U519 (.Q ( n197 ) , .IN2 ( \transceiver/tx_reg [2] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[2] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [3] ) ) ; AO222X1 U518 (.Q ( n198 ) , .IN2 ( \transceiver/tx_reg [1] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[1] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [2] ) ) ; AO221X1 U517 (.IN5 ( sys_rst ) , .Q ( n199 ) , .IN2 ( uart_tx_transceiver ) , .IN1 ( n381 ) , .IN3 ( n380 ) , .IN4 ( n379 ) ) ; OA21X1 U516 (.IN2 ( \transceiver/tx_reg [0] ) , .IN3 ( n475 ) , .IN1 ( n378 ) , .Q ( n379 ) ) ; INVX0 U515 (.QN ( n380 ) , .IN ( n381 ) ) ; AO222X1 U514 (.Q ( n200 ) , .IN2 ( \transceiver/tx_reg [0] ) , .IN1 ( n467 ) , .IN3 ( n465 ) , .IN4 ( \transceiver/tx_reg [1] ) , .IN6 ( csr_di[0] ) , .IN5 ( n466 ) ) ; AO22X1 U513 (.IN1 ( csr_di[7] ) , .IN3 ( \transceiver/tx_reg [7] ) , .IN2 ( n383 ) , .Q ( n201 ) , .IN4 ( n384 ) ) ; NAND3X0 U512 (.QN ( n372 ) , .IN3 ( n386 ) , .IN2 ( n472 ) , .IN1 ( \transceiver/tx_busy ) ) ; NAND3X0 U511 (.QN ( n386 ) , .IN3 ( n378 ) , .IN2 ( \transceiver/tx_bitcount[0] ) , .IN1 ( n370 ) ) ; NOR3X0 U510 (.IN2 ( n110 ) , .QN ( n378 ) , .IN1 ( \transceiver/tx_bitcount[2] ) , .IN3 ( \transceiver/tx_bitcount[1] ) ) ; AO221X1 U509 (.IN5 ( n110 ) , .Q ( n368 ) , .IN2 ( \transceiver/tx_bitcount[2] ) , .IN1 ( n367 ) , .IN3 ( n367 ) , .IN4 ( n376 ) ) ; NAND3X0 U508 (.QN ( n369 ) , .IN3 ( \transceiver/tx_bitcount[2] ) , .IN2 ( n110 ) , .IN1 ( n366 ) ) ; MUX21X1 U507 (.S ( \transceiver/tx_bitcount[2] ) , .IN2 ( n365 ) , .IN1 ( n366 ) , .Q ( n204 ) ) ; NOR2X0 U506 (.QN ( n366 ) , .IN1 ( n364 ) , .IN2 ( n363 ) ) ; OAI221X1 U505 (.IN2 ( n375 ) , .QN ( n257 ) , .IN5 ( n365 ) , .IN4 ( \transceiver/tx_bitcount[0] ) , .IN3 ( \transceiver/tx_bitcount[1] ) , .IN1 ( \transceiver/tx_bitcount[1] ) ) ; INVX0 U504 (.QN ( n365 ) , .IN ( n367 ) ) ; OA221X1 U503 (.IN2 ( \transceiver/tx_bitcount[1] ) , .IN4 ( \transceiver/tx_bitcount[0] ) , .Q ( n367 ) , .IN5 ( n375 ) , .IN1 ( n376 ) , .IN3 ( n376 ) ) ; INVX0 U502 (.QN ( n205 ) , .IN ( n362 ) ) ; MUX21X1 U501 (.S ( \transceiver/tx_bitcount[0] ) , .IN2 ( n375 ) , .IN1 ( n363 ) , .Q ( n362 ) ) ; NOR2X0 U500 (.QN ( n381 ) , .IN1 ( n361 ) , .IN2 ( n370 ) ) ; NOR4X0 U499 (.IN2 ( \transceiver/tx_count16[3] ) , .IN1 ( \transceiver/tx_count16[0] ) , .IN3 ( \transceiver/tx_count16[2] ) , .IN4 ( n360 ) , .QN ( n370 ) ) ;


AO221X1 U498 (.IN5 ( n357 ) , .Q ( n206 ) , .IN2 ( n359 ) , .IN1 ( \transceiver/tx_count16[3] ) , .IN3 ( \transceiver/tx_count16[3] ) , .IN4 ( n358 ) ) ; NOR4X0 U497 (.IN2 ( \transceiver/tx_count16[3] ) , .IN1 ( n109 ) , .IN3 ( n297 ) , .IN4 ( n457 ) , .QN ( n357 ) ) ; NOR2X0 U496 (.QN ( n359 ) , .IN1 ( \transceiver/tx_count16[2] ) , .IN2 ( n376 ) ) ; MUX21X1 U495 (.S ( n297 ) , .IN2 ( n356 ) , .IN1 ( n358 ) , .Q ( n263 ) ) ; NOR2X0 U494 (.QN ( n356 ) , .IN1 ( n109 ) , .IN2 ( n457 ) ) ; NAND3X0 U493 (.QN ( n457 ) , .IN3 ( n472 ) , .IN2 ( \transceiver/tx_count16[0] ) , .IN1 ( n475 ) ) ; OA21X1 U492 (.IN2 ( n376 ) , .IN3 ( n355 ) , .IN1 ( \transceiver/tx_count16[0] ) , .Q ( n458 ) ) ; MUX21X1 U491 (.S ( n355 ) , .IN2 ( n354 ) , .IN1 ( \transceiver/tx_count16[0] ) , .Q ( n208 ) ) ; NAND3X0 U489 (.QN ( n376 ) , .IN3 ( n374 ) , .IN2 ( \transceiver/tx_busy ) , .IN1 ( n352 ) ) ; MUX21X1 U488 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[7] ) , .IN1 ( rx_data[7] ) , .Q ( n209 ) ) ; MUX21X1 U487 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[6] ) , .IN1 ( rx_data[6] ) , .Q ( n210 ) ) ; MUX21X1 U486 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[5] ) , .IN1 ( rx_data[5] ) , .Q ( n211 ) ) ; MUX21X1 U485 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[4] ) , .IN1 ( rx_data[4] ) , .Q ( n212 ) ) ; MUX21X1 U484 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[3] ) , .IN1 ( rx_data[3] ) , .Q ( n213 ) ) ; MUX21X1 U483 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[2] ) , .IN1 ( rx_data[2] ) , .Q ( n214 ) ) ; MUX21X1 U482 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[1] ) , .IN1 ( rx_data[1] ) , .Q ( n215 ) ) ; MUX21X1 U481 (.S ( \transceiver/N137 ) , .IN2 ( \transceiver/rx_reg[0] ) , .IN1 ( rx_data[0] ) , .Q ( n216 ) ) ; MUX21X1 U480 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[1] ) , .IN1 ( \transceiver/rx_reg[0] ) , .Q ( n217 ) ) ; MUX21X1 U479 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[2] ) , .IN1 ( \transceiver/rx_reg[1] ) , .Q ( n218 ) ) ; MUX21X1 U478 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[3] ) , .IN1 ( \transceiver/rx_reg[2] ) , .Q ( n219 ) ) ; MUX21X1 U477 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[4] ) , .IN1 ( \transceiver/rx_reg[3] ) , .Q ( n220 ) ) ; MUX21X1 U476 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[5] ) , .IN1 ( \transceiver/rx_reg[4] ) , .Q ( n221 ) ) ; MUX21X1 U475 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[6] ) , .IN1 ( \transceiver/rx_reg[5] ) , .Q ( n222 ) ) ;


MUX21X1 U474 (.S ( n468 ) , .IN2 ( \transceiver/rx_reg[7] ) , .IN1 ( \transceiver/rx_reg[6] ) , .Q ( n223 ) ) ; MUX21X1 U473 (.S ( n468 ) , .IN2 ( \transceiver/uart_rx2 ) , .IN1 ( \transceiver/rx_reg[7] ) , .Q ( n224 ) ) ; OA22X1 U471 (.IN2 ( n342 ) , .IN4 ( n341 ) , .IN1 ( n343 ) , .IN3 ( \transceiver/rx_count16[3] ) , .Q ( n283 ) ) ; NOR2X0 U470 (.QN ( n341 ) , .IN1 ( n343 ) , .IN2 ( n340 ) ) ; OA21X1 U469 (.IN2 ( n307 ) , .IN3 ( n350 ) , .IN1 ( n340 ) , .Q ( n342 ) ) ; INVX0 U468 (.QN ( n339 ) , .IN ( n338 ) ) ; AO221X1 U467 (.IN5 ( n335 ) , .Q ( n226 ) , .IN2 ( n336 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) ) ; OA221X1 U466 (.IN2 ( n472 ) , .IN4 ( n338 ) , .Q ( n335 ) , .IN5 ( \transceiver/rx_count16[2] ) , .IN1 ( n343 ) , .IN3 ( n343 ) ) ; NOR2X0 U465 (.QN ( n336 ) , .IN1 ( \transceiver/rx_count16[2] ) , .IN2 ( n338 ) ) ; AO221X1 U464 (.IN5 ( n333 ) , .Q ( n227 ) , .IN2 ( n334 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) ) ; OA221X1 U463 (.IN2 ( n472 ) , .IN4 ( n296 ) , .Q ( n333 ) , .IN5 ( \transceiver/rx_count16[1] ) , .IN1 ( n343 ) , .IN3 ( n343 ) ) ; NOR2X0 U462 (.QN ( n334 ) , .IN1 ( \transceiver/rx_count16[1] ) , .IN2 ( n296 ) ) ; AO222X1 U461 (.Q ( n271 ) , .IN2 ( n296 ) , .IN1 ( n337 ) , .IN3 ( n337 ) , .IN4 ( n292 ) , .IN6 ( n343 ) , .IN5 ( \transceiver/rx_count16[0] ) ) ; NAND3X0 U460 (.QN ( n332 ) , .IN3 ( n472 ) , .IN2 ( n292 ) , .IN1 ( \transceiver/uart_rx2 ) ) ; MUX21X1 U459 (.S ( \transceiver/rx_bitcount[2] ) , .IN2 ( n330 ) , .IN1 ( n331 ) , .Q ( n229 ) ) ; INVX0 U458 (.QN ( n330 ) , .IN ( n329 ) ) ; INVX0 U457 (.QN ( n230 ) , .IN ( n328 ) ) ; MUX21X1 U456 (.S ( \transceiver/rx_bitcount[1] ) , .IN2 ( n326 ) , .IN1 ( n327 ) , .Q ( n328 ) ) ; OAI22X1 U455 (.IN3 ( n323 ) , .QN ( n289 ) , .IN1 ( sys_rst ) , .IN4 ( n344 ) , .IN2 ( n324 ) ) ; OA221X1 U454 (.IN2 ( n346 ) , .IN4 ( \transceiver/uart_rx2 ) , .Q ( n323 ) , .IN5 ( n349 ) , .IN1 ( n348 ) , .IN3 ( n348 ) ) ; NOR4X0 U453 (.IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( \transceiver/rx_bitcount[1] ) , .IN3 ( n304 ) , .IN4 ( n293 ) , .QN ( n346 ) ) ; AO221X1 U451 (.IN5 ( n115 ) , .Q ( n321 ) , .IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n329 ) , .IN3 ( n329 ) , .IN4 ( n344 ) ) ; OA21X1 U450 (.IN2 ( n344 ) , .IN3 ( n326 ) , .IN1 ( \transceiver/rx_bitcount[1] ) , .Q ( n329 ) ) ; OA21X1 U449 (.IN2 ( n344 ) , .IN3 ( n325 ) , .IN1 ( n293 ) , .Q ( n326 ) ) ; NAND3X0 U448 (.QN ( n325 ) , .IN3 ( n320 ) , .IN2 ( n324 ) , .IN1 ( n472 ) ) ; NAND2X0 U447 (.IN1 ( n349 ) , .IN2 ( \transceiver/rx_busy ) , .QN ( n320 ) ) ;


NAND3X0 U446 (.QN ( n324 ) , .IN3 ( n303 ) , .IN2 ( n292 ) , .IN1 ( n352 ) ) ; NAND3X0 U445 (.QN ( n322 ) , .IN3 ( n115 ) , .IN2 ( \transceiver/rx_bitcount[2] ) , .IN1 ( n331 ) ) ; ISOLANDX1 U444 (.ISO ( n327 ) , .D ( \transceiver/rx_bitcount[1] ) , .Q ( n331 ) ) ; NAND4X0 U443 (.IN1 ( \transceiver/rx_busy ) , .QN ( n327 ) , .IN2 ( n349 ) , .IN3 ( n472 ) , .IN4 ( n293 ) ) ; OR2X1 U441 (.IN2 ( n450 ) , .IN1 ( \transceiver/enable16_counter[14] ) , .Q ( n452 ) ) ; OR2X1 U440 (.IN2 ( n445 ) , .IN1 ( \transceiver/enable16_counter[13] ) , .Q ( n450 ) ) ; OR2X1 U439 (.IN2 ( n440 ) , .IN1 ( \transceiver/enable16_counter[12] ) , .Q ( n445 ) ) ; OR2X1 U438 (.IN2 ( n435 ) , .IN1 ( \transceiver/enable16_counter[11] ) , .Q ( n440 ) ) ; OR2X1 U437 (.IN2 ( n430 ) , .IN1 ( \transceiver/enable16_counter[10] ) , .Q ( n435 ) ) ; OR2X1 U436 (.IN2 ( n425 ) , .IN1 ( \transceiver/enable16_counter[9] ) , .Q ( n430 ) ) ; OR2X1 U435 (.IN2 ( n420 ) , .IN1 ( \transceiver/enable16_counter[8] ) , .Q ( n425 ) ) ; OR2X1 U434 (.IN2 ( n415 ) , .IN1 ( \transceiver/enable16_counter[7] ) , .Q ( n420 ) ) ; OR2X1 U433 (.IN2 ( n410 ) , .IN1 ( \transceiver/enable16_counter[6] ) , .Q ( n415 ) ) ; OR2X1 U432 (.IN2 ( n405 ) , .IN1 ( \transceiver/enable16_counter[5] ) , .Q ( n410 ) ) ; OR2X1 U431 (.IN2 ( n400 ) , .IN1 ( \transceiver/enable16_counter[4] ) , .Q ( n405 ) ) ; OR4X1 U430 (.IN4 ( \transceiver/enable16_counter[1] ) , .IN2 ( \transceiver/enable16_counter[2] ) , .Q ( n400 ) , .IN1 ( \transceiver/enable16_counter[3] ) , .IN3 ( \transceiver/enable16_counter[0] ) ) ; AO221X1 U429 (.IN5 ( sys_rst ) , .Q ( n235 ) , .IN2 ( csr_di[1] ) , .IN1 ( n474 ) , .IN3 ( n317 ) , .IN4 ( divisor[1] ) ) ; INVX0 U307 (.QN ( n473 ) , .IN ( n311 ) ) ; INVX0 U308 (.QN ( n474 ) , .IN ( n317 ) ) ; INVX0 U309 (.QN ( n475 ) , .IN ( n376 ) ) ; INVX2 U310 (.IN ( n395 ) , .QN ( n476 ) ) ; INVX0 U311 (.QN ( n477 ) , .IN ( n349 ) ) ; NBUFFX2 U305 (.IN ( Scan_Enable ) , .Q ( n471 ) ) ; INVX0 U306 (.QN ( n472 ) , .IN ( sys_rst ) ) ; NBUFFX2 U304 (.IN ( Scan_Enable ) , .Q ( n483 ) ) ; NBUFFX2 U315 (.IN ( Scan_Enable ) , .Q ( n481 ) ) ; NBUFFX2 U316 (.IN ( Scan_Enable ) , .Q ( n482 ) ) ;


INVX0 U317 (.QN ( n484 ) , .IN ( n395 ) ) ; INVX0 U313 (.QN ( n479 ) , .IN ( n462 ) ) ; INVX2 U312 (.IN ( n479 ) , .QN ( n487 ) ) ; INVX32 U319 (.IN ( n486 ) , .QN ( n496 ) ) ; ISOLANDX1 U572 (.ISO ( n471 ) , .D ( n384 ) , .Q ( n467 ) ) ; NOR2X0 U571 (.QN ( n466 ) , .IN1 ( n471 ) , .IN2 ( n373 ) ) ; OR2X1 U570 (.IN2 ( n347 ) , .IN1 ( n471 ) , .Q ( n468 ) ) ; OR2X1 U569 (.IN2 ( n471 ) , .IN1 ( n382 ) , .Q ( n465 ) ) ; MUX21X1 U568 (.S ( n483 ) , .IN2 ( tx_irq ) , .IN1 ( n460 ) , .Q ( n462 ) ) ; DFFX1 \transceiver/rx_reg_reg[0] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[0] ) , .D ( n217 ) ) ; DFFX1 \transceiver/rx_reg_reg[1] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[1] ) , .D ( n218 ) ) ; DFFX1 \transceiver/rx_reg_reg[2] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[2] ) , .D ( n219 ) ) ; DFFX1 \transceiver/rx_reg_reg[3] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[3] ) , .D ( n220 ) ) ; DFFX1 \transceiver/rx_reg_reg[4] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[4] ) , .D ( n221 ) ) ; DFFX1 \transceiver/rx_reg_reg[5] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[5] ) , .D ( n222 ) ) ; DFFX1 \transceiver/rx_reg_reg[6] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[6] ) , .D ( n223 ) ) ; DFFX1 \transceiver/rx_reg_reg[7] (.CLK ( sys_clk ) , .Q ( \transceiver/rx_reg[7] ) , .D ( n224 ) ) ; SDFFX1 \transceiver/rx_data_reg[0] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( \transceiver/rx_count16[3] ) , .D ( n216 ) , .Q ( rx_data[0] ) ) ; SDFFX1 \csr_do_reg[7] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[6] ) , .D ( N87 ) , .Q ( csr_do[7] ) ) ; SDFFX1 \transceiver/rx_data_reg[7] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( rx_data[6] ) , .D ( n209 ) , .Q ( rx_data[7] ) ) ; SDFFX1 \csr_do_reg[6] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[5] ) , .D ( N86 ) , .Q ( csr_do[6] ) ) ; SDFFX1 \transceiver/rx_data_reg[6] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( rx_data[5] ) , .D ( n210 ) , .Q ( rx_data[6] ) ) ; SDFFX1 \csr_do_reg[5] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[4] ) , .D ( N85 ) , .Q ( csr_do[5] ) ) ; SDFFX1 \transceiver/rx_data_reg[5] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[4] ) , .D ( n211 ) , .Q ( rx_data[5] ) ) ; SDFFX1 \csr_do_reg[4] (.CLK ( sys_clk ) , .SE ( n480 ) , .SI ( csr_do[3] ) , .D ( N84 ) , .Q ( csr_do[4] ) ) ; SDFFX1 \transceiver/rx_data_reg[4] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[3] ) , .D ( n212 ) , .Q ( rx_data[4] ) ) ; SDFFX1 \csr_do_reg[3] (.CLK ( sys_clk ) , .SE ( n481 ) , .SI ( csr_do[2] ) , .D ( N83 ) , .Q ( csr_do[3] ) ) ;


SDFFX1 \transceiver/rx_data_reg[3] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[2] ) , .D ( n213 ) , .Q ( rx_data[3] ) ) ; SDFFX1 \csr_do_reg[2] (.CLK ( sys_clk ) , .SE ( n482 ) , .SI ( csr_do[1] ) , .D ( N82 ) , .Q ( csr_do[2] ) ) ; SDFFX1 \transceiver/rx_data_reg[2] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[1] ) , .D ( n214 ) , .Q ( rx_data[2] ) ) ; SDFFX1 \csr_do_reg[1] (.CLK ( sys_clk ) , .SE ( n483 ) , .SI ( csr_do[0] ) , .D ( N81 ) , .Q ( csr_do[1] ) ) ; SDFFX1 \transceiver/rx_data_reg[1] (.CLK ( sys_clk ) , .SE ( n471 ) , .SI ( rx_data[0] ) , .D ( n215 ) , .Q ( rx_data[1] ) ) ; MUX21X1 U567 (.S ( n109 ) , .IN2 ( n457 ) , .IN1 ( n458 ) , .Q ( n459 ) ) ; MUX21X1 U566 (.S ( n476 ) , .IN2 ( n455 ) , .IN1 ( n456 ) , .Q ( \transceiver/N99 ) ) ; AO21X1 U565 (.IN2 ( n454 ) , .IN1 ( divisor[14] ) , .IN3 ( n453 ) , .Q ( n455 ) ) ; MUX21X1 U564 (.S ( n476 ) , .IN2 ( n448 ) , .IN1 ( n449 ) , .Q ( \transceiver/N98 ) ) ; MUX21X1 U563 (.S ( n447 ) , .IN2 ( n300 ) , .IN1 ( divisor[13] ) , .Q ( n448 ) ) ; MUX21X1 U562 (.S ( n476 ) , .IN2 ( n443 ) , .IN1 ( n444 ) , .Q ( \transceiver/N97 ) ) ; AO21X1 U561 (.IN2 ( n442 ) , .IN1 ( divisor[12] ) , .IN3 ( n447 ) , .Q ( n443 ) ) ; MUX21X1 U560 (.S ( n476 ) , .IN2 ( n438 ) , .IN1 ( n439 ) , .Q ( \transceiver/N96 ) ) ; MUX21X1 U559 (.S ( n437 ) , .IN2 ( n299 ) , .IN1 ( divisor[11] ) , .Q ( n438 ) ) ; MUX21X1 U558 (.S ( n484 ) , .IN2 ( n433 ) , .IN1 ( n434 ) , .Q ( \transceiver/N95 ) ) ; AO21X1 U557 (.IN2 ( n432 ) , .IN1 ( divisor[10] ) , .IN3 ( n437 ) , .Q ( n433 ) ) ; MUX21X1 U556 (.S ( n484 ) , .IN2 ( n428 ) , .IN1 ( n429 ) , .Q ( \transceiver/N94 ) ) ; MUX21X1 U555 (.S ( n427 ) , .IN2 ( n298 ) , .IN1 ( divisor[9] ) , .Q ( n428 ) ) ; MUX21X1 U554 (.S ( n484 ) , .IN2 ( n423 ) , .IN1 ( n424 ) , .Q ( \transceiver/N93 ) ) ; AO21X1 U553 (.IN2 ( n422 ) , .IN1 ( divisor[8] ) , .IN3 ( n427 ) , .Q ( n423 ) ) ; MUX21X1 U552 (.S ( n484 ) , .IN2 ( n418 ) , .IN1 ( n419 ) , .Q ( \transceiver/N92 ) ) ; MUX21X1 U551 (.S ( n417 ) , .IN2 ( n302 ) , .IN1 ( divisor[7] ) , .Q ( n418 ) ) ; MUX21X1 U550 (.S ( n476 ) , .IN2 ( n413 ) , .IN1 ( n414 ) , .Q ( \transceiver/N91 ) ) ; AO21X1 U549 (.IN2 ( n412 ) , .IN1 ( divisor[6] ) , .IN3 ( n417 ) , .Q ( n413 ) ) ; MUX21X1 U548 (.S ( n476 ) , .IN2 ( n408 ) , .IN1 ( n409 ) , .Q ( \transceiver/N90 ) ) ; MUX21X1 U547 (.S ( n407 ) , .IN2 ( n295 ) , .IN1 ( divisor[5] ) , .Q ( n408 ) ) ; MUX21X1 U546 (.S ( n476 ) , .IN2 ( n403 ) , .IN1 ( n404 ) , .Q ( \transceiver/N89 ) ) ; AO21X1 U545 (.IN2 ( n402 ) , .IN1 ( divisor[4] ) , .IN3 ( n407 ) , .Q ( n403 ) ) ; AO221X1 U544 (.IN5 ( n476 ) , .Q ( n398 ) , .IN2 ( n397 ) , .IN1 ( n400 )


, .IN3 ( n400 ) , .IN4 ( n305 ) ) ; AO221X1 U543 (.IN5 ( n395 ) , .Q ( n399 ) , .IN2 ( n396 ) , .IN1 ( n402 ) , .IN3 ( n402 ) , .IN4 ( n294 ) ) ; MUX21X1 U542 (.S ( n476 ) , .IN2 ( n393 ) , .IN1 ( n394 ) , .Q ( \transceiver/N87 ) ) ; AO21X1 U541 (.IN2 ( n392 ) , .IN1 ( divisor[2] ) , .IN3 ( n396 ) , .Q ( n393 ) ) ; AO21X1 U540 (.IN2 ( n391 ) , .IN1 ( \transceiver/enable16_counter[2] ) , .IN3 ( n397 ) , .Q ( n394 ) ) ; NOR2X0 U539 (.QN ( n397 ) , .IN1 ( \transceiver/enable16_counter[2] ) , .IN2 ( n391 ) ) ; OR2X1 U538 (.IN2 ( \transceiver/enable16_counter[1] ) , .IN1 ( \transceiver/enable16_counter[0] ) , .Q ( n391 ) ) ; MUX21X1 U537 (.S ( n476 ) , .IN2 ( n389 ) , .IN1 ( n390 ) , .Q ( \transceiver/N86 ) ) ; MUX21X1 U536 (.S ( \transceiver/enable16_counter[1] ) , .IN2 ( \transceiver/enable16_counter[0] ) , .IN1 ( n306 ) , .Q ( n390 ) ) ; MUX21X1 U535 (.S ( n476 ) , .IN2 ( divisor[0] ) , .IN1 ( \transceiver/enable16_counter[0] ) , .Q ( n387 ) ) ; NOR2X0 U534 (.QN ( \transceiver/N190 ) , .IN1 ( sys_rst ) , .IN2 ( n386 ) ) ; OA222X1 U533 (.IN1 ( n476 ) , .IN5 ( n385 ) , .IN3 ( n476 ) , .IN2 ( \transceiver/enable16_counter[15] ) , .IN4 ( n452 ) , .IN6 ( n395 ) , .Q ( \transceiver/N100 ) ) ; MUX21X1 U532 (.S ( n453 ) , .IN2 ( n301 ) , .IN1 ( divisor[15] ) , .Q ( n385 ) ) ; NOR2X0 U531 (.QN ( n453 ) , .IN1 ( divisor[14] ) , .IN2 ( n454 ) ) ; NOR2X0 U530 (.QN ( n447 ) , .IN1 ( divisor[12] ) , .IN2 ( n442 ) ) ; NOR2X0 U529 (.QN ( n437 ) , .IN1 ( divisor[10] ) , .IN2 ( n432 ) ) ; NOR2X0 U528 (.QN ( n427 ) , .IN1 ( divisor[8] ) , .IN2 ( n422 ) ) ; NOR2X0 U527 (.QN ( n417 ) , .IN1 ( divisor[6] ) , .IN2 ( n412 ) ) ; NOR2X0 U526 (.QN ( n407 ) , .IN1 ( divisor[4] ) , .IN2 ( n402 ) ) ; NOR2X0 U525 (.QN ( n396 ) , .IN1 ( divisor[2] ) , .IN2 ( n392 ) ) ; OR2X1 U524 (.IN2 ( divisor[1] ) , .IN1 ( divisor[0] ) , .Q ( n392 ) ) ; AO222X1 U523 (.Q ( n193 ) , .IN2 ( \transceiver/tx_reg [6] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[6] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [7] ) ) ; AO222X1 U522 (.Q ( n194 ) , .IN2 ( \transceiver/tx_reg [5] ) , .IN1 ( n467 ) , .IN3 ( n466 ) , .IN4 ( csr_di[5] ) , .IN6 ( n465 ) , .IN5 ( \transceiver/tx_reg [6] ) ) ; assign csr_do[16] = 1'b0; endmodule


Netlist After Synthesis:

module uart_transceiver_DW01_dec_0 ( A, SUM );

input [15:0] A;

output [15:0] SUM;

wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n14, n15, n16, n17,

n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28;

INVX0 U1 ( .IN(n23), .QN(n12) );

INVX0 U2 ( .IN(n22), .QN(n11) );

INVX0 U3 ( .IN(n21), .QN(n10) );

INVX0 U4 ( .IN(n20), .QN(n9) );

INVX0 U5 ( .IN(n19), .QN(n8) );

INVX0 U6 ( .IN(n18), .QN(n7) );

INVX0 U7 ( .IN(n17), .QN(n6) );

INVX0 U8 ( .IN(n16), .QN(n5) );

INVX0 U9 ( .IN(n15), .QN(n4) );

INVX0 U10 ( .IN(n28), .QN(n3) );

INVX0 U11 ( .IN(n27), .QN(n2) );

INVX0 U12 ( .IN(n26), .QN(n1) );

INVX0 U13 ( .IN(A[0]), .QN(SUM[0]) );

INVX0 U14 ( .IN(A[14]), .QN(n14) );

AO21X1 U15 ( .IN1(A[9]), .IN2(n5), .IN3(n15), .Q(SUM[9]) );








AO21X1 U23 ( .IN1(A[1]), .IN2(A[0]), .IN3(n23), .Q(SUM[1]) );

XNOR2X1 U24 ( .IN1(n24), .IN2(A[15]), .Q(SUM[15]) );

NAND2X0 U25 ( .IN1(n25), .IN2(n14), .QN(n24) );

XNOR2X1 U26 ( .IN1(n14), .IN2(n25), .Q(SUM[14]) );


NOR2X0 U28 ( .IN1(n1), .IN2(A[13]), .QN(n25) );


NOR2X0 U30 ( .IN1(n2), .IN2(A[12]), .QN(n26) );



NOR2X0 U32 ( .IN1(n3), .IN2(A[11]), .QN(n27) );


NOR2X0 U34 ( .IN1(n4), .IN2(A[10]), .QN(n28) );

NOR2X0 U35 ( .IN1(n5), .IN2(A[9]), .QN(n15) );

NOR2X0 U36 ( .IN1(n6), .IN2(A[8]), .QN(n16) );

NOR2X0 U37 ( .IN1(n7), .IN2(A[7]), .QN(n17) );

NOR2X0 U38 ( .IN1(n8), .IN2(A[6]), .QN(n18) );

NOR2X0 U39 ( .IN1(n9), .IN2(A[5]), .QN(n19) );

NOR2X0 U40 ( .IN1(n10), .IN2(A[4]), .QN(n20) );

NOR2X0 U41 ( .IN1(n11), .IN2(A[3]), .QN(n21) );

NOR2X0 U42 ( .IN1(n12), .IN2(A[2]), .QN(n22) );

NOR2X0 U43 ( .IN1(A[1]), .IN2(A[0]), .QN(n23) );

endmodule

module uart_transceiver_DW01_dec_1 ( A, SUM );

input [15:0] A;

output [15:0] SUM;

wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n15, n16, n17,

n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28;

INVX0 U1 ( .IN(n23), .QN(n13) );

INVX0 U2 ( .IN(n22), .QN(n12) );

INVX0 U3 ( .IN(n21), .QN(n11) );

INVX0 U4 ( .IN(n20), .QN(n10) );

INVX0 U5 ( .IN(n19), .QN(n9) );

INVX0 U6 ( .IN(n18), .QN(n8) );

INVX0 U7 ( .IN(n17), .QN(n7) );

INVX0 U8 ( .IN(n16), .QN(n6) );

INVX0 U9 ( .IN(n15), .QN(n5) );

INVX0 U10 ( .IN(n28), .QN(n4) );

INVX0 U11 ( .IN(n27), .QN(n3) );

INVX0 U12 ( .IN(n26), .QN(n2) );

INVX0 U13 ( .IN(A[0]), .QN(SUM[0]) );

INVX0 U14 ( .IN(A[14]), .QN(n1) );










AO21X1 U23 ( .IN1(A[1]), .IN2(A[0]), .IN3(n23), .Q(SUM[1]) );

XNOR2X1 U24 ( .IN1(n24), .IN2(A[15]), .Q(SUM[15]) );


XNOR2X1 U26 ( .IN1(n1), .IN2(n25), .Q(SUM[14]) );


NOR2X0 U28 ( .IN1(n2), .IN2(A[13]), .QN(n25) );


NOR2X0 U30 ( .IN1(n3), .IN2(A[12]), .QN(n26) );


NOR2X0 U32 ( .IN1(n4), .IN2(A[11]), .QN(n27) );


NOR2X0 U34 ( .IN1(n5), .IN2(A[10]), .QN(n28) );

NOR2X0 U35 ( .IN1(n6), .IN2(A[9]), .QN(n15) );

NOR2X0 U36 ( .IN1(n7), .IN2(A[8]), .QN(n16) );

NOR2X0 U37 ( .IN1(n8), .IN2(A[7]), .QN(n17) );

NOR2X0 U38 ( .IN1(n9), .IN2(A[6]), .QN(n18) );

NOR2X0 U39 ( .IN1(n10), .IN2(A[5]), .QN(n19) );

NOR2X0 U40 ( .IN1(n11), .IN2(A[4]), .QN(n20) );

NOR2X0 U41 ( .IN1(n12), .IN2(A[3]), .QN(n21) );

NOR2X0 U42 ( .IN1(n13), .IN2(A[2]), .QN(n22) );

NOR2X0 U43 ( .IN1(A[1]), .IN2(A[0]), .QN(n23) );

endmodule

module uart_transceiver ( sys_rst, sys_clk, uart_rx, uart_tx, divisor, rx_data,

rx_done, tx_data, tx_wr, tx_done );

input [15:0] divisor;

output [7:0] rx_data;

input [7:0] tx_data;

input sys_rst, sys_clk, uart_rx, tx_wr;

output uart_tx, rx_done, tx_done;

wire N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31,

N32,

N33, N34, N36, N37, N38, N39, N40, N41, N42, N43, N44, N45, N46,

N47,

N48, N49, N50, N51, N85, N86, N87, N88, N89, N90, N91, N92, N93,

N94,


N95, N96, N97, N98, N99, N100, uart_rx2, uart_rx1, rx_busy, tx_busy,

N190, n19, n21, n22, n23, n24, n27, n28, n29, n30, n31, n32, n35, n36,

n37, n38, n39, n40, n41, n42, n43, n44, n46, n47, n48, n49, n50, n51,

n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65,

n66, n67, n68, n69, n70, n73, n74, n75, n76, n77, n78, n79, n80, n81,

n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,

n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,

n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,

n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,

n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,

n141, n142, n143, n144, n145, n146, n147, n148, n149, n1, n2, n3, n4,

n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n20,

n25, n26, n33, n34, n45, n71, n72;

wire [15:0] enable16_counter;

wire [3:0] rx_count16;

wire [3:0] rx_bitcount;

wire [7:0] rx_reg;

wire [3:0] tx_count16;

wire [3:0] tx_bitcount;

wire [7:0] tx_reg;

uart_transceiver_DW01_dec_0 sub_48 ( .A(enable16_counter), .SUM({N51,

N50,

N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37,

N36})

);

uart_transceiver_DW01_dec_1 r349 ( .A(divisor), .SUM({N34, N33, N32, N31,

N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19}) );

DFFX1 \rx_bitcount_reg[3] ( .D(n141), .CLK(sys_clk), .Q(rx_bitcount[3]),

.QN(n19) );

DFFX1 \rx_data_reg[7] ( .D(n125), .CLK(sys_clk), .Q(rx_data[7]) );







DFFX1 \rx_reg_reg[0] ( .D(n133), .CLK(sys_clk), .Q(rx_reg[0]) );

DFFX1 \tx_reg_reg[0] ( .D(n114), .CLK(sys_clk), .Q(tx_reg[0]) );

















DFFX1 \tx_bitcount_reg[1] ( .D(n117), .CLK(sys_clk), .Q(tx_bitcount[1]),

.QN(n29) );

DFFX1 \tx_count16_reg[3] ( .D(n123), .CLK(sys_clk), .Q(tx_count16[3]), .QN(

n30) );

DFFX1 uart_rx2_reg ( .D(uart_rx1), .CLK(sys_clk), .Q(uart_rx2) );

DFFX1 \rx_count16_reg[3] ( .D(n148), .CLK(sys_clk), .Q(rx_count16[3]) );


.QN(n23) );

DFFX1 \rx_count16_reg[0] ( .D(n149), .CLK(sys_clk), .Q(rx_count16[0]), .QN(

n27) );

DFFX1 \tx_bitcount_reg[2] ( .D(n116), .CLK(sys_clk), .Q(tx_bitcount[2]) );



n32) );


n31) );


.QN(n21) );

DFFX1 \tx_bitcount_reg[3] ( .D(n119), .CLK(sys_clk), .QN(n28) );


.QN(n22) );


DFFX1 \tx_bitcount_reg[0] ( .D(n118), .CLK(sys_clk), .Q(tx_bitcount[0]) );

DFFX1 \tx_count16_reg[2] ( .D(n120), .CLK(sys_clk), .Q(tx_count16[2]) );

DFFX1 rx_busy_reg ( .D(n147), .CLK(sys_clk), .Q(rx_busy), .QN(n24) );

DFFX1 tx_busy_reg ( .D(n122), .CLK(sys_clk), .Q(tx_busy) );


DFFX1 \enable16_counter_reg[15] ( .D(N100), .CLK(sys_clk), .Q(

enable16_counter[15]) );

























DFFX1 uart_tx_reg ( .D(n107), .CLK(sys_clk), .Q(uart_tx) );







DFFX1 tx_done_reg ( .D(N190), .CLK(sys_clk), .Q(tx_done) );

DFFX1 rx_done_reg ( .D(n14), .CLK(sys_clk), .Q(rx_done) );

DFFX1 uart_rx1_reg ( .D(uart_rx), .CLK(sys_clk), .Q(uart_rx1) );

NAND3X0 U3 ( .IN1(n60), .IN2(n71), .IN3(tx_busy), .QN(n59) );


INVX0 U5 ( .IN(n51), .QN(n6) );

INVX0 U6 ( .IN(n67), .QN(n18) );


INVX0 U7 ( .IN(n100), .QN(n13) );

AO22X1 U8 ( .IN1(N33), .IN2(n100), .IN3(N50), .IN4(n13), .Q(N99) );

NOR2X0 U9 ( .IN1(n43), .IN2(n42), .QN(n41) );

NOR2X0 U10 ( .IN1(n72), .IN2(n42), .QN(n40) );



NAND2X0 U13 ( .IN1(tx_wr), .IN2(n71), .QN(n44) );

INVX0 U14 ( .IN(tx_wr), .QN(n72) );

INVX0 U15 ( .IN(n64), .QN(n10) );

INVX0 U16 ( .IN(n49), .QN(n4) );

INVX0 U17 ( .IN(n57), .QN(n9) );

INVX0 U18 ( .IN(n43), .QN(n8) );

NAND4X0 U19 ( .IN1(n33), .IN2(n68), .IN3(n69), .IN4(n70), .QN(n67) );


INVX0 U21 ( .IN(n66), .QN(n14) );

INVX0 U22 ( .IN(n77), .QN(n16) );

INVX0 U23 ( .IN(n98), .QN(n20) );

INVX0 U24 ( .IN(n97), .QN(n33) );

INVX0 U25 ( .IN(n75), .QN(n17) );

INVX0 U26 ( .IN(n70), .QN(n45) );

INVX0 U27 ( .IN(n83), .QN(n26) );

AO21X1 U28 ( .IN1(n29), .IN2(n72), .IN3(n50), .Q(n47) );


OA21X1 U30 ( .IN1(n43), .IN2(sys_rst), .IN3(n44), .Q(n64) );

ISOLANDX1 U31 ( .D(n44), .ISO(n1), .Q(n42) );

NOR3X0 U32 ( .IN1(n38), .IN2(sys_rst), .IN3(n46), .QN(n1) );


NOR2X0 U34 ( .IN1(tx_count16[3]), .IN2(tx_count16[2]), .QN(n101) );

NAND3X0 U35 ( .IN1(n12), .IN2(n72), .IN3(tx_busy), .QN(n43) );

INVX0 U36 ( .IN(n91), .QN(n12) );

NAND3X0 U37 ( .IN1(n10), .IN2(n72), .IN3(tx_count16[0]), .QN(n57) );

NAND3X0 U38 ( .IN1(n6), .IN2(n72), .IN3(tx_bitcount[0]), .QN(n49) );

AO222X1 U39 ( .IN1(tx_data[0]), .IN2(n40), .IN3(tx_reg[1]), .IN4(n41), .IN5(

tx_reg[0]), .IN6(n42), .Q(n114) );


tx_reg[1]), .IN6(n42), .Q(n113) );


tx_reg[2]), .IN6(n42), .Q(n112) );


tx_reg[3]), .IN6(n42), .Q(n111) );



tx_reg[4]), .IN6(n42), .Q(n110) );


tx_reg[5]), .IN6(n42), .Q(n109) );


tx_reg[6]), .IN6(n42), .Q(n108) );




AO22X1 U49 ( .IN1(uart_tx), .IN2(n35), .IN3(n36), .IN4(n7), .Q(n107) );


INVX0 U51 ( .IN(n35), .QN(n7) );

NOR2X0 U52 ( .IN1(n39), .IN2(sys_rst), .QN(n35) );

AO22X1 U53 ( .IN1(tx_bitcount[2]), .IN2(n47), .IN3(n48), .IN4(tx_bitcount[1]),

.Q(n116) );

NOR2X0 U54 ( .IN1(tx_bitcount[2]), .IN2(n49), .QN(n48) );

AO22X1 U55 ( .IN1(tx_count16[2]), .IN2(n55), .IN3(n56), .IN4(tx_count16[1]),

.Q(n120) );

NOR2X0 U56 ( .IN1(tx_count16[2]), .IN2(n57), .QN(n56) );

AO22X1 U57 ( .IN1(n64), .IN2(tx_count16[0]), .IN3(n65), .IN4(n10), .Q(n124)

);

NAND2X0 U58 ( .IN1(tx_count16[0]), .IN2(n72), .QN(n65) );

AO22X1 U59 ( .IN1(tx_count16[1]), .IN2(n58), .IN3(n9), .IN4(n31), .Q(n121)

);

AO22X1 U60 ( .IN1(tx_bitcount[0]), .IN2(n51), .IN3(n52), .IN4(n6), .Q(n118)

);

NOR2X0 U61 ( .IN1(tx_wr), .IN2(tx_bitcount[0]), .QN(n52) );

AO22X1 U62 ( .IN1(n42), .IN2(tx_reg[7]), .IN3(tx_data[7]), .IN4(n40), .Q(

n115) );

AO22X1 U63 ( .IN1(tx_bitcount[1]), .IN2(n50), .IN3(n4), .IN4(n29), .Q(n117)

);


OAI21X1 U65 ( .IN1(n38), .IN2(tx_reg[0]), .IN3(n8), .QN(n37) );

NOR3X0 U66 ( .IN1(n61), .IN2(sys_rst), .IN3(n46), .QN(N190) );


OR2X1 U68 ( .IN1(n61), .IN2(n46), .Q(n60) );

OAI21X1 U69 ( .IN1(tx_bitcount[0]), .IN2(tx_wr), .IN3(n6), .QN(n50) );

OAI21X1 U70 ( .IN1(n62), .IN2(n30), .IN3(n63), .QN(n123) );

NAND4X0 U71 ( .IN1(tx_count16[2]), .IN2(tx_count16[1]), .IN3(n9), .IN4(n30),

.QN(n63) );


OA21X1 U72 ( .IN1(tx_wr), .IN2(tx_count16[2]), .IN3(n11), .Q(n62) );

INVX0 U73 ( .IN(n55), .QN(n11) );

OAI21X1 U74 ( .IN1(n53), .IN2(n28), .IN3(n54), .QN(n119) );

NAND4X0 U75 ( .IN1(tx_bitcount[2]), .IN2(tx_bitcount[1]), .IN3(n4), .IN4(n28),

.QN(n54) );

OA21X1 U76 ( .IN1(tx_wr), .IN2(tx_bitcount[2]), .IN3(n5), .Q(n53) );

INVX0 U77 ( .IN(n47), .QN(n5) );

INVX0 U78 ( .IN(sys_rst), .QN(n71) );


NOR4X0 U80 ( .IN1(enable16_counter[12]), .IN2(enable16_counter[11]), .IN3(

enable16_counter[10]), .IN4(enable16_counter[0]), .QN(n103) );





AO21X1 U83 ( .IN1(n68), .IN2(rx_busy), .IN3(n79), .Q(n77) );

NAND3X0 U84 ( .IN1(rx_bitcount[0]), .IN2(n77), .IN3(n33), .QN(n75) );

NAND4X0 U85 ( .IN1(uart_rx2), .IN2(n33), .IN3(n68), .IN4(n45), .QN(n66) );


AO21X1 U87 ( .IN1(uart_rx2), .IN2(n24), .IN3(n91), .Q(n99) );













AO22X1 U100 ( .IN1(n87), .IN2(rx_busy), .IN3(n88), .IN4(n15), .Q(n147) );

NOR2X0 U101 ( .IN1(sys_rst), .IN2(rx_busy), .QN(n88) );

INVX0 U102 ( .IN(n87), .QN(n15) );

ISOLANDX1 U103 ( .D(n89), .ISO(n79), .Q(n87) );

AO22X1 U104 ( .IN1(n16), .IN2(rx_bitcount[0]), .IN3(n78), .IN4(n33), .Q(n144)

);

NOR2X0 U105 ( .IN1(rx_bitcount[0]), .IN2(n16), .QN(n78) );

AO22X1 U106 ( .IN1(rx_bitcount[2]), .IN2(n73), .IN3(n74), .IN4(


rx_bitcount[1]), .Q(n142) );

NOR2X0 U107 ( .IN1(rx_bitcount[2]), .IN2(n75), .QN(n74) );

AO22X1 U108 ( .IN1(rx_bitcount[1]), .IN2(n76), .IN3(n17), .IN4(n22), .Q(n143)

);

AO22X1 U109 ( .IN1(rx_reg[0]), .IN2(n14), .IN3(rx_data[0]), .IN4(n66), .Q(

n132) );


n131) );


n130) );


n129) );


n128) );


n127) );


n126) );


n125) );

AO22X1 U117 ( .IN1(n18), .IN2(uart_rx2), .IN3(rx_reg[7]), .IN4(n67), .Q(n140)

);

AO22X1 U118 ( .IN1(n18), .IN2(rx_reg[1]), .IN3(rx_reg[0]), .IN4(n67), .Q(

n133) );


n134) );


n135) );


n136) );


n137) );


n138) );


n139) );

NOR4X0 U125 ( .IN1(n91), .IN2(rx_count16[0]), .IN3(n102),

.IN4(rx_count16[1]), .QN(n68) );

OR2X1 U126 ( .IN1(rx_count16[3]), .IN2(rx_count16[2]), .Q(n102) );




NAND2X0 U129 ( .IN1(rx_busy), .IN2(n71), .QN(n97) );

AO221X1 U130 ( .IN1(n80), .IN2(n26), .IN3(rx_count16[2]), .IN4(n81), .IN5(

n82), .Q(n145) );

NOR2X0 U131 ( .IN1(rx_count16[2]), .IN2(n84), .QN(n80) );


AO221X1 U133 ( .IN1(n85), .IN2(rx_count16[0]), .IN3(rx_count16[1]),

.IN4(n86), .IN5(n82), .Q(n146) );



NOR2X0 U136 ( .IN1(n84), .IN2(rx_busy), .QN(n82) );




NAND4X0 U139 ( .IN1(rx_count16[2]), .IN2(n26), .IN3(n95), .IN4(n33),

.QN(n94) );

OAI21X1 U140 ( .IN1(n96), .IN2(n20), .IN3(rx_count16[3]), .QN(n93) );



OR3X1 U143 ( .IN1(rx_busy), .IN2(uart_rx2), .IN3(n91), .Q(n90) );

AO21X1 U144 ( .IN1(n2), .IN2(rx_bitcount[3]), .IN3(n3), .Q(n141) );


AND4X1 U146 ( .IN1(rx_bitcount[2]), .IN2(rx_bitcount[1]), .IN3(n17), .IN4(

n19), .Q(n3) );

AOI21X1 U147 ( .IN1(n26), .IN2(rx_count16[2]), .IN3(n97), .QN(n96) );

AO221X1 U148 ( .IN1(n25), .IN2(n27), .IN3(n20), .IN4(rx_count16[0]), .IN5(

n82), .Q(n149) );

INVX0 U149 ( .IN(n84), .QN(n25) );

NAND4X0 U150 ( .IN1(rx_bitcount[3]), .IN2(rx_bitcount[0]), .IN3(n22), .IN4(

n21), .QN(n70) );


NAND2X0 U152 ( .IN1(rx_count16[1]), .IN2(rx_count16[0]), .QN(n83) );

NOR3X0 U153 ( .IN1(tx_bitcount[1]), .IN2(tx_bitcount[2]), .IN3(n28), .QN(n38)

);

NAND2X0 U154 ( .IN1(tx_bitcount[0]), .IN2(n38), .QN(n61) );

NAND3X0 U155 ( .IN1(rx_busy), .IN2(n92), .IN3(n68), .QN(n89) );

AO21X1 U156 ( .IN1(n34), .IN2(uart_rx2), .IN3(n45), .Q(n92) );

INVX0 U157 ( .IN(n69), .QN(n34) );

endmodule


module uart ( sys_clk, sys_rst, csr_a, csr_we, csr_di, csr_do, rx_irq, tx_irq,

uart_rx, uart_tx );

input [13:0] csr_a;

input [31:0] csr_di;

output [31:0] csr_do;

input sys_clk, sys_rst, csr_we, uart_rx;

output rx_irq, tx_irq, uart_tx;

wire csr_a_1, csr_a_0, uart_tx_transceiver, tx_wr, thru, N80, N81, N82,

N83, N84, N85, N86, N87, N88, N89, N90, N91, N92, N93, N94, N95, n1,

n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,

n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n35, n36,

n37, n38, n39, n40;

wire [15:0] divisor;

wire [7:0] rx_data;

assign csr_a_1 = csr_a[1];

assign csr_a_0 = csr_a[0];

assign csr_do[31] = 1'b0;
















uart_transceiver transceiver ( .sys_rst(sys_rst), .sys_clk(sys_clk),

.uart_rx(uart_rx), .uart_tx(uart_tx_transceiver), .divisor(divisor),

.rx_data(rx_data), .rx_done(rx_irq), .tx_data(csr_di[7:0]), .tx_wr(

tx_wr), .tx_done(tx_irq) );

DFFX1 \divisor_reg[15] ( .D(n32), .CLK(sys_clk), .Q(divisor[15]) );














DFFX1 thru_reg ( .D(n33), .CLK(sys_clk), .Q(thru), .QN(n1) );




DFFX1 \csr_do_reg[15] ( .D(N95), .CLK(sys_clk), .Q(csr_do[15]) );
















NBUFFX32 U69 ( .IN(n35), .Q(uart_tx) );

AO22X1 U70 ( .IN1(uart_rx), .IN2(thru), .IN3(uart_tx_transceiver), .IN4(n1),

.Q(n35) );

INVX0 U71 ( .IN(n14), .QN(n38) );


AND2X1 U73 ( .IN1(n16), .IN2(n7), .Q(n15) );

INVX0 U74 ( .IN(n8), .QN(n39) );

AND3X1 U75 ( .IN1(csr_we), .IN2(n6), .IN3(n7), .Q(tx_wr) );

NOR4X0 U76 ( .IN1(csr_a[11]), .IN2(csr_a[10]), .IN3(csr_a[13]), .IN4(


csr_a[12]), .QN(n6) );

NOR2X0 U77 ( .IN1(csr_a_0), .IN2(csr_a_1), .QN(n7) );

AND3X1 U78 ( .IN1(n16), .IN2(n40), .IN3(csr_a_1), .Q(n13) );


AND3X1 U80 ( .IN1(csr_we), .IN2(n6), .IN3(n11), .Q(n36) );

AO222X1 U81 ( .IN1(rx_data[0]), .IN2(n15), .IN3(n13), .IN4(thru), .IN5(n38),

.IN6(divisor[0]), .Q(N80) );


AO22X1 U83 ( .IN1(divisor[0]), .IN2(n8), .IN3(csr_di[0]), .IN4(n9), .Q(n17)

);


);


);


);


);


);

AO22X1 U89 ( .IN1(divisor[10]), .IN2(n8), .IN3(csr_di[10]), .IN4(n9), .Q(n27) );






AO22X1 U95 ( .IN1(n38), .IN2(divisor[1]), .IN3(rx_data[1]), .IN4(n15), .Q(

N81) );


N82) );


N83) );


N84) );


N85) );


N86) );


N87) );


AO22X1 U102 ( .IN1(n37), .IN2(csr_di[0]), .IN3(thru), .IN4(n12), .Q(n33) );

INVX0 U103 ( .IN(n12), .QN(n37) );

NAND2X0 U104 ( .IN1(n13), .IN2(csr_we), .QN(n12) );

AO221X1 U105 ( .IN1(divisor[1]), .IN2(n8), .IN3(csr_di[1]), .IN4(n39), .IN5(

sys_rst), .Q(n18) );







ISOLANDX1 U109 ( .D(n6), .ISO(sys_rst), .Q(n16) );

ISOLANDX1 U110 ( .D(divisor[8]), .ISO(n14), .Q(N88) );








NOR2X0 U118 ( .IN1(n40), .IN2(csr_a_1), .QN(n11) );

INVX0 U119 ( .IN(csr_a_0), .QN(n40) );

endmodule


Reports:

After FP:

Power:

****************************************

Report : power

-analysis_effort low

Design : cuart

Version: E-2010.12-ICC-SP5-3

Date : Wed Apr 25 15:24:39 2012

****************************************

Library(s) Used:

saed90nm_typ (File:

/home/111060752015/pract/dvd2_assign_3/ref/models/saed90nm_typ.db)

Operating Conditions: TYPICAL Library: saed90nm_typ

Wire Load Model Mode: top

Global Operating Voltage = 1.2

Power-specific unit information :

Voltage Units = 1V

Capacitance Units = 1.000000pf

Time Units = 1ns

Dynamic Power Units = 1mW (derived from V,C,T units)

Leakage Power Units = 1pW

Cell Internal Power = 290.9029 uW (85%)

Net Switching Power = 53.0924 uW (15%)

---------

Total Dynamic Power = 343.9954 uW (100%)

Cell Leakage Power = 14.7794 uW


QOR:

Information: The design has horizontal rows, and Y-symmetry has been used

for sites. (MWDC-217)

Floorplan loading succeeded.

****************************************

Report : qor

Design : cuart


Date : Wed Apr 25 15:24:50 2012

****************************************

Timing Path Group 'sys_clk'

-----------------------------------

Levels of Logic: 4.00

Critical Path Length: 0.66

Critical Path Slack: 0.50

Critical Path Clk Period: 6.66

Total Negative Slack: 0.00

No. of Violating Paths: 0.00

Worst Hold Violation: 0.00

Total Hold Violation: 0.00

No. of Hold Violations: 0.00

-----------------------------------

Cell Count

-----------------------------------

Hierarchical Cell Count: 0

Hierarchical Port Count: 0

Leaf Cell Count: 353

Buf/Inv Cell Count: 19

CT Buf/Inv Cell Count: 0

Combinational Cell Count: 257

Sequential Cell Count: 96

Macro Count: 0

-----------------------------------


Area

-----------------------------------

Combinational Area: 2220.389009

Noncombinational Area: 2831.167999

Net Area: 0.000000

Net XLength : 0.00

Net YLength : 0.00

-----------------------------------

Cell Area: 5051.557008

Design Area: 5051.557008

Net Length : 0.00

Design Rules

-----------------------------------

Total Number of Nets: 399

Nets With Violations: 2

Max Trans Violations: 1

-----------------------------------

Hostname: localhost.localdomain

Compile CPU Statistics

-----------------------------------------

Resource Sharing: 0.22

Logic Optimization: 0.74

Mapping Optimization: 2.43

-----------------------------------------

Overall Compile Time: 5.34

Overall Compile Wall Clock Time: 5.82


Timing:

****************************************

Report : timing

-path full

-delay max

-max_paths 1

Design : cuart


Date : Wed Apr 25 15:25:17 2012

****************************************


Startpoint: uart_rx (input port clocked by sys_clk)

Endpoint: uart_tx (output port clocked by sys_clk)

Path Group: sys_clk

Path Type: max

Point Incr Path

-----------------------------------------------------------

clock sys_clk (rise edge) 0.00 0.00

clock network delay (ideal) 0.00 0.00

input external delay 1.50 1.50 r

uart_rx (in) 0.00 1.50 r

U393/Q (MUX21X1) 0.07 1.57 r

U568/Q (MUX21X1) 0.08 1.65 r

U304/QN (INVX0) 0.09 1.73 f

U305/QN (INVX8) 0.42 2.16 r

uart_tx (out) 0.00 2.16 r

data arrival time 2.16



clock uncertainty -2.50 4.16

output external delay -1.50 2.66

data required time 2.66

-----------------------------------------------------------


data arrival time -2.16

-----------------------------------------------------------


slack (MET) 0.50

Area:

****************************************

Report : area

Design : cuart


Date : Wed Apr 25 15:25:02 2012

****************************************

Library(s) Used:

saed90nm_typ (File:

/home/111060752015/pract/dvd2_assign_3/ref/models/saed90nm_typ.db)

Number of ports: 87

Number of nets: 399

Number of cells: 353

Number of combinational cells: 257

Number of sequential cells: 96

Number of macros: 0

Number of buf/inv: 19

Number of references: 27

Combinational area: 2220.389009

Noncombinational area: 2831.167999

Net Interconnect area: undefined (No wire load specified)

Total cell area: 5051.557008

Total area: undefined

1


After Placement:

Timing:

****************************************

Report : timing

-path full

-delay max

-max_paths 1

Design : cuart


Date : Mon Apr 23 10:58:32 2012

****************************************

* Some/all delay information is back-annotated.


Startpoint: Scan_Enable

(input port clocked by sys_clk)


Path Group: sys_clk

Path Type: max

Point Incr Path

-----------------------------------------------------------



input external delay 1.50 1.50 f

Scan_Enable (in) 0.00 1.50 f

U304/Q (NBUFFX2) 0.09 * 1.59 f

U568/Q (MUX21X1) 0.11 * 1.70 r

U313/QN (INVX0) 0.04 * 1.74 f

U312/QN (INVX2) 0.05 * 1.79 r

U318/QN (INVX16) 0.03 * 1.82 f

U319/QN (INVX32) 0.12 * 1.94 r

uart_tx (out) 0.02 * 1.96 r








-----------------------------------------------------------



-----------------------------------------------------------

slack (MET) 0.70

Power:

****************************************

Report : power


Design : cuart


Date : Mon Apr 23 10:58:18 2012

****************************************

Library(s) Used:

saed90nm_typ (File:

/home/111060752015/dvd2_assign_3/ref/models/saed90nm_typ.db)





Voltage Units = 1V


Time Units = 1ns






---------



Area:

****************************************

Report : area

Design : cuart


Date : Mon Apr 23 10:58:56 2012

****************************************

Library(s) Used:

saed90nm_typ (File:


Number of ports: 87

Number of nets: 406




Number of macros: 0









Qor:

Information: The design has horizontal rows, and Y-symmetry has been used

for sites. (MWDC-217)

Floorplan loading succeeded.

****************************************

Report : qor

Design : cuart


Date : Mon Apr 23 10:58:44 2012

****************************************


-----------------------------------










-----------------------------------

Cell Count

-----------------------------------








Macro Count: 0


-----------------------------------

Area

-----------------------------------



Net Area: 0.000000

Net XLength : 4569.23

Net YLength : 5477.69

-----------------------------------

Cell Area: 5151.479008


Net Length : 10046.92

Design Rules

-----------------------------------




-----------------------------------



-----------------------------------------




-----------------------------------------




After CTS:

Power:

****************************************

Report : power


Design : cuart


Date : Mon Apr 23 11:03:44 2012

****************************************

Library(s) Used:

saed90nm_typ (File:






Voltage Units = 1V


Time Units = 1ns





---------




Timing:

****************************************

Report : timing

-path full

-delay max

-max_paths 1

Design : cuart


Date : Mon Apr 23 11:03:55 2012

****************************************



Startpoint: thru_reg (rising edge-triggered flip-flop clocked by sys_clk)


Path Group: sys_clk

Path Type: max

Point Incr Path

-----------------------------------------------------------


clock network delay (propagated) 1.51 1.51

thru_reg/CLK (SDFFX1) 0.00 1.51 r

thru_reg/Q (SDFFX1) 0.23 1.74 f

U393/Q (MUX21X1) 0.10 * 1.84 r

U568/Q (MUX21X1) 0.08 * 1.92 r

U313/QN (INVX0) 0.04 * 1.96 f

U312/QN (INVX2) 0.02 * 1.98 r

U318/QN (INVX2) 0.08 * 2.07 f

U319/QN (INVX32) 0.02 * 2.09 r

U323/QN (INVX32) 0.02 * 2.11 f

U322/QN (INVX32) 0.02 * 2.12 r

U321/QN (INVX32) 0.01 * 2.14 f

U320/QN (INVX32) 0.12 * 2.25 r

uart_tx (out) 0.03 * 2.28 r








-----------------------------------------------------------



-----------------------------------------------------------

slack (MET) 0.38

QOR:

****************************************

Report : qor

Design : cuart


Date : Mon Apr 23 11:04:07 2012

****************************************


-----------------------------------










-----------------------------------

Cell Count

-----------------------------------









Macro Count: 0

-----------------------------------

Area

-----------------------------------



Net Area: 0.000000



-----------------------------------

Cell Area: 5307.289003



Design Rules

-----------------------------------




-----------------------------------



-----------------------------------------




-----------------------------------------




Area:

****************************************

Report : area

Design : cuart


Date : Mon Apr 23 11:04:16 2012

****************************************

Library(s) Used:

saed90nm_typ (File:


Number of ports: 87

Number of nets: 410




Number of macros: 0









After Routed:

Power:

****************************************

Report : power


Design : cuart


Date : Mon Apr 23 11:07:53 2012

****************************************

Library(s) Used:

saed90nm_typ (File:






Voltage Units = 1V


Time Units = 1ns





---------




Timing:

****************************************

Report : timing

-path full

-delay max

-max_paths 1

Design : cuart


Date : Mon Apr 23 11:07:39 2012

****************************************



Startpoint: thru_reg (rising edge-triggered flip-flop clocked by sys_clk)


Path Group: sys_clk

Path Type: max

Point Incr Path

-----------------------------------------------------------


clock network delay (propagated) 1.50 1.50

thru_reg/CLK (SDFFX1) 0.00 1.50 r

thru_reg/Q (SDFFX1) 0.23 1.74 f

U393/Q (MUX21X1) 0.10 * 1.84 r

U568/Q (MUX21X1) 0.08 * 1.92 r

U313/QN (INVX0) 0.04 * 1.96 f

U312/QN (INVX2) 0.02 * 1.98 r

U318/QN (INVX2) 0.08 * 2.06 f

U319/QN (INVX32) 0.02 * 2.08 r

U323/QN (INVX32) 0.02 * 2.10 f

U322/QN (INVX32) 0.02 * 2.12 r

U321/QN (INVX32) 0.02 * 2.13 f

U320/QN (INVX32) 0.12 * 2.25 r

uart_tx (out) 0.02 * 2.27 r








-----------------------------------------------------------



-----------------------------------------------------------

slack (MET) 0.39

Area:

****************************************

Report : area

Design : cuart


Date : Mon Apr 23 11:07:20 2012

****************************************

Library(s) Used:

saed90nm_typ (File:


Number of ports: 87

Number of nets: 410




Number of macros: 0








1


QOR:

****************************************

Report : qor

Design : cuart


Date : Mon Apr 23 11:07:29 2012

****************************************


-----------------------------------










-----------------------------------

Cell Count

-----------------------------------








Macro Count: 0

-----------------------------------

Area

-----------------------------------




Net Area: 0.000000



-----------------------------------

Cell Area: 5307.289003



Design Rules

-----------------------------------




-----------------------------------



-----------------------------------------




-----------------------------------------




Tetramax Reports

Reports of Faults: Uncollapsed Stuck Fault Summary Report

-----------------------------------------------

fault class code #faults

------------------------------ ---- ---------

Detected DT 3040

Possibly detected PT 0

Undetectable UD 70

ATPG untestable AU 0

Not detected ND 0

-----------------------------------------------

total faults 3110

test coverage 100.00%

-----------------------------------------------

Pattern Summary Report

-----------------------------------------------

#internal patterns 53

#basic_scan patterns 53

-----------------------------------------------

Report of Patterns

Pattern Summary Report

-----------------------------------------------

#internal patterns 53

#basic_scan patterns 53

-----------------------------------------------


STIL File:

STIL 1.0 { Design 2005; }

Header {

Title " TetraMAX (TM) E-2010.12-SP5-i110710_172605 STIL output";

Date "Wed Apr 25 16:39:12 2012";

Source "Minimal STIL for design `cuart'";

History {

Ann {* Mon Apr 23 15:36:22 2012 *}

Ann {* DFT Compiler E-2010.12-SP5-2 *}

Ann {* Uncollapsed Stuck Fault Summary Report *}

Ann {* ----------------------------------------------- *}

Ann {* fault class code #faults *}

Ann {* ------------------------------ ---- --------- *}

Ann {* Detected DT 3040 *}

Ann {* Possibly detected PT 0 *}

Ann {* Undetectable UD 70 *}

Ann {* ATPG untestable AU 0 *}

Ann {* Not detected ND 0 *}

Ann {* ----------------------------------------------- *}

Ann {* total faults 3110 *}

Ann {* test coverage 100.00% *}

Ann {* ----------------------------------------------- *}

Ann {* *}

Ann {* Pattern Summary Report *}

Ann {* ----------------------------------------------- *}

Ann {* #internal patterns 53 *}

Ann {* #basic_scan patterns 53 *}

Ann {* ----------------------------------------------- *}

Ann {* *}

Ann {* rule severity #fails description *}

Ann {* ---- -------- ------ --------------------------------- *}

Ann {* B8 warning 25 unconnected module input pin *}

Ann {* B10 warning 16 unconnected module internal net *}

Ann {* *}

Ann {* clock_name off usage *}

Ann {* ---------------- --- -------------------------- *}

Ann {* sys_clk 0 master shift *}

Ann {* *}


Ann {* port_name constraint_value *}

Ann {* ---------------- --------------- *}

Ann {* Test_Mode 1 *}

Ann {* *}

Ann {* There are no equivalent pins *}

Ann {* There are no net connections *}

Ann {* Unified STIL Flow *}

Ann {* n_shifts = 2 *}

Ann {* serial_flag = 0 *}

Ann {* Automatic Shift Registers Identification enabled *}

}

}

Signals {

"sys_clk" In; "sys_rst" In; "csr_a[13]" In; "csr_a[12]" In; "csr_a[11]" In;

"csr_a[10]" In;

"csr_a[9]" In; "csr_a[8]" In; "csr_a[7]" In; "csr_a[6]" In; "csr_a[5]" In; "csr_a[4]"

In;

"csr_a[3]" In; "csr_a[2]" In; "csr_a[1]" In; "csr_a[0]" In; "csr_we" In; "csr_di[31]"

In;

"csr_di[30]" In; "csr_di[29]" In; "csr_di[28]" In; "csr_di[27]" In; "csr_di[26]" In;






"csr_di[0]" In; "uart_rx" In { ScanIn; } "Scan_Enable" In; "Test_Mode" In;

"csr_do[31]" Out;

"csr_do[30]" Out; "csr_do[29]" Out; "csr_do[28]" Out; "csr_do[27]" Out;

"csr_do[26]" Out;


"csr_do[21]" Out;


"csr_do[16]" Out;


"csr_do[11]" Out;

"csr_do[10]" Out; "csr_do[9]" Out; "csr_do[8]" Out; "csr_do[7]" Out; "csr_do[6]"

Out;

"csr_do[5]" Out; "csr_do[4]" Out; "csr_do[3]" Out; "csr_do[2]" Out; "csr_do[1]"

Out;

"csr_do[0]" Out; "rx_irq" Out; "tx_irq" Out; "uart_tx" Out { ScanOut; }


}

SignalGroups {

"_pi" = '"Scan_Enable" + "Test_Mode" + "csr_a[0]" + "csr_a[10]" + "csr_a[11]" +

"csr_a[12]" + "csr_a[13]" + "csr_a[1]" + "csr_a[2]" + "csr_a[3]" + "csr_a[4]" +

"csr_a[5]" + "csr_a[6]" + "csr_a[7]" + "csr_a[8]" + "csr_a[9]" + "csr_di[0]" +

"csr_di[10]" + "csr_di[11]" + "csr_di[12]" + "csr_di[13]" + "csr_di[14]" +






"csr_di[9]" + "csr_we" + "sys_clk" + "sys_rst" + "uart_rx"'; // #signals=52

"_in" = '"sys_clk" + "sys_rst" + "csr_a[13]" + "csr_a[12]" + "csr_a[11]" +


"csr_a[4]" + "csr_a[3]" + "csr_a[2]" + "csr_a[1]" + "csr_a[0]" + "csr_we" +







"csr_di[1]" + "csr_di[0]" + "uart_rx" + "Scan_Enable" + "Test_Mode"'; //

#signals=52

"all_inputs" = '"Scan_Enable" + "Test_Mode" + "csr_a[0]" + "csr_a[10]" +

"csr_a[11]" + "csr_a[12]" + "csr_a[13]" + "csr_a[1]" + "csr_a[2]" +


"csr_a[9]" + "csr_di[0]" + "csr_di[10]" + "csr_di[11]" + "csr_di[12]" +






"csr_di[7]" + "csr_di[8]" + "csr_di[9]" + "csr_we" + "sys_clk" + "sys_rst" +

"uart_rx"'; // #signals=52

"_po" = '"csr_do[0]" + "csr_do[10]" + "csr_do[11]" + "csr_do[12]" +

"csr_do[13]" + "csr_do[14]" + "csr_do[15]" + "csr_do[16]" + "csr_do[17]" +






"csr_do[7]" + "csr_do[8]" + "csr_do[9]" + "rx_irq" + "tx_irq" + "uart_tx"'; //

#signals=35

"_si" = '"uart_rx"' { ScanIn; } // #signals=1

"all_outputs" = '"csr_do[0]" + "csr_do[10]" + "csr_do[11]" + "csr_do[12]" +







#signals=35

"all_ports" = '"all_inputs" + "all_outputs"'; // #signals=87

"_clk" = '"sys_clk"'; // #signals=1

"_so" = '"uart_tx"' { ScanOut; } // #signals=1

"_out" = '"csr_do[31]" + "csr_do[30]" + "csr_do[29]" + "csr_do[28]" +







#signals=35

}

Timing {

WaveformTable "_allclock_launch_capture_WFT_" {

Period '100ns';

Waveforms {

"all_inputs" { 0 { '0ns' D; } }

"all_inputs" { 1 { '0ns' U; } }

"all_inputs" { Z { '0ns' Z; } }

"all_inputs" { N { '0ns' N; } }

"all_outputs" { X { '0ns' X; '40ns' X; } }

"all_outputs" { H { '0ns' X; '40ns' H; } }

"all_outputs" { L { '0ns' X; '40ns' L; } }

"all_outputs" { T { '0ns' X; '40ns' T; } }

"sys_clk" { P { '0ns' D; '45ns' U; '55ns' D; } }

}

}

WaveformTable "_multiclock_capture_WFT_" {

Period '100ns';


Waveforms {

"all_inputs" { 0 { '0ns' D; } }

"all_inputs" { 1 { '0ns' U; } }








}

}

WaveformTable "_allclock_launch_WFT_" {

Period '100ns';

Waveforms {

"all_inputs" { 0 { '0ns' D; } }

"all_inputs" { 1 { '0ns' U; } }








}

}

WaveformTable "_allclock_capture_WFT_" {

Period '100ns';

Waveforms {

"all_inputs" { 0 { '0ns' D; } }

"all_inputs" { 1 { '0ns' U; } }








}

}


WaveformTable "_default_WFT_" {

Period '100ns';

Waveforms {

"all_inputs" { 0 { '0ns' D; } }

"all_inputs" { 1 { '0ns' U; } }








}

}

}

ScanStructures {

ScanChain "1" {

ScanLength 96;

ScanIn "uart_rx";

ScanOut "uart_tx";

ScanInversion 0;

ScanCells "cuart.\transceiver/uart_rx1_reg .SI" !

"cuart.\transceiver/uart_rx2_reg .D" !

"cuart.\transceiver/rx_reg_reg[7] .D" "cuart.\transceiver/rx_reg_reg[6] .D"




"cuart.\transceiver/tx_reg_reg[7] .SI" "cuart.\transceiver/tx_reg_reg[6] .D"

"cuart.\transceiver/tx_reg_reg[5] .D" "cuart.\transceiver/tx_reg_reg[4] .D"



"cuart.\csr_do_reg[0] .SI" "cuart.\csr_do_reg[1] .SI" "cuart.\csr_do_reg[2]

.SI"


.SI"


.SI"


.SI"


"cuart.\csr_do_reg[12] .SI" "cuart.\csr_do_reg[13] .SI"

"cuart.\csr_do_reg[14] .SI"

"cuart.\csr_do_reg[15] .SI" "cuart.\divisor_reg[0] .SI" "cuart.\divisor_reg[1]

.SI"

"cuart.\divisor_reg[2] .SI" "cuart.\divisor_reg[3] .SI" "cuart.\divisor_reg[4]

.SI"


.SI"


.SI"

"cuart.\divisor_reg[11] .SI" "cuart.\divisor_reg[12] .SI"

"cuart.\divisor_reg[13] .SI"

"cuart.\divisor_reg[14] .SI" "cuart.\divisor_reg[15] .SI" "cuart.thru_reg.SI"

"cuart.\transceiver/enable16_counter_reg[0] .SI"
















"cuart.\transceiver/rx_bitcount_reg[0] .SI"



"cuart.\transceiver/rx_bitcount_reg[3] .SI" "cuart.\transceiver/rx_busy_reg

.SI"

"cuart.\transceiver/rx_count16_reg[0] .SI"





"cuart.\transceiver/rx_data_reg[0] .SI" "cuart.\transceiver/rx_data_reg[1]

.SI"


.SI"


.SI"


.SI"

"cuart.\transceiver/rx_done_reg .SI" "cuart.\transceiver/tx_bitcount_reg[0]

.SI"

"cuart.\transceiver/tx_bitcount_reg[1] .SI"

"cuart.\transceiver/tx_bitcount_reg[2] .SI"

"cuart.\transceiver/tx_bitcount_reg[3] .SI" "cuart.\transceiver/tx_busy_reg

.SI"

"cuart.\transceiver/tx_count16_reg[0] .SI"




"cuart.\transceiver/uart_tx_reg .SI" "cuart.\transceiver/tx_done_reg .SI" ;

ScanMasterClock "sys_clk" ;

}

}

PatternBurst "_burst_" {

PatList { "_pattern_" {

}

}}

PatternExec {

PatternBurst "_burst_";

}

Procedures {

"multiclock_capture" {

W "_multiclock_capture_WFT_";

F { "Test_Mode"=1; }

C { "all_inputs"=N1\r47 N 01N;

"all_outputs"=\r35 X ; }

V { "_pi"=\r52 # ; "_po"=\r35 # ; }

}

"allclock_capture" {

W "_allclock_capture_WFT_";





V { "_pi"=\r52 # ; "_po"=\r35 # ; }

}

"allclock_launch" {

W "_allclock_launch_WFT_";




V { "_pi"=\r52 # ; "_po"=\r35 # ; }

}

"allclock_launch_capture" {

W "_allclock_launch_capture_WFT_";




V { "_pi"=\r52 # ; "_po"=\r35 # ; }

}

"load_unload" {

W "_default_WFT_";



"Internal_scan_pre_shift": V { "Scan_Enable"=1; }

Shift { W "_default_WFT_";

V { "_clk"=P; "_si"=#; "_so"=#; }

}

}

}

MacroDefs {

"test_setup" {

W "_default_WFT_";

C { "all_inputs"=\r52 N ;


V { "Test_Mode"=1; "sys_clk"=0; "sys_rst"=1; }

V { }

}

}

Pattern "_pattern_" {


W "_multiclock_capture_WFT_";

"precondition all Signals": C { "_pi"=\r52 0 ; "_po"=\r35 X ; }

Macro "test_setup";

Ann {* chain_test *}

"pattern 0": Call "load_unload" {

"uart_rx"=001100110011001100110011001100110011001100110011001100

110011001100110011001100110011001100110011; }

Call "multiclock_capture" {

"_pi"=1100111111000110100010101001010111010110000110110011;

"_po"=LHHLLHHLLLLLLLLLLLLLLLHLLHLLHHLLHLL; }


"uart_tx"=LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH

LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH;

"uart_rx"=000010110111111111111101001110000000000000001111111111

000000000101010110101011110111101010100110; }


"_pi"=0111110010001100111111110001101110101010001101110P11;

"_po"=HHLHLHLLLLLHLLLLLLLLLLLLLHLHLHHLHLH; }


"uart_tx"=LHLLHLLHLHHLHHHHHHHHLLLLLLLLLHHHHHHHLHHHHHHHLHL

LLLLLLLLLHHLHHLLLLLLLLLLLLLLLLLHHLHHHHLHLHLHLLHLH;

"uart_rx"=100011101000101010101110011110000000000000001100100001

000100000000000110100111001010110101011011; }


"_pi"=0110000011011111101000001011001010000110011101110P00;

"_po"=HLLLLLLLLLLHLLLLLLLLLLHLLLLHLHHLLHL; }


"uart_tx"=LLLLLLHLHLLLHLHLHLHLHHHLLHHHHLLHLLLLHLLLLHHHLHLLHL

LLLHLLLHLLLLLLHLLLLHLLLHLLLLLLHLHLHHLHLHLHHLHL;

"uart_rx"=100010101111111110000000110010000000000000001011011110

110010001010100010111011101011010000100011; }



"_pi"=0100000101111001110010111100000011011100111101011P01;

"_po"=HLHLHLHLLLLHLLLLLLLLLLLLLHHHLHLLHHL; }


"uart_tx"=LHLLHHHLHLLHLLLHLLLLLLLHLHLHLHHLHHHHLHHLLLHHLHHHL

HHHHLHHLLHLLLLLLLLLLLLLLLLLLLLHLHHLHLLLLLHLLLHH;

"uart_rx"=110010101010010000000000110000000000000000001011011000

000000001111101110111101110100101110110111; }


"_pi"=0110000000110100011111110001010001101111110111111P01;

"_po"=HLHHHHHLLLLLLLLLLLLLLLHLLHHHLHHHLHH; }


"uart_tx"=LHLLHHHHLHLLLHLLLLLLLLLHHHLLHHHLHLHHHHHHHHHHLLHH

HHHHHHHHHLHHHLHHLHHLLLLLLLLLLLHLHLLHLLHHLHHLHHHH;

"uart_rx"=100101011111101111010111001000000000000001111001000000

000000001111011001110110010001010001011101; }


"_pi"=0110000001101000100000000000100011011101001000001P01;

"_po"=LHLHHHHLLLLHLLLLLLLLLLHLLLHHHLLHHHL; }


"uart_tx"=LLLHLHLHHHHLHLHHHHLHLHHHLLHLLLLLLLLLLLLLLHHLLLLLLL

LLLLLLLHLLLHLHLLLLLLLLLLLLLLLHLLLHLHLLLHLHHHHH;

"uart_rx"=010010111011001000000000100000000000000000001000001010

000000000100011000011010001110001111010111; }


"_pi"=0110000000010111111111101010010001101000010110110P00;

"_po"=LHLLLHLLLLLHLLLLLLLLLLLLLHHLLLLHHLH; }


"uart_tx"=LLLLHHHLLHLLLLHLLLLLLLLHLLLLHLLLLHLLHHHHHHHHLLLLLLH

LHLLLLLLLLLLLLLHLHLLLLLLLLLLHHHLLLLHHHHLHLHHL;

"uart_rx"=000000010110011111101101110011111100000000001100100010

101001111000110000010000110111010111111111; }



"_pi"=0100000000101111011111010100100011010000101000111P01;

"_po"=LHHLLLHLLLLLLLLLLLLLLLLLLLHLLLLLLLH; }


"uart_tx"=LLLLHHHLLHLLLHHHHHHLHHLHHHLLHHHHHLHHHHHHHHHHLH

LLHLLLHLHLHLLHHHLLLLLLLLLHHHHHHLLLLLHLLLLHHHHHHHHH;

"uart_rx"=100001110100100000010000110110000000000000001110111000

001000001011001101001001011101111100110110; }


"_pi"=0100000010011000111100000010010001110111011101000P01;

"_po"=HLLHHLHLLLLLLLLLLLLLLLLLLHLLHLHHLHH; }


"uart_tx"=LLLHHLHHLHLLHLLLLLLHLLLHHHHLLHLHHHLLLLLLHHHHLHHLH

HHLLLLLHLLLLLLLLLLLLLHLLLLLLHLHHHLHHHHLLHHLHHLH;

"uart_rx"=001111111001010010010011111110000000000000001010000000

000000000110011110100010101110111110010000; }


"_pi"=0100000000110001111000000101100011101110110111011P01;

"_po"=LHLLHHLLLLLHLLLLLLLLLLLLLLLHLHHHHLL; }


"uart_tx"=LLLLHHHLLHLLLHLLHLLHLHLLHHHHHLHHHHHHHHHHHHHHLLH

LLLLLLLLLLLLLLLLLLLLLLLLHLLHLLHHHHHLHHHHHHLLHLLLH;

"uart_rx"=000101110011101000100000101110000000000000001010001111

111111011100111010100100000111000111010000; }


"_pi"=0110111101100010110000001010000111011001010000111P10;

"_po"=LHHLLHHLLLLLLLLLLLLLLLHLLLLHLHLHHLL; }


"uart_tx"=LHLHLHLHLLHLHLHLLLHLLLLLLLLLLHLLLHHHHHHHHHHLHLLLLL

LLLLLLHHLHHLLLLLLLLLLLLLLLLLLLLHHHLLLHHHLHLLLL;

"uart_rx"=010110101010111100111011110001011001011011001100000100

010000100011011110010100100101100100111111; }



"_pi"=0100000000000010000010111100011001100000101111001P10;

"_po"=LHLHHLLLLLLLLLLLLLLLLLHLLLHLLHHHLLL; }


"uart_tx"=LHLHHLLLHLHLHHHHLLHHLLLLLLLLLLLLLLHLLLHLLLLLLHLLLLLL

LLLLHHLHHLLLLLLLLLLLLLLLLLHLLHLHHLLHLLHHHHHL;

"uart_rx"=110010110010110000100000110111011111111111001100101101

111111111100010000111101010100100101000111; }


"_pi"=0110000011000011100111010000100100010101110000111P01;

"_po"=HHLLLHHLLLLLLLLLLLLLLLHLLHHHLLLLLHH; }


"uart_tx"=LHLLHLHHLLHLHHLLLLHLLLLLHHLHHHLHHHHHHHHHHLHHLHL

HHHLLHHLLLLHLLHLLHLHHLHHHHHHHHHLHLHLLHLLHLHLLLHHH;

"uart_rx"=100010101000001111011111001110000000000000001010100100

100000001000100101100001001010011010100000; }


"_pi"=0110001010000110101110100011001000101111010001101P01;

"_po"=HLHLLLHLLLLLLLLLLLLLLLLLLLLHHLHLLHL; }


"uart_tx"=LLLLHHHLHLHLLLHHHHLHLHHHHLLLLHLHLLHLLLHHHHHHLLHL

HLLHLLHLLLLLLLLLLLLLLLLLLLLLLLLHLHLLHLHLHLHLLLLH;

"uart_rx"=101110010010001101100001100011100101000000001110100000

001110111011100001011011100011001010001001; }


"_pi"=0100000111001011011111101100000110001000100101110P00;

"_po"=HLHHHLHLLLLHLLLLLLLLLLLLLHHLHLLLLHL; }


"uart_tx"=LLHHHLLHLLHLLLHHLHHLLLLHHLLLHHHLLHLLHHHHHHHHLHHL

HLLLLLLLHHHLHHLLLLLLLLLLLLLLLHHLLLHHLLHLHLLLHLHL;

"uart_rx"=011101100100010110101110111000000000000000001010010000

000000000111000110011010110001111101000101; }



"_pi"=0101000010010110011111011000001100010001101011111P00;

"_po"=LLLHHHLLLLLHLLLLLLLLLLLLLHHLLHHLLLH; }


"uart_tx"=LHLLHLHLLHLLLHLHHLHLHHHHHHHLLHLLLHHHHHHHHHHHLLH

LLHLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHLLLHHHHHLHLLLHHL;

"uart_rx"=011010101101110011000111101000000000000000001101000000

000000000100100011101001011110111001111001; }


"_pi"=0110100011101010111100111001001111110011110001001P01;

"_po"=HLHLLHLLLLLLLLLLLLLLLLLLLHLHHHLLHLH; }


"uart_tx"=LHHLHHHLHHLLHHLLHHLLHLLLHLHLLLLHHHHHHHHHHHHHLHL

HLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHLHHHLLHHHHLHH;

"uart_rx"=000010100011101111110000100100000000000000001111110110

101000110011101110100010111001010011110100; }


"_pi"=0110010000010011011010011000001000110001000100101P00;

"_po"=LLHHHLLLLLLHLLLLLLLLLLLLLLLHLHHHHLL; }


"uart_tx"=LHLLHHHLHHLLHLHHHHHHLLLHHLLHHHHHHLHHLHLHLLLHHHH

HHHLHHLHLHLLLHHLLLLLLLLLLLLLLLLHHLLHLHLLHHHHLHLLL;

"uart_rx"=100001011100101000111010010000000000000000001100000000

000000000111011011011110111100101001110000; }


"_pi"=0100111000100110010100110000010001100100101001010P10;

"_po"=LHLHHHLLLLLHLLLLLLLLLLHLLHHLHHLHLHL; }


"uart_tx"=LHLLLHLHHHLLHLHLLLHHLLLLLLLLLHHHHHHHHHHHHHHHLHLL

LLLLLLLLHHLHHLLLLLLLLLLLLLLLLLHHHHLLHLHLLHHHLLLL;

"uart_rx"=010010010010110111101101010010010010101011101101100010

000000001110110111010000011110011100111000; }



"_pi"=0100000101001100001001100000100011001001010010111P00;

"_po"=LHHLHHHLLLLLLLLLLLLLLLLLLLHLHHHLLLL; }


"uart_tx"=LHLLHLLHLLHLHHLHHHHLHHLHLHLLHLLHLLHLHLHLHHLHLLLH

HLLLHLLLLLLLLLLLLLLLLLLLLLLLLHLHHHHLLHHHLLHHHLLL;

"uart_rx"=001010101000110100000000110010000000000000001110001010

000001001101101001101110101111001110011111; }


"_pi"=0110000010011001010011000010000110010110000101100P10;

"_po"=LLHHLHHLLLLHLLLLLLLLLLHLLHLHHLLHLLL; }


"uart_tx"=LHHLHLLLHLLLHHLHLLLLLLLLLLLLLHLLLHLHLLLLLLLHLHLLLLLL

LLLLHHLHHLLLLLLLLLLLLLLLLLHLHHHHLLHHHLLHHHHL;

"uart_rx"=111001000010011011110000010011000000000000001000101000

000000101011010001101001010111101111001101; }


"_pi"=0100000000110011000110000101001100101000001011011P00;

"_po"=HHLHHLHLLLLLLLLLLLLLLLLLLHLHHLLLLHH; }


"uart_tx"=LLLLHHHLLHLLLHHLHHHHLLLLLHLLHLHHHHHHHHHHHHHHLLLL

HLHLLLLLLLLLHLLLLLLLLLLHHLHHHHLHLLHLHHHHHHLLHHHL;

"uart_rx"=010010110111001111100000111110000000000000001110100000

000000001100001001110011001101101000111100; }


"_pi"=0111010110100001001110100001001110000110010000010P01;

"_po"=HLLLLHHLLLLHLLLLLLLLLLLLLLHHHLLHHLH; }


"uart_tx"=HHLLHHLHLLLLLLHHHHHLLLLHHLLLLHLLHHHHHHHHHHHHLHH

LHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHLHHLLLLHHHHLLH;

"uart_rx"=100010110100001000000000110010000000000000001101000100

000000000010111111011010110000111111011110; }



"_pi"=0110010010000101011111101000001011011100000110011P01;

"_po"=LHHLHLLLLLLHLLLLLLLLLLLLLHHLHHHHLHH; }


"uart_tx"=LHLLHHHHLHHHHHHLHHHHLLLHLHLHLLHLLLLHHHHHHHHHLHL

HLLLHLLLLLLLLLLLLLLLLLLLLLLLLLLHHLLLLHHHHHHLHHHLH;

"uart_rx"=110100100010100011000001110110000000000000001001010110

010000001111010011010111011110000110111001; }


"_pi"=0110011011001100111101111001000001101110101010001P01;

"_po"=HHLHHHHLLLLHLLLLLLLLLLHLLLHLHHLLLHH; }


"uart_tx"=LHLHLHHLLLHLHLLLHHLLLLHLHHLHHLHLHLHHLLLHHHHHLLLHL

HLHHLLHLLLLLLLLLLLLLLLLLLLLLLLHHHHLLLLHHLHHHLHH;

"uart_rx"=000110110111110101100000110010000000000000001101011111

100011011110100101000110101111010011011110; }


"_pi"=0100111110011000111011110001000011011001110100010P01;

"_po"=LLHLHHHLLLLHLLLLLLLLLLHLLLLLHLHLHLH; }


"uart_tx"=LLLHHHHHLHHHHHHLHHLLLLLHLHLHLLHLHHHHHHLLLHHLHHL

HLHHHHHHLLLHHLHLLLLLLLLLLLLLLLLHLHHHHLHLLHHLHHHLH;

"uart_rx"=110111100000000100000000101000000000000000001001000110

111111110111100010101110010001111010110110; }


"_pi"=0111000111110110010101001001010001100001001110000P00;

"_po"=LLHHHHLLLLLHLLLLLLLLLLHLLHLHLHLLLHH; }


"uart_tx"=LHLHLLHLLLLLLLLHLLLLLLLHHLHLHLHLLLHHLHHHHHHHHLLHLL

LHHLHHHHHHHHLLLLLLLLLLLLLLLLLHLLLHHHLHLHHLHHLL;

"uart_rx"=000001101100101011111001000100010000000000001100000000

000000001111000000001001001000110011011000; }



"_pi"=0100000111101101101010010000100011000100011100011P00;

"_po"=HLLHHHHLLLLLLLLLLLLLLLLLLHLLLLLLLLL; }


"uart_tx"=LLLLLHHLHHLLHLHLHHHHHLLHLLLHLLLLHHHHHHHHHHHHLHLL

LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLHLLLHHLLHHLHHLLL;

"uart_rx"=111101000110010111110110010111100110100110001101010111

101100010100101000010011100010010110110100; }


"_pi"=0110110000011100110110001011010001011100111110010P00;

"_po"=HLHLLHLLLLLHLLLLLLLLLLLLLLHLLLLHLHL; }


"uart_tx"=LHHHLHLLLHHLLHLHHHHHLHHLLHLHHHHLLHHLHLLHLHHHLHL

HLHLHHHHLHHLLLHLLLLLLLLLLLLLLLLHLLLHLLHLHHLHHLHLL;

"uart_rx"=011001111001000100111111001000001101010000000101011100

011010101001010110101111110001011011011010; }


"_pi"=0101100000111000101100010100100010111011011100111P01;

"_po"=HHLHLLHLLLLHLLLLLLLLLLHLLHLHLHHLHLH; }


"uart_tx"=LHHLLHHHHLLLLLLHLLHHHHHHLLHLLLLLHHLHLHLLLLLLHHLHL

HHHLLLHHLHLHLLLLLLLLLLLLLLLLLHHLLLHLHHLHHLHHLLH;

"uart_rx"=100101001010101011100000100010000000000000001101110011

100001010010101010001001011000101101101110; }


"_pi"=0111001001110001011000101011000101110110111001100P01;

"_po"=HLHLHLLLLLLLLLLLLLLLLLLLLHLLLHLHLHH; }


"uart_tx"=LLLHLHLLHLHLHLHLHHHLLLLHHLLHLLHHHLLHHHLLLLHLHHLHH

HLLHHHLLLLHLHLLLLLLLLLLLLLLLLLHHLLLHLHLHHLHHHLH;

"uart_rx"=100010111111100010010000111010000000000000001111001110

001100100101010101010111001100011110110111; }



"_pi"=0110011011100011110001010101001011101011010011010P00;

"_po"=HHLHLHLLLLLHLLLLLLLLLLHLLLHLHLHLHHL; }


"uart_tx"=LLLLHHHHHLLLHLLLHLLHLLLHHHHHLHHLLHHHLLLHHLLLLHHHL

LHHHLLLHHLLHLLLLLLLLLLLLLLLLLLHHLLLHLHHLHHLHHHL;

"uart_rx"=100101110000110011110100110010000000000000001001000100

010101010000110010110110110000011111010010; }


"_pi"=0111110000110011000111000001101101001111100110100P01;

"_po"=LHHLLLLLLLLHLLLLLLLLLLHLLLHHLHLLLHL; }


"uart_tx"=LLHLHLHHLLLLHHLLHHHHLHLHHHLLHLHLLLHLLLHLHLHLHLLHL

LLHLLLHLHLHLHLLLLLLLLLLLLLLLLHHLLLLLHHHHHLHLLLH;

"uart_rx"=000010100101101101100010110010000000000000001100010001

010110100001100111100110011000010111101010; }


"_pi"=0111101001100111101110000011011010011101001101001P00;

"_po"=LLHHLLLLLLLHLLLLLLLLLLHLLLLHHHHLHLL; }


"uart_tx"=LLLLHHHLLHHLHLHHLHHLLLHHHHLLHLLLHLLLHLHLHHLLLHLLL

HLLLHLHLHHLHLLLLLLLLLLLLLLLLLHHLLLLHLLHHHHLHLLL;

"uart_rx"=110010110011001010011000110010000000000000001000000001

100100010011111011101101101100010100100111; }


"_pi"=0110100011111100111011000101011001110011011100100P00;

"_po"=HHHHHLLLLLLLLLLLLLLLLLHLLHLHHHLHHHH; }


"uart_tx"=LHLLHHHHHHLLLLHLHLLHHLLHHHLLHLLLLLLLHHLLHLLLHLLLLL

LLLHHLLHLLLHLLLLLLLLLLLLLLLLLHHLLLHLLHLLHLLHHL;

"uart_rx"=110010101011001000101001000000110001001001100001000000

001111110111000000100011100110011001000000; }



"_pi"=1100000011001011110001001000011110101001111111111P00;

"_po"=HLLHHHLLLLLHLLLLLLLLLLLLLLLHLLLLHHH; }


"uart_tx"=HLLHLHLHLHHLLHLLLHLHLLHLLLLLLHHLLLHLLHLLHHLLLLHLLLL

LLLLHHHHHHLHHHLLLLLLHLLLHHHLLHHLLHHLLHLLLLLLL;

"uart_rx"=011001110010111011010000100110000000000000001101000100

100000111110110010100110000011001001110001; }


"_pi"=0110010110100101000101010001010000011000011001011P00;

"_po"=LHHLHHHLLLLHLLLLLLLLLLHLLLLHLHLLLLL; }


"uart_tx"=LHHHHLHHLLHLHHHLHHLHLLLHHLHLLLHLLLHLLHLLLLLHHHLHL

LLHLLHLLLLLHHLLLLLLLLLLLLLLLLLLLLHHLLLLHHHLLLHL;

"uart_rx"=111110100001101001100000101110000000000000001100010010

001011111101100011110110100001101100111010; }


"_pi"=0110101101001010101010100000100000110010110010100P00;

"_po"=LLHHLHHLLLLHLLLLLLLLLLHLLLHHHHLLHHL; }


"uart_tx"=LHHHHHHLLLLLHLHLLHHLLLLHHHLLLLLLHLLHLLLHLHHHHHLLL

HLLHLLLHLHHHHLLLLLLLLLLLLLLLLHLLLLHHLHLLHHHLHLL;

"uart_rx"=011100110000001110011111101110000000000000001000001100

110010101011110011100101100000100001001101; }


"_pi"=0100101010100111010010000010101100101100100011101P00;

"_po"=HHHHHLHLLLLLLLLLLLLLLLHLLLLHHHLLLLH; }


"uart_tx"=LHHHLHHHLLLLLLHHHLLHLLLLHLHHHLLLLHHLLHHLLHLLLLLLLL

HHLLHHLLHLHLLLLLLLLLLLLLLLLLHLLLLLHLLLLHLLHHHL;

"uart_rx"=110111100001111001010000100000000000000000001000110011

101011010111100010011101110000000000100100; }



"_pi"=0101010101001110000100000110011001011001100111010P00;

"_po"=HLHHHHLLLLLLLLLLLLLLLLHLLHHLLHLLHHH; }


"uart_tx"=LHLHLLHLLLLLHHHLLHLHLLLHHLLLHLLHHLLHHHLHLHHLHLLLH

HLLHHHLHLHHLHLLLLLLLLLLLLLLLLHHLLLLLLLLLLHLLHLL;

"uart_rx"=011101110001010100100000110010000000000000001010001000

111011111111110001000101101000001111010001; }


"_pi"=0101010010101110001111001101011111111010101000000P01;

"_po"=HHHHHHHLLLLLLLLLLLLLLLHLLLLLHLLLHLH; }


"uart_tx"=LHLLHLHHLLLLLHLHLLHLLLLHLHLHLHLLLHLLLHHHLHHHHLHLLL

HLLLHHHLHHHHLLLLLLLLLLLLLLLLHLHLLLLLHHHHLHLLHH;

"uart_rx"=110111100000010001000101011011010100000001010000100011

101111111111100000101000010100000111100000; }


"_pi"=0100100101011101111110011001111111110001010000000P00;

"_po"=LLHHHHHLLLLLLLLLLLLLLLLLLHLHLLLLLHH; }


"uart_tx"=LHLHHHHLLLLLLHLLLHLLLHLHLHHLHHLHLHLLLLLLLHLHHLLLHL

LLHHHLHHHHHHLLLLLLLLLLLLLLLLLHLHLLLLLHHHHLLLLL;

"uart_rx"=100000100100001010001111100100000000000100001010001110

111111111111000100100010101010010011110011; }


"_pi"=0111000010111010111100110010111111100110000000010P01;

"_po"=LLLHHHHLLLLHLLLLLLLLLLLLLLLHLLHLLHL; }


"uart_tx"=LLLLLLHLLHLLLLHLHLLLHHHHHLLHLLLLLLLLLLLLHHHHLLHLLLH

HHLHHHHHHHHLLLLLLLLLLLLLLLLHLHLHLLHLLHHHHLLHH;

"uart_rx"=011001001001111011011111111101001111101000001001111111

101000101110111010100011100101001110101010; }



"_pi"=0111111101000110011110100110010010000111100110011P00;

"_po"=HHHLHHHLLLLHLLLLLLLLLLLLLLLHLHLHHLH; }


"uart_tx"=LHHLLHLLHLLLHHHLHHLHHHHHHHHHLHLLHHHHHLLHHHHHLLL

HHHHHHHHLHLLLHLLLLLLLLLLLLLLLLLHLLHLHLLHHHLHLHLLL;

"uart_rx"=101100110111011011010011000001001100010000001110111010

011100001101000101000001100010111000000110; }


"_pi"=0100000010111110011010001100001001000010001010011P01;

"_po"=HLLHLHHLLLLLLLLLLLLLLLLLLLLLHLHLHHH; }


"uart_tx"=LLLLHHHLLHLLLHHLHHLHLLHHLLLLLHLLHHLLLLHHHHHHLHHLH

HHLHLLHHHLLLLLLLLLLLLLHHLHHLHLLHLHLHLHLLLLLLHLH;

"uart_rx"=101011011000010000010001111000000000100000001011101010

000000001010001010110111010001011100000010; }


"_pi"=0100000101111100010100011001010010000000110100110P00;

"_po"=HLLLHLHLLLLHLLLLLLLLLLHLLLHHLHLHLHL; }


"uart_tx"=LLHLHHLHHLLLLHLLLLLHLLLHHHHLLLLLLLLLLHHHHHHHLLHHH

LHLHLLLLLLLLLLLLLLLLLLLLLLLLLLHLLLHLHHHLLLLLLLL;

"uart_rx"=101110011110011110010000010010000010000000001111101000

000000000100100100010110111000101001010011; }


"_pi"=0101111011001011101111110001001001001100101111010P01;

"_po"=LLHLLHLLLLLHLLLLLLLLLLHLLLHLLLHLLHH; }


"uart_tx"=LLHHHLLHHHHLLHHHHLLHLLLLLHLLHLLLLLLHHHHHHHHHLHHH

HLHLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHLLLHLHLLHLHLLHH;

"uart_rx"=011111010010000101101000110000011000000000001110101101

011111001001001110111100011100011100101011; }



"_pi"=0101110110010111111111100000010010011001011110100P01;

"_po"=LLLHLLHLLLLLLLLLLLLLLLHLLHHHLHHHLLH; }


"uart_tx"=LHHHHHLHLLHLLLLHLHHLHLLLHHLLLLLHLHHHHHHHHHHHLHH

LHLHHLHLHHHHHLLLLLLLLLLLLLLLLLLLHHHLLLHHHLLHLHLHH;

"uart_rx"=100010111100011100110001011100100000000000001011111001

100011000010101010111100111110010001000111; }


"_pi"=0100011100011100011000000001001001111001111011110P00;

"_po"=LLHLHLLLLLLLLLLLLLLLLLHLLHHHLHLHLHL; }


"uart_tx"=LLLLHLHHHHLLLHHHLLHHLLLHLHHHLLLHHHHHHHHHHHHHLLH

HHHHLLHHLLLHHLLLLLLLLLLLLLLLLLLHHHHHLLHLLLHLLLHHL;

"uart_rx"=011011001111011100100000010110000000000000001110000010

111001010101100100001110101111001111110011; }


"_pi"=0101001000001011110111000001111110111000110001010P01;

"_po"=LLHHLHLLLLLHLLLLLLLLLLHLLHLLLLHLHLH; }


"uart_tx"=LHHLHHLLHHHLLHHHLLHLLLLLLHLHHHLLLLLHLHHHLLHLHHHLL

LLLHLHHHLLHLHLLLLLLLLLLLLLLLLHLHHHHLLHHHHHHLLHH;

"uart_rx"=011101110010000011101111110100000000000000101000001001

001101101011001100111000110111101111111011; }


"_pi"=0100011000010111101110000010111101110011000010110P01;

"_po"=LLLHHLHLLLLLLLLLLLLLLLLLLHHHLLHHLLH; }


"uart_tx"=LHHHLHHHLLHLLLLLHHHLHHHHHHLHLLLLLLLLLLLLLLLHLLLLLL

HLLHLLHHLHHLLLLLLLLLLLLLLLLLHHLHHHHLHHHHHHHLHH;

"uart_rx"=101111100101001110001111000010101110001100011000100110

010011010110011100000111011011100111111100; }



"_pi"=0100111000101110011100000111111011100100000101100P01;

"_po"=HHLLHHLLLLLHLLLLLLLLLLHLLLLLLLHHHHL; }


"uart_tx"=LLHHHHHLLHLLLLHHHLLLHHHHLLLLHLHLHHHLLLHHLLLLLLLLH

LLHHLLHLLHHLHLLLLLLLLLLLLLLLLLHHLHHHLLHHHHHHHLH;

"uart_rx"=110001010100000001110110101011001100011001110010011011

100110101100111000011101101101100011111111; }


"_pi"=1111110001011100111000001110110111001000001011010P00;

"_po"=HHHLLHHLLLLLLLLLLLLLLLHLLHHLLLLHLHH; }

"end 52 unload": Call "load_unload" {

"uart_tx"=HLLLHLHLHLLLLLLLHHHLHHLHLHLHHLLHHLLLHHLLHHHLLHLLH

HLHHHLLHHLHLHHLLHHHLLLLHHHLHHLHHLHHLLLHHHHHHHHL; }

}

// Patterns reference 163 V statements, generating 5293 test cycles

Tetramax Testbench:

// Verilog STILDPV testbench written by TetraMAX (TM) E-2010.12-SP5-

i110710_172605

// Date: Wed Apr 25 16:39:12 2012

// Module tested: cuart

`timescale 1 ns / 1 ns

module cuart_test;

integer verbose; // message verbosity level

integer report_interval; // pattern reporting intervals

integer diagnostic_msg; // format miscompares for TetraMAX diagnostics

parameter NINPUTS = 52, NOUTPUTS = 35;

// The next two variables hold the current value of the TetraMAX pattern

number

// and vector number, while the simulation is progressing. $monitor or

$display these

// variables, or add them to waveform views, to see these values change with

time


integer pattern_number;

integer vector_number;

wire sys_clk; reg sys_clk_REG ;

wire sys_rst; reg sys_rst_REG ;

wire csr_we; reg csr_we_REG ;

wire rx_irq;

wire tx_irq;

wire uart_rx; reg uart_rx_REG ;

wire uart_tx;

wire Scan_Enable; reg Scan_Enable_REG ;

wire Test_Mode; reg Test_Mode_REG ;

wire [13:0] csr_a;

reg [13:0] csr_a_REG;

wire [31:0] csr_di;

reg [31:0] csr_di_REG;

wire [31:0] csr_do;

// map register to wire for DUT inputs and bidis

assign sys_clk = sys_clk_REG ;

assign sys_rst = sys_rst_REG ;

assign csr_a = csr_a_REG;

assign csr_we = csr_we_REG ;

assign csr_di = csr_di_REG;

assign uart_rx = uart_rx_REG ;

assign Scan_Enable = Scan_Enable_REG ;

assign Test_Mode = Test_Mode_REG ;

// instantiate the design into the testbench

cuart dut (

.sys_clk(sys_clk),

.sys_rst(sys_rst),

.csr_a(csr_a),

.csr_we(csr_we),

.csr_di(csr_di),

.csr_do(csr_do),

.rx_irq(rx_irq),

.tx_irq(tx_irq),

.uart_rx(uart_rx),

.uart_tx(uart_tx),


.Scan_Enable(Scan_Enable),

.Test_Mode(Test_Mode) );

// STIL Direct Pattern Validate Access

initial begin

//

// --- establish a default time format for %t

//

$timeformat(-9,2," ns",18);

vector_number = 0;

//

// --- default verbosity to 0; use '+define+tmax_msg=N' on verilog compile

line to change.

//

ìfdef tmax_msg

verbose = `tmax_msg ;

èlse

verbose = 0 ;

èndif

//

// --- default pattern reporting interval is every 5 patterns;

// use '+define+tmax_rpt=N' on verilog compile line to change.

//

ìfdef tmax_rpt

report_interval = `tmax_rpt ;

èlse

report_interval = 5 ;

èndif

//

// --- support generating Extened VCD output by using

// '+define+tmax_vcde' on verilog compile line.

//

ìfdef tmax_vcde

// extended VCD, see Verilog specification, IEEE Std. 1364-2001 section

18.3

if (verbose >= 1) $display("// %t : opening Extended VCD output file",

$time);


$dumpports( dut, "sim_vcde.out");

èndif

//

// --- default miscompare messages are not formatted for TetraMAX

diagnostics;

// use '+define+tmax_diag=N' on verilog compile line to format errors for

diagnostics.

//

ìfdef tmax_diag

diagnostic_msg = `tmax_diag ;

èlse

diagnostic_msg = 0 ;

èndif

// '+define+tmax_parallel=N' on the command line overrides default

simulation, using parallel load

// with N serial vectors at the end of each Shift

// '+define+tmax_serial=M' on the command line forces M initial serial

patterns,

// followed by the remainder in parallel (with N serial vectors if

tmax_parallel is also specified)

// +define+tmax_par_force_time on the command line overrides default

parallel check/load time

ìfdef tmax_par_force_time

$STILDPV_parallel(,,,`tmax_par_force_time);

èndif

// TetraMAX parallel-mode simulation required for these patterns

ìfdef tmax_parallel

// +define+tmax_serial_timing on the command line overrides default

minimal-time for parallel load behavior

ìfdef tmax_serial_timing

èlse

$STILDPV_parallel(,,0); // apply minimal time advance for parallel

load_unload

// if tmax_serial_timing is defined, use equivalent serial load_unload

time advance

èndif


ìfdef tmax_serial

$STILDPV_parallel(`tmax_parallel,`tmax_serial);

èlse

$STILDPV_parallel(`tmax_parallel,0);

èndif

èlse

ìfdef tmax_serial




èlse


load_unload


time advance

èndif

$STILDPV_parallel(0,`tmax_serial);

èlse




èlse


load_unload


time advance

èndif

// default parallel mode with 2 serial vectors at end of each Shift.

$STILDPV_parallel(2,0);

èndif

èndif

if (verbose>3) $STILDPV_trace(1,1,1,1,1,report_interval,diagnostic_msg);

// verbose=4; + trace each Vector

else if (verbose>2)

$STILDPV_trace(1,0,1,1,1,report_interval,diagnostic_msg); // verbose=3; +

trace labels

else if (verbose>1)


trace WFT-changes


else if (verbose>0)


trace proc/macro entries

else $STILDPV_trace(0,0,0,0,0,report_interval,diagnostic_msg); //

verbose=0; only pattern-interval

$STILDPV_setup( "all_pats.stil",,,"cuart_test.dut" );

while ( !$STILDPV_done()) #($STILDPV_run( pattern_number,

vector_number ));

$display("Time %t: STIL simulation data completed.",$time);

$finish; // comment this out if you terminate the simulation from other

activities

end

// STIL Direct Pattern Validate Trace Options

// The STILDPV_trace() function takes '1' to enable a trace and '0' to disable.

// Unspecified arguments maintain their current state. Tracing may be

changed at any time.

// The following arguments control tracing of:

// 1st argument: enable or disable tracing of all STIL labels

// 2nd argument: enable or disable tracing of each STIL Vector and current

Vector count

// 3rd argument: enable or disable tracing of each additional Thread (new

Pattern)

// 4th argument: enable or disable tracing of each WaveformTable change

// 5th argument: enable or disable tracing of each Procedure or Macro entry

// 6th argument: interval to print starting pattern messages; 0 to disable

// For example, a separate initial block may be used to control these options

// (uncomment and change time values to use):

// initial begin

// #800000 $STILDPV_trace(1,1);

// #600000 $STILDPV_trace(,0);

// Additional calls to $STILDPV_parallel() may also be defined to change

parallel/serial

// operation during simulation. Any additional calls need a # time value.

// 1st integer is number of serial (flat) cycles to simulate at end of each shift

// 2nd integer is TetraMAX pattern number (starting at zero) to start parallel

load

// 3rd optional value '1' will advance time during the load_unload the same

as a serial


// shift operation (with no events during that time), '0' will advance

minimal time

// (1 shift vector) during the parallel load_unload.

// For example,

// #8000 $STILDPV_parallel( 2,10 );

// end // of initial block with additional trace/parallel options

Endmodule


Screen Shots:

FP Netlist:

Placed Netlist:


CTS Netlist:

Routed Netlist:

B4 Assignment 4

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Transcript of B4 Assignment 4