Avago LTE PA

ACPM-5017LTE Band12/17 (698-716 MHz) 3 x 3 mm Power Amplifier Module

Data Sheet

DescriptionThe ACPM-5017 is a fully matched 10-pin surface mount module developed for LTE Band12 and Band 17. This power amplifier module operates in the 698-716MHz bandwidth. The ACPM-5017 meets stringent LTE (MPR=0dB) linearity requirements up to 27.5 dBm output power. The 3 x 3 mm form factor package is self contained, incorporating 50 ohm input and output matching networks.

The ACPM-5017 features 5th generation of CoolPAM circuit technology which supports 3 power modes – bypass, mid and high power modes. The CoolPAM is stage bypass tech-nology enhancing PAE (power added efficiency) at low and medium power range. Active bypass feature is added to 5th generation to enhance PAE further at low output range and it enables the PA to have exceptionally low quiescent current. Without a DC-DC converter, it dramati-cally saves the CDG and DG09 average power consump-tion and accordingly extends the talk time of mobiles and prolongs a battery life. It can be used with APT (Average Power Tracking) operation to reduce the power consump-tion when Vcc1 is connected to the battery and Vcc2 is connected to a DC-DC converter, which adjusts the Vcc2 voltage according to the output power level.

A directional coupler is integrated into the module and both coupling and isolation ports are available exter-nally, supporting daisy chain. The integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. The coupler directivity, or the output power variation into the mismatched load, is critical to the TRP and SAR per-formance of the mobile phones in real field operations as well as compliance tests for the system specifications.

The ACPM-5017 has integrated on-chip Vref and on-module bias switch as the one of the key features of the CoolPAM-5, so an external constant voltage source is not required, eliminating the external LDO regulators and switches from circuit boards of mobile devices. It also makes the PA fully digital-controllable by the Ven pin that

Features• Thin Package (0.9 mm typ.)

• Excellent Linearity

• 3-mode power control with Vbp and Vmode Bypass / Mid Power Mode / High Power Mode

• High Efficiency at max output power

• 10-pin surface mounting package

• Internal 50 ohm matching networks for both RF input and output

• Integrated coupler Coupler and Isolation ports for daisy chain

• Green - Lead-free and RoHS compliant

• Compatible with APT application

Applications• LTE Band12, Band 17 Handset, Datacard

Ordering Information

Part Number Number of Devices Container

ACPM-5017-TR1 1000 178 mm (7”) Tape/Reel

ACPM-5017-BLK 100 Bulk

Description (Cont.)simply turns the PA on and off from the digital control logic input from baseband chipsets. All of the digital control input pins such as the Ven, Vmode and Vbp are fully CMOS compatible and can operate down to the 1.35 V logic. The current consumption by digital control pins is negligible.

The power amplifier is manufactured on an advanced InGaP HBT (hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering state-of-the-art reliability, temperature stability and ruggedness.

2

Absolute Maximum RatingsNo damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value.

Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage.

Description Min. Typ. Max. UnitRF Input Power (Pin) 0 10.0 dBm

DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V

Enable Voltage (Ven) 0 2.6 3.3 V

Mode Control Voltage (Vmode) 0 2.6 3.3 V

Bypass Control (Vbp) 0 2.6 3.3 V

Storage Temperature (Tstg) -55 25 +125 °C

Recommended Operating Condition

Description Min. Typ. Max. UnitDC Supply Voltage

Vcc1Vcc2*

3.20.5

3.4–

4.23.4

VV

Enable Voltage (Ven) LowHigh

01.35

02.6

0.53.1

VV

Mode Control Voltage (Vmode) LowHigh

01.35

02.6

0.53.1

VV

Bypass Control Voltage (Vbp) LowHigh

01.35

02.6

0.53.1

VV

Operating Frequency (fo) 697 716 MHz

Ambient Temperature (Ta) -20 25 90 °C

* Switching power should be adjusted depending on linearity margin required.

Operating Logic Table

Power Mode Ven Vmode Vbp Pout (LTE MPR = 0 dB)High Power Mode High Low Low ~ 27.5 dBm

Mid Power Mode High High Low ~ 16 dBm

Bypass Mode High High High ~ 6.5 dBm

Shut Down Mode Low Low Low –

3

Electrical Characteristics – Conditions: Vcc = 3.4 V, Ven = 2.6 V, Ta = 25° C, Zin/Zout = 50 ohm

Characteristics Condition Min. Typ. Max. Unit

Operating Frequency Range 698 – 716 MHz

Maximum Output Power (High Power Mode)

LTE MPR = 0 dB 27.5 dBm

Gain High Power Mode, Pout = 27.5 dBm 29 32 35 dB

Mid Power Mode, Pout = 16 dBm 20 23 26 dB

Bypass Mode, Pout = 6.5 dBm 12 15 17 dB

Bypass Mode, Pout ≤ -10 dBm 16

Power Added Efficiency High Power Mode, Pout = 27.5 dBm 37.1 %

Mid Power Mode, Pout = 16 dBm 18.2 %

Bypass Mode, Pout = 6.5 dBm 9.7 %

Total Supply Current High Power Mode, Pout = 27.5 dBm 410 445 490 mA

Mid Power Mode, Pout = 16 dBm 50 64 76 mA

Bypass Mode, Pout = 6.5 dBm 8 13 17 mA

Quiescent Current High Power Mode 80 105 140 mA

Mid Power Mode 10 17 24 mA

Bypass Mode 2 3 5 mA

Enable Current High Power Mode 100 µA

Mid Power Mode 100 µA

Bypass Mode 100 µA

Mode Control Current Mid Power Mode 100 µA

Bypass Mode 100 µA

Bypass Control Current Bypass 100 µA

Total Current in Power-down mode Ven = 0 V, Vmode = 0 V, Vbp = 0 V 10 µA

LTEAdjacent Channel Leakage Ratio

E-UTRAACLR Pout < (maximum power –MPR) -36 -33 dBc

UTRAACLR1 Pout < (maximum power –MPR) -39 -36 dBc

UTRAACLR2 Pout < (maximum power –MPR) -41 -38 dBc

Harmonics Suppression

2 fo3 fo

High Power Mode, Pout = 27.5 dBm -39-54

-35-50

dBcdBc

Input VSWR 2:1

Stability (Spurious Output) VSWR 5:1, All phase -70 dBc

Rx band Noise Power 10 MHz LTE, +30 MHz offset from Tx, average +/-4.5 MHz , 20RB

-123 -122 dBm/Hz

GPS Band Noise Power High Power Mode, Pout = 27.5 dBm -140 dBm/Hz

ISM Band Noise Power High Power Mode, Pout = 27.5 dBm -143 dBm/Hz

Phase Discontinuity By pass mode → mid power mode, at Pout = 6.5 dBmmid power mode → high power mode, at Pout = 16 dBm

+14

-9

deg

deg

Ruggedness Pout < 27.5 dBm, Pin < 10 dBm, All phase High Power Mode

10:1 VSWR

Coupling factor RF Out to CPL port -18 -20 -22 dB

Daisy Chain Insertion Loss ISO port to CPL port, Ven = Low 698 ~ 2620 MHz,

0.3 dB

4

FootprintAll dimensions are in millimeter

X-RAY TOP VIEW

0.1250.10

0.35

0.35

0.60

0.10

1.50

0.25

0.3

Pin 1

Pin Description

Pin # Name Description Pin # Name Description1 Vcc1 DC Supply Voltage 6 CPL Coupling port of Coupler

2 RFin RF Input 7 GND Ground

3 Vbp Bypass Control 8 ISO Isolation port of Coupler

4 Vmode Mode Control 9 RFOut RF Out

5 Ven PA Enable 10 Vcc2 DC Supply Voltage

Package Dimensions

2

3

4

Pin 1 Mark

1

5

9

8

7

10

6

3 ± 0.1

3 ± 0.1

0.5

0.9 ± 0.1

All dimensions are in millimeter

VCC1

RFIN

Vpp

VMODE

VEN

VCC2

RFOUT

ISO

GND

CPL

1

2

3

4

5

10

9

8

7

6

5

Marking SpecificationPin 1 Mark

Manufacturing Part Number

Lot NumberP Manufacturing InfoYY Manufacturing YearWW Work WeekAAAAA Assemby Lot Number

A5017

PYYWW

AAAAA

Metallization

Solder Mask Opening

Solder Paste Stencil Aperture

PCB Design GuidelinesThe recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging.

Stencil Design GuidelinesA properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads.

The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Con-sidering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline.

0.30

0.60

0.35

0.55

0.45

on 0.5 mm pitchØ 0.3 mm

0.475

connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout

0.65

0.45

0.50

0.60

1.50

1.30

0.525

0.55 0.45

1.10

1.10

0.60

0.35

0.475

6

C1

A5017PYYWWAAAAA

C2 C3

C4 C6

C5 C7

Evaluation Board Schematic

Evaluation Board Description

1 Vcc1

2 RF In

3 Vbp

4 Vmode

5 Ven

Vcc2 10

RF Out 9

GND 7

CPL 6 Ven

Vmode

RF In

Vcc1 Vcc2

Isolation

C1100 pF

C2 100 pF

2.2 µFC6 C7

680 pFC5

2.2 µF

Vbp

C3100 pF

ISO 8

RF Out

Coupler

50 ohm

680 pFC4

7

Application for APT

Application InformationThe use of DC / DC converter can enhance the efficiency of the ACPM-50xx PAs and this note presents an example of their APT applications in a 3 G / 4 G system.

1. The Vcc1 pin of PAs is directly connected to a battery or the phone power: 3.2 V to 4.2 V

2. The Vcc2 pin of PAs can be adjusted to its lowest value according to Tx average power level over discrete intervals that still meets the linearity requirements (e.g., ACLR1 -39 dBc @ Rel’99): 0.5 V to 3.4 V

• DC-DC converter generates the voltage for the Vcc2 port and it is controlled by the PDM signal from BB chipsets.

• Bypass Capacitors (22 pF and 0.1 µF) should be placed as close to the module as possible (the Vcc1 Pin and the Vcc2 Pin, respectively).

• Bypass Capacitors (0.1 µF and 4.7 µF) should be shared by other band PAs to minimize noises and have best RF performance.

8

Advantage of APT applicationThe best efficiency can be achieved when the voltage of the Vcc2 is continuously adjusted based on the output power requirement of the PA. The voltage to the Vcc2 can be lowered to a point where the PA meets the linearity re-quirement. Average power tracking with ACPM-50xx PAs allows significant power saving as shown in the data here (the battery current vs. Tx output power with / without APT). Higher efficiency incurs less DC power consumption and lowers heat generated by the PA, and accordingly extends the talk time of mobiles and prolongs a battery life.

Tape and Reel Information

Dimension List

Annote MillimeterA0 3.40±0.10

B0 3.40±0.10

K0 1.35±0.10

D0 1.55±0.05

D1 1.60±0.10

P0 4.00±0.10

P1 8.00±0.10

Annote MillimeterP2 2.00±0.05

P10 40.00±0.20

E 1.75±0.10

F 5.50±0.05

W 12.00±0.30

T 0.30±0.05

Tape and Reel Format – 3 mm x 3 mm

A5017PYYW

WAAAAA

9

Plastic Reel Format (all dimensions are in millimeters)

Reel Drawing

NOTES:1. Reel shall be labeled with the following information (as a minimum).

a. manufacturers name or symbol b. Avago Technologies part numberc. purchase order number d. date code e. quantity of units

2. A certificate of compliance (c of c) shall be issued and accompany each shipment of product.3. Reel must not be made with or contain ozone depleting materials.4. All dimensions in millimeters (mm)

50 min.

12.4 +2.0-0.0

18.4 max.

25min wide (ref)

Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart)

BACK VIEW

FRONT VIEW

178

Shading indicates thru slots

+0.4-0.2

21.0 ± 0.8

13.0 ± 0.2

1.5 min.

10

Handling and Storage

ESD (Electrostatic Discharge)Electrostatic discharge occurs naturally in the environ-ment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result.

ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site.

MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature.

Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at

Moisture Classification Level and Floor Life

MSL Level Floor Life (out of bag) at factory ambient = < 30° C/60% RH or as stated1 Unlimited at = < 30° C/85% RH

2 1 year

2a 4 weeks

3 168 hours

4 72 hours

5 48 hours

5a 24 hours

6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label

Note:1. The MSL Level is marked on the MSL Label on each shipping bag.

various temperatures and relative humidity, and times. After soak, the components are subjected to three con-secutive simulated reflows.

The out of bag exposure time maximum limits are deter-mined by the classification test describe below which cor-responds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033.

ACPM-5017 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM-5017 is targeted at 260° C +0/-5° C. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5° C.

11

Reflow Profile Recommendations

Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C

Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C

Profile Feature Sn-Pb Solder Pb-Free SolderAverage ramp-up rate (TL to TP) 3° C/sec max 3° C/sec max

Preheat– Temperature Min (Tsmin)– Temperature Max (Tsmax)– Time (min to max) (ts)

100° C150° C60-120 sec

150° C200° C60-180 sec

Tsmax to TL – Ramp-up Rate 3° C/sec max

Time maintained above: – Temperature (TL) – Time (TL)

183° C60-150 sec

217° C60-150 sec

Peak temperature (TP) 240 +0/-5° C 260 +0/-5° C

Time within 5° C of actual Peak Temperature (TP) 10-30 sec 20-40 sec

Ramp-down Rate 6° C/sec max 6° C/sec max

Time 25° C to Peak Temperature 6 min max 8 min max

25

Time

Tem

pera

ture

Tp

TL

tp

tL

t 25° C to Peak

Ramp-up

ts

Tsmin

Ramp-downPreheat

Critical ZoneTL to Tp

Tsmax

12

Storage ConditionPackages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at < 40° C and 90% relative humidity (RH) J-STD-033 p.7.

Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions < 30° C and 60% RH.

BakingIt is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the con-ditions above have not been satisfied. The baking condi-tions are 125° C for 12 hours J-STD-033 p.8.

CAUTIONTape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking).

Board Rework

Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200° C. This method will minimize moisture related component damage. If any component temperature exceeds 200° C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature.

Removal for Failure AnalysisNot following the above requirements may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism.

Baking of Populated BoardsSome SMD packages and board materials are not able to withstand long duration bakes at 125° C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125° C. Batteries and electrolytic capaci-tors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 andIPC-7721.

Derating due to Factory Environmental ConditionsFactory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient envi-ronmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30° C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device.

Table on next page lists equivalent derated floor lives for humidities ranging from 20-90% RH for three tempera-ture, 20° C, 25° C, and 30° C.

Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table:

1. Activation Energy for diffusion = 0.35eV (smallest known value).

2. For ≤60% RH, use Diffusivity = 0.121exp (-0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30° C).

3. For >60% RH, use Diffusivity = 1.320exp (-0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30° C).

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-3006EN - August 31, 2011

Recommended Equivalent Total Floor Life (days) @ 20° C, 25° C & 30° C, 35° CFor ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Maximum Percent Relative Humidity

Package Type and Body ThicknessMoisture Sensitivity Level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90%

Body Thickness ≥3.1 mmIncludingPQFPs >84 pin,PLCCs (square)All MQFPsorAll BGAs ≥1 mm

Level 2a ∞∞∞∞

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Level 3 ∞∞∞∞

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Body 2.1 mm≤ Thickness<3.1 mm includingPLCCs (rectangular)18-32 pinSOICs (wide body)SOICs ≥20 pins,PQFPs ≤80 pins


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Body Thickness <2.1 mmincludingSOICs <18 pinAll TQFPs, TSOPsorAll BGAs <1 mm bodythickness


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