Automated Implementation of Digital Circuits in Current-mode FPGA Chips
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Transcript of Automated Implementation of Digital Circuits in Current-mode FPGA Chips
8/3/2019 Automated Implementation of Digital Circuits in Current-mode FPGA Chips
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223
Automated Implementation of Digital Circuits
In Current-Mode FPGA Chips
Oleg Maslennikow, Przemyslaw Soltan
Abstracf - In this paper, the automated, procedure to
implementation of target digital circuits into current-mode
FPGA chips liked to Xilinx FF'GAs is proposed. The paper
purpose is the investigation of the possibility of designing and
realization the whole programmable mixed ana log-digital system
on a single die without subs trate interference effect.
Keywords - Mixed analog-digital system, Field programmable
gate array ( P G A ) , Current-mode gate, Computer-aided design,
Mapping, placement an d routing procedures.
I. INTRODUCTION
Modem application specific systems contain both d igital and
analog parts, where the first part usually is the specialized
parallel processor, while the analog part is the preprocessing
and interface unit between digital part and external world.
Advances of the modem VLSl technology permit to
implement such mixed systems on a single die. However, the
problem of influence of digital part on the analog part of such
a system-on-chip must be solved during system design.
Switching transients (noise) of the digital part ca n perturb the
analog part of a system owing to the coupling through the
substrate [1,2]. Radical reduction of this noise is based on theimplementation of the mixed system digital part with the
current mode gates [4,5]. Due to the nearly constant value of
the power supply current at the different gate states, the level
of its noise is essentially lower in comparison with the
classical voltage type gates. Moreover, based on the current-
mode gates, several digital circuits were designed, which are
characterized by smaller number of gates in comparison with
their prototypes constructed with classical voltage CMOS-
type gates [ 5 ] .Note that physical and logical properties of the
current-mode gates differ flom corresponding properties of
Oleg Maslennikow, Przemyslaw Soltan - Electronics Depmment,Technical University ofKosralin, Partyzantow se.,17, Korzalin,75-41 1, POLAND,e-mails: olee~ ie.hl.ko szalin.D I, [email protected]
classical voltage-mode gates.
Therefore, in the paper [SI, we use the approach to
designing.current-mode digital circuits for synthesizing of the
functional prototype of the hasic block of Xilinx FPGA cells -
the Spartan 11 FPGA's slice [3]. Results of VHDL-model
simulations and results of experimental verification of the
full-custom ASIC chip consisted of the current-m ode slice, In-
Out block (IOB) and configuration memory block have shown
the correct work of this circuit. This enables to construct the
whole current-mode FPGA chip with the internal smcture
and functional possibilities liked to Spartan-II FPGAs.
However, because physical and logical properties of the
current-mode gates as well as approaches to designing
current-mode digital circuits are unknown to most designers.
Therefore, in this paper, we propose the approach to automatic
implementation of the target digital circuits in the current-
mode FPGA chips. In this approach we assume, that current-
mode FPGA chip is the functional prototype of an arbitrary
known FPGA chip, for example from Spartan or Virtex FPGA
families [3]. In this case, the proposed procedure consists of
the following steps:
design of the VHDL-model of the target circuit in the
classical voltage technique and its verification using
arbitrary taken VHDL simulator;
synthesis of th e verified model (mapping, placement and
routing procedures) in the selected FPGA chip. n e esult
of this step is the . n d file and the .xdl file (when Xilinx
Founda tion environment is used). These files include
information about used slices, IOBs, switches, etc. and
their interconnections;
analysis of the obtained .xdl file and its conversion to the
corresponding file for selected current-mode FPGA chip
based on currentmode blocks libmy. To realize it, the
corresponding program-converter is used, which also
CADSM'2003, February 18-22,2003, Lviv-Slasko, Ukraine
8/3/2019 Automated Implementation of Digital Circuits in Current-mode FPGA Chips
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allows generate the VHDL description of the target
circuit in the current-mode technique. I l is enables to
simulate the obtained VDHL-model in the arbitrary
VHDL simulator (for example, Active-HDL
environment), in which current-mode table of resolution
and current-mode gate libraries were included.
The paper purpose is the investigation of the possibility of
designing and realization the whole programmable mixed
analog-digital system on a single die.
11. PROCESS OF DESIGNING AND
IMPLEMENTATION OF CURRENT-MODE
VHDL PROJECT
In this designing process, we assume, that we have the
current-mode FPGA chip, which is the functional prototype of
an arbitrary Xilinx FPGA chip, for example from Spartan or
Virtex families. In this case, the design of the VHDL-model
of the target circuit in the standard classical voltage technique
and its verification is performed in fust, using arbitrary taken
VHDL simulator. Then the Xilinx Foundation environment is
used for mapping, placement and routing of the target digital
circuit in the selected FPGA chip. Fig. 1 illustrates the result
of implementation of the two-inputs AND function C = A and
Bi n the Spartan I1 FPGA
I
MATRIX OF SWITCKES
Fig.1.Result of implementation
ofthetwo-inputs AND function
in
the SPARTAN II FPGA
The result of this stage is the .ncd file, which further sho uld be
transformed to the .xdl file format. The last file includes the
information about slices, IOBs, switches and others blocks,
which have been used, and their interconnections. The
fragment of the..xdl tile for the two-inputs AND fun ction
C =A and B is presented in the Fig. 2.
design ""U"c2s1Scs144-6 " 2 . 4 6 i
inst "a" "IOB" , placed LRB K3 ,
cfg "PAD:a: 1NBUF:c-a: uNx::1 " iinst "b" "108" , placed L R8 L1 ,
cfg "PAD:b: 1NBUF:C-b: IMWX::l " iinst "c" "108" , placed LR 8 K2
cfg "0mBUF:C-c: PAD:=: cMJX::O 0UTMUX::l;
inst "N-C" "SLICE" , placed R8C1 CLB-R8Cl.S0,
cfg "YUSED: O G:C3:ILUT:D=(AZ*Al) - : : G " ;
net "N-a", outpin r ta t 'I, inpin "N-c" G Z ;
net "N-b", outpin "b" I, inpin "N-c" Gli
ne t "N-c", outpin "N-c" Y, inpin '"E" 0;
Fig. 2.The fragment of the xdl tile for project of two-inputsAND function
Each of used blocks from Fig. 1 is respectively configured.
Information about FPG A cells is represented in the .xdl file as
the text string, where keywords SLICE, IOB and PA D denote
names of corresponding FPGA blocks, while keywords NET.
OUTPIN and INPIN fmd the interconnections between used
blocks (see Fig. 2) . Keyword CFG denotes here the operation
mode of the corresponding FPGA block. Fig. 3 illustrates the
example of configuration and interconnections for the SLICE
block, which have been used in the project of the two-inputs
AND function.
Next stage is analysis of the obtained .xdl file and its
conversion to the corresponding file for selected current-mode
FPGA chip based on current-mode blocks library. To realize
it, the corresponding program-converter GEDEON was
designed. For each used SLICE block this program defmes the
logical function realized in the look-up-table blocks (LUTs)
and configuration data of all multiplexers. For each used IOB
block program defines the configuration data of PAD and
multiplexers blocks. Then program GEDEON transformsobtained data to the binary data stream, which are saved as he
configuration file for the currentmode FPGA chip. In an
order for this, the library of the cu rrent-mode gates is used.
CADSM'2003, Fetiruary 18-22,2003. Lviv-Slasko; U kraine
8/3/2019 Automated Implementation of Digital Circuits in Current-mode FPGA Chips
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225
cfg "yUSED::O G:C3:MLUT:D-(~*All- A4 0x0
D- A3
G A2
GI- A I
WS DI - , / ' D=A2 an d A1I I
= I1
-A2
a A3
= a4
a DI l
C 0.2
' F f O- 8AH
. . . . . - ...
. . . . .
. . . . .
...... -
. . . . . ...
- . . . . . . .
............
. . ........
Configuration mode Work mode
Fig. 3. The example of configuration and simulation for the SLICE block
The proposed program also allows generate the V F L
description of the target circuit in the current-mode technique.
This enables to simulate'the obtained VDHL-model in the
arbitrary VHDL simulator (for example, Active-HDL
environment), in which current-mode table of resolution and
current-mode gate libraries were included.
. 111. CONCLUSIONS
In this paper, the automated procedure to implementation oftarget digital circuits into current-mode FPGA chips is
proposed. This procedure is suitable for currentmode FPGA
chips, which are the functional prototypes of known FPGA
chips of Spanan or Virtex families. Proposed procedure is
based on the GEDEON prografn, which inalyses the input file
with information ahout slices, IOBs, switches, and others
FPGA blocks, which have been used in the project, and theG
interconnections. Then program transforms obtained data to
the binary data stream, which are-saved as the configuration
tile for the current-mode FPGA chip. In an order for this, the
library of the currentmode gates is used. T he paper purpose is
the investigation of the possibility of designing and realization
the whole programmable mixed analog-digital system on a
single die without substrate interference effect.
, .
REFERENCES
[I ] R. Gonzalez,B.M. Gordon , M.A. Horowitz, "Supply and
Threshold V oltage Scaling for Low Power CM OS , IEEE
I. Solid-state Circuits, 1997, vol. 32, No. 8, pp. 1210-
1215.
[2] M. Ingels, M.S.J. Steyaen, "Design strategies and de-
coupling techniques for reducing the effects o f electrical
interferen ce in mixed-mode Ics", IEE E J. Of Solid-state
Circu its, 19 97, N7, pp. 1136-1141.
[3] "The Programmable Logic Data Book", X i l h , Inc., 2001.
[4] A. Guzinski, P. Pawlowski, D. Cnv yrow , J. Kaniewski, 0.
Maslennikow, N.Maslennikowa, D. Rataj, "D esign of
Digital Circuits with C urrent-Mode Gates," Bulletin of the
Polish Academy of Sciences, Technical Sciences, vol. 48,
no. I, pp.73-91,2000.. . .
[SI0. MaSkMikOW, "Approaches to Designing and Examples
of D igital Circuits Based on the Current-Mode Gates,"
Data R ecording, Storage & Processing, vol. 3, no. 2,
pp.84-98,2001,
-
The work is supported by the grant KBN 7TI I B 004 20.
CADSM'2003, February 18-22,2003, Lviv-Slasko, U kraine