Automated High-Throughput Assembly for Photonic Packaging...Automated High-Throughput Assembly for...

© 2016 IBM CorporationPhotonics Summit, Cadence, 6th September 2017, San Jose

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Automated High-Throughput

Assembly for Photonic Packaging

IBM Assembly and Test - Bromont

IBM Research - Watson / TRL

P. Fortier

N. Boyer

A. Janta-Polczynski

E. Cyr

R. Langlois

Y. Yoshi

H. Numata

T. Barwicz

Photonics Summit, Cadence, 6th September 2017, San Jose CA 2

IBM Assembly and Test – Bromont, Canada

160K sq. ft. Dedicated Development Facility (C2MI)

850K sq. ft. Manufacturing Facility


IBM Packaging Development & Research

IBM Assembly & Test, Bromont

IBM Tokyo Research Lab

IBM Zurich Research LabIBM T.J. Watson Research Center


What to do in Bromont?


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Outline

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Introduction

Silicon Photonic Packaging Vision

Compliant Polymer

Fiber array

Photonic Flip Chip

Connector (pluggable)

Conclusion


Device: Complex Packaging: Childs play

Historical view of packaging

Where the innovation is An afterthought

Brick wall


Device performance improvement scaling by node is slowingDevices run hotter and are more fragileDisaggregate functionality –> Package integration

Packaging – The new era

Electrical Performance

Thermal Management Cost

ManufacturabilityReliability

Optical Performance

CPIMiniaturization

Packaging is critical for success

Co-design with packaging

Packaging innovation• SiP• 2.5D / 3D


Cost breakdown

Packaging / Test

Device

Packaging is key to lower cost of photonics

Packaging cost is a big piece of the pie for Photonics

Microelectronic packaging is geared towards low cost

MicroelectronicsPhotonics

Leverage the microelectronic industry


Trends in data communication and processing

Embedded

Mid-BoardBGA or socket

Card edge

Optical

Connector CPU / ASICSPhotonic IC

Optics integration: Moving closer to the processing

• Signal speed

• Bandwidth density

• Bandwidth density

• Reach

Increased use of SM optics in the Datacenter

Packaging will play a key role

Silicon Photonics well suited to enable above trends


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Outline

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Introduction


Compliant Polymer

Fiber array

Photonic Flip Chip


Conclusion



• Active alignment

• One connection at a time

• Custom design

• Self alignment

• Multiple connections at a time

• Standard design

Leverage Microelectronic Packaging Infrastructure / Knowhow

Lower packaging cost / Increased scalability

Manual / Low volume Automated / High volume


Packaging Development Focus Areas

Typical 2D MCM package with integrated optics

Fiber PolymerPhotonic flipchip Connector (pluggable)

Silicon

photonicsElectrical

ICASICS

Clip

Ferrule

Optical path

Can be applied to 2.5D and 3D package configurations


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Outline

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Introduction


Compliant Polymer

Fiber array

Photonic Flip Chip


Conclusion


Fiber Array – Concept

Parallel channel array (12ch TV)

O, S, C, L bands compatible

Couples both polarizations (TE / TM)

Assembly using high throughput pick n place tools

MT fiber ferruleV-groove / butt

couple to SiPh chip

V-groove

array

Standard MT

ferrule fiber stub

Polymer lid


Fiber Array – Concept

Fiber

LidMode converter

Adhesive

A

A

Venting holes

Section A-A: 3D tomography

Top view without fiber / lid

V-groove

Suspended membrane

T.Barwicz et al. OFC 2015


Fiber Array – Assembly Sequence

Dual vacuum

pick-tip

Angled

sliding plane

Silicon chip

Buffer

feeding

Fiber stub

feeding

Buffer

vacuum port

Ferrule

vacuum port

1 2 3

N.Boyer et al. ECTC 2017

Off the shelf fiber stub

Dual vacuum picktip handles fiber stub and buffer separately

UV light

UV transparent picktip


Fiber Array – Self-alignment

Tolerances

V-groove

Fiber core

Fiber clad

Montecarlo tolerance analysis (SS=10K)

Picktip

Photonic die

Lid

Fiberlid

Chip

Fiber clad

Fiber core

Close-up of fiber to Si WG alignment

Si WG

T.Barwicz et al. ECTC 2015

Self alignment to < 2µm


Fiber Array – Lateral fiber butting


Sliding force Fixed base

Forcedecomposition

Sliding base

Chip moves this way

Picker

Angle sliding plane


Controlled vertical force translated to horizontal motion for fiber butting

Compatible with high throughput placement tools


Fiber Array – Fiber position validation

Vertical polish through lidFocused Ion Beam cut

Fiber

Metamaterial converter

Adhesive

AssemblySection A-A

Photonic die

Fib

er

A

A

Fibers well seated in v-groove and butted to metamaterial converter


Fiber Array – Optical coupling

TE spectral ripple from

on-chip Fabry-Perot

resonator induced by

patterning imperfection.

Automated, self-aligned results

-3

-2

-1

-3

-2

-1

Wavelength (um)1.265 1.285 1.305 1.325 1.345 1.365

TE data (raw and F-P filtered)

TM data (raw and F-P filtered)

0 - 0.75 dB MT loss

Test site: 12 ports form 6 loopbacks

port 5-6 is polarization ref.

Roundtrip includes MT connection

MT

lo

ss +

Fib

er

to S

i w

ave

gu

ide

lo

ss (

-dB

)

-1.3 dB

1.3 dB peak transmission and > 100nm bandwidth



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Outline

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Introduction


Compliant Polymer

Fiber array

Photonic Flip Chip


Conclusion


Compliant Polymer - Concept

MT fiber ferrule

butt couple

Adiabatic couple

to SiPh chipPolymer ribbon

Ferrule

Ferrule lid

Parallel channel array (dense 50µm pitch – 12ch TV)

O, S, C, L bands compatible

Couples both polarizations (TE / TM)

Compliant material for CPI risk mitigation

Assembly using high throughput pick n place tools

Polymer coupling region

--8 x 2.5µm

0.5 x 0.2µm


Compliant Polymer - Concept

Plug in standard

fiber MT ferrule



Compliant Polymer – Self alignment to chip

Sectional view (Features not to scale)

Placement

misalignment

Polymer ribbon

Polymer waveguides

Chip waveguides

ridge

groove

Photonic chip Photonic chip

-10 -5 0 5 10

-8

-6

-4

-2

0

2

4

6

8

Purposefully induced misalignment (um)

Resultin

g m

isalignm

ent

(um

)

Brut data

top left

top right

bottom left

bottom right

Acceptable target range

Intentionally induced misalignment (µm)

Re

su

ltin

g a

lig

nm

en

t (µ

m)

Top view


Self align to < 2µm using standard high throughput placement tools (±10µm)


Compliant Polymer – Self alignment to ferrule Y.Taira et al. ECTC 2015

Self-alignment structureFerrule

Ferrule lid

Polymer ribbon backing

Polymer waveguides

100 um

Micrograph of polished ferrule facet

New design

Old design



Compliant Polymer – Adhesive bondline control

Chamfered picktip design

Adhesive thickness profileConfocal Interferometry (non destructive)

Sectional view

N.Boyer et al. ECTC 2016

Thicker adhesive at chip and taper edge

reduces scattering.

Thin adhesive in adiabatic coupling region

UV light

UV transparent picktip

Top view


Compliant Polymer – Optical Coupling

1.4 to 2.6 dB loss over ~100 nm bandwidth. Both polarizations / all channels.

Connector pin alignment can add < 0.5 dB loss.

No impact from preliminary stressing with 25 cycles at -40 to 85ºC.

T.Barwicz et al. FIO 2016


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Outline

6

Introduction


Compliant Polymer

Fiber array

Photonic Flip Chip


Conclusion


Photonic flipchip – Concept

Compatible with high-throughput microelectronic assembly low cost, scalable.

Surface tension re-alignment known for decades addressing 3D accuracy and yield.

Secondary photonic die (InP)

Si photonic die or wafer

Solder-induced self-alignment

Pick and place (±10 μm), then anneal (< ±1 μm)

Si photonic die or wafer

Si photonic die

Secondary photonic die (InP)

10

μm

Photonic connection

Photonic interconnect

along this edge


Photonic flipchip – Experimental demonstration

10 μm

Vertical and lateral stop on photonic die

Lateral stop on flipped chip

Si photonic die/wafer

Secondary photonic die

Butting

Cross-section of stops after assembly Infrared view through assembly at anneal

Cross-section of solder pads after assembly

10 μm

Pad on bottom chip

Pad on top chip Align stop

50 μm

SnAg solderSi photonic die

Secondary photonic die

JW.Nah et al. ECTC 2015

Solder pads offset by design for sustained force at butting


Photonic flipchip – Optical coupling demonstration

Si photonic die

Self-aligned secondary photonic

dies

Wavelength (μm)

Chip

-to

-ch

ip lo

ss (

dB

)

1.51 1.53 1.55 1.57 1.59 1.613.5

3.0

2.5

2.0

1.5

1.0

0.5

X (μm)

Y (μm)

0.26

0.58

Solder-aligned loss with nanotaper coupler

Corresponding misalignment range

Silicon used as top & bottom die for convenience, but any material is possible.

1.1 dB loss consistent with misalignment due to accuracy of lithographic stops.

T.Barwicz al. OFC 2017


Photonic flipchip – Yield improvement

Composite image of advanced designwith solder volume self-balancing

Tolerances with solder reservoirs

Solder forces in typical designs

Plated solder thickness (μm)

Lateral force6%

10.510.09.59.0 11.0

200

100

0

Plated solder thickness (μm)

8764 95 10

So

lde

r fo

rce

(μ

N) 120

60

0

Lateral force

~2X

Vertical misalignmentHorizontal misalignment

So

lde

r fo

rce

(μ

N)

Optical

IR

Sensitivity to solder-volume as a yield-limiting mechanism

Working on solder volume self-balancing through integrated reservoirs

Y.Martin et al. ECTC 2016/2017


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Outline

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Introduction


Compliant Polymer

Fiber array

Photonic Flip Chip


Conclusion


Connector – Concept

Standard MTmulti-fiber cable

Demo Silicon Photonic Module

with embedded connector

Clip design is for demo purposes.

Clip is permanently attached to module.

Low profile.

Assembly using high throughput pick n place tools.


Connector – Concept

lid

Si Ph

clip

Optical

Interface

to chip

Standard

MT Fiber

interface

Laminate

substrate

System Ferrule ready to be connected

Mated Module

System ferrule within latches

Clip and MT interface on polymer are secured to the lid overhang

Exploded view

A.Janta-Polczynski et al. Photonics North 2017


Conclusion

Packaging is one of the critical keys to success

Leverage microelectronic knowhow and infrastructure for photonic packagingCost / Scalability

Demonstration of (singlemode, multi-channel array) photonic assembly compatible with

high-throughput microelectronic facilities

Focus on 3 photonic interconnect packaging processes

Parallelized fiber assembly Compliant polymer interface Solder-aligned photonic flip-chip


Team and Acknowledgement

IBM Watson, NY USADesign, fabrication, analysis

GlobalFoundries (former IBM)Chip manufacturing

IBM Bromont – C2MIAssembly, measurement

IBM Research - TokyoRibbon-ferrule assembly Outside partners

Shotaro Takenobu

Katsuki Suematsu

Matsuhiro Iwaya

Masato Shiino

Ted Lichoulas

Eddie Kimbrell


Photonic flipchip – Concept

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Follow our progress:

Through our IBM Research website Google “Silicon nanophotonic packaging.”

Thank you!

IBM Packaging and Test: www.ibm.com/assembly

[email protected]

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