August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC)...
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Transcript of August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC)...
![Page 1: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/1.jpg)
August 06August 06
PKUnity: A SoC PKUnity: A SoC Design and Verification PlatformDesign and Verification Platform
Lu JunlinMicroProcessor R&D Center (MPRC)
Peking University
![Page 2: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/2.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Outline
• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works
![Page 3: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/3.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Outline
• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works
![Page 4: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/4.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
What for
• Providing a PLATFORM for implementing and verifying NEW IDEALS in Nanotechnologies
Behavioral Level Simulation Behavioral Level Simulation (SystemC)(SystemC)
RTL Simulation/EmulationRTL Simulation/Emulation
(Verilog/VHDL)(Verilog/VHDL)
FPGA PrototypingFPGA Prototyping
Silicon ProvingSilicon Proving
New IdeasNew Ideas
Multi-MediaMulti-Media
ProcessingProcessing
CPUCPU
On-chipOn-chip
communicationcommunication
NetworkNetwork
CompilerCompiler
SoftwaresSoftwares
PKUnity PlatformPKUnity Platform
SynthesisSynthesis
Low PowerLow Power
![Page 5: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/5.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
What is
• PKUnity Platform includes:– a scalable and configurable SoC architecture– a series of UniCore CPU– plenty of communication IPs – a verification framework– some verification tools– compilation tool chain and OS based on UniCore
![Page 6: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/6.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
PKUnity Architecture
UniCoreUniCoreCPUCPU
Memory and Memory and High Speed I/OHigh Speed I/O
Low Speed I/OLow Speed I/Oandand
System ModulesSystem Modules
![Page 7: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/7.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Design Features
![Page 8: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/8.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Design Features
• CPU– 600MHz UniCore– 8-Stage Pipeline– 64-bit Floating Point Co-Processor– 16KB I/D Cache– 2-Port Bus Interface
• Main Memory– DDR (Double Data Rate) SDRAM– 166MHz Clock and 64-bit Width– 2 Memory Access Channels
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August 06August 06
ICDFN 2006ICDFN 2006
Design Features
• High Speed I/O Devices– 10M/100M/1G Ethernet MAC– 66MHz PCI Bridge– IDE SATA Controller– USB OTG Controller
• Low Speed I/O Devices– UART– I2C– SPI– AC’97– PS/2
![Page 10: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/10.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Design Flow
SystemC-based
HW/SW Co-verification
SystemC-based
HW/SW Co-verification
RTL Simulationand Emulation
RTL Simulationand Emulation
FPGA Prototyping
FPGA Prototyping
Design and
Implementation
Design and
Implementation
RTL Sign OffRTL Sign Off
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August 06August 06
ICDFN 2006ICDFN 2006
Challenges
• Complex Communication Protocol
• Lots of Asynchronous Clock Domains
DesignDesign
VerificationVerification&&
• Gap between CPU and Main Memory
• Different Bus Bandwidth Requirements
• Power Supply
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August 06August 06
ICDFN 2006ICDFN 2006
Design Solutions
• Two-Layer bus– CPU-MEM bus– IO-MEM bus
CPU-MEM BusCPU-MEM Bus
IO-MEM BusIO-MEM Bus
Slow ClockSlow ClockEnough Enough
PerformancePerformance
ReduceReduce the power the power
supplysupply
Fast ClockFast ClockBest Best
PerformancePerformance
Minimize Minimize CPU-MEM CPU-MEM
bandwidth gapbandwidth gap
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August 06August 06
ICDFN 2006ICDFN 2006
Verification Solutions
• Multi-Layer Verification Framework– For Complex Communication Protocol
• CDC Verification Tool– For Lots of Asynchronous Clock Domains
![Page 14: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/14.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Outline
• PKUnity SoC Platform Features
• Multi-Layers Verification FrameworkMulti-Layers Verification Framework
• CDC Verification Tool
• Future Works
![Page 15: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/15.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Verification Challenges
• Complex Communication Protocol– AHB vs. DDR SDRAM– AHB vs. PCI– AHB vs. MAC– AHB vs. USB OTG– AHB vs. IDE– APB vs. AC’97– … It’s hard to cover all the It’s hard to cover all the
transaction types!transaction types!
![Page 16: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/16.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Verification Methodology
• Multi-Layer– Signal Layer– Bus Layer– Transaction Layer– Scenario Layer
![Page 17: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/17.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Self Checking
• Self Checking by two channels
![Page 18: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/18.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Verification Framework
![Page 19: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/19.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Example
Veri fi cat i on Coverage(3)
0
20
40
60
80
100
Modul e Name
Cove
rage
(%)
Li ne CoverageBranch CoverageCondi t i on Coverage
Veri fi cat i on Coverage(1)
0. 00
20. 00
40. 00
60. 00
80. 00
100. 00
Modul e Name
Cove
rage
(%)
Li ne CoverageBranch CoverageCondi t i on Coverage
Ver i fi cat i on Coverage(2)
0. 00
20. 00
40. 00
60. 00
80. 00
100. 00
Modul e Name
Cove
rage
(%)
Li ne CoverageBranch CoverageCondi t i on Coverage
Veri fi cat i on Coverage(4)
0
20
40
60
80
100
Modul e Name
Cove
rage
(%)
Li ne CoverageBranch CoverageCondi t i on Coverage
• Ethernet MAC Verification Coverage
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August 06August 06
ICDFN 2006ICDFN 2006
Outline
• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification ToolCDC Verification Tool
• Future Works
![Page 21: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/21.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
What’s CDC
• CDC: Clock Domain Crossing
CLKA
FF1 FF2
CLKB
R1 R3R2QD QD QD
FF3
CYCLE 2CYCLE 1 CYCLE 3
setup time hold time
CLKA
R1
CLKB
R2
R3
metastable
![Page 22: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/22.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Challenges
• Lots of Asynchronous Clock Domains– The relationship of clocks is static in the normal simul
ation– It’s difficult to find setup time and hold time violation
(metastable state)
![Page 23: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/23.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Method (Step 1)
1. Find all the CDC paths– Handshake Logic– Gray code counter– ...
HCLK domainICLK domain
FF1
QDram_out[7:0]
QD
QD QD
sample_en
QD
FF2 FF3FF4
Q
D
EN
combinationlogic
CYCLE 1
HCLK
ICLK
ram_r1 ram_r2
ram_out 0x5A 0xA5
ram_r1CDC_state
CYCLE 2 CYCLE 3 CYCLE 4
CDC State Normal
ram_r2CDC_state CDC State Normal
Normal
Normal
sample_enCDC_state CDC State NormalNormal
CYCLE 5
critical to propagation
QD
![Page 24: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/24.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Method (Step 2)
2. Insert a module which can provide random delays on each CDC paths
A 1 2 3
Clka
B
Clkb
Clkb
4 C
CDC_delay U_RdDMA_D (.in(RdDMAH), .out(RdDMAH_d));
CDC_delay U_WrDMA_D (.in(WrDMAH), .out(WrDMAH_d));
Clk_jitter U_ICLK(.in(ICLK), .out(ICLK_j));CDC_monitor U_RdDMA_M (.in(RdDMAH_d));CDC_monitor U_WrDMA_M (.in(WrDMAH_d));
always @ (posedge HCLK)begin RdDMAH <= (RWCON & !RdDMAH); WrDMAH <= (!RWCON & !WrDMAH);end
assign XCS <= !WrDMAH_d & !RdDMAH_d & CS0;
always @ (posedge ICLK_j) NCS <= (WrReqI | RdReqI) & XCS;
![Page 25: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/25.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Method (Step 3)
3. Add reasonable delays on the CDC paths in simulation repeatedly
It’s hard to reach It’s hard to reach
100% coverage, 100% coverage,
but it does find some but it does find some
severe bugs missed in severe bugs missed in
the normal simulation!the normal simulation!
RdDMAH WrDMAH
XCS
RdReqH WrReqH
WrReqI_Meta
WrReqI
RdReqI_Meta
RdReqI
NCS
!WrDMAH & !RdDMAH & CS
(WrReqI | RdReqI) & XCS@ICLK
@ICLK @ICLK
@ICLK @ICLK
Starting Vertex
Observable Vertex
Combinational Logic
Sequential Logic
![Page 26: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/26.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Example
• A commercial ATA-5 IDE controller IP
- The table shows coverage
comparability after 30 transactions
finished
- The right diagram show the full
coverage growth
Table 1: Comparing Code Coverage with CDC Coverage.
Module Name Function DescriptionNum.
of LinesLine
CoverageNum. of CDC
coverage pointsCDC
Coverage
m3s010fa Asynchronous FIFO 426 97.14% 14336 0.40%
m3s008fa Asynchronous FIFO Control 917 95.14% 5170 0.39%
m3s007faIDE PIO/DMA Timing
Control353 100% 1458 0.27%
m3s012fa IDE UDMA Timing Control 470 100% 972 0.41%
m3s005fa AMBA AHB DMA Control 471 95.70% 620 2.26%
0
10
20
30
40
50
60
70
0 1, 000 2, 000 3, 000 4, 000 5, 000 6, 000
Transact i on Num.
CDC
Cove
rage
(%)
![Page 27: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/27.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Outline
• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future WorksFuture Works
![Page 28: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/28.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Future Works
• Communication Architecture• Bandwidth Allocation Algorithm• CDC Coverage Improvement• …
![Page 29: August 06 PKUnity: A SoC Design and Verification Platform Lu Junlin MicroProcessor R&D Center (MPRC) Peking University.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649d435503460f94a1fd59/html5/thumbnails/29.jpg)
August 06August 06
ICDFN 2006ICDFN 2006
Thank You!