Atul Pandey Guido Clemens Marius Sida Mentor Graphics Deutschland Gmbh Arnulfstr 201, Munich,...

Atul Pandey

Guido Clemens

Marius Sida

Mentor Graphics Deutschland Gmbh

Arnulfstr 201, Munich, Germany – 80634

Coverage Driven Verification for Analog Design Based on UCIS

© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com

Design Process : Birds Eye View

Verify

Analog and Digital design process are “similar” and follow same phases

Product/IP specification Implement


Digital Design and Verification Process

Product/IP specification Impleme

nt

Verify

entity oqpsk_modulator is port ( signal chip_I : in std_logic; signal chip_Q : in std_logic; signal start : in std_logic;

Coverage db

Coverage db

Merged coverage db

Coverage analysiso Current coverage statuso Coverage holes/Exclusionso Trend analysiso Effective testso Resource allocationo Report generation

TestPlan

Coverage db


(Current)Analog Design and Verification Process

Product/IP specification

Product/IP specification Impleme

nt

Verify

o What is the current status of the design?

o Have we verified all specifications?o Who needs help?o Are we on the right track?o Report for team members/manager

More corners means more data to Analyze

We’ve got a problem here!


Analog Verification Components

Analog Verification

Nature of Specification

Temporal

Frequency

Yield

Parametric

Verification

PVT

Regression

SPICE

(Tool and Language)

Waiver/Exclusion

Mechanism

Pre-Layout verification

Post-Layout verification


UCIS based CDV for Analog Design

Stimulus (incl. PVT) and cover points

DUT (SPICE)Simulation

(SPICE)

EXT_SOA Postprocessor

UCIS API

Coverage UCIS db

Testplan

Design/verification specification doc

MergeCoverage viewerCoverage analysis Coverage report Trend analysis Questa®SIM - UCIS Framework


An Implementation Example

OPAMP to be used in LDO

in_n

in_p

out_p

vdd

vssbias_in

op_en

Hobson, Dean

Slide seems a bit light on content? Also needs a title?


Specification of an OPAMP Design for a LDO


TestPlan# Description Link Type Weight Goal Response Checking Priority Responsible1 AC Analysis 1 100 1.1 Gain is > 70dB gain Assertion 1 100 atpandey1.2 3db bandwidth is > 8k Hz 3db_bw Assertion 1 100 spice sim 1atpandey1.3 UGB is > 10Mhz ugb Assertion 1 100 spice sim 1atpandey1.4 Phase margin > 60 deg ph_margin Assertion 1 100 spice sim 1atpandey2 Transient analysis 1 100 2.1 SlewRate > 100V/us slewrate Assertion 1 100 spice sim 1atpandey2.2 rise_delay -- rise vin to rise vout delay between 1ps

and 1nsrise_delay Assertion 1 100 spice sim atpandey

2.3 overshoot above logic level overshoot Assertion 1 100 spice sim 1atpandey2.4 undershoot below logic level undershoot Assertion 1 100 spice sim 1atpandey2.5 Quiescent power in power down mode <1nW qp_pd Assertion 1 100 spice sim 1atpandey

2.6 Quiescent power in active mode <1uW qp_amd Assertion 1 100 spice sim 1atpandey

2.7 Max power in active mode <10uW mxp_amd Assertion 1 100 spice sim 1atpandey2.8 check on all nmos devices that VDS <1.2 ovstress_n_ch

eckAssertion 1 100 spice sim 1atpandey

2.9 check on all pmos devices that VDS <1.2 ovstress_p_check

Assertion 1 100 spice sim 1atpandey

3 DC Analysis 1 100 3.1 offset , crossing point at 0, should be less than 5mV offset Assertion 1 100 spice sim 1atpandey

3.2 value of max dc current in dc analysis : upper limit 100u

ivdd_max Assertion 1 100 spice sim 1atpandey

3.3 max dc power < 10uW mxp_dc Assertion 1 100 spice sim atpandey


Waveform postprocessing

Coverage db

TestPlan

Simulation A (ex. Transient)

Simulation N (ex. AC ,PVT,Yield)


Coverage Analysis

Coverage status at Later design stage

Coverage Status at certain design stage

Hobson, Dean

what is meant by "some"? early? (as opposed to later)


Novel Aspects of this work

Compatible coverage based verification between Analog and Digital design verification— Coverage generation and analysis infrastructure is

common between Analog and Digital design— Information exchange format is UCIS

Unique characteristics of analog design and verification are addressed— Use of existing language and tool for analog design— Can be basis of Regression data Management/Analysis

Scalable to most analog designs Design debug information is annotated Extendable to cover Physical

Specification/Verification requirements


Digital Design Analog Design

Coverage viewerCoverage analysisCoverage reportTrend analysis

Coverage Driven verification

Questions?

Executable Process Management and TrackingFor Mixed-Signal designs


References

[1] Alon Gluska: Coverage-Oriented Verification of Banias, Design Automation Conference, 2003. Proceedings

[2] Andrew Piziali: Functional Verification Coverage Measurement and Analysis; Springer link

[3] G. Al Sammane, M.H. Zaki, Z.J. Dong and S. Tahar: Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL; Proc. Languages for Formal Specification and Verification, Forum on Specification & Design Languages (FDL'07), Barcelona, Spain, September 2007, pp. 293-298

[4] Unified Coverage Interoperability Standard: http://www.accellera.org/activities/committees/ucis

[5] Eldo® Reference Manual: online, www.supportnet.mentor.com [6] Questa® SIM User’s Manual: online, www.supportnet.mentor.com [7] UCIS standard 1.0:

http://www.accellera.org/downloads/standards/ucis/UCIS_Version_1.0_Final_June-2012.pdf

[8] Willy M. C. Sansen, Measurement of Operational Amplifier Characteristics in the Frequency Domain, IEEE Transactions on Instrumentation and Measurements, Vol. 1M-34, No. I, March 1985

http://www.accellera.org/activities/committees/ucis

http://www.supportnet.mentor.com/

http://www.supportnet.mentor.com/




Coverage Driven Verification based on UCIS

UCIS is an Accellera standard [4] Facilitates interoperability between

various coverage sources & tools Standard coverage models for

commonly used metrics Extendable to add user defined

attributes Used as the basis of coverage

infrastructure in this work

Atul Pandey Guido Clemens Marius Sida Mentor Graphics Deutschland Gmbh Arnulfstr 201, Munich,...

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