ATPG - test pattern generation process 1. Target faults 2. Generate test cube: 1-5% 3. Random fill:...

ATPGATPG - - test pattern generation process test pattern generation process

1. Target faults1. Target faults2. Generate test cube: 1-5%2. Generate test cube: 1-5%

3. Random fill: 99-95%3. Random fill: 99-95%

4. Stimuli on ATE4. Stimuli on ATE5. Response on ATE5. Response on ATE

Scan/ATPGScan/ATPG - - non-embedded solution non-embedded solution

ATE stimuliATE stimuli

The same widthThe same width

The same frequencyThe same frequency

ATE referenceATE reference

Mirror images: ATE and scanMirror images: ATE and scan

ATPG - the bandwidth problemATPG - the bandwidth problem

Non-Embedded+ Simplicity

- Limited number of

scan chains

- Limited bandwidth

Deterministic + High fault coverage

+ Arbitrary fault models

+ Minimal number of

patterns

Logic BISTLogic BIST

ControlControl

PPRRPPGG

MMIISSRR

100%100%100%100%

Fault coverageFault coverage

Logic BIST + test pointsLogic BIST + test points

Logic BISTLogic BISTBIST-ready core requirement Random pattern testable X-free responses


ControlControl

PPRRPPGG

MMIISSRR

EEqquuaalliizzeerr

Generators• Pseudorandom - PRPG• Biased • Smart• Deterministic

Test data eliminated completely Deigned for board and system test


Embedded- More complex

+ Unlimited number

of scan chains

+ Short scan load time

Pseudorandom+ No stored patterns

- Lower coverage

- More patterns

- BIST-ready design

EDT™ - Embedded Deterministic TestEDT™ - Embedded Deterministic Test

Standard scan On-chip continuous flow

decompressor On-chip continuous flow

selective compactor Highly compressed

deterministic patterns

ATEATEATEATECompressedStimuli

CompressedStimuli

CompactedResponsesCompactedResponses

CCOOMMPPAACCTTOORR

CCOOMMPPAACCTTOORR

DDEECCOOMMPPRREESSSSOORR

DDEECCOOMMPPRREESSSSOORR

Embedded- More complex

+ Unlimited number

of scan chains


Embedded and deterministic testEmbedded and deterministic test

Embedded+ Simple

+ Unlimited number

of scan chains


Deterministic + High fault coverage

+ Arbitrary fault models

+ Minimal number of

patterns

ATPG cycles, coverage, and volumeATPG cycles, coverage, and volume

0%

20%

40%

60%

80%

100%

ATPG volume

ATPG volume

ATPG coverage

ATPG coverage

Cycles

LBIST cycles, coverage, and volumeLBIST cycles, coverage, and volume

0%

20%

40%

60%

80%

100%

BISTBIST coverage

coverage

ATPG top-up volume

ATPG top-up volume

ATPG top-up coverageATPG top-up coverage

Cycles

EDT 10X cycles, volume, and energyEDT 10X cycles, volume, and energy

0%

20%

40%

60%

80%

100%

Cycles

ATPG top-up coverageATPG top-up coverage

ATPG top-up volume

ATPG top-up volume

ATPG volume

ATPG volume

ATPG coverage

ATPG coverage

BISTBIST coverage

coverage

EDT 10XEDT 10XEDT 10XEDT 10X LBISTLBISTLBISTLBIST LTPGLTPGLTPGLTPG ATPGATPGATPGATPG

Radar View of DFT TechnologiesRadar View of DFT Technologies

ReferenceReferenceQuality

Area

TTM

Learning

DiagnosisTest Time

Energy

Core Test

Volume

ATPGATPG

ATPGATPG

EDTEDT

LBISTLBIST

LTPGLTPG

Quality

Area

TTM

Learning

DiagnosisTest Time

Energy

Core Test

Volume

ATPG, Logic BISTATPG, Logic BIST

ATPGATPG

EDTEDT

LBISTLBIST

LTPGLTPG

Quality

Area

TTM

Learning

DiagnosisTest Time

Energy

Core Test

Volume

… … Logic BIST & ATPG top up patternsLogic BIST & ATPG top up patterns

ATPGATPG

EDTEDT

LBISTLBIST

LTPGLTPG

Quality

Area

TTM

Learning

DiagnosisTest Time

Energy

Core Test

Volume

EDTEDT

Quality

Area

TTM

Learning

DiagnosisTest Time

Energy

Core Test

Volume

4466

881010

ATPGATPG

EDTEDT

LBISTLBIST

LTPGLTPG

Logic BIST summaryLogic BIST summary

Logic BIST is ideally suited for applications where stored patterns are prohibitive, i.e. system test

Test coverage objectives are achieved by pseudorandom patterns and test points

Unknown states have to be eliminated to allow signature based compaction

For manufacturing test ATPG top up patterns are required to achieve the desirable test quality

For very long test experiments some un-modeled defects can be detected

EDT summaryEDT summary

EDT is designed for optimized manufacturing test Based on standard scan

• No test point are required• Handles unknown states

Supports effectively variety of fault models, including path delay faults

Uses tester to execute the test

Deterministic forms of embedded testDeterministic forms of embedded test

Designed for optimized manufacturing test Tester controls test application Very similar flow to scan/ATPG

• Based on standard scan• Supports the same fault models as ATPG• No test points necessary• No bounding of X states necessary (in EDT)

On-chip hardware facilitates the improved efficiency• Compression of volume of scan test data • Reduction of scan test time

AcknowledgementsAcknowledgements

Alfred Crouch, Motorola

Graham Hetherington, Texas Instruments

Mark Croft, Mentor Graphics

Geir Eide, Teseda

Rudy Garcia, NP Test

Abu Hassan, Mentor Graphics

Mark Kassab, Mentor Graphics

Nilanjan Mukherjee, Mentor Graphics

Jun Qian, CISCONagesh Tamarapalli, Mentor Graphics

Robert Thompson, Magma DA

Janice Lawson Richards , Mentor Graphics

References and sourcesReferences and sources

Conference proceedings and tutorial materialConference proceedings and tutorial material• International Test ConferenceInternational Test Conference• Design Automation ConferenceDesign Automation Conference• Design and Test in Europe ConferenceDesign and Test in Europe Conference• VLSI Test SymposiumVLSI Test Symposium

WorkshopsWorkshops• Testing Embedded Core-based SystemsTesting Embedded Core-based Systems• Memory Technology, Design and TestingMemory Technology, Design and Testing• DFT and BIST WorkshopsDFT and BIST Workshops• Test Synthesis WorkshopTest Synthesis Workshop


Magazines and journalsMagazines and journals• IEEE Design and Test of Computers IEEE Design and Test of Computers • IBM Journal of Research and DevelopmentIBM Journal of Research and Development• ATT Technical JournalATT Technical Journal• IEEE Transactions on CAD of IC&SIEEE Transactions on CAD of IC&S• IEEE Transactions on ComputersIEEE Transactions on Computers• Journal of Electronic Testing (JETTA)Journal of Electronic Testing (JETTA)

BooksBooks• Abramovici et al., “Digital System Testing and Testable Abramovici et al., “Digital System Testing and Testable

Design”, Computer Science Press, 1990Design”, Computer Science Press, 1990• Bardel et al., “Built-In Test for VLSI”, Wiley, 1987Bardel et al., “Built-In Test for VLSI”, Wiley, 1987


BooksBooks• Van der Goor, “Testing Semiconductor Memories: Van der Goor, “Testing Semiconductor Memories:

Theory and Practice”, John Wiley and Sons, 1991Theory and Practice”, John Wiley and Sons, 1991• Alfred Crouch, “Design-For-Test for Digital ICs and Alfred Crouch, “Design-For-Test for Digital ICs and

Embedded Core Systems”, Prentice Hall, 1999Embedded Core Systems”, Prentice Hall, 1999• Janusz Rajski and Jerzy Tyszer, “Arithmetic Built-In Janusz Rajski and Jerzy Tyszer, “Arithmetic Built-In

Self Test for Embedded Systems”, Prentice Hall, 1998Self Test for Embedded Systems”, Prentice Hall, 1998 Commercial EDA reference manuals and web pagesCommercial EDA reference manuals and web pages ASIC vendors reference manuals and web pagesASIC vendors reference manuals and web pages Patent descriptions and US Patent and Trademark Patent descriptions and US Patent and Trademark

Office web siteOffice web site

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