ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics &...

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28 July 20 04 Interfaces to ROD Crate Components - Mat t Warren 1 ATLAS SCT/Pixel TIM FDR/PRR Physics & Astronomy HEP Electronics Matthew Warren John Lane, Martin Postranecky TIM Interfaces to ROD Crate Components ATLAS SCT TIM FDR/PRR 28 June 2004

Transcript of ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics &...

Page 1: ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane,

28 July 2004

Interfaces to ROD Crate Components - Matt Warren

1ATLAS SCT/Pixel TIM FDR/PRR

Physics & AstronomyHEP Electronics

Matthew Warren John Lane, Martin Postranecky

TIM Interfaces to ROD Crate Components

ATLAS SCT TIM FDR/PRR28 June 2004

Page 2: ATLAS SCT/Pixel TIM FDR/PRR 28 July 2004 Interfaces to ROD Crate Components - Matt Warren1 Physics & Astronomy HEP Electronics Matthew Warren John Lane,

28 July 2004

Interfaces to ROD Crate Components - Matt Warren

2ATLAS SCT/Pixel TIM FDR/PRR

Overview

• TIM located in center of ROD crate (slot 13) for optimal signal paths.

• Sends Clock and Control signals over a custom J3 backplane.

• Receives TTC Signals into front-panel via optical fibre.

RCC ROD/BOC1-8

ROD/BOC9-16

ROD Crate

TIM!

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28 July 2004

Interfaces to ROD Crate Components - Matt Warren

3ATLAS SCT/Pixel TIM FDR/PRR

TIM Connections Overview

BOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOC

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

RODFP/POResets

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

RODSignals Busses

ROD (Read-Out Drive

r)

Front-End Modules Clock & Control (optical)

(48/BOC)

ROD Busys

MRMW v1.0 17-06-04

Clocks Fanout

TTC (optical)

ROD Crate Busy

VME

NIM/ ECL

Signals

ROD

Read-Out Driver

RCC

ROD Crate Controller

BOC

Back Of Crate

TIM

TTC Interface Module

TIM-OK

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Interfaces to ROD Crate Components - Matt Warren

4ATLAS SCT/Pixel TIM FDR/PRR

ROD-Crate-Controller Interface

• Standard VME Slave

• A24/A32

• D16

• D32 (top word unused)

• Preset or Geographical base-

addressTIM

TTC Interface Module

RCC

ROD Crate Controller

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28 July 2004

Interfaces to ROD Crate Components - Matt Warren

5ATLAS SCT/Pixel TIM FDR/PRR

Back-Of-Crate Interface

• TIM distributes the BC clock to the BOC– BOC feeds clock to ROD in same slot

• To minimise Skew/Jitter:– point-to-point same length lines– differential signalling (PECL)

BOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCBOCTIM

BOC

Back Of Crate

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28 July 2004

Interfaces to ROD Crate Components - Matt Warren

6ATLAS SCT/Pixel TIM FDR/PRR

Read-Out Driver Interface

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

RODFP/POResets

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD

ROD (Read-Out Drive

r)

ROD

TIM

• TIM distributes 8 Control Signals to RODs

• As TIM is in the middle of crate, there are 2 busses - left and right - terminated at ends.

• TIM is can adjust phase of the signals to satisfy ROD’s setup and hold times.

• Signal assignment is flexible– can be re-mapped in firmware

• Signals active for one clock period.

• TIM introduces dead-time after its stand-alone signals to compensate for longer FE signals from the ROD.

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Interfaces to ROD Crate Components - Matt Warren

7ATLAS SCT/Pixel TIM FDR/PRR

Control Signals Description• L1A – Level-1 Trigger Accept

• ECR – Reset Event Counter (L1ID) • First L1A after ECR is zero

• BCR – Reset Bunch Counter (BCID)- once per LHC orbit• BCID value is in the range 0 – 3563 with LHC orbit BCRs.• If no BCR occurs, BCID is 0 – 4095.

• CAL – Calibration pulse command for front-end amplifiers

• SID – Serialised Trigger ID - 24 L1ID + 12 BCID bits

• STT – Serialised Trigger Type - 8 TType + 2 reserved bits• ID's have a single start bit, no stop bit• SID, STT values are independently queued before TX

• FER – Reserved - could be a separate periodic reset

signal

• SPR – Spare

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Interfaces to ROD Crate Components - Matt Warren

8ATLAS SCT/Pixel TIM FDR/PRR

ROD Busy/TIM-OK

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

RODFP/POResets

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD (Read-Out Drive

r)

ROD

ROD (Read-Out Drive

r)

ROD

Read-Out Driver

TIM

ROD-Busy• Received by TIM from RODs.• point-to-point signal.• Active low, pulled high on TIM

– So empty slots are not indicated busy.

TIM-OK• Bussed to all slots in crate.• Pulled down.• Asserted when selected TIM clock is

good.