Atlas Programming Guide Preli

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© 1999-2003 Centrality Commnications, Inc. 2520 Mission College Blvd. Suite #103, Santa Clara, CA 95054

Atlas™

Programming Guide Preliminary Revision 0.6, April 2003

**Preliminary and Confidential under NDA, DO NOT DISTRIBUTE

Atlas™ Programming Guide **Preliminary and Confidential under NDA, DO NOT DISTRIBUTE - 1 -

Table of Contents 1 Introduction ..........................................................................................................................................7

1.1 Documentation Conventions ........................................................................................................ 7 1.2 Referenced Documents................................................................................................................ 8 1.3 Architectural Overview.................................................................................................................. 9 1.4 Key Features .............................................................................................................................. 11

2 RISC Subsystem................................................................................................................................12 2.1 Operation Overview.................................................................................................................... 12 2.2 RISC Address Mapping.............................................................................................................. 12 2.3 Boot-up Control .......................................................................................................................... 14 2.4 Wait State Control ...................................................................................................................... 15 2.5 Write Pulse Control..................................................................................................................... 16 2.6 Timeout Control .......................................................................................................................... 17

3 DSP Subsystem.................................................................................................................................18 3.1 Operation Overview.................................................................................................................... 18 3.2 DSP Memory Address Mapping ................................................................................................. 19 3.3 DMA Operation........................................................................................................................... 20

3.3.1 Setting Memory Status ........................................................................................................ 20 3.3.2 Starting DMA Transfer......................................................................................................... 20 3.3.3 Endian Mode for DMA......................................................................................................... 21 3.3.4 Byte Select Mode ................................................................................................................ 21

3.4 Controlling Peripherals ............................................................................................................... 23 3.5 DSP and RISC Cooperation....................................................................................................... 24

3.5.1 RISC Control DSP by Interrupt ........................................................................................... 24 3.5.2 Data exchange between the RISC and the DSP ................................................................ 26

3.6 Differences between the DSP and ADI’s ADSP2181................................................................. 27 3.6.1 Memory ............................................................................................................................... 27 3.6.2 Instructions .......................................................................................................................... 27 3.6.3 Biased-rounding mode ........................................................................................................ 27 3.6.4 Non-memory mapped registers........................................................................................... 27 3.6.5 Memory mapped registers................................................................................................... 27 3.6.6 Critical path limitation .......................................................................................................... 27

4 Dynamic Memory Interface................................................................................................................29 4.1 Operation Overview.................................................................................................................... 29 4.2 Pin Sharing ................................................................................................................................. 30 4.3 Normal Operation ....................................................................................................................... 31 4.4 Wake-up Operation .................................................................................................................... 33 4.5 Clock Switching Operation ......................................................................................................... 34 4.6 Self-refresh Mode ....................................................................................................................... 35

5 Static memory Interface.....................................................................................................................36 5.1 Operation Overview.................................................................................................................... 36 5.2 Instruction Access Mode ............................................................................................................ 36 5.3 Direct Access Mode.................................................................................................................... 38 5.4 DMA Access Mode ..................................................................................................................... 39

5.4.1 DMA read ............................................................................................................................ 39 5.4.2 DMA write............................................................................................................................ 40

6 Clocks and Power Manager...............................................................................................................47 6.1 Operation Overview.................................................................................................................... 47 6.2 Change Clock Source................................................................................................................. 48 6.3 Change Clock Ratio.................................................................................................................... 49

6.3.1 Change the System and I/O Clock Ratio ............................................................................ 49 6.3.2 Change the External Memory Clock Ratio .......................................................................... 49

6.4 Change PLL Frequency.............................................................................................................. 51 6.5 Power Mode ............................................................................................................................... 52



6.5.1 Normal Mode....................................................................................................................... 52 6.5.2 Turbo Mode ......................................................................................................................... 52 6.5.3 Idle Mode............................................................................................................................. 52 6.5.4 Standby Mode ..................................................................................................................... 53 6.5.5 Sleep Mode ......................................................................................................................... 53

7 GPIO ..................................................................................................................................................55 7.1 Operation Overview.................................................................................................................... 55 7.2 Configure GPIO Pin Sharing ...................................................................................................... 56 7.3 Configure GPIO as Input ............................................................................................................ 57 7.4 Configure GPIO as Output ......................................................................................................... 58 7.5 Configure GPIO as Open-Drain ................................................................................................. 59 7.6 Configure GPIO as Wake-up Source ......................................................................................... 60 7.7 Configure GPIO to be Accessed by DSP................................................................................... 61

8 Resource Sharing Controller .............................................................................................................62 8.1 Operation Overview.................................................................................................................... 62 8.2 DMA Channel Sharing................................................................................................................ 63 8.3 External Pin Multiplex ................................................................................................................. 64

9 DMA Controller ..................................................................................................................................66 9.1 Operation Overview.................................................................................................................... 66 9.2 Initialization................................................................................................................................. 67 9.3 DMA Interrupt Handling.............................................................................................................. 69 9.4 Single and Burst DMA ................................................................................................................ 70 9.5 1-D and 2-D DMA ....................................................................................................................... 71 9.6 Loop DMA................................................................................................................................... 73 9.7 DSP Control of DMA................................................................................................................... 76

10 PCMCIA Interface ..............................................................................................................................77 10.1 Operation Overview ................................................................................................................ 77 10.2 Pin-mux Programming ............................................................................................................ 78 10.3 M6730 Register Programming................................................................................................ 79 10.4 Power Logic Register Programming ....................................................................................... 81 10.5 Memory Window Configuration............................................................................................... 82 10.6 I/O Window Configuration....................................................................................................... 83 10.7 Timing Control......................................................................................................................... 84 10.8 Management Interrupt Operation............................................................................................ 84 10.9 Card Interrupt Operation......................................................................................................... 86 10.10 Socket Initialization Sequence................................................................................................ 87

11 Extension port ....................................................................................................................................88 11.1 Operation Overview ................................................................................................................ 88 11.2 Pin-mux Programming ............................................................................................................ 89 11.3 Timing Register Programming ................................................................................................ 90 11.4 Fixed Latency Access ............................................................................................................. 91 11.5 Variable Latency Access......................................................................................................... 92 11.6 DSP Access ............................................................................................................................ 93

12 Universal Serial Port ..........................................................................................................................94 12.1 Operation Overview ................................................................................................................ 94 12.2 USP Reset and Power up....................................................................................................... 95 12.3 USP Initialization..................................................................................................................... 96

12.3.1 USP Work Mode Initialization.............................................................................................. 96 12.3.2 Sample Code of USP Initialization ...................................................................................... 99

12.4 USP Transmitting Operation................................................................................................. 105 12.4.1 I/O Mode Transmit by Interrupt ......................................................................................... 105 12.4.2 I/O Mode Transmit by Polling FIFO Status ....................................................................... 105 12.4.3 DMA Transmitting Mode.................................................................................................... 105

12.5 USP Receiving Operation..................................................................................................... 107 12.5.1 I/O Mode Receiving by Interrupt ....................................................................................... 107



12.5.2 I/O Mode Receiving by Polling FIFO Status...................................................................... 107 12.5.3 DMA Recieving Mode........................................................................................................ 108

12.6 Interralation of Transmitting and Receiving .......................................................................... 109 12.6.1 Independent Operation for Transmitting and Receiving ................................................... 109 12.6.2 concurrent Operation for Transmitting and Receiving ...................................................... 109 12.6.3 Alternate Operation for Transmitting and Receiving ......................................................... 109

12.7 Pin I/O Mode Operations ...................................................................................................... 109 12.8 USP Reconfiguration ............................................................................................................ 111 12.9 SIB Initialization .................................................................................................................... 112 12.10 SIB Operations...................................................................................................................... 114

12.10.1 Register Writing ............................................................................................................. 114 12.10.2 Register Reading ........................................................................................................... 114 12.10.3 Audio Data Transfer....................................................................................................... 114 12.10.4 Telecom Data Transfer .................................................................................................. 115

13 Audio CODEC Interface...................................................................................................................116 13.1 Operation Overview .............................................................................................................. 116 13.2 AudioCODEC Controller Initialization ................................................................................... 117 13.3 AC’97 CODEC Configuration................................................................................................ 118 13.4 I2S CODEC Configuration .................................................................................................... 122

14 Camera Interface .............................................................................................................................124 14.1 Operation Overview .............................................................................................................. 124 14.2 Initialize Operations .............................................................................................................. 125

14.2.1 Initialize Camera Interface ................................................................................................ 125 14.2.2 Camera Interrupt Operation .............................................................................................. 125

14.3 DMA Operations ................................................................................................................... 127 14.3.1 Initialize DMA Interface ..................................................................................................... 127 14.3.2 DMA Interrupt Operation ................................................................................................... 127 14.3.3 DMA operation .................................................................................................................. 128

14.4 Sensor Operations ................................................................................................................ 129 14.4.1 Initialize Sensor Control Module ....................................................................................... 129 14.4.2 Sensor Clock Operation .................................................................................................... 129 14.4.3 Capture Image Operation.................................................................................................. 129 14.4.4 Slave Mode Operation....................................................................................................... 130 14.4.5 Pixel Data Shift Operation................................................................................................. 131 14.4.6 Inverse Control Operation ................................................................................................. 132 14.4.7 Sample Pixel Clock Operation .......................................................................................... 132 14.4.8 Master Mode Operation..................................................................................................... 133

14.5 I2C Master Operations.......................................................................................................... 135 14.5.1 Initialize Unit ...................................................................................................................... 135 14.5.2 Write n Bytes to External Device....................................................................................... 135 14.5.3 Read n Bytes from External Device .................................................................................. 136

14.6 I2C Slave Operations............................................................................................................ 137 14.6.1 Initialize Unit ...................................................................................................................... 137 14.6.2 Normal Operation .............................................................................................................. 137

14.7 Quick Reference ................................................................................................................... 138 15 USB 1.1 Device Interface ................................................................................................................139

15.1 Operation Overview .............................................................................................................. 139 15.2 Initialization ........................................................................................................................... 141 15.3 Control Transfer .................................................................................................................... 143 15.4 I/O Operation ........................................................................................................................ 145 15.5 DMA Operation ..................................................................................................................... 147 15.6 Quick Reference ................................................................................................................... 149

16 Host Port Interface ...........................................................................................................................150 16.1 Operation Overview .............................................................................................................. 150 16.2 Address Mapping .................................................................................................................. 151



16.3 Initialization ........................................................................................................................... 152 16.4 I/O & DMA Operation ............................................................................................................ 155 16.5 Handshaking with Host ......................................................................................................... 157

17 Secure Disk (SD) / Multi-Media Card Interface (MMC) ...................................................................158 17.1 Operation Overview .............................................................................................................. 158 17.2 Internal Regsiter Programming............................................................................................. 159 17.3 I/O Operation ........................................................................................................................ 160 17.4 DMA Operation ..................................................................................................................... 161 17.5 Initialization ........................................................................................................................... 162 17.6 No Data Command/Response Transaction.......................................................................... 163 17.7 Single Block Operation ......................................................................................................... 164

17.7.1 Single Block Write ............................................................................................................. 164 17.7.2 Single Block Read ............................................................................................................. 164

17.8 Multiple Block Operation....................................................................................................... 165 17.8.1 Multiple Block Write........................................................................................................... 165 17.8.2 Multiple Block Read........................................................................................................... 165 17.8.3 Multiple Block Write Using Number Blocks ....................................................................... 166 17.8.4 Multiple Block Read Using number Blocks ....................................................................... 166

18 Nand Flash Memory Interface .........................................................................................................167 18.1 Operation Overview .............................................................................................................. 167 18.2 Initialization ........................................................................................................................... 167 18.3 I/O Operation ........................................................................................................................ 167

18.3.1 IO Read ............................................................................................................................. 167 18.3.2 IO Write ............................................................................................................................. 168

18.4 DMA Operation ..................................................................................................................... 168 18.5 DMA read example ............................................................................................................... 169 18.6 DMA write example............................................................................................................... 169 18.7 NAND Boot-loader ................................................................................................................ 170

18.7.1 ARM Init Process............................................................................................................... 171 18.7.2 Flash Controller’s global register init process ................................................................... 172 18.7.3 Read Device ID ................................................................................................................. 172 18.7.4 Search File “NK.BIN”......................................................................................................... 172 18.7.5 Read “NK.BIN” and Parse It .............................................................................................. 172

18.8 Special Notes........................................................................................................................ 173 19 LCD Controller Interface ..................................................................................................................174

19.1 Operation Overview .............................................................................................................. 174 19.2 Initialization ........................................................................................................................... 174 19.3 DMA Operation ..................................................................................................................... 176 19.4 Configuration Comparison for Different Mode ...................................................................... 177 19.5 Palette ................................................................................................................................... 178

19.5.1 Color Palette...................................................................................................................... 178 19.5.2 Grey Palette of FRC Sequence......................................................................................... 178

19.6 Special Register Configuration ............................................................................................. 179 19.6.1 Pixel Clock Divider ............................................................................................................ 179 19.6.2 FIFO Request Watermark Control .................................................................................... 179

19.7 Power Sequence / Back Light Control for LCD Displays...................................................... 179 20 Revision History ...............................................................................................................................180



List of Figures Figure 1. Atlas™ Block Diagram .......................................................................................................... 9 Figure 2. DSP Byte Select Mode........................................................................................................ 22 Figure 3. Data Mapping in 8-bit External Data Bus............................................................................ 37 Figure 4. Data Mapping in 16-bit External Data Bus.......................................................................... 37 Figure 5. Static Memory Interface Simple WriteTiming...................................................................... 41 Figure 6. Static Memory Interface Fixed Sequence WriteTiming....................................................... 43 Figure 7. Static Memory Interface Fixed Sequence WriteTiming....................................................... 45 Figure 8. Atlas™ Pin Multiplex Diagram............................................................................................. 64 Figure 9. 2-D DMA.............................................................................................................................. 71 Figure 10. 2-D DMA Wrap Around (X-Length > Width)........................................................................ 72 Figure 11. Loop-mode DMA ................................................................................................................. 73 Figure 12. NAND Boot Flow Diagram................................................................................................. 171



List of Tables Table 1. Reference Documents .............................................................................................................. 8 Table 3. DSP memory address mapping.............................................................................................. 19 Table 4. DSP memory usage guide...................................................................................................... 20 Table 5. DSP peripheral registers address mapping ............................................................................ 23 Table 6. Staitic Memory Chip Select Mapping...................................................................................... 36 Table 7. Staitic Memory Chip Select Mapping...................................................................................... 39 Table 8. Atlas™ DMA Channel Multiplex.............................................................................................. 63 Table 9. Atlas™ Pin Multiplex ............................................................................................................... 64 Table 10. Pixel Shift Number vs DMA Register Setting .................................................................... 138 Table 11. USB Device Endpoint Configuration ................................................................................. 149 Table 12. Differences between Master and Slave Mode .................................................................. 178 Table 13. FRC Sequence Table Example......................................................................................... 178



1 Introduction This document detailed descriptions and examples of programming and developing using the Centrality Communications’ Atlas™ Processor. It is intended for the use of Centrality customers, partners, and other interested parties to gain a detailed understanding of Centrality’s technology and architecture for design purposes. Detailed programming guide, flow chart, and sample code are contained in this manual to provide the user with a solid background.

1.1 Documentation Conventions

• In some sections, the documentation is still being finalized. In this case, a “TBD” will be in its place meaning“To Be Determined”.

• Important items to make note are in blue and bold: i.e. NOTE: when laying out the SDRAM

Traces …

• Register names will be in all capital letters with an underscore for spacing. Examples include: INT_FIQ_PENDING

• Include common conventions and assumptions for MSB, LSB, high, low, enable, etc…

• In this document, we refer to the ARM922T core as either RISC, RISC core, or ARM core.

These all refer to same ARM922T core licensed from ARM®.

• Figure Labels are placed below the figure; wheras table labels are placed above the tables they are referring to.

• When diagrams include memory addresses, these are with respect to a specific memory domain.

When a figure describes a memory address, it will either explicitly include the memory domain (i.e. PCMCIA, NAND Flash, SD…) or it is safe to assume it belongs to the domain of the relevant section.

• Binary Values: Often in the register definitions specific fields within a 32 bit register are assigned

values. These values are represented by the following notation: For example if a three bit field has the value of “3”, then the representation would be 2’b011.

• Hexadecimal Values: There are two types of representation of hexadecimal values: such as

16’h55AA, or 0x55AA.



1.2 Referenced Documents The following documents can be obtained from Centrality Communications to enhance the supplement of the Atlas™ Processor. Table 1. Reference Documents

File Name Description ARM922T.PDF ARM922T processor core technical reference manual. BlueApp.PDF Mindtree Consulting Bluetooth Baseband Controller Application

Document BlueArch.PDF Mindtree Consulting Bluetooth Baseband Controller Architechture

Document BlueImp.PDF Mindtree Consulting Bluetooth Baseband Controller Implementation

Document BlueVer.PDF Mindtree Consulting Bluetooth Baseband Controller Verification

Document I2C-Bus Specification.PDF

The I2C Bus Specification version 2.1

M6730 Design Document.PDF

Virtual IP Group M6730 – PCI to PC Card Host Adaptor Block Level Design Document

M6730 Users Guide.PDF Virtual IP Group M6730 PCI to PC Card Host Adapter User Guide V9012S_PM User Guide.PDF

Virtual IP Group V9012S_PM – USB Device Controller User Guide

Atlas_dev1.PDF Centrality Communications Atlas™ Processor layout schematics reference

Developer’s Manual Lite.PDF

Centrality Communications Atlas™ Processor Developer’s Manual (Lite)



1.3 Architectural Overview Figure 1 is the block diagram for Atlas™.

Figure 1. Atlas™ Block Diagram

• RISC Core Atlas™ has an integrated ARM922T core with the AMBA ASB bus. The RISC acts as a controller, which controls the other functional blocks via writing/reading memory-mapped registers. The RISC accesses external memory via the memory bus and acts as a bus master. • DSP Core Most of the computation required for the multimedia and communication applications can be performed in the Digital Signal Processor (DSP). The advantages of using a DSP include an increase in the computation horsepower, effectiveness, and reduced memory footprint and bandwidth. The DSP operates independent from the RISC processor and contains its own program and data memory space. The DSP is also a bus master and can DMA data to/from external memory via the memory bus. However, the DSP is controlled by the RISC processor through a shared register file. The RISC processor can write commands into the register file and start/stop DSP programs. The DSP can also write to the register file and transfer data/status to the RISC. The RISC and DSP can symbiotically interrupt each other. Both the RISC and the DSP can read/write to memory-mapped control registers to configure or read the status of a peripheral block. This accesses takes place on two distinct buses, the RISC I/O Bus (RBUS) and DSP I/O Bus (DBUS). Each block has a Control Register Interface to decode the register accesses from the RISC and DSP and resolve any potential conflict. (Note: The RISC and the DSP can simultaneously read/write two separate registers, as long as they are not in the same functional block). • System Memory Bus The system memory bus is a 32-bit high-performance, low-power bus. In the Atlas™ architecture, there are 4 bus masters: RISC, DSP, I/O Bridge, and LCD Controller. The Bus Arbitrator arbitrates requests of the four bus masters and directs the appropriate accesses to the single system memory bus slave – the Memory Controller. • Memory Controller

ARM 922T

DSPSubsystem

System MemoryBus Arbiter

MemoryController

ROM Interface

LCD Controller

I/O Bridge

NAND Flash Smart Media

USB 1.1Interface

SD/MMCInterface

PCMCIA/CFHost/Slave_

Extension Port

Camera Interface Serial Ports GPS

Baseband Bluetooth Baseband

SDRAM/SRAM Flash/ROM

LCD Panel LCD Driver

GPIOs Keyboard

Bluetooth RF GPS RF IrDA, UART CODEC, Tch-Scrn

CMOS/CCD Sensor

NAND FlashSmartmedia

USB Host SD/MMCCard

CF/PCMCIAHost/Slave

Extension Chip



The Memory Controller controls all access to external memory. The Memory Controller supports SDRAM as the main memory for program and data storage during the chip’s normal operational mode. During boot, the RISC processor will first transfer the code stored in Flash memory to the program space in the SDRAM. After boot-up, the Flash memory can be considered as a peripheral device. • Peripheral Subsystem Atlas™ is a multi-functional platform, so it contains several peripheral interface blocks:

1) 16 channel GPS baseband 2) Bluetooth baseband 3) USB device interface 4) NAND Flash/Smart Media interface 5) CMOS/CCD sensor interface 6) NOR Flash/ROM interface 7) Universal Serial Ports 8) Audio CODEC interface 9) SD/MMC interface 10) LCD interface

All of these interface blocks have the same functionality: they each provide a means to transfer data between Atlas™ and an external device. There are two types of transfer: I/O read/write and DMA. Some blocks only support I/O read/write, such as the Bluetooth and GPS blocks. Some blocks support both I/O read/write and DMA, such as the serial port, CMOS sensor, NAND Flash/Smartmedia, Flash/ROM, SD/MMC and USB interface. Each peripheral has its own SRAM FIFO. The I/O read/write can be executed by either the RISC or DSP, via the RBUS or DBUS respectively. The DMA can be executed via the I/O memory bus. The peripheral blocks with DMA channel will connect to the I/O Bridge via the I/O memory bus. The I/O Bridge is responsible for the arbitration of the DMA requests from the peripherals. But it can only grant the I/O memory bus to the peripheral when it's granted the system memory bus from the Bus Arbiter.



1.4 Key Features Unlike other application processors on the market today, the Atlas™ processor provides the following key features integrated on-chip.

240MHz ARM922T RISC core

o 8KB I-Cache

o 8KB D-Cache

o Memory Management Unit

o Debug Capability via JTAG port

120MHz DSP core for optimized low-power acceleration for: MP3, Image Video compression and processing, GPS, VOIP, and MIDI

o 2Kx24bit Program Memory

o 3Kx16bit Data Memory

16 channel GPS baseband specific hardware

Bluetooth baseband specific hardware

CMOS/CCD sensor interface

NAND Flash support with integrated Bootloader

100MHz SDRAM bus with support for 2.5V Mobile SDRAM

Graphic LCD controller with UMA for Active TFT and monochrome LCD panels

Advanced power management features including dynamic Processor Voltage Scaling, fine-grained clock-gating to dynamically turn off peripherals

USB 1.1 device

4 Universal serial ports

Multiple card support: PCMCIA, SmartMedia®, SD, MMC, Compact Flash, etc.

28 General-purpose I/O and 116 programmable I/O

291 pin TFBGA (16x16mm)1 package

Low-power 0.18u CMOS

1 12x12mm package option available



2 RISC Subsystem

2.1 Operation Overview The RISC Subsystem includes an ARM922T RISC core (with 8KB I-Cache and 8KB D-Cache) and a RISC interface. The RISC interface can translate the ARM922T bus cycles into Atlas™ internal system bus cycles. There are two types of basic bus cycle of ARM922T: I/O cycle and Memory cycle. It’s decided by the address to define if a RISC bus cycle is I/O or Memory cycle. The I/O cycle will be transferred to the internal RISC I/O bus (RBUS). And the Memory cycle will be transferred to the internal system memory bus (MBUS). All buses mentioned above are in 32-bit.

2.2 RISC Address Mapping The ARM922T has a 32-bit address bus, which will be translated by the RISC interface into either an access to cacheable data memory, non-cacheable data memory, or memory-mapped registers. Bits <26:0> of the address are used as the physical address bus. All address mapping registers must be inside the RISC interface. The RISC interface will be responsible for all address decoding before it issues the command cycles to the system. The boot ROM should have instructions about how to initialize these address-mapped registers. The programmer needs to provide the system with the initialization routine. • ROM & PCMCIA The address mapping is defined starting from CPU reset vector (0x0000-0000). There is 512MB set aside for ROM. However, not all of this space can be used. For security reasons, this memory must be mirrored. Thus, the maximum size that can be set for the ROM cannot exceed 256MB. Also, because the mirrored memory is laid out onto two sequential 256MB segments, accessing 0x0000-0000 and 0x1000-0000 directly will yield the same result. The memory space from 512MB to 1GB is allocated to two PCMCIA sockets. Each socket takes 256MB of memory. • DSP Shared Memory & Extension Port The Extension port takes 128MB space starting from 1GB address. And the DSP shared memory takes another 128MB based on Extension port. If the RISC reads from the reserved address space, a data abort operation will result. Writes to the reserved address space have no effects. • Internal Registers Every peripheral device occupies 64K-byte space starting from 2GB to 3GB. • System Memory The system memory is between 3GB and 4GB. The actual memory size is also defined in the boot ROM or by the memory auto-sizing program. The following table shows the memory address mapping of Atlas™.



Table 2. System Memory Mapping

Address Range Usage Resource Size E800_0000~FFFF_FFFF Reserved 384MB E000_0000~E7FF_FFFF Zero Bank 128MB C000_0000~DFFF_FFFF System Memory 512MB 8000_0000~BFFF_FFFF Internal Registers 1GB 5000_0000~7FFF_FFFF Reserved 768MB 4800_0000~4FFF_FFFF DSP Shared Memory 128MB 4000_0000~47FF_FFFF Extension Port 128MB 3000_0000~3FFF_FFFF PCMCIA Socket 1 256MB 2000_0000~2FFF_FFFF PCMCIA Socket 0 256MB 0000_0000~1FFF_FFFF Flash/ROM 512MB



2.3 Boot-up Control There is a RISCINT_BOOT_UP register that can be used by software to record the boot-up status. If the chip is boot-up from power on, then after boot-up software should set the COLD_BOOT bit in this register. Otherwise, the software should set the WARM_BOOT bit. Based on the value of this register, software can decide how to handle the following boot-up procedure. When boot-up from NOR-Flash or ROM, the boot program needs to do re-direct the NOR-Flash/ROM access to the shadowed SDRAM memory space somewhere between the boot-up. This is also done by setting the COLD_BOOT bit. To make sure the setting taking effect as soon as possible, user can write the FIFO_FLUSH bit in RISCINT_FIFO_FLUSH register right after set this Boot-up register. RISCINT_BOOT_UP = 0x1; RISCINT_FIFO_FLUSH = 0x3; After the COLD_BOOT bit is set, all CPU access to address 0~0x0FFF_FFFF will be re-directed to the system memory space (0xC000_0000~0xCFFF_FFFF). But the CPU can still access the NOR-Flash/ROM memory by issuing the address of it’s mirror image sitting on 0x1000_0000~0x1FFF_FFFF. Due to the pipeline nature of the RISC core, after the Boot-up register been set, user CANNOT access the ROM address space at once. It needs to insert at least one NOP between them.



2.4 Wait State Control Most peripherals in Atlas™ are in I/O clock domain (please refer to the section 6 “Clocks and Power Manager”), while the RISC Subsystem is running at a higher system clock domain. So there is need for inserting wait states when the RISC read those slow I/O devices. Besides, due to the parastic capacitance in the silicon, the data read from a block that is far from the CPU will have longer dealy. Sometimes the delay might be longer than one system clock cycle. In this case, there is also need for inserting wait states. There are totally 8 groups of wait state register bits (WS0~7); each is used to control the wait states of one group of I/O devices. The allocation is as following:

• WS0 – RISC Interface, Interrupt Controller, OS Timer • WS1 – DSP Interface, GPS Baseband, SDRAM Controller • WS2 – LCD Controller, Reset Controller, Real-time Clock Controller • WS3 – Power Manager, Resource Sharing Controller • WS4 – Bus Arbiter, DMA Controller, Flash/ROM Controller, Camera Interface • WS5 – USP0, USP1, USP2, USP3, Audio CODEC Interface • WS6 – GPIO, Extension Port, SD/MMC Interface, Host Port, PCMCIA Interface • WS7 – Bluetooth Baseband

Among those groups, WS0~WS3 are used to insert wait states for the blocks in system clock domain. While WS4~6 are used to insert wait states of the blocks in I/O clock domain. WS7 is used for only Bluetooth Baseband because it’s the only asynchronous device of the whole chip. Because each group of wait state register bits are shared among several devices (except for WS7), those devices will always have the same wait states setting. That is to say, if user want to increase wait states for one block, then the other blocks in the same group will all have more wait states.



2.5 Write Pulse Control The wait states insertion can only solve the issues when RISC read slow devices. But if RISC is trying to write the slow device, the write enable pulse has to be adjusted too. The write enable pulse width should be exactly the same as the slow device’s clock period. Otherwise, the data might be written to the slow device twice. This might be OK sometimes, but sometimes unkown result may occur. The I/O clock domain can be programmed to run at ½ or ¼ of the clock frequency of the system (pleaser refer to the section 6 “Clocks and Power Manager”). So there are two different configurations for the write pulse width:

• When I/O clock is ½ of the system clock domain, the write enable pulse should be 2 system clock cycles: RISCINT_WIDTH = 0x10;

• When I/O clock is ¼ of the system clock domain, the write enable pulse should be 4 system

clock cycles:

RISCINT_WIDTH = 0x30;



2.6 Timeout Control When RISC accesses I/O device and the device has no response in a certain period, the RISC interface will be timeout and generate an interrupt. This certain period can be programmed by settting a 16-bit number in RISCINT_TIMEOUT register. By default his register is not used at all. But if user like, he can easily enable the Timeout check by setting the TIMEOUT_EN bit (bit<31> of RISCINT_TIMEOUT register). When Timeout check is enabled and the device response is longer than the Timeout value, the RISC interface will generate an interrupt to the CPU in RISCINT_TIMEOUT_INT register.



3 DSP Subsystem

3.1 Operation Overview The DSP used in Atlas™ processor acts as a acceleration computational parts for GPS, MP3, Image processing etc. The DSP core is provided by Faraday Technology Corp. and is instruction compatible with ADI’s ADSP2181 except for minor differences. The DSP is an independent processor. It has it’s own program and data memory. The RISC core can read/write data throught it’s IDMA port and can interrupt the DSP. The DSP can do data exchange between it’s data or program memory and SDRAM by operating the DMA controller of DSP interface. It can also control some of the peripherals such as DMA controller, serial port interface, interrupt controller, GPIO and extension interface by accessing the peripherals’ registers.



3.2 DSP Memory Address Mapping The DSP core has three sets of buses to access three parts of memory named program memory, data memory and program-data memory. For simplification, we call these three parts of memory PM, DMX and DMY respectively. DMX is mapped to the DSP’s data memroy space, PM and DMY are mapped to the DSP’s program memory space. Memory read/write instructions can only access DMY. DMX and PM are further split to two parts, one part is accessed by DSP only (named DMX-in and PM-in respectively), and another part can either be configured as accessed by DSP or accessed by DMA controller (named DMX-swap and PM-swap respectively). This gives flexibility to change program or move data when the DSP is running and is the compensation to small memory space. The DSP can change memory settings by configure memory control registers and do DMA transfer by configure the DMA control registers. DMX-swap and PM-swap can be configured as single buffer or double buffer. When configured as double buffer, the buffer is spitted into two parts: one part is accessed by the DSP and another part is accessed by the DMA controller side. When configured as single buffer, the buffer is either accessed by the DSP or accessed by the DMA controller. NOTE: Though double buffer gives the flexibility of programming, it is hard to control it in program because the DSP compiler does not support such features. And in most cases, it does not significantly improve the performance. Use this feature with caution. The total size of DMY is 4k WORD. 1k WORD is in DSP interface and can be accessed by the DSP or the DMA controller, other 3k WORD is in GPS baseband module and can only be accessed by the DSP. This 3k buffer can be used by DSP as normal data memory while GPS function is not activated. The following table is the summary of the DSP memory spaces. Table 3. DSP memory address mapping

Memory Starting Address Size(WORD) Word Length Accessed By DMX-in 0x0000 (DM) 1024 16 DSP only DMX-swap (single) 0x0400 (DM) 1024 16 DSP/SDRAM DMX-swap (double) 0x0400 (DM) 512 16 DSP/SDRAM DMY (DSP interface) 0x3c00 (PM) 1024 16 DSP/SDRAM DMY (GPS baseband) 0x3000 (PM) 3072 16 DSP only PM-in 0x0000 (PM) 1024 24 DSP only PM-swap (single) 0x0400 (PM) 1024 24 DSP/SDRAM PM-swap (double) 0x0400 (PM) 512 24 DSP/SDRAM



3.3 DMA Operation DMA of DSP interface can do data transfer between SDRAM and the DSP’s program or data memory. The buffer DMX-swap, PM-swap and DMY all can be configured as accessed by DSP or accessed by DMA controller. Because of the size limitation of the DSP’s memory, exchanging data between the DSP’s memory and SDRAM gives the flexibality of accessing data and program with almost unlimited size. The compiler of the DSP support overlay programming which means separate pages of program or data memory overlay on the same address. By exchanging contents in DMX-swap and PM-swap, the overlay feature can be used, because different data transfer from SDRAM to the DSP’s memory, it is virtually to select different pages of memory. Generally, different memory of the DSP used by different purpose as the following table shows: Table 4. DSP memory usage guide

Memory Usage DMX-in Global variables, constant arrays used by all pages of programs DMX-swap Local variables, data need to be stored in SDRAM DMY Global variables, constant arrays PM-in Start up program, main routine, subroutines called frequently PM-swap Other programs

3.3.1 Setting Memory Status The DSP can set memory status by setting register DSP_MEM_MODE. To simplify programming, macro can be used in DSP program to do memory status setting. The following is an example of macro that setting DMA controller to access the DMX-swap buffer named sdram_dm: { let DMA controller access dm } .macro sdram_dm; ar = dm(DSP_MEM_MODE); ar = setbit 3 of ar; dm(DSP_MEM_MODE) = ar; .endmacro; Similar macros can be defined to set status of PM or DMY. 3.3.2 Starting DMA Transfer The DSP starts DMA by writing DMA control registers including DSP_DMA_MODE and other DMA parameter registers. Normally DMA parameters include physical address of SDRAM where DMA starts, address offset of the DSP’s memory, x and y lengh of DMA. The DMA can be either one dimensional or two dimensional. The latter one is mainly used on image processing. DSPDMA_PITCH_LO and DSPDMA_PITCH_HI register should be set prior to starting two dimensional DMA transfer. When set y length to 0, normal one dimensional DMA will occur. Set DMA parameters first and then set register DSP_DMA_MODE to start a DMA. NOTE1: At any time, there should be only one DMA running. Start another one after the previous one completed. NOTE2: For DMX-swap and DMY, the DSP memory address offset is in double WORD and is half of the value addressed by DSP, for PM, address offset is the same seen by DSP. Address offset is from the beginning of the buffer, so address offset 0 in DMX-swap means address 0x400, address offset 1 means address 0x402 etc.



NOTE3: X length is count of double word. But for PM, a 24bit WORD is treated as a 32bit double word and valid data is in lower 24 bits. A serial of macros can be defined to simplify programming. The following is an example to do DMA between DMX-swap and SDRAM without waiting it completed. { do DMA transfer without waiting it complete} { syntax: transfer_dm_nowait(READ_DM/WRITE_DM, sdram_hi, sdram_lo, sram, xlen, ylen); } { READ_DM is defined as 13 (2’b1101), WRITE_DM is defined as 5 (2’b0101) } .macro transfer_dm_nowait(%0, %1, %2, %3, %4, %5); i0 = DSPDMA_LENGTH_X; dm(i0, m1) = %4; { xlength } dm(i0, m1) = %5; { ylength } dm(i0, m1) = %2; { SDRAM address low } dm(i0, m1) = %1; { SDRAM address high } ar = %3; { SRAM address } dm(DMX_START_ADD) = ar; ar = %0; dm(DSPDMA_MODE) = ar; { do transfer } .endmacro; The following macro waits the DMA completed. { wait for transfer complete } .macro wait_trans; .local transfer_loop; transfer_loop: ar = dm(DSPDMA_MODE); ar = tstbit 0 of ar; { completed? } if ne jump transfer_loop; .endmacro; 3.3.3 Endian Mode for DMA Endian mode for DMA set the endian of DMA between SDRAM and DMX transfer. Default normal endian mode is big endian and invert endian mode is little endian. Word format data read/write will use little endian because the RISC uses the same endian mode. Byte format data read/write or bit stream read/write will use big endian because it will concatenate MSB of next byte to the LSB of previous byte. DMA between SDRAM and DMY transfer can only use little endian. The following is an example of macro set to little endian. { set little endian mode } .macro little_endian; ar = dm(DSP_MEM_MODE); ar = setbit 4 of ar; dm(DSP_MEM_MODE) = ar; .endmacro; 3.3.4 Byte Select Mode Writing data from SDRAM to DMX is on 32bit DWORD unit. In normal state, two lower bits of SDRAM address will be ignored. It has a limitation that DSP has to load data from four-byte boundary. By set BYTE_MODE bit to 1 in register DSP_BYTE_MODE, byte select mode is enabled. Byte select mode use



the lowest 2 bit of SDRAM address as byte selection, load data from the selected byte address and read four bytes each time. It will use the following method (assume lowest two bit of SDRAM address is 01): First, four bytes aligned to DWORD boundary will be read in as A0 A1 A2 A3, A0 will be discarded and last three bytes A1 A2 A3 will be put into storage registers S0 S1 S2. Then the second DWORD B0 B1 B2 B3 will be read in, B0 will concatenate to the storage registers to form a four-bytes DWORD and be written into DMX-swap, last three bytes B1 B2 B3 will be put into storage registers. And this process continuous with third read in DWORD appends C0 to B1 B2 B3 then store C1 C2 C3 etc. The total result is x length multiply 4 numbers of bytes transfered to DMX from SDRAM at address which contains data A1. If the lowest 2 bit of SDRAM is 10, data will transfer to DMX-swap from A2, if the lowest 2 bit of SDRAM is 11, data will transfer to DMX-swap from A3. This method is useful while loading data from unaligned address. When lowest two bit is 00, it will act as byte select not enabled, when lowest two bit is not 00, x length should be increased by 1 to ensure actual number of DWORD written to DMX-swap is x length.

Figure 2. DSP Byte Select Mode

The discard operation after the first read is optional. Normally, the first few bytes should be discarded. But if the second DMA transfer need to concatenate data to the first DMA (for example, load data from a circular buffer in SDRAM, the first transfer passes the end of buffer and the second transfer concatenate the first one from the beginning of the buffer), the second DMA should not discard the first read in data and data in storage registers.

A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3

Discarded (Optional)

S0 S1 S2

A1 A2 A3 B0

S0 S1 S2 S0 S1 S2

B1 B2 B3 C0

…

Data In:

Data out:

A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 …

D0 D1 D2 D3 E0 E1 E2 E3 F0 F1 F2 F3 …

G0 G1 G2 G3 H0 H1 H2 H3 I0 I1 I2 I3 …

…

A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3D1 D2 D3 E0 E1 E2 E3 F0 F1 F2 F3G1 G2 G3 H0 H1 H2 H3 I0 I1 I2 I3

X0Y0Z0

…

Data In:

S0 S1 S2 = Storage registers



3.4 Controlling Peripherals The DSP can control the following peripherals

GPS baseband Interrupt controller DMA controller GPIO Serial port Bluetooth interface Extension interface

The registers of GPS baseband and interrupt controller are mapped to the DSP’s data memory space, registers of other peripherals are mapped to the DSP’s IO space. The following table is an overview of address mapping: Table 5. DSP peripheral registers address mapping

DSP Address Address space Device Mapped 0x0800~0x17FF DM GPS baseband 0x1800~0x19FF DM Interrupt controller 0x000~0x0FF IO DMA Controller 0x100~0x1FF IO General-purposed I/O 0x200~0x2FF IO Serial Port 0 0x300~0x3FF IO Serial Port 1 0x400~0x4FF IO Serial Port 2 0x500~0x5FF IO Serial Port 3 0x600~0x6FF IO Reserved 0x700~0x7FF IO Extension Interface

NOTE: The DMA controller refers to the system’s DMA controller. It is different from the DMA controller of the DSP interface which only do DMA between SDRAM and the DSP’s memory. Read or write these registers with normal data memory access instructions and IO instructions. On default, peripherals are controlled by RISC. Each peripheral has it’s own control bit to determine whether it is controlled by the RISC or controlled by the DSP. When one peripheral is controlled by the RISC, the DSP can not access it’s registers. Peripheral can interrupt the DSP, the interrupt are connected to the DSP’s IRQ2 input and can be set to either level trigger or edge trigger. For details of how to operate each peripheral, refer to the programming guide of corresponding peripheral.



3.5 DSP and RISC Cooperation The DSP acts as an independent unit in the Atlas™ processor. It runs parallel with the RISC. Some communication methods are available between the DSP and the RISC. The DSP and the RISC can interrupt each other. The interrupt from the RISC are connected to the DSP’s IRQL1 input. The RISC can access the DSP’s memory through it’s IDMA interface. 3.5.1 RISC Control DSP by Interrupt The RISC should control DSP by following sequence: 1. Safely reset DSP and DSP interface and enable DSP memory output. 2. Write start up program and other program put in PM-in to DSP through IDMA interface. 3. Write data put in DMX-in to DSP through IDMA interface. 4. Other data and program will be loaded to DMX-swap, PM-swap and DMY should be in SDRAM. 5. Start DSP by write PM at address 0 through IDMA interface. 6. Interrupt the DSP with the subroutine entry address to let the DSP run it’s program. 7. Wait the interrupt signal sent by the DSP when it completed running it’s routine. Following is example code of how to control the DSP // Enable DSP interrupt INT_RISC_MASK |= INT_MASK_DSP; // reset DSP interface RESET_SR |= RESET_SR_DIFACE_RST; // enable DSP core and DSP interface clock PWR_CLK_EN |= PWRCLK_DSP_EN; // reset DSP RESET_SR |= RESET_SR_DSP_RST; // release DSP reset signal RESET_SR &= ~RESET_SR_DSP_RST; // release DSP interface reset signal RESET_SR &= ~RESET_SR_DIFACE_RST; // Allow Risc access DMA register DSPREG_MODE = 1; // Set UP SRAM OE DSPDMA_MODE = 0x30000; // Allow DSP access DMA register DSPREG_MODE = 0; for (i = 1; i < pm_in_size; i ++) ProgramMemory[I] = pm_in_code[i]; WritePM(0, pm_in_code[0]); DspInt = 0; RISC_INT_DSP = (unsigned)routine_entry; while(!DspInt); The variable DspInt is a volatile variable, which should be set to no-zero in the RISC’s interrupt service routine when receiving an interrupt from the DSP.



On the DSP side, if nothing need to be done, DSP should be in IDLE mode to save power. Program should accept interrupt from the RISC and run the routine code. After it finished the routine, send an interrupt to RISC. The DSP should be programmed by the following sequence. 1. Enable interrupt of IRQ2, IRQL1 and other IRQ bits needed. 2. Enter the IDLE mode by executing idle instruction to wait an interrupt occur. 3. If the interrupt is from IRQL1 (eg. The RISC interrupts the DSP), jump to the subroutine with the

entry address given by the RISC. 4. After the subroutine completed, inform the RISC by sending an interrupt. 5. Go back to IDLE mode and wait for the next interrupt. An example is given as following. .module/ram/abs=0/seg = pm_in PM_IN_PROG; .entry Subroutine; StartDSP: nop; imask = 0x0300; /* #0000 0011 0000 0000 B; */ ena ints; jump idle_loop; irq2_srv: jump irq2_int_srv; nop; nop; nop; irql1_srv: ar = 1; dm(GEN_REG2_L) = ar; rti; nop; idle_loop: icntl = 0x5; /* set irq2 edge */ idle; ar = dm(GEN_REG2_L); ar = pass ar; if eq jump idle_loop; i4 = dm(RISC_INT_DSP); jump (i4); return_addr: ar = 0; dm(DSP_INT_RISC) = ar; jump idle_loop; irq2_int_srv: ena sec_reg; ar = 0; dm(GEN_REG2_L) = ar; dis sec_reg; rti; Subroutine: /* execute program */

/* when completed return by executing the following sentence */ jump return_addr;



.endmod NOTE: General purpose register GEN_REG2_L is used to differentiate interrupts from the RISC and from the peripheral. If the interrupt is from peripheral, when go back from the interrupt service routine, the DSP should directly go back to IDLE mode. 3.5.2 Data exchange between the RISC and the DSP The RISC can directly access DSP’s memory through the DSP’s IDMA interface. The read or write operation can be done parallel with the execution of the DSP. The DSP can not access it’s program memory by instruction, so the only way to write to the PM-in buffer is through the IDMA interface. IDMA interface is very convenient for the RISC to exchange data with the DSP, but it will take tens of cycles to read or write a single WORD. So usually, the IDMA interface is used when the RISC initialize the DSP and do a few WORDs of data exchange when the DSP is running. When large amount of data need to be exchanged between the RISC and the DSP, use the DSP’s DMA function



3.6 Differences between the DSP and ADI’s ADSP2181 Though the DSP is intruction compatible with the ADI’s ADSP2181, there are minor differences between them. Programmer should take care of these differences when writing code. 3.6.1 Memory As described above, the DSP’s internal memory are divided into three separate parts. Because instructions accessing program memory are actually accessing the 16bit program-data memory, so there is no PX register. Writing to PX register is a null operation, and reading from PX register always gets 16-bit zero value. 3.6.2 Instructions Some of the ADSP2181 instructions are not supported in the DSP. These instructions will be treated as NOP. These non-supported instructions are listed in the following:

Call or Jump on Flag In Modify Flag Out ENA INTS and DIS INTS

3.6.3 Biased-rounding mode The biased rounding mode is also supported in Faraday’s DSP. Because bit 12 of memory mapped register at address 0x3ff3 is used by other purpose, the rounding mode control bit is moved to bit 10 of memory mapped register at address 0x3fff. When this bit is set to default value 0, unbiased rounding mode is used, when this bit is set to 1, biased rounding mode is used. 3.6.4 Non-memory mapped registers The definition of ICNTL is different from that of ADSP2181: the IRQ2 sensitivity is defined on bit 0 and IRQ0 sensitivity is defined on bit 2. The operation of counter CNTR (used for conditional jump/call that test CE instructions) is opposite to that of ADSP2181. For instructions: IF NOT CE JUMP/CALL <addr>; If CE is true, CNTR will be decremented by 1. If CE is not true then the top of count stack will be popped to CNTR. The definition of PMOVLAY register is different from that of ADSP2181. Bit 7-4 of PMOVLAY register is defines program-data memory overlay number and bit 3-0 defines program-code memory overlay number. Writing 0xMN to PMOVLAY will set program-data memory overlay to M and program-code memory overlay to N. If M or N is 0xF, the value will be unchanged. For PALM-II, there is no overlay memory in program memory and PMOVLAY will always set to default value 0. 3.6.5 Memory mapped registers The address and meaning of memory mapped registers are totally different from ADSP2181. The description of those registers are listed in “F2016 16-bit DSP Microcomputer specification” and other Atlas™ specified registers are listed in “Atlas™ Developer’s Manual” 3.6.6 Critical path limitation There is critical path in the DSP on following instruction combination: I register read from data memory followed by a data memory access using this I register. That is because data memory read will get



effective data on data bus at the next cycle of read, while it should be put on the address bus at the same cycle. The existing of critical path limites program with such instruction combination can not run over 120MHz. Programmer should eleminate critical path instructions by inserting NOP or changing instruction sequence.



4 Dynamic Memory Interface

4.1 Operation Overview Atlas™ supports the SDRAM interface at a maximum frequency of 100 MHz. The SDRAM Interface supports up to four groups of SDRAMs. All the SDRAMs used should be of the same type, operate at the same clock frequency and voltage. Each group can be placed in self-refresh mode independently. The bit-width of the SDRAM can be either 16 or 32 bits wide. In 16-bit mode, two consecutive pieces of data – each 16-bits wide - is fetched by the SDRAM interface and returned to system memory as a 32-bit wide data. The memory mapping from SDRAM to internal system memory is done automatically through hardware logic. The Memory controller can be programmed into normal operation mode. It can also be put into sleep mode by software or hardware.



4.2 Pin Sharing The MCS<3:2>, MCE<3:2> pins of SDRAM chip select 2,3 are shared with GPIO. If user needs SDRAM chip select up to 3 or 4, user needs to program RSC block to enable the SDRAM controller’s control over these pins. The following sample code is used to enable the SDRAM controller’s control over these pins.

RSC_PIN_MUX |= 0x1e0; //use MCKE<2:3>,MCS_B<2:3> as SDRAM pins PWR_PIN_RELEASE = 1; //release power manage pin holding //Configure system clock; … //Configure SDRAM; …



4.3 Normal Operation When booting from static memory interface or NAND flash, user need to program the Dynamic Memory Interface for proper type of SDRAM used on the board. Registers MEMC_SDTIM, MEMC_CFG, MEMC_SDCFG contain the timing information for the type of SDRAM used on the board. In the following example the MT48LC8M16A2-75 is used, the system & SDRAM interface is expected to run at 96Mhz (TSYS =10.4ns). MT48LC8M16A2-75 is a 16bit width SDRAM. To form 2 group of 32-bit SDRAM, 4 chips are needed. For MEMC_SDTIM Register:

1) MEMC_SDTIM<3:0> defines Number of refresh cycles in initialization. E.g. MT48LC8M16A2-75 requires 2 auto-refresh commands in initialization: MEMC_SDTIM<3:0> = 2

2) MEMC_SDTIM <7:4> defines Number of NOP cycles after SDRAM Bank Active command. E.g. For MT48LC8M16A2-75, tRCD = 20 ns. 2*T SYS = 20.8ns > tRCD: MEMC_SDTIM<7:4> = 2

3) MEMC_SDTIM <11:8> defines Number of NOP cycles after SDRAM Precharge command. E.g. For MT48LC8M16A2-75, tRP = 20 ns. 2*T SYS = 20.8ns > tRP : MEMC_SDTIM<11:8> = 2

4) MEMC_SDTIM<15:12> defines Number of NOP cycles after SDRAM Refresh command. E.g. For MT48LC8M16A2-75, tRFC = 66 ns. 7*T SYS = 72.8ns > tRFC: MEMC_SDTIM<15:12> = 7

5) MEMC_SDTIM<26:16> defines Refresh Period, in number of 16*system memory clock (MCLK) cycles. E.g. MT48LC8M16A2-75 needs one auto-refresh every 15.625 us, 93*16*T SYS = 15.475us <

16.625 us: MEMC_SDTIM<26:16> = 93.

6) MEMC_SDTIM<28:27> defines CAS Latency. E.g. To define CAS latency to be 3. MEMC_SDTIM<28:27> = 3

7) MEMC_SDTIM<31:29> defines Memory Type. E.g. MT48LC8M16A2-75 is a piece of 8M*16 SDRAM MEMC_SDTIM<31:29> = 5

For MEMC_CONFIG Register:

1) MEMC_CONFIG<8> defines the SDRAM data bus width. For example, 32-bit SDRAM data bus is used: MEMC_CONFIG<8> = 1

2) MEMC_CONFIG<9> should be written as 1

3) All other register are for test purpose and should be written as 0 For MEMC_SDCFG Register:



1) MEMC_SDCFG<3:0> defines the Number of chip select signals used. For example, 2 group of SDRAM are used (2 chip select): MEMC_SDCFG<3:0> = 0xC.

2) All other register are for test purpose and should be written as 0 If program is booting on static memory interface or NAND flash, the SDRAM can be configured as following. The MEMC_POWER register needs to be programmed to initialize SDRAM.

//Configure System clock. … MEMC_SDTIM=0xB85D7222; MEMC_CONFIG=0x200; MEMC_SDCFG=0xc; MEMC_POWER=0x4F;



4.4 Wake-up Operation After wake up from sleep, the SDRAM pins are hold by Resource Sharing Controller. User should release the pin before initialize the SDRAM. For the example used previously, the SDRAM should be initialized like following:

//Configure System clock. … MEMC_SDTIM=0xB85D7222; MEMC_CONFIG=0x200; MEMC_SDCFG=0xc; PWR_SLEEP_STATUS = 0x8; // clear SDRAM_HOLD bit if wakeup from

sleep mode MEMC_POWER=0x4F;



4.5 Clock Switching Operation User is able to switching system clock when the software is still running (Pleaser refer to the Chapter 6 “Clocks and Power Manager”). However when system clock is changed, the SDRAM interface timing changed accordingly. User should change the timing register MEMC_SDTIM before clock switch actually happen, There are two types of clock switching: 1) Clock switch from PLL to 12MHz Oscillator Before the switching actually happens, refresh period needs to be reconfigured; otherwise the refresh period will be too big and does not meet the SDRAM requirement. When SDRAM refresh period is changed to smaller value, user need to manually refresh SDRAM by reading one value from each column in the SDRAM. After the switching actually happens, user can change all other timing value for system performance. However, if 12MHz is only a temporary setting (clock will be switched back to PLL soon), user does not need to change those values. 2) Clock switch from 12MHz Oscillator to PLL Before the switching actually happens, user needs to change the timing values except for refresh period for correct SDRAM interface timing. After the switching actually happens, user needs to change refresh period to an appropriate value to make the system performance more effective. The following sample codes detail the clocking switch from 96MHz to 12MHz, and then back to 96MHz:

volatile int TempReadValue; int i; … MEMC_SDTIM= (MEMC_SDTIM & 0x7FF0000) | 0x 30000; // read one data from each column for refresh purpose, for(i=0;i<=0x2000000;i=i+512*4) {

// SDRAM start address is mapped to 0xC0000000. This address should be un-cacheable.

//the total SDRAM size is 0x2000000 in bye. Each column contains 512*4 byte.

TempReadValue = (volatile unsigned *) (0xC0000000 + i); } … //Switch clock to 12MHz … //Change other timing value in MEMC_SDTIM for performance only. … //Change other timing value in MEMC_SDTIM to fit the new system clock. … //Switch clock to new system clock …



//Change refresh period in MEMC_SDTIM for performance only. …

4.6 Self-refresh Mode User can put SDRAM into self-refresh mode when needed. However after SDRAM is put into self-refresh mode, if program fetches data from SDRAM again, the SDRAM will be waked up automatically. So it is necessary to put the code on to CPU’s Instruction Cache to make sure there is no SDRAM access after SDRAM is put into self-refresh mode. The following codes will put SDRAM into self-refresh mode and should already be put on CACHE.

MEMC_POWER=0x7e;//make all chip select self refresh … MEMC_POWER=0x7f;//make all chip select out of self refresh

In the previous sample code there are 4 chip-select signals being used. But even if there are only 1, 2 or 3 chip-select signals being used, the code can still be used. The unused chip-select will not affect anything if they are programmed to be GPIO.



5 Static memory Interface

5.1 Operation Overview The static memory interface has three functions:

• Boot-loader device during boot-up • Storage device after boot-up. • Extended interface for SRAM-like fixed latency I/O (FLIO) after boot-up.

When powered up, the central processor will boot up from the static memory interface. It will execute boot code on the Flash or ROM. The boot code will read and copy the program from the Flash or ROM into main system memory (SDRAM). In other words, in boot-up mode, the Flash/ROM will be shadowed as part of system memory. However, after boot-up, the static memory interface can also be file related, such as a storage device. During boot-up, the static memory interface is mapped to the bottom of system address starting from 0x0000 0000. The code in the Flash or ROM should have an appropriate boot-loader at the base address. The processor will execute the boot-loader first, during which it will configure the SDRAM and initialize the hardware properly. The boot-load code will then copy the program code into system memory. Two methods are available to execute this copy:

• The processor can read a chunk of 32-bit word from the static memory interface directly and then it write the word to the system memory.

-- or -- • The processor can configure the static memory interface into DMA mode and wait until DMA

finishes. After boot-up, the static memory interface can be considered a simple I/O device. It has a dedicated DMA channel for data transfer to/from SDRAM. Most operations related to static memory will be act like "file related" operations. For example, the system can save an image file into the Flash, just like it would a regular storage device. Besides access through DMA, the processor may still be able to access the static memory interface via memory mapped addresses. This comes in extremely useful since some FAT related operations do not need to be done through DMA. In summary, the static memory interface will have two operation modes after boot-up: memory mapped access ( direct access) and DMA. The static memory interface register should be properly programmed for these different operational modes. In DMA mode, the static memory interface uses DMA channel 4.

5.2 Instruction Access Mode This is recommended for use only during boot-up. The chip select 0 of Static Memory is set into Instruction Access Mode on reset. Other 3 chip select can be configured into Instruction Access Mode by software. When RISC read data from address 0x1000_0000 to 0x1fff_ffff, the RISC Interface will redirect the read command to read data from Static Memory Interface. The following table shows the mapping from different internal address to different chip selects. Table 6. Staitic Memory Chip Select Mapping

Chip select 0 0x1000_0000~ 0x13FF_FFFF Chip select 1 0x1400_0000 ~ 0x17FF_FFFF



Chip select 2 0x1800_0000 ~ 0x1bFF_FFFF Chip select 3 0x1C00_0000 ~ 0x1FFF_FFFF

After reset, the address space from 0x0000_0000~0x0FFF_FFFF is shadowed with 0x1000_0000 ~ 0x1FFF_FFFF. RISC will fetch the first instruction from address 0x0000_0000. When NAND_BOOT is pulled-low, it is redirect to Static memory chip select 0. In this mode, all the read are 32-bit wide. For different Static Memory Interface bit width, the 32-bit DWORD is mapped as little endian, which is shown in the following figures:

Figure 3. Data Mapping in 8-bit External Data Bus

Figure 4. Data Mapping in 16-bit External Data Bus In Instruction Access Mode any write command from RISC is ignored by the Static Memory Interface.

D<31:24> D<23:16> D<15:8> D<7:0>

Internal Data Bus (32-bit)

D<31:24>

D<23:16>

D<15:8>

D<7:0>

External Data Bus (8-bit)

{A<23:2>, 2’b00} {A<23:2>, 2’b11}

{A<23:2>, 2’b10}

{A<23:2>, 2’b01}

{A<23:2>, 2’b00}

D<31:24> D<23:16> D<15:8> D<7:0>

Internal Data Bus (32-bit)

D<31:16>

D<15:0>

External Data Bus (16-bit)

{A<23:2>, 2’b00} {A<23:2>, 2’b10}

{A<23:2>, 2’b00}



5.3 Direct Access Mode In this mode, the Static Memory Interface will be considered as a simple IO device. It will respond to RISC Access on address 0x1000_000 to 0x1FFF_FFFF. The address to chip select mapping is the same as Instruction access mode. The different between this mode and Instruction Access Mode is as following:

• Instruction Access Mode do now allow write, all write are treated as nop command. • Direct Access Mode allow write to Static Memory. • Instruction Access Mode’s access width is always 32-bit access. • Direct Access Mode’s access width depends on the Static Memory Interface width set in the

ROM_CFG_CS register. For 8bit width Static Memory Interface, user can only use 8-bit access in software, other access will cause unknown operation on the Static Memory Interface. For 16bit width Static Memory Interface, user can only use 16-bit access in software, other access will cause unknown operation on the Static Memory Interface. The mapping from internal data access to static memory is the same in Instruction Access mode. Following sample code is used to access 8-bit width FLASH. char FlashData; int FlashAddress; // Configure chip select 1 as direct access mode, 8 bit width ROM_CFG_CS01= ROM_CFG_CS01 &0xFFFCFFFF; FlashAddress=0x1; // Direct read data from offset 0x01 in chip select 1 FlashData = (*((volatile unsigned char *)(0x14000000 + FlashAddress))); // Perform a direct write to offset 0x01 in chip select 1 (*((volatile unsigned char *)(0x14000000+ FlashAddress))) = FlashData ; Following sample code is used to access 16-bit width FLASH. In 16-bit access, the offset address should be multiple of 2, because the address 0 is always zero in 16-bit width mode. short FlashData; int FlashAddress; // Configure chip select 2 as direct access mode, 8 bit width ROM_CFG_CS23 = (ROM_CFG_CS23 & 0xFFFFFFFC ) | 0x1 ; // Direct read data from offset 0x02 in chip select 2 FlashAddress=0x2; FlashData = (*((volatile unsigned short *)(0x18000000 + FlashAddress))); // Perform a direct write to offset 0x01 in chip select 1 (*((volatile unsigned short *)(0x18000000 + FlashAddress)))= FlashData ;



5.4 DMA Access Mode In this mode, Static Memory Interface will perform bulk data read/write through internal FIFO, relieve the burden of CPU to do every transaction. The internal FIFO can talk with both RISC through read/write IO register and system memory through DMA channel 4. 5.4.1 DMA read User should properly configure ROM_CFG_CS01, ROM_CFG_CS23 for each chip select of Static Memory Interface. User should configure which chip select will be used in DMA, DMA will start from which address in the chip select. This is done by configure ROM_START_ADDR Register. SA<27:26> define which chip select to use in DMA as shown in the following table. Table 7. Staitic Memory Chip Select Mapping

SA<27:26> 2’b00 2’b01 2’b10 2’b11 Chip select 0 Active in DMA Chip select 1 Active in DMA Chip select 2 Active in DMA Chip select 3 Active in DMA

SA<25:0> decide the byte address from which to start DMA. User should set the FIFO control register for proper direction, DMA length, refer to FIFO controller for more information. User should also configure DMA controller for proper direction, DMA length, System memory start address. Refer to FIFO controller for more information. Following sample code is for DMA Read. #define DMA_MASK_BURST 0x08 #define DMA_MASK_WIDTH_0 0x00 #define DMA_MASK_TO_SDRAM 0x00 //configure dma and start dma,(the rom is not started yet, so no problem) DMA_WIDTH0 = 0xfff;//using DMA_WIDTH0 DMA_CH4_XLEN = 32; //Transfer 32 DWORD DMA_CH4_YLEN = 0x00; DMA_CH4_CTRL = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_TO_SDRAM); DMA_CH4_ADDR = (0x200000); //DMA start address in SDRAM //configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register



// Chip Select 1 use 16 bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width , Transfer 32 DWORD ROM_START_ADD = 0x2000000 ; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x06;// DMA, FLUSH // This is the FIFO_CTRL register setting for Static Memory Interface ROM_FIFO_CTRL_REG=0xFC; // set FIFO level check ROM_FIFO_LEVEL_CHK_REG = ( ( 0xa << 20 ) | ( 0x8 << 10 ) | ( 0x4 ) ); //start read DMA ROM_FIFO_OP_REG=0x01; //wait for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 ); 5.4.2 DMA write User should properly configure ROM_CFG_CS01, ROM_CFG_CS23 for each chip select of Static Memory Interface. User should configure ROM_START_ADDR register. It is the same as DMA read. User should set the FIFO control register for proper direction, DMA length, refer to FIFO controller for more information. User should also configure DMA controller for proper direction, DMA length, System memory start address. Refer to FIFO controller for more information. User should also configure ROM_WRITE_CTRL and ROM_WRITE_SEQ<2:0> registers for different write mode. 5.4.2.1 Simple Write Mode Static Memory Interface will perform one write operation for one data write. User should program ROM_WRITE_CTRL with

• TWC= actual write cycle time; • NWC= 1; • ADINT=0; • NSEQ=0;

The Interface timing diagram is should in the following figure.



Figure 5. Static Memory Interface Simple WriteTiming Notes: SA0, SA1 are address from ROM_START_ADDR. FD0, FD1 are data from FIFO. Depending on Interface Width, one 32-bit data in FIFO will be splitted into 2 or 4 FD. The data in FIFO is ordered as little endian. Following sample code is for DMA Simple Write. #define DMA_MASK_BURST 0x08 #define DMA_MASK_WIDTH_0 0x00 #define DMA_MASK_FROM_SDRAM 0x04 unsigned int twc; DMA_WIDTH0 = 0xfff; //using DMA_WIDTH0 only DMA_CH4_XLEN = 32; DMA_CH4_YLEN = 0x00; DMA_CH4_CTRL = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_FROM_SDRAM); DMA_CH4_ADDR = 0x100000;//Start address of dat in SDRAM; //configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register // Chip Select 1 use 16-bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width, Transfer 32 DWORD ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory , no flush ROM_FIFO_CTRL_REG=0x00; ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff;

FD0

T twc

SA0

X_FCE_B

FWE_B

FA

FD

SA1

FD1



ROM_WRITE_CTRL= ( ((0)&(0x3))<<12 | ((0)&(0x1))<<11 | ((1)&(0x7))<<8 | (twc)&(0xff) ); //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 ) { }; } 5.4.2.2 Fixed Sequence Write Mode Static Memory Interface will perform several (max 4) write operation for one data write. The leading several writes for one data write will be fixed data and address from registers ROM_WRITE_SEQ<2:0>. User should program ROM_WRITE_CTRL with

• TWC= actual write cycle time; • NWC= number of writes for one data write; (Max 4) • ADINT=0; • NSEQ=NWC-1; (Max 3 )

The Interface timing diagram is showed in the following figure. NWC is set to 3. There is totally 3 write operation for one write cycle. For the first data, there are 3 write operations. The First write operation write to the address stored in ROM_WRITE_SEQ0 with data stored in ROM_WRITE_SEQ0. The second write operation write to the address stored in ROM_WRITE_SEQ1 with data stored in ROM_WRITE_SEQ1. The last write operation write to current address stored in ROM_START_ADDR with data from FIFO. The address in ROM_START_ADD will increase automatically according to different Interface width. For the second data, there are 3 write operations. The First write operation write to the address stored in ROM_WRITE_SEQ0 with data stored in ROM_WRITE_SEQ0. The second write operation write to the address stored in ROM_WRITE_SEQ1 with data stored in ROM_WRITE_SEQ1. The last write operation write to current address stored in ROM_START_ADDR with data from FIFO. The address in ROM_START_ADD will increase automatically according to different Interface width.



Figure 6. Static Memory Interface Fixed Sequence WriteTiming Notes: SEQ0, SEQ1 are data and address from ROM_WRITE_SEQ0, ROM_WRITE_SEQ1 SA0, SA1 are address from ROM_START_ADDR. FD0, FD1 are data from FIFO. Depending on Interface Width, one 32-bit data in FIFO will be splitted into 2 or 4 FD. The data in FIFO is ordered as little endian. User needs to change the configure of ROM_WRITE_CTRL In the previos sample code. And add the configuration of registers ROM_WRITE_SEQ<1:0>. #define DMA_MASK_BURST 0x08 #define DMA_MASK_WIDTH_0 0x00 #define DMA_MASK_FROM_SDRAM 0x04 unsigned int twc; DMA_WIDTH0 = 0xfff; //using DMA_WIDTH0 only DMA_CH4_XLEN = 32; DMA_CH4_YLEN = 0x00; DMA_CH4_CTRL = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_FROM_SDRAM); DMA_CH4_ADDR = 0x100000;//Start address of dat in SDRAM; //configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register // Chip Select 1 use 16-bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; ROM_DMA_IO_LEN_REG = 32*2; //16 bit width, Transfer 32 DWORD ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory , no flush

T twc

SEQ0

X_FCE_B

FWE_B

FA

FD

SEQ0

SEQ1

SEQ1

SA0

FD0

SEQ0

SEQ0

SEQ1

SEQ1

SA1

FD1

NWC=3



ROM_FIFO_CTRL_REG=0x00; ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; ROM_WRITE_CTRL= (((2)&(0x3))<<12 | ((0)&(0x1))<<11 | ((3)&(0x7))<<8 | (twc)&(0xff)); ROM_WRITE_SEQ0 = sequence0; ROM_WRITE_SEQ1 = sequence1; //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 ); 5.4.2.3 Variable Sequence Write Mode Static Memory Interface will perform several (max 4) write operation for one data write. Each write operation’s address and data are got from FIFO. User should program ROM_WRITE_CTRL with:

• TWC= actual write cycle time; • NWC= number of writes for one data write; (Max 4) • ADINT=1; • NSEQ=0;

The Interface timing diagram is showed in the following figure. NWC is set to 3. There are totally 3 write operations for one write cycle:

• The First write operation will read one 32-bit from FIFO, only LSB 28-bit are used as write address. After that it will read another 32-bit from FIFO, only LSB 16/8-bit(depending on interface width) are used as write data.

• The Second write operation will read one 32-bit from FIFO, only LSB 28-bit are used as write address. After that it will read another 32-bit from FIFO, only LSB 16/8-bit(depending on interface width) are used as write data.

• The Third write operation will read one 32-bit from FIFO, only LSB 28-bit are used as write address. After that it will read another 32-bit from FIFO, only LSB 16/8-bit(depending on interface width) are used as write data.



Figure 7. Static Memory Interface Fixed Sequence WriteTiming Notes: FA0 … FA6, FD0 .. FD6 are data from FIFO. Each 32-bit data in FIFO only contain only FA or on FD. ROM_START_ADDR, ROM_WRITE_SEQ<2:0> registers will not be used in this mode. Their value will be unknown. Following code is the sample for DMA variable sequence write. #define DMA_MASK_BURST 0x08 #define DMA_MASK_WIDTH_0 0x00 #define DMA_MASK_FROM_SDRAM 0x04 unsigned int twc; DMA_WIDTH0 = 0xfff; //using DMA_WIDTH0 only DMA_CH4_XLEN = 32; DMA_CH4_YLEN = 0x00; DMA_CH4_CTRL = (DMA_MASK_BURST | DMA_MASK_WIDTH_0 | DMA_MASK_FROM_SDRAM); DMA_CH4_ADDR = 0x100000;//Start address of dat in SDRAM; //configure Static Memory Interface //reset fifo ROM_FIFO_OP_REG=0x2; ROM_FIFO_OP_REG=0x0; ROM_INT_STATUS=0xfff; //Static Memeory Interface register // Chip Select 1 use 16-bit data bus width ROM_CFG_CS01= ROM_CFG_CS01 | 0x10000; //16 bit width, Transfer 32 DWORD, both data and address are get from FIFO ROM_DMA_IO_LEN_REG = 32*2*2; ROM_START_ADD = = 0x2000000; //start from offset 0 ROM_DMA_IO_CTRL_REG=0x0;//dma, write to static memory, no flush ROM_FIFO_CTRL_REG=0x00;

T twc

FA0

X_FCE_B

FWE_B

FA

FD

FD0

FA1

FD1

FA3

FD3

FA4

FD4

FA5

FD5

FA6

FD6

NWC=3



ROM_FIFO_LEVEL_CHK_REG=(0xb);//fifo level check //twc is the actually write cycyle time, user needs to change the vaule to //fit the actual system twc=0xff; ROM_WRITE_CTRL= (((0)&(0x3))<<12 | ((1)&(0x1))<<11 | ((3)&(0x7))<<8 | (twc)&(0xff)); //start dma ROM_FIFO_OP_REG=0x1; //waiting for done status while( (ROM_INT_STATUS&ROM_INT_MASK_DONE)==0 );



6 Clocks and Power Manager

6.1 Operation Overview There are totally 4 clock sources in Atlas™: 32.768 KHz Oscillator, 12 MHz Oscillator, and two programmable PLL’s. And there are 7 clock domains:

• System Clock Domain (including DSP, Memory Controller, LCD Controller, System Arbiter, and other system control modules)

• CPU Clock Domain (including the ARM922T RISC core) • I/O Clock Domain (including the I/O Bridge, DMA Controller, and all the peripheral modules) • External Memory Clock Domain (only for external SDRAM chips) • USB Clock Domain (only for USB device core) • Bluetooth Clock Domain (only for Bluetooth baseband core) • External Clock Domain (only for External Clock Output)

Except for the Bluetooth Clock Domain (which is clocked by external Bluetooth RF module), each clock domain can be programmed to select one of these 4 clock sources. Besides of that, some clock domains can be configured to different clock ratios. NOTE: CPU is actually involved with two clock domains: CPU Clock Domain and System Clock Domain. The reason is that the CPU has two clock inputs: one for core clock and the other for bus clock. The bus clock is always the same as Atlas™ system clock (i.e. in System Clock Domain); the core clock is in CPU Clock Domain. User can change the PLL output frequency from 12MHz up to 240MHz by programming the PLL Configuration Registers (PWR_PLL1_CONFIG & PWR_PLL2_CONFIG). To save the power consumption, most blocks’ clock can be disabled independently by software. And for even lower power consumption, the Atlas™ can be forced into the sleep mode. NOTE: When SDRAM is used as system memory, user needs to be careful when changing the system clock rate. In some cases, the SDRAM refresh rate needs to change accordingly. Please refer the section 4.4 “Clock Swithcing Operation” for more details.



6.2 Change Clock Source The Atlas™ system can be programmed to use either PLL1 or PLL2 as the clock source. In addition, it can also select the oscillator (12MHZ or 32.768KHz) outputs as the clock source. The switching of the clocks can take place in real-time while Atlas™ is running. If the 32.768KHz oscillator output is selected, the whole system will run at the same 32.768KHz frequency. Otherwise, different parts of the system can be switched to different clock sources independently:

• The system clocks (including the CPU bus clock, the DSP clock, the GPS clock, the LCD clock, etc.), external memory clock, and internal I/O clocks can only be switched to different clock sources at the same time.

• The CPU clock, USB clock, and the External clock outputs can be switched to different clock sources separately.

During the Atlas™ boot-up, the following clock switching steps need to be followed:

• After reset, both PLL1 and PLL2 are in power-down mode, and will be bypassed by the system clock. The clock will use the 12MHz oscillator by default.

• The boot-up program will set up the clock configuration registers (PWR_PLL1_CONFIG) and turn on the PLL.

• After the PLL is stable, the boot-up program will switch the clock from the 12MHz oscillator to the PLL.

NOTE: Before switch the clock source to PLL, make sure the PLL has already powered up and stable. Here is an example to switch the clock source to PLL1: //All clocks switch to pll1 PWR_CLK_SWITCH = 0x55; for (i=1;i<=10;i++); NOTE: It’s suggested to delay for several cycles for the operations for waiting the clock switch finishes. In some cases, the whole system can run from a single clock source and the other unused PLL(s) can be powered down to save power.



6.3 Change Clock Ratio Although the system clocks, external memory clock, and internal I/O clocks are using the same clock source, they can be programmed to different clock ratios by configuring the clock ratio register:

• System clocks can be programmed to be either 1/1 or ½ of the clock source • External memory clock can also be programmed to be 1/1 or ½ of the System clocks • Internal I/O clocks can be programmed to be ½ or ¼ of the System clocks

6.3.1 Change the System and I/O Clock Ratio Here is an example to change the system clock to be ½ of the clock source, and the I/O clock to be ¼ of the clock source. //system clock ratio = 1:2, I/O clock ratio = 1:4 PWR_CLK_RATIO = 0x3; for (i=1;i<=10;i++); NOTE: It’s suggested to delay for several cycles for the operations for waiting the clock ratio change finishes. In the above example, if the clock source is 100 MHz, then the system clock will be 50 MHz and the I/O clock will be 25 MHz. The capability of changing system clock ratio provides a way to achieve better performance/power ratio. For example, for those applications needs intensive CPU power but less data input/output, user can configure the system clock to be half of the CPU clock. Besides, the capability of changing I/O clock ratio can better fit applications requirements of the I/O clock speed. One thing needs to be noted is: when user configure the system clock ratio to be 1:2, then it means the CPU may not be in Fast Bus mode1 anymore. User can still configure the CPU to be in Fast Bus mode in this case, but then the CPU core clock will be the same as the bus clock (system clock), i.e. ½ of the clock source. Or, user can configure the CPU to be in Synchronous or Asynchronous mode, i.e. CPU core clock is twice of the CPU bus clock. This is called Turbo mode and more details can be found in the section 6.5.2. Besides, when the I/O clock ratio is changed, the RISCINT_WIDTH register needs to be changed accordingly. // When I/O clock ratio is 1:2 RISCINT_WIDTH = 0x10; // When I/O clock ratio is 1:4 RISCINT_WIDTH = 0x30; 6.3.2 Change the External Memory Clock Ratio The following example shows the changing of external memory clock ratio: //memory clock ratio 1:2 MEMC_CFG = 0x300; for (i=1;i<=10;i++); 1 ARM922T has three different clocking modes: Fast Bus mode, Synchronous mode, and Asynchronous mode. Please refer to the ARM922T datasheet for more details.



The capability of changing the clock ratio provides a further tunning of performance/power ratio. For example, for those applications do not need high memory bandwidth but has intensive DSP calculations, then we can configure the memory clock to be half of the system clock. NOTE: To change the external memory clock ratio must be done when program is running either on Flash/ROM or in Instruction Cache. Otherwise, unexpected result may happen.



6.4 Change PLL Frequency To change the PLL frequency, user needs to program the PLL configuration registers (PWR_PLL1_CONFIG & PWR_PLL2_CONFIG). And it’s suggested to following the steps as:

1. Switch the clock source to other PLL or oscillators (if the current PLL is in use) 2. Stop the current PLL 3. Re-configure the current PLL 4. Start the current PLL 5. Wait for PLL stable 6. Switch the clock source back to the current PLL

Here is a basic example showing the above programming steps: // Switch the clock source to PLL2 PWR_CLK_SWITCH=0xAA; for(i=1;i<=10;i++);

// Stop PLL1 PWR_CLK_CTRL = 0x2; // Configure PLL1 PWR_PLL1_CONFIG = 0x3099; //150Mhz

// Start PLL1 PWR_CLK_CTRL = 0x03; for(i=1;i<=40;i++); // wait for PLL stable // Switch back to PLL1 PWR_CLK_SWITCH=0x55; for(i=1;i<=10;i++); NOTE: Due to the PLL limitation, the output frequency has to be the multiple of 6 MHz (half of the 12 MHz Crystal input). Or, in another words, the pre-divider (MS<5:0>) has to be set to 1 or 2.



6.5 Power Mode The Atlas™ can operate at different operation modes:

• Turbo mode: the CPU runs at its peak frequency (higher than System clocks) • Normal mode: the CPU runs at its normal frequency (equal to the System clocks) • Idle mode: the CPU enters IDLE mode and each of the other blocks in system can be disabled

separately too • Standby mode: the whole system runs at the 32.768KHz • Sleep mode: the most of the system stops clocking except the RTC and Power Manager

The Atlas™ contains power management logic that controls the transition between all these different modes of operations. This part of logic can only be controlled by the RISC but not DSP Core. 6.5.1 Normal Mode Normal mode is the normal operating mode of the Atlas™: all power supplies are enabled, all clocks are running, and every on-chip resource is functional. And the CPU runs at the same clock rate as the other part of the system (except for the I/O peripherals). Under usual conditions, the chip enters normal mode after successful power-up and reset of the part. 6.5.2 Turbo Mode In Turbo Mode, the CPU clock runs at a higher clock rate (than System clocks) that is either asynchronous to or double of the System clocks. For example, the system clock runs at 100MHz, while the CPU runs at 200MHz or even 240MHz. To configure the Atlas™ into Turbo mode, there are two things need to be done:

1. Configure the CPU into Synchronous or Asynchronou mode 2. Configure the CPU core clock (CPU Clock Domain) and bus clock (System Clock Domain)

Here is an example to configure the CPU in Synchronous or Asynchronous clock modes:

LDR r0, =0x0 IF :DEF:ARMCPU_ASYNC_MODE

IF ARMCPU_ASYNC_MODE = "ON" INFO 0, "Using ARM922 Asynchronous Mode" LDR r0, =0xc0000000 ENDIF

ENDIF

IF :DEF:ARMCPU_SYNC_MODE IF ARMCPU_SYNC_MODE = "ON"

INFO 0, "Using ARM922 Synchronous Mode" LDR r0, =0x40000000 ENDIF

ENDIF As for how to configure the CPU core clock and bus clock, please refer to the previous sections. 6.5.3 Idle Mode



Idle mode allows software to put each block into idle, even the RISC itself. When RISC is in idle, it continues to monitor interrupt service requests on or off-chip. When an interrupt occurs, the RISC is reactivated. The RISC enters the idle mode by executing a three-instruction sequence consisting of the CP15 instruction ‘disable clock switching’, a load from non-cacheable memory location (C=B=0), and the CP15 instruction ‘wait for interrupt’. Following are the code example of force RISC into idle mode: ldr r1, =0xA8000000 ; just an arbitrary uncachable location mcr p15, 0, r0, c15, c2, 2 ; disable clock switching ldr r0, [r1] mcr p15, 0, r0, c15, c8, 2 ; go idle nop nop mcr p15, 0, r0, c15, c1, 2 ; (re)enable clock switching The RISC can also put other blocks into idle, including the DSP Core1, by programming a corresponding register bit in PWR_CLK_EN to disable or enable the clock of that block. Here is an example: // enable all block's clock PWR_CLK_EN = 0x1FFFF; 6.5.4 Standby Mode In Standby Mode, the whole system runs at the clock rate the same as the RTC (32.768KHz). This is useful when sometimes the system is doing a non-urgent job but need to stay alive for a long time. To enter the Standby mode, user just needs to write: // Switch all clocks to 32KHz

PWR_CLK_SWITCH = 0x03; for(i=1;i<=10;i++); But when system is using SDRAM as the external system memory, it’s impossible to use the clock as low as 32.768 KHz. It’s too slow for the SDRAM refresh. In this case, user might want to use a higher frequency crystal or oscillator (e.g. 1MHz) to replace the 32.768 KHz crystal. 6.5.5 Sleep Mode Sleep mode offers the greatest power savings to the user and consequently the lowest level of available functionality. In the transition from run or idle to sleep mode, the Atlas™ performs an orderly shutdown of on-chip activity, applies an internal reset to the processor, and then negates the PWR_EN pin indicating to the external system that the Atlas™ is in sleep mode. Running off the 32.768 kHz Oscillator, the sleep state machine watches for a preprogrammed wake-up event to occur, after which it asserts PWR_EN pin, and steps through an orderly wake-up sequence. When the power supply and clocks are stable, the power manager brings the Atlas™ out of reset. There are two methods to enter the sleep mode: by software or by hardware. The usage of software sleep is: when power down button is pressed, the software will stops all the current jobs being running; and then configure the Atlas™ to sleep mode in the following sequence:

• Enable 12MHz Oscillator power down in sleep mode (PWR_CONFIG) – only when if needed 1 The DSP Core has its own 'idle' mode too. By issuing IDLE instruction, the DSP Core will wait indefinitely in a low power state until an interrupt to DSP occurs. That 'idle' is in different level with this idle mode. Please refer to the DSP section for more details.



• Set wakeup event (PWR_WAKEUP_EN) o It can be waked up by GPIO, or, o It can be waked up by Real-time Clock Alarm

• Set wakeup wait time for power ramp and Oscillator stable (PWR_WAIT_TIME) • Set force sleep bit (PWR_CTRL)

Here is an example of the software sleep: #define RTC_DIVISION 1000 #define ALARM_VALUE 1000 #define WAIT_OOK_TIME 0xff #define WAIT_OPU_TIME 0xff

// Enable 12MHz crystal power down in sleep mode PWR_CONFIG=0x01; // Set real-time clock division RTC_DIV = RTC_DIVISION; RTC_COUNTER = 0x0; // Set Alarm value RTC_ALARM = ALARM_VALUE; // alarm value // Set wakeup event PWR_WAKEUP_EN = 0x80000000; // wakeup by alarm PWR_WAIT_TIME = (WAIT_OOK_TIME | (WAIT_OPU_TIME << 16)); // Enter sleep mode PWR_CTRL=0x01; While the hardware sleep is for another usage: when the system battery or power source is fail to provide enough current to Atlas™, the Atlas™ will go to sleep mode automatically to save the power consumption. This is done by the BATT_FAULT or VDD_FAULT pin. The power-down sequence is almost the same as the software sleep, except user does not need to set the force sleep bit in PWR_CTRL register. When Atlas™ is waked up from the sleep mode, user can read the PWR_SLEEP_STATUS register to find out if it’s a wakeup from software sleep or hardware sleep.



7 GPIO

7.1 Operation Overview The Generous Purpose Input Output (GPIO) logic of the Atlas™ processor controls 28 pins through the use of 16 registers which control the pin direction (input or output) pin function, pin state (outputs only), pin level detection (inputs only). Some of the GPIOs can be used to bring the Atlas™ processor out of Sleep mode. In all the following configurations, PWR_PIN_RELEASE must be set to 1 so that Resource Sharing Controller does not control GPIO pins anymore.



7.2 Configure GPIO Pin Sharing

• GPIO<24:27> are shared with memory interface pin MCKE<2:3>, MCS_B<2:3>.

RSC_PIN_MUX &= 0xfffffe1f; //use MCKE<2:3>, MCS_B<2:3> as GPIO<24:27> PWR_PIN_RELEASE = 1; //release power manage pin holding

• GPIO<23:21> are shared with USP0 port.

RSC_PIN_MUX &= 0xfffeffff; //use SCLK0, TFS0, RFS0 as GPIO<21:23> PWR_PIN_RELEASE = 1; //release power manage pin holding

• GPIO<20:16> are shared with the JTAG interface.

• GPIO<20:16> are used as JTAG pin when JTAG mode is selected on reset (TEST_MODE<1:0>

=2’b10 on reset). Otherwise those pins are used as GPIO pins.

• GPIO<15:8> are shared with the LCD Controller.

RSC_PIN_MUX &= 0xfffffffe; //use LDD<8:15> as GPIO<8:15> PWR_PIN_RELEASE = 1; //release power manage pin holding



7.3 Configure GPIO as Input The following codes configure GPIO0 as an input and will generate interrupt on rising-edge.

GPIO_INT_EN &= 0Xfffffffe; //disable GPIO interrupt on gpio0 GPIO_OUT_EN &= 0xfffffffe; //configure GPIO0 as input GPIO_PULL |= 0x01; //set GPIO0 as pull down GPIO_INT_TYPE |= 0x1; // set GPIO0 as edge triggered interrupt GPIO_INT_HT |= 0x1; // with GPIO_INT_TYPE set to 1, set the GPIO0

rising-edge as the interrupt source GPIO_INT_LT &= 0xfffffffe; //disable falling-edge on GPIO0 to generate

interrupt. GPIO_OD &= 0xfffffffe; // do not use GPIO0 as open-drain. GPIO_INT_STATUS &= 0x01; //clear GPIO0 interrupt before enable the

interrupt GPIO_INT_EN |= 0X01; //enable GPIO interrupt on gpio0

To get the current value of GPIO0, user can access register GPIO_DATA_IN:

value = GPIO_DATA_IN & 0x01;



7.4 Configure GPIO as Output The following codes configure GPIO0 as an output.

GPIO_DATA_OUT &= 0xfffffffe; //set GPIO0 output value as 0 GPIO_OUT_EN |= 0x01; //configure GPIO0 as output

If GPIO0 is already set as output, user only need to change GPIO_DATA_OUT to desired value.

GPIO_DATA_OUT |= 0x01; //set GPIO0 output value as 1



7.5 Configure GPIO as Open-Drain User can program GPIO_OD to put GPIO into open-drain mode. In open-drain mode, if GPIO_DATA_OUT is 0, the pin will output 1’b0; if GPIO_DATA_OUT is 1, the pin is served as an input and pulled to high using internal pull high resistor. In open-drain mode the GPIO_OUT_EN is not used. The following codes configure GPIO0 as an open-drain and output a logic 0.

GPIO_DATA_OUT &= 0xfffffffe; //set GPIO0 output value as 0 GPIO_OD |= 0x01; // set GPIO0 as an open-drain pad.

After GPIO is configured as open user can change the GPIO_DATA_OUT to set the open-drain as logic 0 or high impedance.

GPIO_DATA_OUT |= 0x01; //set GPIO0 as high impedance. In the open-drain mode, user can also use the GPIO as a source for the interrupt. The following codes configure GPIO0 as an open-drain pad and will generate interrupt on rising-edge.

GPIO_INT_EN &= 0xfffffffe; //disable GPIO interrupt on gpio0 GPIO_DATA_OUT |= 0x01; //set GPIO0 as high impedance. GPIO_OD |= 0x01; // set GPIO0 as an open-drain pad. GPIO_INT_TYPE |= 0x1; // set GPIO0 as edge triggered interrupt GPIO_INT_HT |= 0x1; // with GPIO_INT_TYPE set to 1, set the GPIO0

rising-edge as the interrupt source GPIO_INT_LT &= 0xfffffffe; //disable falling-edge on GPIO0 to generate

interrupt. GPIO_INT_STATUS &= 0x01; //clear GPIO0 interrupt before enable the

interrupt GPIO_INT_EN |= 0X01; //enable GPIO interrupt on gpio0



7.6 Configure GPIO as Wake-up Source GPIO<0:15> can be used to wake the Atlas™ in sleep mode. Before the chip go into sleep mode user need to configure GPIO_SL_VAL, GPIO_SL_OE to set the value and output enable of GPIO in sleep mode. In sleep mode the pin sharing of GPIO is not needed, all the pin are controlled by GPIO. The following codes set all the GPIO as input in sleep mode, use GPIO0 high to wake-up the Atlas™.

GPIO_SL_VAL=0x0; GPIO_SL_OE=0x0; // set GPIO as input in sleep mode GPIO_PULL = 0xffffffff; // set GPIO as pull down GPIO_INT_HT=0x00;//enable GPIO high trigger for GPIO [0] GPIO_INT_LT=0x01;//disable GPIO low trigger for GPIO [0] PWR_WAKEUP_EN= 0x3ff0001; //use GPIO [0] to wake up Atlas™. PWR_CTRL=0x01; //force up Atlas™ into sleep mode. …

After Atlas™ is put into sleep, the GPIO_SL_MODE register is set to 1. Even after wake up this register is also set to 1, user need to clear this register to put GPIO into normal function mode.

GPIO_SL_MODE= 0x0; //after wake-up, put GPIO into normal function mode.



7.7 Configure GPIO to be Accessed by DSP GPIO_DSP_EN register is used to put the GPIO to be controlled by DSP. The following code set GPIO0 to be controlled by DSP. After this register is set, RISC cannot control all other registers of GPIO except for this one. RISC needs to clear this register before it needs to access the corresponding GPIO.

GPIO_DSP_EN |= 0x01; // set GPIO0 to be controlled by DSP



8 Resource Sharing Controller

8.1 Operation Overview The Resource Sharing Controller (RSC) manages the two major resources of Atlas™: one is the peripheral pin; the other is the DMA channel.



8.2 DMA Channel Sharing The DMA channel 6, 7 & 9, 10 are shared between the four Universal Serial Ports and the Audio CODEC. The following table shows the DMA channel multiplex managed by RSC: Table 8. Atlas™ DMA Channel Multiplex

USP0 USP1 USP2 USP3 CODEC DMA Ch6 - - - Yes Yes DMA Ch7 - - - Yes Yes DMA Ch9 Yes Yes Yes Yes - DMA Ch10 Yes Yes Yes Yes -

By default DMA Channel 6&7 are occupied by CODEC, and Channel 9&10 are occupied by USP0. When other USP needs to use DMA, it needs to change the RSC_DMA_MUX register as following:

RSC_DMA_MUX = 0x3C // USP3 occupy DMA channel 6&7 The reason why USP3 may needs at most 4 DMA channels is: the USP3 has a special SIB bus mode, which the other USP’s do not have. In this mode, there are both Audio data and Telecommunication data need to be transferred in the same frame. And both data transfers are bi-directional. NOTE: Please make sure the related DMA channels are in idle state when programming this register.



8.3 External Pin Multiplex After power-on reset of boot-up, the Resource Sharing Controller controls all the peripheral pins. In this mode, the input/output or pull-up/down status of each pin is fully programmable. Only after the PWR_PIN_RELEASE register in the Power Manager was set, those pins can released to each peripherals. If the pin is multiplexed between more than two functions, by default the pins are released to the first function peripheral. User can switch the pins to the second (or third) function by configuring the RSC register RSC_PIN_MUX. The Atlas™ multiplexed pins managed by the RSC are shown in the next table (the memory interface pin multiplex is not managed by RSC): Table 9. Atlas™ Pin Multiplex

Pads First Function Second Function A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C2, C3, C4

SmartMedia®/NAND Flash interface CMOS/CCD Sensor

H1, H2, H5, J1, J2, J3, J5, K3 GPIO<15:8> LCD controller Serial Port 0 N3, N5, P5 GPIO<23:21> TIC

P1, P2, P3, R3 Serial Port 1 Audio CODEC R1, T1, T3, U1 Serial Port 2 Bluetooth SPI U5, U6, V5, W4, W5 GPIO<20:16> JTAG

Host port K18, K19, L15, L17, L18, M18, M19, P10, P11, P12, P13, P14, R17, R18, T17, T18, T19, U10, U11, U12, U13, U14, U15, U16, U17, U18, U19, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, W10, W11, W12, W13, W14, W15, W16, W17, W18, W19

PCMCIA interface

Extension port

M17, N15, N17, N18, N19, P15 PCMCIA interface SD interface

A6, B6, C51, C6 NOR Flash/ROM interface SmartMedia®/NAND Flash interface

The following figure shows how the Atlas™ pins are multpiexed:

Figure 8. Atlas™ Pin Multiplex Diagram 1 If NAND_BOOT=1, then the C5 will be used by SmartMedia®/NAND Flash interface first.

1st Function

2nd Function

RSC

PAD



Basically each bit in RSC_PIN_MUX register controls the multiplex of two groups of pins. But there are some special cases:

1. Some pins are used for TIC/BIST1, JTAG, or Scan chain test besides of the functions listed above. Among those functions, the TIC/BIST, JTAG, or Scan chain has the highest priority. When Atlas™ is configured to those special test modes, those pins cannot be used by the normal functions any more.

2. Host Port and Extension port are all shared pin with PCMCIA interface. So bit<3> and <4> should be set to 1’b1 at the same time. But if user writes 1’b1 to both two bits, the bit<4> (HOST_EN) has higher priority than bit<3> (EXT_EN). In another words, if bit<4> is set to 1’b1, then Host Port will occupy those pins no matter bit<3> is 1’b1 or 1’b0.

Besides, the RSC_PIN_MUX and PWR_PIN_RELEASE register have to work together with the PWR_CLK_EN register to decide the pin multiplex. If user wants the pins to be enabled for a dedicated block, then he needs to enable the clock of that block too. Otherwise, the pins are still controlled by Resource Sharing Controller. For example, to enable the pins for Camera port: // set PIN_RELEASE PWR_PIN_RELEASE = 1; // enable Camera clock PWR_CLK_EN |= 0x80; // enable Camera port RSC_PIN_MUX |= 0x400; NOTE: On the other side, if the block is not using pins, then please turn off its clock. Otherwise, it will still consuming power and unkown result may occur.

1 TIC is the abbreviation of Test Interface Controller, which is for testing ARM922T.



9 DMA Controller

9.1 Operation Overview The DMA controller consists of 12 independent DMA channels. Each channel can be programmed to execute certain DMA operations independently. The DMA transfer can be in single mode or burst mode. In single mode, each data transfer is only 1-DWORD. But in burst mode, each data transfer will be 4-DWORD long. According to the DMA addressing modes, the DMA operations can be divided into 1-D and 2-D operations. The 2-D operation mode is more suitable for image processing (like Camera) applications. Normally DMA has a start address and length. When the specified number of data is transferred, the DMA will stop. But there are some applications need to transfer data to a specified memory area repeatedly without stop (like Audio). So Atlas™ DMA Controller has a special loop mode for this type of applications.



9.2 Initialization In order to setup a DMA, the programmer needs to know a few things: 1) Is this a read from memory or write to memory? 2) Where to get the data? 3) Where to put the data? 4) How to get the data (i.e. consecutively, or with jumps in between)? 5) What is the priority of this transfer? These parameters are defined by a series of registers that the programmer must set in order to setup a DMA properly. Each of the channels listed above has its own registers, which means that DMA’s for different channels can co-exist at the same time. Each set of the registers defines the following values (Note: registers for DMA channel 0 is used as an example here. All the channels have the same register definitions): • Starting Address – This is a 25-bit address that defines the starting address of the DMA transfer in

System Memory (i.e. either SDRAM or SRAM). If SRAM is used, then the top bits are ignored. The starting address is defined in register: DMA_CH0_ADDR (Note: DMA_CH0_ADDR1 will trigger the start of a DMA and must be set AFTER all the other registers). The Starting Address is a DWORD address.

• X value – This is a 16-bit value which defines how many consecutive DWORDs to access per line of DMA. This value is in the register DMA_CH0_XLEN.

• Y value – This a 16-bit value which defines how many lines of DMA to perform. The actual line number of DMA is Y+1. For example, to DMA one line, Y = 0; to DMA 10 lines, Y = 9. This value is in register DMA_CH0_YLEN.

• DMA width – This is a 10-bit value which specifies the spacing between two lines (in DWORD). For example, if the width = 100, X = 10, and Y = 5, then each time when the DMA gets 10th DWORD, it will jump 90 DWORDs to reach the start of the next line. Since width registers are often fixed for a particular application, the Palm-2 provides a set of 4 width values (DMA_WIDTH0, DMA_WIDTH1, etc.) that can be pre-initialized. A particular DMA only needs to specify which of the 4 registers to use in the DMA_CH0_CTRL register.

Both RISC and DSP can start the DMA. Before user starts the DMA, it needs to configure the DMA_CH_DSP_CTRL register to determine either RISC or DSP will have the control of each DMA channel. Some most commonly used parameters must be set up in the initialization routine1. The common parameters include:

• Width registers (DMA_WIDTH0, DMA_WIDTH1, etc) • Interrupt enable register (DMA_INT_EN) • Direction, mode, width selection, etc. (DMA_CHx_CTRL) • Loop enable if needed (DMA_CH_LOOP_CTRL) • Horizontal length (DMA_CHx_XLEN)

The Vertical length (DMA_CHx_YLEN) needs to be set up every time user wants to start a new DMA. If user wants to start a 1-D DMA, then this register does not need to be set up. Besides of the above register set up, user also needs to set up some peripheral FIFO parameters such as:

1 Some of these registers have defaults values that can already be used.



• DMA or I/O mode selection • Bit width selection (byte/word/dword) • FIFO request level • FIFO interrupt threshold

As for the detail about the FIFO initialization, please refer to the section describes peripheral FIFO. To start the DMA, user just needs to write to the DMA_CHx_ADDR register1. Here is a simple example for 1-D DMA from SDRAM to Flash Memory (DMA channel 4) initialization: #define BURST 1 #define DIR 1 #define WIDTH 0 #define XLEN 0x10 #define YLEN 0 #define SDRAM_ADDR 0x100000 // set dma width registers DMA_WIDTH0 = 0x1; DMA_WIDTH1 = 0x4; DMA_WIDTH2 = 0x8; DMA_WIDTH3 = 0xc; //set dma int enable DMA_INT_EN = DMA_CH4_INT; //clear all dma interrupts DMA_CH_INT = 0xffff; //configure and start dma DMA_CH4_CTRL = ((BURST<<3) | (DIR<<2) | WIDTH); DMA_CH4_XLEN = XLEN; DMA_CH4_YLEN = YLEN; DMA_CH4_ADDR = SDRAM_ADDR;

1 Except for the loop mode (please refer to section 9.6)



9.3 DMA Interrupt Handling When the DMA finishes, it will generate an interrupt in the DMA_CH_INT register. So RISC or DSP can know that this DMA is finished. Following is a simple example shows the DMA interrupt handling: #define DMA_CH4_INT 0x10 #define DMA_MASK_TO_SDRAM 0x00 #define DMA_MASK_FROM_SDRAM 0x04 volatile int bDMAReadDone; volatile int bDMAWriteDone; void __irq Irq_Handler() { int iStatus; iStatus = INT_PENDING; if(iStatus & INT_MASK_DMA_CTRL) { if(DMA_CH_INT & DMA_CH4_INT) { DMA_CH_INT = DMA_CH4_INT; // clear the DMA interrupt if((DMA_CH4_CTRL & 0x04) == DMA_MASK_TO_SDRAM) { bDMAWriteDone = 1; } if((DMA_CH4_CTRL & 0x04) == DMA_MASK_FROM_SDRAM) { bDMAReadDone = 1; } } } } The interrupt handling for loop mode DMA is a little bit different. Please refer to section 9.6 for the details.



9.4 Single and Burst DMA As we specified before, the DMA has two data transfer modes: single and burst mode. In single transfer mode, the DMA controller executes one 32-bit word read/write at a time; while in burst mode, 4 32-bit words a time. The user can select the transfer mode by programming one of the register bit in DMA_CHx_CTRL. In burst mode, X-length should be in 16-byte boundary normally; but it’s allowed to be set to any value. For example, if X-length = 5, then the DMA controller is actually doing 2 bursts. But in the last burst, the DMA controller will only do one D-word data transfer to/from the peripheral. For 1-D DMA, it is not so important because the last data transfer in the whole DMA will not affect the peripheral FIFO anyway. But in 2-D DMA, and if X-length is not in 16-byte boundary, then the last burst of every line will only do 1 D-word data transfer. So the DMA controller will not do extra data transfer and will not affect the data sequence in the peripheral FIFO. Please note that from the system memory’s point of view, it will still see 2 bursts on each line, i.e., the 5 D-word data transfer of each line will take 8-Dword’s memory space. It is suggested to use burst mode DMA whenver it is possible. It can make the data transfer more effiecient and faster. NOTE: In burst mode, the DMA address is better to be in 16-DWORD boundary. Otherwise, the transfer will be split into multiple single-word transfers in the system bus (Because the system bus does not allow the non-aligned burst transfer) and the bus efficiency will be desperately low.



9.5 1-D and 2-D DMA The Atlas™ DMA controller supports both 1-D and 2-D DMA. In 2-D DMA, the system memory space is considered as a 2-D layout instead of linear layout. In another word, the system memory is considered as many data lines. The length of the data line is determined in the user-selected DMA_WIDTH register. Then user can specify a data window that user wants to read/write by three parameters:

• Start address • X length • Y length

The idea of 2-D DMA is shown in the following diagram.

Figure 9. 2-D DMA

If the user specifies the Y length as 0 or X length equals to the DMA Width, then this 2-D DMA will actually has the same effect as 1-D DMA. If user set up the X length greater than DMA Width, then the extra data will be wrapped around to the next data line. It will corrupt the DMA transfer for multiple-line 2-D DMA. But if it’s 1-D DMA, then there is no problem. The following diagram shows the wrap around of the extra data in case of X length greater than DMA Width.

X length

DMA Width

Y length

Start Address



Figure 10. 2-D DMA Wrap Around (X-Length > Width)

DMA Width

DMA X-Length

Extra data

Extra data



9.6 Loop DMA If X-length is set to 0, it is a special mode of the DMA: loop mode. In loop mode, the start and stop conditions are all different. For loop-mode DMA, set the start address will not start the DMA at once. User needs to set the DMA_CH_LOOP_CTRL to start the DMA. But before start a new DMA, user still needs to configure this start address register to clear the internal status of last DMA. The loop-mode DMA will never finish until user force to stop it (by writing a 1’b0 to the DMA_CH_VALID register). The DMA will keep looping as described in the following figure:

Figure 11. Loop-mode DMA

As shown in the above figure, the DMA address will keep increasing, until reaching the end of a loop area whose size is defined by (DMA_WIDTH * Y_LENGTH). Then the DMA address will go back to the beginning of this area. If Y_LENGTH or DMA_WIDTH is equal to 0, then the DMA address will not change at all. And the DMA will keep transferring the data to the same DMA address until user force to stop it. In loop mode, the DMA data region is always divided into two halves: BUFA and BUFB. The DMA controller will generate interrupt twice during each loop: one time is when the DMA address reaches the end of BUFA; the other time is when the DMA address reaches the end of the BUFB. And of course the interrupt can only be generated when the corresponding interrupt enable (DMA_INT_ENABLE) bit is set. Each half (BUFA & BUFB) has its own buffer valid register bit, which can be programmed by user. The loop DMA will not be really started until the current buffer valid register bit is asserted. For example, if when the DMA goes to the end of BUFA and the valid bit of BUFB is not set, then the DMA will stop at the end of BUFA until the valid bit of BUFB is set. Here is a simple example showing the loop DMA from SDRAM to Flash Memory: //configure and start dma

DMA_WIDTH

Y-LENGTH

BUFA

BUFB



DMA_CH4_CTRL = ((BURST<<3) | (DIR<<2) | WIDTH); DMA_CH4_XLEN = 0; DMA_CH4_YLEN = 0; DMA_CH4_ADDR = SDRAM_ADDR; DMA_CH_LOOP_CTRL = 0x100010; And the interrupt handling of the loop mode DMA is a little different with normal DMA. The following example shows how to handle the loop mode DMA interrupt: #define DMA_CH4_INT 0x10 #define DMA_MASK_TO_SDRAM 0x00 #define DMA_MASK_FROM_SDRAM 0x04 volatile int bDMAReadDone; volatile int bDMAWriteDone; void __irq Irq_Handler() { int iStatus; iStatus = INT_PENDING; if(iStatus & INT_MASK_DMA_CTRL) { if(DMA_CH_INT & DMA_CH4_INT) { DMA_CH_INT = DMA_CH4_INT ; // clear the DMA interrupt if((DMA_CH4_CTRL & 0x04) == DMA_MASK_TO_SDRAM) { bDMAWriteDone = 1; if (DMA_CH_LOOP_CTRL & 0x10) { // if in loop mode, swap the buffer valid DMA_CH_LOOP_CTRL &= 0xfff0eff; DMA_CH_LOOP_CTRL |= 0x100000; } else if (DMA_CH_LOOP_CTRL & 0x100000) { DMA_CH_LOOP_CTRL &= 0xfef0fff; DMA_CH_LOOP_CTRL |= 0x10; } } if((DMA_CH4_CTRL & 0x04) == DMA_MASK_FROM_SDRAM) { sim_step(19); bDMAReadDone = 1; if (DMA_CH_LOOP_CTRL & 0x10) { // if in loop mode, swap the buffer valid DMA_CH_LOOP_CTRL &= 0xfff0fef; DMA_CH_LOOP_CTRL |= 0x100000; } else if (DMA_CH_LOOP_CTRL & 0x100000) { DMA_CH_LOOP_CTRL &= 0xfef0fff; DMA_CH_LOOP_CTRL |= 0x10; } } }



} } To finish a loop DMA, user needs to write the DMA_CH_VALID register. For example, if user wants to stop the DMA channel 4 which is a loop-mode DMA:

// stop loop mode DMA DMA_CH_VALID = 0x10;



9.7 DSP Control of DMA By default all the DMA channels are controlled by RISC. But the RISC can set DMA_CH_DSP_CTRL register to give some control of the DMA controller to DSP. Each DMA channel can be switch to be controlled by RISC or DSP separately. And the switch can only be done by RISC, not DSP (i.e. DMA_CH_DSP_CTRL is only accessible to RISC). For example, if user wants to use DSP to control DMA channel 4: DMA_CH_DSP_CTRL |= 0x10; Because there might be some channels controlled by RISC and some others by DSP at the same time, some DMA control registers need to be separated for RISC and DSP. Those registers include:

• DMA Width Registers (DMA_WIDTH0, 1, 2, 3) • DMA Interrupt Enable Register (DMA_INT_EN) • DMA Loop Control Register (DMA_CH_LOOP_CTRL)



10 PCMCIA Interface

10.1 Operation Overview AtlasTM PCMCIA interface is compliant with PC Card Standard 2.1, PCMCIA 2.1 and JEIDA 4.1. The application typically access PC card through the socket/card services software interface. The PCMCIA interface operates in 32-bit mode, even when supporting 8-bit or 16-bit PC card, PCMCIA has the logic to route 32-bit operation to narrow bus operation. On PC card side, PCMCIA interface support Socket or Card interrupt (activated by PC card) and Management interrupt ( invoked by PC card status change). PCMCIA I/F also provide timing control register to accormodate interface to slower PC card or other I/O interface. The PCMCIA interface operation includes:

Pin_mux programming M6730 Register programming Power logic register programming Memory window configuration I/O window configuration Timing control Management interrupt operation Card interrupt operation Card initialization sequence



10.2 Pin-mux Programming In AtlasTM there is different clock source for each peripheral for better power control, before PCMCIA interface configuration, user needs to program the power management register to provide clock to Atlastm PCMCIA interface first; And the pin of PCMCAI interface is muxed with extension port, SD interface and host port, by default the pin is defined for PCMCIA interface. The pin_mux programming can access the following registers: 1. PWR_CLK_EN, see AtlasTM developer’s manual section 5.6.3 for details register description. Set bit

14 of PWR_CLK_EN to be 1’b1. #define PCMCIA_CLK_EN 0x4000; PWR_CLK_EN |= PCMCIA_CLK_EN;

2. RSC_PIN_MUX, see AtlasTM developer’s manual section 5.8.2 for details register description. To

make sure that bit 3 and bit 4 of register RSC_PIN_MUX is 1’b0. Since the pin of SD I/F only muxes with PCMCIA I/F highest 6-bit address lines, when PCMCIA interface only use the lower address bus, the SD interface pin can also be enabled.



10.3 M6730 Register Programming PCMCIA interface intergrates an IP core named M6730, which implements the conversion from PCI bus to PCMCIA interface. The M6730's internal device control, window mapping, extension and timing registers are accessed through a pair of operation registers - an index register and a data register. Before reading/writing M6730 register, user needs to program the index register first, The index register is used to specify which of the internal registers the CPU will access next. The data register is used by the CPU to read and write into the internal register specified by the Index register.The M6730 also has Extension registers. Within this Extension registers is an Extended Index register and Extended Data register that provides access to more registers. The registers accessed through extended index and data registers are thus double indexed. For M6730 its base address in AtlasTM is fixed to be 0x2000_0000, the address for index register in AtlasTM is 0x2000_0000, for data register it’s 0x2000_0001. The order of M6730 register operation is as follows: 1. For register write operation, write index and data to base address 0x2000_0000 in word mode with

low byte is index value and high byte is data value.

#define PCMCIA_IO_PHYSICAL_BASE 0x20000000

value_short = register_index | (((unsigned short)register_data)<<8); *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned

short)value_short; 2. For register read operation,

a) write index to base address 0x2000_0000 in byte mode first; b) Read base address 0x2000_0000 in word mode; c) Extract the high byte of read data.

*((volatile unsigned char *) PCMCIA_IO_PHYSICAL_BASE ) = (unsigned

char)register_index; value_short = *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE); register_data = (value_short & 0xFF00) >>8;

3. For extended register write operation a) Write extended index to extended index register (0x2E) b) Write register value to extended data register (0x2F) value_short = 0x2E | (((unsigned short)extended_index)<<8); *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned

short)value_short;

value_short = 0x2F | (((unsigned short)extended_data)<<8); *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned

short)value_short; 4. For extended register read operation

a) Write extended index to extended index register (0x2E) b) Read extended data register(0x2F).

value_short = 0x2E | (((unsigned short)extended_index)<<8);



*((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE) = (unsigned short)value_short;

*((volatile unsigned char *) PCMCIA_IO_PHYSICAL_BASE ) = (unsigned char) 0x2F;

value_short = *((volatile unsigned short *) PCMCIA_IO_PHYSICAL_BASE); register_data = (value_short & 0xFF00) >>8;



10.4 Power Logic Register Programming AtlasTM realizes PCMCIA power management in a different way from M6730. User needs to program AtlasTM GPIO or extended GPIO to control the power supply logic and switch the power on /off. After PCMCIA I/F detects the PC Card insertion, the power logic must be initialized before the other logic Since the auto power scheme in M6730 doesn’t work in AtlasTM PCMCIA interface, the power logic register programming should follow the steps below: 1.1 After the PCMCIA card insertion is detected, CPU reads External Data Register (extended index

0x0A) bit[1:0] to decide the VCC operating voltage supplied to PC card. The power supply selection logic depends on hardware board design.

1.2 Set POWER_CONTROL (index 0x2) bit 4 to indicate the Vcc power is applied to the card. 1.3 Set POWER_CONTROL (index 0x2) bit 8 to indicate the card is enabled. 1.4 Set EXTENSION CONTROL 1 (extended index 0x03) bit 1 to disable auto power clear bit.



10.5 Memory Window Configuration There are five programmable memory windows in AltasTM PCMCIA I/F. Those memory windows can be configured to be attribute memory window or common memory window independently. And also the window bus size and timing control may also be different, depending on window configuration. When RISC accesses memory PC card, the AtlasTM address [31:24] is compared with Memory Upper Address register, the address [23:12] is compared with Start Address Register and End Address Register, if the access address is within the range of programmed memory window, M6730 will respond to the RISC access. Also M6730 will convert the AtlasTM address into physical PC card address. The AtlasTM address [23:12] will be added with the Offset Address Register [25:12] to get PC card address [25:12]. The lower 12 bits just pass through of RISC address [11:0]. For example, we want a memory window located at AtlasTM 0x24008000 with length 8K, the corresponding physical PC card address is 0x000000, we will program:

• Memory Upper Address Register to 0x24 • Memory Start Address High Register to 0x0 • Memory Start Address Low Register to 0x08 • Memory End Address High Register to 0x0 • Memory Start Address High Register to 0x0f • Memory offset Address High Register to 0x3f • Memory offset Address High Register to 0xf8

Besides the window space setting, the memory window configuration includes: - Bus size

The bus size of Memory Window is configured by setting the bit <7> of Start Address High Register. If bit 7 is set to ‘1’, the memory window is 16-bit to PC card, if ‘0’ 8-bit size.

- Memory attribute If bit 6 of Offset Address High Register is ‘0’, the memory window is for common memory. If bit 6 of Offset Address High Register is ‘1’, the memory window is for attribute memory. When attribute memory is selected, the signal “pcm_reg_b” is asserted to be LOW when the address located between the memory window is accessed.

- Timer Select The bit [7:6] of End Address High Register is used to select the timer set. When 2’b00, the timer set0 is selected, otherwise the timer set1 is selected.

The memory window programming can be in the following steps: 1. Program the memory window Start Address Register, End Address Register, Upper Address

Register and Offset Address Register to decide the range of memory window. 2. Select the memory window bus size; 3. Set the memory window attribute; 4. Select the timing control register; 5. Configure the Mapping Enable Register (index 0x06) to enable the corresponding memory window.



10.6 I/O Window Configuration There are two I/O windows in PCMCIA interface. The PCMCIA I/O space in AtlasTM is 64K and ranges from 0x2000_0000 to 0x2400_0000. Before the AtlasTM PCMCIA I/O address reaches to M6730 megacell, the AtlasTM address 0x2xxx_xxxx is converted to M6730 I/O addresss 0x0xxx_xxxx. For M6730 megacell, the I/O address is from 0x0 to 0x400_0000. The I/O window space should be within that space. There is no Upper Address register for I/O window. The physical address to PC card is generated by adding M6730 I/O address with I/O Offset Address Register. For I/O window, the configuration includes: - I/O map address register

Include: I/O Start Address, I/O End Address, I/O Offset Address.

- Auto size Bit 5 and Bit-1 of I/O window control register are used to set the auto size of I/O windows. Under Auto size mode, the data size of I/O access will be decided by IOIS16_b input from PC card. When IOIS16_b is asserted to be LOW, the data bus is 16-bit in width, if IOIS16_b is 1’b1 the data bus is 8-bit in width.

- Data Size Bit 4 and bit 0 of I/O window control register are used to configure the data size of I/O window. When ‘1’, the data size is 16-bit, when ‘0’ the data size is 8-bit.

- Timer select Bit 7 and bit 3 are used to select the timer register for I/O windows. When ‘1’, Timer 1 is selected, ‘0’

Timer 0 is selected. The I/O window configuration is in the same step as memory window.



10.7 Timing Control The timing of PCMCIA interface is programmable; there are two sets of timing registers. The selection of timer is controlled by I/O window and Memory window timer control register bits. For different windows, there is different PCMCIA interface timing. For PC card, the timing of attribute memory is fixed as PCMCIA standard has specified. The timing of common memory and I/O interface is decided by PCMCIA CIS information. Because the timing of PCMCIA I/ F is programmable, besides PC card PCMCIA I/F may also be used to connect some SRAM-like variable latency I/O interface. When AtlasTM accesses such interface through PCMCIA I/F, the timer register configuration and timer selection are decided by AC specification of the external device. The timer registers include: setup timing, recovery timing and command timing. The setup timing register controls the setup time before PC card control signals (that’s pcm_oe_b, pcm_we_b, pcm_iord_b, pcm_iowe_b) become active. It defines the time from the assertion of pcm_ce1_b (pcm_ce2_b or pcm_reg_b) to assertion of those control signals mentioned above. If Nsetup is the programmed value in setup timer register, TPCMCIA is PCMCIA I/F internal clock period (PCMCIA I/F internal clock is always equal to AtlasTM I/O clock), the setup time is: Tsetup = 2* (Nsetup+1) * TPCMCIA The command timing registser controls how long the PC card active control signals will be. The data in the command timing register represents the number of clock cycles for the active command. For timer 0 and timer 1, the default value of command timing register is 0x3 and 0x9 respectively. If Ncommand is the programmed value in command timer register, TPCMCIA is PCMCIA I/F internal clock period (PCMCIA I/F internal clock is always equal to AtlasTM I/O clock), the command time is:

Tcommand = 2* (Ncommand+1) * TPCMCIA

The recovery timing registers for each timer set controls how long a PC card cycle's recovery (that’s pcm_oe_b, pcm_we_b, pcm_iord_b, pcm_iowe_b) time will be, in terms of the internal clock cycles. It defines the time from the de-assertion of control signal to de-assertion of pcm_ce1_b (pcm_ce2_b or pcm_reg_b). If Nrecovery is the programmed value in recovery timer register, TPCMCIA is PCMCIA I/F internal clock period (PCMCIA I/F internal clock is always equal to AtlasTM I/O clock), the recovery time is:

Trecovery = 2* (Nrecovery+1) * TPCMCIA The timing control register operation steps are: 1. Decide the clock cycles for setup, command and recovery timer according to AC specification of PC

card or external I/O device. 2. Select the right timer register set for corresponding window.

10.8 Management Interrupt Operation There are four changes in the PC card status that can be programmed to cause management interrupt. 1. Card detection interrupt when card is inserted or removed; 2. Battery dead or I/O type card status change; 3. Battery warning change on the memory PC card; 4. Ready status change on the memory PC card;



There are two interrupt modes in M6730: PCI interrupt signaling and External interrupt signaling mode. But AtlasTM only supports external interrupt signaling mode, and the irq10 is assigned to M6730 management interrupt. During initializing PCMCIA I/F, the card detect interrupt needs to be initialized. The initialization sequence is: 1. Set bit 6 of MISC CONTRL 2 register (index is 0x1E) to enable debounce for card detect. 2. Set external interrupt mode in MISC CONTROL3 (extended register, extended index is 0x25); 3. Set bit 3 of Management Interrupt Configuration register (index 0x05) to enable card detect

interrupt. 4. Program management IRQ in Management Interrupt Configuration register, by default

management IRQ is set to be “4’hA”. 5. Clear bit4 of Interrupt And General Control Register (index 0x03) to enable M6730 mamgement

interrupt. 6. Set bit 6 of PCMCIA Interrupt Mask Register (PCMCIA I/F register, 0x0018) to enable PCMCIA

Management interrupt 7. Set bit11 of INTR_RISC_MASK register (See “Interrupt Controller” section for details) to enable

PCMCIA interrupt. For memory type PCMCIA card, management interrupts include card detect interrupt, battery warning interrupt, battery dead interrupt and ready status change interrupt. For I/O type PCMCIA card, management interrupts includes card detect interrupt and card status change interrupt. For each management interrupt, there is corresponding interrupt enable bit in Management Interrupt Configuration, the step 3 is different for different management interrupt, all the other steps should be same. After the PCMCIA interrupt is triggered, the handling of management interrupt must be the following steps: 1. Disable PCMCIA interrupt in INTR_RISC_MASK register; 2. Check Bit 7 of PCMCIA_STATUS register to see whether it’s M6730 management interrupt who

triggers the PCMCIA interrupt; 3. If Bit 7 is 1’b1, there is pending M6730 management interrupt; write 1’b1 to Bit 7 of

PCMCIA_STATUS to clear PCMCIA interrupt, then go to step 4. If Bit 7 is 1’b0, there is other pending interrupt.

4. Read M6730 Card Status Change register (index 0x04) to judge the source of management interrupt. The register is cleared to be 0x0 after reading.

5. If bit 3 of Card Status Change register is 1’b1, it indicates that card status changes. The Card Status Change register indicates the source of a management interrupt generated by the M6730. For the management interrupts to be generated, the corresponding enables should be set in the Management Interrupt Configuration register. So is the other management interrupt.



10.9 Card Interrupt Operation The Socket or Card interrupt is initiated by the I/O type PC card activating the rdy/nireq signal. In AtlasTM we assign IRQ9 for M6730 Card interrupt and only the external signaling mode is supported.The card interrupt is only valid for I/O type PC card. For memory type PC card, no card interrupt is generated. The initialization of card interrupt is: 1. Set external interrupt mode in MISC CONTROL3 (extended register, extended index is 0x25); 2. Program Interrupt and General Control register (index 0x03) to set card interrupt IRQ to be 0x09; 3. Check bit5 of Interrupt and General Control register (index 0x03) to make sure that “Card is I/O” is

set. 4. Set bit 8 of PCMCIA_INTR_MASK register (PCMCIA I/F register) to enable PCMCIA card interrupt. 5. Set bit 11 of INTR_RISC_MASK register (See “Interrupt Controller” section for details) to enable

PCMCIA interrupt. By programming Interrupt and General Control register (index 0x03) to set card interrupt IRQ to be 0x00 can clear card interrupt. The card interrupt detect is simpler than management interrupt: 1. Disable PCMCIA interrupt in INTR_RISC_MASK register; 2. Check Bit 8 of PCMCIA_STATUS register to see whether it’s M6730 card interrupt who triggers the

PCMCIA interrupt; 3. Clear interrupt generated by PC card by accessing the PC card. 4. If Bit 8 is 1’b1, there is pending M6730 card interrupt; write 1’b1 to Bit 8 of PCMCIA_STATUS to

clear PCMCIA interrupt, then go to step 4. If Bit 8 is 1’b0, there is other pending interrupt.



10.10 Socket Initialization Sequence For PCMCIA interface, the socket initialization sequence is: 1. Provide clock to PCMCIA interface and enable PCMCIA pin 2. Enable card detect interrupt 3. Configure one memory window to be attribute memory windows. 4. After the card insertion is detected, program the power logic registers and provide power to PC card

(Section 10.4) 5. Read PC card CIS information to decide the card type, if I/O type PC card is detected, set

Card_is_IO is Interrupt and General Control register. 6. Allocate resource to PC card according to CIS information; configure the I/O windows or memory

windows. 7. Configre the timing registers and select the right timer for windows. 8. If I/O card is detected, enable card interrupt; if memory card is detected, enable battery warning and

other management interrupt. PCMCIA can also connect to variable latency I/O device, when PCMCIA is used to access those device, they are generally accessed through PCMCIA attribute memory, the steps are: 1. Provide clock to PCMCIA interface and enable PCMCIA pin 2. Program the power logic register (according to the step in section 10.4) to active the M6730

hardware logic. 3. Program the timing register according to external I/O device timing requirement. 4. Configure one memory window to be attribute memory window, the memory space is for external I/O

device. 5. Select the timer for attribute memory window.



11 Extension port

11.1 Operation Overview AtlasTM extension port supports both I/O mode and DMA mode. Extension port I/O mode is used by AtlasTM to access the external I/Odevice in fixed-latency or variable latency mode. But the DMA mode is realizeded through Atlas internal bus protocol, external glue logic is needed to implement the DMA data transfer. Here only the I/O mode operation is described. The pin of extension port is muxed with PCMCIA and host port. The extension port programming includes: 1. Pin_mux programming 2. Timing register programming 3. Fixed latency access 4. Variable latency access 5. DSP access



11.2 Pin-mux Programming Before configure extension port, user needs to program the power management register to provide clock to AtlasTM extension port interface first; and the pin of extension port interface is muxed with PCMCIA I/F and host port, use needs to program the resource sharing register to enable the pin of extension port. The pin_mux programming can access the following registers: 1. PWR_CLK_EN, see AtlasTM developer’s manual section 5.6.3 for details register description. Set bit

14 of PWR_CLK_EN to be 1’b1. 2. RSC_PIN_MUX, see AtlasTM developer’s manual section 5.8.2 for details register description. To

set bit 3 of register RSC_PIN_MUX. 3. INT_RISC_MASK, see AtlasTM developer’s manual section 2.2 for details register description. To

set bit 13 to enable extension port interrupt.



11.3 Timing Register Programming There are two timer registers to control the timing of extension port. The read and write operations have two separate timer sets. EXT_TIMER2 controls the setup and recovery time and EXT_TIMER1 controls the wait status of extension port. The setup register controls how many cycles there are from ext_sel_b assertion to control signals (ext_rd_b or ext_wt_b) assertion in terms of AtlasTM I/O clock. The recovery timers controls the clock cycles from control signal de-assertion to ext_sel_b (and address) de-assertion. The setup and recovery timer registers are valid for both fixed-latency and variable latency mode. The EXT_TIMER1 controls how many wait state cycles there are to be inserted during accessing external I/O device. The wait state control register is only valid when extension port is configures as internal wait state mode; in this mode, extension port can visit the fixed-latency I/O device. When extension port works under external wait state mode, the data transfer is controlled by signal “ext_rdy_b” asserted by external device. If Nvalue is the timer register value, Tioclock is the period of AtlasTM I/O clock, the time controlled by extension port register is: T = Nvalue * Tioclock. Note: The extension port timer register is onlu valid for RISC access, having no effect on DSP access.



11.4 Fixed Latency Access When extension port accesses the fixed latency I/O device, the configuration steps must follow: 1. Pin_mux programming according to 11.3 section. 2. Configure EXT_RISC_CTRL register to enable EXT_EN, RISC_EN, set WAIT_MODE to be internal

wait mode. EXT_RISC_CTRL = 0x3;

3. Programe EXT_TIMER1 and EXT_TIMER2 register according to external device AC specification.



11.5 Variable Latency Access When extension port accesses the fixed latency I/O device, the configuration steps must follow: 1. Pin_mux programming according to 11.3 section. 2. Configure EXT_RISC_CTRL register to enable EXT_EN, RISC_EN, set WAIT_MODE to be internal

wait mode. EXT_RISC_CTRL = 0x13;

3. Programe EXT_TIMER2 register to set setup and recovery time according to external device AC specification.



11.6 DSP Access AtlasTM DSP can also visit external device through extension port. The timing of DSP access is controlled by DSP interface. DSP can only access the fixed latency I/O device directly. Before DSP can access the external device, RISC needs to initialize the extension port first: 1. Pin_mux programming to enable extension port 2. Clear bit 0 of EXT_MODE register to switch the control of extension port from RISC to DSP, allowing

DSP to access extension port. After DSP is enabled to access extension port, RISC can’t access the other extension port register any more. RISC needs to set EXT_REG_MODE again for RISC access of extension port registers.

Before DSP access the external device, DSP needs to initialize extension port: 1. Set DSP wait state; 2. Configure EXT_DSP_CTRL register to enable EXT_EN, DSP_EN, set WAIT_MODE to be internal

wait state. 3. If necessary, configure EXT_DSP_HI_ADDR to extend the high 8-bit address.



12 Universal Serial Port

12.1 Operation Overview USP is the multi-function serial interface to communicate with many common serial ports, so before using the USP, user should make acertain that the serial interface to be connected is supported by the USP. Please refer the developer’s manual for the detail information. USP supports the following four kinds of serial bus,

• ASYNC serial bus (UART or IrDA) • TFS as the the chip select or enable signal (SPI) • TFS/RFS as the Frame synchronous signal (PCM etc) • TFS as state machine transfer control signal of the external device (SFS of PBA313)

The different bus has the different operation steps, but the basic operation steps of the USP is the same as following:

• Reset then power up the USP • USP work mode1 initialization • TX FIFO/RX FIFO configuration and initializaion • Transmit/Receive • … • USP work mode2 reinitialization(if need) • Reconfiguration (if need) • Transmit/Receive (if need) • …

In some application, USP must be configure to several kind of serial bus, so before the USP is used, it need to be reconfigured to the corresponding mode.



12.2 USP Reset and Power up Before initializing the USP, software must first reset the USP one time, and then release the reset, and then power up the the USP, and release the pins of USP at last. All the following sample code is for USP0. It’s the same operation for another three USP’s. All the register bits and register name (it indicates its I/O address) below can be refered to the Developers Manual.

PWR_CLK_EN | = SP0_EN; RESET_SR | = SP0_RST; RESET_SR &= SP0_RST; PWR_PIN_RELEASE=1;

Because some pins of USP0 mux the pin with GPIO, if they are used, one more register should be set,

RSC_PIN_MUX= SP0_EN; If USP is controlled by the DSP, RISC must first write 1 to the RISC_DSP_SEL bit of RISC/DSP Mode Register, and then DSP can access the USP.

USP_RISC_DSP_MODE = 0x1;

Before USP0 work, clear all pending interrupts USP0_INT_STATUS = USP_INT_MASK_ALL; If the DMA is used for data transferring, software must enable the DMA controller

PWR_CLK_EN | = DMA_EN;



12.3 USP Initialization 12.3.1 USP Work Mode Initialization The USP initialization has something to do with the work mode of it. Before initializing the USP registers, please read the relative section in the Atlas™ Developers Manual to make sure how to describe the frame characteristics all the USP. The configuration procedure has been described in the Chapter 6.5.7 USP Frame Configuration detailedly. All the register bits decription refers to chapter 6.5.8 of the Developers Manual. With the reference of Figure 54-58, Chapter 6.5.7-6.5.8, user can configure the register bits to the correct work mode of USP by following the register sequence described below 12.3.1.1 USP Pin Mode Register Bits Firstly, set all the USP pins that will be used to USP function and the rest pin can be set to I/O mode for other usage. The default value is USP function mode. Quick Reference Mode Register 1

SCLK_PIN_MODE, RFS_PIN_MODE, TFS_PIN_MODE, RXD_PIN_MODE, TXD_PIN_MODE, SCLK_IO_MODE, RFS_IO_MODE, TFS_IO_MODE, RXD_IO_MODE, TXD_IO_MODE

12.3.1.2 SCLK Related Register Bits The following charaterisctic is the main consideration for the SCLK.

1. Synchronous/Asynchronous mode. (If it is asynchronous mode, no sclk is need) 2. SCLK slave/master mode. 3. SCLK IDLE toggle/stop mode (the IDLE state of SCLK when the serial bus frame is in the IDLE

state) 4. SCLK IDLE high/low level mode (the SCLK stop at logic 0 or logic 1 if SCLK will stop when IDLE) 5. Count the divider number from the SYSCLK according to the frequency of SCLK 6. If the SCLK is slave, decide whether the glitch-free circuit is needed to used.

All the characteristics are mapped to by the fowllowing register bits. Quick Reference Mode Register 1

SYNC_MODE, CLOCK_MODE, SCLK_IDLE_MODE, SCLK_IDLE_LEVEL Mode Register 2

USP_CLK_DIVISOR Transmit Frame Control Register

SLAVE_CLK_SAMPLE 12.3.1.3 TFS Related Register Bits If the serial bus is not asynchronous mode, software should configure the TFS with the following charateristic.

1. TFS slave/master mode 2. TFS active high/low level 3. TFS source mode (if TFS is master mode, it is generated by hardware and software) 4. The valid TFS length 5. The whole transmitting frame length

Configure the TFS signal by setting the following register bits related with the the TFS



Quick Reference Mode Register 1

TFS_ACT_LEVEL Mode Register 2

TFS_MS_MODE, TFS_SOURCE_MODE, Transmit Frame Control Register

TX_SYNC_LEN, TX_FRAME_LEN 12.3.1.4 TXD Related Register Bits TXD is the transmitted data line. All the following characteristics must be considered and set.

1. TX data is driven by the rising/falling edge of SCLK if serial bus is synchronous mode. 2. TX data is MSB/LSB on the data line 3. TX data length in one transmitted frame 4. TX data delay length after TFS is valid or frame starts 5. TX data shifter length when transmitting 6. the last data/zero is sent out repeatedly if the underflow happens

All the characteristics above are mapped to by the fowllowing register bits. Quick Reference

Mode Register 1 TXD_ACT_EDGE, ENDIAN_CTRL, TX_UFLOW_REPEAT

Mode Register 2 TXD_DELAY_LEN

Transmit Frame Control Register TX_DATA_LEN TX_SHIFTER_LEN

12.3.1.5 RFS Related Register Bits Receiving operation shares the one frame synchronous signal with the transmiting usually, but in some application, especially in the RFS slave mode, they use the different ones. So in these cases, software must still configure the RFS by the following characteristics

1. RFS slave/master mode 2. RFS active high/low level 3. the whole receving frame length

Configure the RFS signal by setting the following register bits related with the the RFS. Quick Reference

Mode Register 1 RFS_ACT_LEVEL

Mode Register 2 RFS_MS_MODE

Receive Frame Control Register RX_FRAME_LEN

12.3.1.6 RXD Related Register Bits RXD is the received data line. All the following characteristics must be considered and set.

1. RX data is driven by the rising/falling edge of SCLK if serial bus is synchronous mode. 2. RX data length in one receiving frame 3. RX data delay length after RFS/TFS is valid or frame starts 4. RX data shifter length when receiving

All the characteristics above are mapped to by the fowllowing register bits.



Configure the RXD signal by setting the following register bits related with the the RXD. Quick Reference

Mode Register 1 RXD_ACT_EDGE

Mode Register 2 RXD_DELAY_LEN

Receive Frame Control Register RX_DATA_LEN, TX_SHIFTER_LEN

12.3.1.7 Other Frame Setting Related Register Bits Till now, software has configured most mode setting register bits, but some other more register still need to setting to configure the frame completely. If the current USP is set to IrDA mode, those register bits below must be set:

• IrDA related register bits


HPSIR_EN, IRDA_WIDTH_DIV, IrDA_IDLE_LEVEL Mode Register 2

IRDA_DATA_WIDTH Software needs to enable all the interrupt that it is used by setting the Interrrupted enable register

• Interrupted related register bits The last two registers bits are showed below. They are very important for controlling the transmit/receive operation sequency and continuity. Software can make the transmitting and receiving happen in the same frame or different frame, simultenuously or alternatively, etc.

• TX/RX work mode related register bits


ENA_CTRL_MODE, FRAME_CTRL_MODE Till now you have finished configure all the registers related the transmitting/receiving frame. Thereafter you must configure the TX FIFO/RX FIFO related register bits to make them work rightly. 12.3.1.8 TX FIFO/RX FIFO related register bits You must first set the DMA I/O MODE register of both TX FIFO and RX FIFO to decide whether the DMA or IO control the data transmitting/receiving. After that, the data length of transmitting/receiving must be set. Then you must set the FIFO_WIDTH bit in the (TX_FIFO/RX_FIFO) control register to decide exchange a byte/word/dowrd data with the FIFO. If the DMA mode is select, FIFO_WIDTH must be set to 0x2.



If DMA mode is used, one more register, USP TX_FIFO level check register, must be set to decide when to apply the DMA request for the TX_FIFO/RX_FIFO. Quick Reference TX FIFO related registers:

USP TX_FIFO DMA I/O MODE register USP TX_FIFO DMA I/O length register USP TX_FIFO control register USP TX_FIFO operation register USP TX_FIFO status register

RX FIFO related registers: USP RX_FIFO DMA I/O MODE register USP RX_FIFO DMA I/O length register USP RX_FIFO control register USP RX_FIFO operation register USP RX_FIFO status register

After finishing all the register setting, software must reset and start the TX_FIFO and RX_FIFO, and then set the USP_EN bit of the register USP0_MODE1 to enable USP transmit and receive hardware logic After configuration of USP, enable the USP transmit and receiving logic by setting the USP_EN bit in register of USP_MODE1.

// fifo Start USP0_TXFIFO_OP = 0x1;

USP0_RXFIFO_OP = 0x1; // fifo Start

USP0_TXFIFO_OP = 0x2; USP0_RXFIFO_OP = 0x2;

//enable all the transmit and receive logic USP0_MODE1 |= 0x20; 12.3.2 Sample Code of USP Initialization Have known the key factor of each pin signal of USP and the frame description, here the initialization of some kind of serial bus is introduced below. The function of following sample code is initialization of the USP to the corresponding work mode. Each section is for a kind of serial bus. All the sample code below is initialized to IO mode for both TX_FIFO and RX_FIFO. 12.3.2.1 Uart Mode Initial The following code is for 1 start bit 8 data bit, 1 stop bit, and without parity bit. Because there is some state transfer on the TXD, in order to avoid the influence of it to the other device, TXD should first be set to I/O output mode and output logic 1 to it. After finishing all the initialization, set the TXD to USP function again. #define USP_LITTLE_ENDIAN 0x10 #define USP_TXD_AS_GPIO 0x10000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20

// count the clock divider usp_baud_rate = (IO_CLOCK/8/baudrate + 1)/2-1;



// Set to RS232 asynchronous mode USP0_MODE1 = USP_LITTLE_ENDIAN | USP_TXD_AS_GPIO; USP0_PIN_IO_DATA=0x8; // output logic 1 to TXD USP0_MODE2 = 1 | (1 << 8) | (usp_baud_rate << 21); // TX and RX frame setting USP0_TX_FRAME_CTRL = 0x7 | (0x8 << 8) | (0x9 << 16) | (0x7<< 24); USP0_RX_FRAME_CTRL = 0x7 | (0x9 << 8) | (0x7 << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = (0x04 << 2); USP0_RXFIFO_CTRL = (0x0C << 2); … // Enable TX and RX logic USP0_MODE1 |= USP_ENABLE; //enable all the transmit and receive

logic for(i=0; i<1000; i++); // some time delay is needed before start

to work USP0_PIN_IO_DATA=0; USP0_MODE1 &= ~USP_TXD_AS_GPIO;

12.3.2.2 IrDA Mode Initial The following code is for 1 start bit 8 data bit, 1 stop bit, and without parity bit. The valid data pulse on the RXD is logic 0, and the data width is 1.6µs on both TXD and RXD. #define USP_LITTLE_ENDIAN 0x10 #define USP_HPSIR_EN 0x8 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20

// count the clock divider usp_baud_rate = (IO_CLOCK/8/baudrate + 1)/2-1; irda_width_div = 16*IO_CLOCK/10000000+1;

// Set to IrDA asynchronous mode USP0_MODE1 = USP_LITTLE_ENDIAN | HPSIR_EN | (1<<30) | (irda_width_div

<<22); USP0_MODE2 = 1 | (1 << 8) | (usp_baud_rate << 21) | (1<<31); // TX and RX frame setting USP0_TX_FRAME_CTRL = 0x7 | (0x8 << 8) | (0x9 << 16) | (0x7<< 24); USP0_RX_FRAME_CTRL = 0x7 | (0x9 << 8) | (0x7 << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = (0x04 << 2); USP0_RXFIFO_CTRL = (0x0C << 2); …



// Enable TX and RX logic USP0_MODE1 |= USP_ENABLE; //enable all the transmit and receive

logic for(i=0; i<1000; i++); // some time delay is needed before start

to work 12.3.2.3 SPI Mode (PH2401) Initial #define USP_SYNC_MODE 0x1 #define USP_LITTLE_ENDIAN 0x10 #define USP_RX_DATA_EDGE_NEG 0x40 #define USP_TX_DATA_EDGE_NEG 0x80 #define USP_ENA_AUTO_CLEAR 0x10000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20

//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_LITTLE_ENDIAN | USP_RX_DATA_EDGE_NEG |

USP_TX_DATA_EDGE_NEG; USP0_MODE2 = 9 | (1 << 8) | (39 << 21) | USP_ENA_AUTO_CLEAR; //

1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0x11 << 8) | (0x13 << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0x7 | (0x13 << 8) | (0x7 << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = USP_TXFIFO_WIDTH_WORD | (0x04 << 2); USP0_RXFIFO_CTRL = (0x0c << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE;

12.3.2.4 SPORT Mode (AD73322) Initial USP use the SDOFS as the Frame synchronous signal of both transmitting and receiving frame and SDOFS is feed back to SDIFS also. #define USP_SYNC_MODE 0x1 #define USP_CLK_SLAVE_MODE 0x2 #define USP_RX_SYNC_VALID_HIGH 0x100 #define USP_TX_SYNC_VALID_HIGH 0x200 #define USP_SCLK_IDLE_TOGGLE 0x400 #define USP_UFLOW_RPT_ZERO 0x80000000 #define USP_RFS_SLAVE 0x80000 #define USP_TFS_SLAVE 0x100000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20



//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_CLK_SLAVE_MODE |

USP_TX_SYNC_VALID_HIGH | USP_RX_SYNC_VALID_HIGH | USP_SCLK_IDLE_TOGGLE | USP_UFLOW_RPT_ZERO;

USP0_MODE2 = 1 | USP_RFS_SLAVE|USP_TFS_SLAVE; // for slave tfs, delay_length-1

USP0_TX_FRAME_CTRL = 0xf | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE;

12.3.2.5 ASPORT Mode (AD6521) Initial #define USP_SYNC_MODE 0x1 #define USP_TX_SYNC_VALID_HIGH 0x200 #define USP_SCLK_IDLE_TOGGLE 0x400 #define USP_ENA_AUTO_CLEAR 0x10000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20

//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_TX_SYNC_VALID_HIGH |

USP_SCLK_IDLE_TOGGLE; USP0_MODE2 = 1 | (1<<8) | USP_ENA_AUTO_CLEAR | (39 << 21); // 1/80 of

ioclk USP0_TX_FRAME_CTRL = 0xf | (0x13 << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0x13 << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE;

12.3.2.6 BSPORT Mode (AD6521) Initial



#define USP_SYNC_MODE 0x1 #define USP_RX_SYNC_VALID_HIGH 0x100 #define USP_TX_SYNC_VALID_HIGH 0x200 #define USP_SCLK_IDLE_TOGGLE 0x400 #define USP_UFLOW_RPT_ZERO 0x80000000 #define USP_RFS_SLAVE 0x80000 #define USP_TFS_SLAVE 0x100000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20


USP_RX_SYNC_VALID_HIGH | USP_SCLK_IDLE_TOGGLE | USP_UFLOW_RPT_ZERO; USP0_MODE2 = 1 | USP_RFS_SLAVE | USP_TFS_SLAVE | (39 << 21); //

1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE;

12.3.2.7 VSPORT Mode (AD6521) Initial #define USP_SYNC_MODE 0x1 #define USP_TX_SYNC_VALID_HIGH 0x200 #define USP_SCLK_IDLE_TOGGLE 0x400 #define USP_RFS_SLAVE 0x80000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20


USP_SCLK_IDLE_TOGGLE; USP0_MODE2 = USP_TFS_SLAVE | (39 << 21); // 1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2);



USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE;

12.3.2.8 SI Mode (PBA313) Initial #define USP_SYNC_MODE 0x1 #define USP_LITTLE_ENDIAN 0x10 #define USP_RX_DATA_EDGE_NEG 0x40 #define USP_TX_DATA_EDGE_NEG 0x80 #define USP_TX_SYNC_VALID_HIGH 0x200 #define USP_SCLK_IDLE_TOGGLE 0x400 #define USP_SOFT_TFS 0x40000 #define USP_TX_IO_MODE 0x1 #define USP_RX_IO_MODE 0x1 #define USP_ENABLE 0x20

//USP work mode initial USP0_MODE1 = USP_SYNC_MODE | USP_LITTLE_ENDIAN | USP_RX_DATA_EDGE_NEG |

USP_TX_DATA_EDGE_NEG | USP_SCLK_IDLE_TOGGLE | USP_TX_SYNC_VALID_HIGH;

USP0_MODE2 = USP_SOFT_TFS | (39 << 21); // 1/80 of ioclk USP0_TX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16) | (0xf << 24); USP0_RX_FRAME_CTRL = 0xf | (0xf << 8) | (0xf << 16); // TX FIFO/RX FIFO and other initial USP0_TX_DMA_IO_CTRL = USP_TX_IO_MODE; USP0_RX_DMA_IO_CTRL = USP_RX_IO_MODE; USP0_TX_DMA_IO_LEN = 0; USP0_RX_DMA_IO_LEN = 0; USP0_TXFIFO_CTRL = 0x1 | (0x4 <<2); USP0_RXFIFO_CTRL = 0x1 | (0xc << 2); … // Enable TX and RX USP0_MODE1 |= USP_ENABLE;



12.4 USP Transmitting Operation There are three methods for the Atlas™ to access the TX_FIFO and transmit the data out, please refer the chapter 6.5.5.2 of Developers Manual, for detailed information of method division and description. 12.4.1 I/O Mode Transmit by Interrupt Before software begins to transmit, USP0_INT_MASK must be set in the INT_RISC_MASK to enable the USP0 interrupt in the interrupt controller. Then all the interrupt to be used must be enabled There are three interrupts for use, TX_DONE, TX_FIFO_EMPTY, TXFIFO_THD_REACH. Software can select one of them to use according to the application. If one data is transmitted at one time, TX_DONE interrupt is enough, if several data are needed to transmit at one time; the last two interrupts are more suitable for high efficiency. The following operation step after the USP initialization use the TX_DONE interrupt as the example, other two interrupt have the similar step.

1. Enable the USP0 interrupt by set the INT_RISC_MASK with INT_MASK_SERIAL_0 (0x00100000)

2. Enable TX_DONE interrupt of the USP 3. Enable the TX_ENA bit in the TX_RX_ENABLE register 4. RISC/DSP writes a data to be transmitted to TX_FIFO and USP will transmit the data out to TXD

automatically 5. Having finished transmitting, USP hardware will trigger TX_DONE interrupt automatically, then

software will come into the ISR (Interrupt Service Routing) of TX_DONE interrupt 6. In ths ISR, software should first clear the INT_RISC_MASK, and clear TX_DONE interrupt in the

register of USP0_INT_STATUS, and then inform the end of transmitting to other routing. 7. Before return back from the ISR, enable the INT_RISC_MASK with INT_MASK_SERIAL_0 again. 8. If you want to continue to transmit more data, you can return to step 2 if TX_ENA is cleared

automatically after transmitting the previous data, otherwise return to step 3, and then begin the new transmitting routing.

12.4.2 I/O Mode Transmit by Polling FIFO Status This work mode is similar to the first transmitting work mode. Software can poll the TX_FIFO status register. If TX_FIFO is not full, software can write new data to be transmitted to the TX_FIFO. Software can write more than one data to the TX_FIFO if it is not full. The following operation steps use the FULL flag as the sample step after the USP initialization.

1. Enable the TX_ENA bit in the TX_RX_ENABLE register 2. RISC/DSP read the USP0_TXFIFO_STATUS register periodely 3. If TX_FIFO is not FULL, RISC/DSP can write one data to be transmitted to TX_FIFO, and USP

will transmit the data out to TXD automatically 4. If you want to continue to transmit more data, you can return to step 1 if TX_ENA is cleared

automatically after transmitting the previous data, otherwise return to step 2, and then begin the new transmitting routing.

Software can use not only the FULL flag, but also the EMPTY, or one capacity threshold of TX_FIFO to decide whether to write new data to TX_FIFO. 12.4.3 DMA Transmitting Mode This work mode is suitable for a large mount of data to be transmitted out



If DMA access the TX_FIFO, software should be careful the initialization of TX_FIFO related register in the USP initialization introduction. The sample step of DMA operation after the USP initialization is showed below


2. Enable DMA_IO_TX_DONE interrupt of the USP 3. Enable the TX_ENA bit in the TX_RX_ENABLE register, and the TX_ENA will not be cleared

automatically 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA controller) 5. Set the RSC_DMA_MUX assign DMA CH9 to USP0 TX_FIFO 6. Setup the DMA channel 9 by setting the DMA_CH9_XLEN, DMA_CH9_YLEN,

DMA_CH9_CTRL 7. Reset and start the TX_FIFO 8. Assign the memory address of the data block to be transmitted to register of DMA_CH9_ADDR,

which will start DMA transfer. DMA controller will write the data to TX_FIFO, and USP then transmits them out one by one after all the data have been sent out of the TXD pin, the DMA_IO_TX_DONE interrupt will be trigger by the hardware of USP.

9. In the ISR of DMA_IO_TX_DONE interrupt, software first clear the INT_RISC_MASK, and then clear DMA_IO_TX_DONE interrupt in the register of USP0_INT_STATUS, software can then inform other software routing that the current DMA transmitting finishes.

10. If software needs to start another DMA transmitting operation, it can return to step 7.



12.5 USP Receiving Operation As the receiving operation, the receiving has also three main kinds of operation method. 12.5.1 I/O Mode Receiving by Interrupt Before software begins to receive, USP0_INT_MASK must be set in the INT_RISC_MASK to enable the USP0 interrupt in the interrupt controller. Then all the interrupt to be used must be enabled There are three interrupts for use, RX_DONE, RX_FIFO_FULL, RXFIFO_THD_REACH. Software can select one of them to use according to the application. If RISC/DSP wants to read one data being received at one time, RX_DONE interrupt is enough, and the RX_FIFO acts as as receive register in this case. If software wants to read several data at one time, the last two interrupts are more suitable, but software must guarantee no overlow will happen to RX_FIFO. The following operation step after the USP initialization use the RX_DONE interrupt as the example, other two have the similar step.


2. Enable RX_DONE interrupt of the USP 3. Enable the RX_ENA bit in the TX_RX_ENABLE register, and the RX_ENA will not be cleared

automatically 4. Rx_shifter always monitor and receive the data on the RXD. If a new valid frame is detected.

After all the data bit in a valid received frame have been received, the received data is sent to RX_FIFO from the rx_shifter automatically, which will trigger the RX_DONE interrupt

5. In the ISR of the RX_DONE interrupt, software first clear the INT_RISC_MASK, clear RX_DONE interrupt in the register of USP0_INT_STATUS, and then can read the data out from the RX_FIFO and inform the end of reading to other routing.

6. Before return back from the ISR, enable the INT_RISC_MASK with INT_MASK_SERIAL_0 again.

7. If you want to continue to read more data, you can return to step 3 if RX_ENA is cleared automatically after receiving the previous data, otherwise return to step 4 to wait for another receive operation

12.5.2 I/O Mode Receiving by Polling FIFO Status This work mode is similar to the first receiving work mode. Software can poll the RX_FIFO status register. If RX_FIFO is not empty, software can read new data out from the RX_FIFO. Software can also read more than one data to the TX_FIFO has morel. The following operation steps use the EMPTY flag as the sample step after the USP initialization.

1. Enable the RX_ENA bit in the TX_RX_ENABLE register 2. RISC/DSP read the USP0_RXFIFO_STATUS register periodely. Rx_shifter always monitor

and receive the data on the RXD If a new valid frame is detected, after all the data bit in a valid received frame have been received, the received data is sent to RX_FIFO from the rx_shifter automatically

3. If RX_FIFO is not empty, RISC/DSP can read one data out from RX_FIFO 4. If you want to continue to receive more data, you can return to step 1 if RX_ENA is cleared

automatically after read the previous data, otherwise return to step 2, and then begin the new receiving routing.

Software can use not only the EMPTY flag, but also the FULL, or one capacity threshold of RX_FIFO to decide whether to read new data from RX_FIFO.



12.5.3 DMA Recieving Mode This work mode is suitable for a large mount of data to be received out. If DMA access the RX_FIFO, software should be careful the initialization of RX_FIFO related register in the USP initialization introduction. Don’t forget set the flush bit in the RX_FIFO DMA I/O MODE register. The sample step of DMA receiving operation after the USP initialization is showed below


2. Enable DMA_IO_RX_DONE interrupt of the USP 3. Enable the RX_ENA bit in the TX_RX_ENABLE register 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA controller) 5. Set the RSC_DMA_MUX assign DMA CH10 to USP0 RX_FIFO 6. Setup the DMA channel 10 by setting the DMA_CH10_XLEN, DMA_CH10_YLEN, and

DMA_CH10_CTRL (Please refer to the DMA controller). 7. Reset and start the RX_FIFO 8. Assign the memory address of the memory block to store the data from the RX_FIFO to

register of DMA_CH10_ADDR to start DMA transfer. DMA controller will read the data from RX_FIFO if there is some DMA request from the RX_FIFO. Of course rx_shifter always monitor and receive the data on the RXD If a new valid frame is detected, after all the data bit in a valid received frame have been received, the received data is sent to RX_FIFO from the rx_shifter automatically

9. After all the data defined by the RX_FIFO DMA I/O length register have been received in the memory, the DMA_IO_RX_DONE interrupt will be trigger by the hardware of USP.

10. In the ISR of DMA_IO_RX_DONE interrupt, software first clear the INT_RISC_MASK, and then clear DMA_IO_RX_DONE interrupt in the register of USP0_INT_STATUS, software can then inform other software routing the end of the current DMA receiving.

11. If software needs to start another DMA transmitting operation, it can return to step 7.



12.6 Interralation of Transmitting and Receiving There are three main interralation between the transmitting and receiving operation:

• Transmitting and receiving are independent of each other • Transmitting and receiving happen at the same time • Transmitting and receiving happen alternately

12.6.1 Independent Operation for Transmitting and Receiving The relationship of independence between transmitting and receiving are the simplest. Software can divide the transmitting and receiving into two different section to control. Software can follow the transmitting and receiving operation step described before. Usually the TX_ENA and RX_ENA need set only once in this kind of bus, so the TX_RX_ENABLE register should not be cleared after one data is transmitted or received. BSPORT of AD6521, UART, and IrDA are this kind of bus. 12.6.2 concurrent Operation for Transmitting and Receiving There are two sub-types for this kind of serial bus. One is that transmiting and receiving always happen together; the other is that they sometimes happen together, sometimes only transmiting or receiving happens. PCM bus, ASPORT and VSPORT of AD 6521, the SPORT of AD73322 are in the first type, while SPI bus of PH2401, and SI bus of PBA313 are in the latter. First type is also simple. Though they are happen together, but software can treat the transmitting and receiving as independent of each other. So the TX_ENA and RX_ENA can be set to either auto-cleared mode or not. If they are cleared, they must be set each time before trasnmsitting and receiving happen. As for the second, TX_ENA and RX_ENA must be set to auto-cleared mode. If transmitting/receiving will happen next time, only set TX_ENA/RX_ENA only, otherwise set both of them before operation. 12.6.3 Alternate Operation for Transmitting and Receiving In some application, the transmitting and receiving will happen alternately. SPI bus of T8536 belongs to it. So the TX_ENA and RX_ENA must set to auto-cleared mode. Before transmitting happens, set the TX_ENA. After the operation finishes, TX_ENA will be cleared automatically. If the next operation is receiving, set the RX_ENA before receiving starts. So the current operation will not influence the next one. The setting of the TX_ENA or RX_ENA controls the next operation is transmitting or receiving. The complex operation of writing and reading to the external device can be realized by this method.

12.7 Pin I/O Mode Operations If some pins of USP are not used as the USP function, they can be set to IO function for other application. If the pin is set to output mode, the value of pin will follow the corresponding bit value of USP Pin I/O Data Register, and if the pin is set to input mode, the value of pin is reflected on the corresponding bit of USP Pin I/O Data Register.



The following example is set the RXD pin of USP0 to output mode After the USP is reset and set the RXD to logic 1.

… USP_MODE1 | = 0x2000; … USP_PIN_IO_DATA | = 0x1;

The following example is set the RXD pin of USP0 to input mode After the USP is reset and read value of RXD pin to a integer of rfs_in .

… USP_MODE1 | = 0x42000; … rfs_in = USP_PIN_IO_DATA & 0x1;



12.8 USP Reconfiguration The reconfiguration of the USP is the key character of flexibily of USP. In some application, there may be several bus formats to be used in one application such as EEPROM X25C040. The register bits USP_EN in the USP_MODE1 register is used for the change of work mode. After the USP finishes transmitting and receive work in one mode, software can clear the USP_EN bit, which will reset all the transmitting and receiving logic of USP, then software can set all the register of the USP to another work mode. After that, set 1 to USP_EN again and USP can work in the new work mode correctly. The following is the general step for work mode changing.

1. USP is initialized to the first work mode 2. USP transmit/receive data under the first work mode 3. After USP finishes the data transfer, disable the USP_EN bit 4. Reinitialize the USP to second mode 5. USP transmit/receive data under the second work mode 6. After USP finishes the data transfer, disable the USP_EN bit 7. Reinitialize the USP to three mode 8. …



12.9 SIB Initialization There are three kinds of operation to the SIB, external register reading/writing, audio data transferring, telecom data transferring. Before you operate the SIB you should first initialize it, and initialize the register of external SIB device by writing it, then you can enable the audio data transfer or telecom data transfer. SIB initialization step:

1. reset and power up the USP3 2. release pins of USP3 3. configure the SIB control register SIB_CTRL with all the correct setting of SIB bus to make the

SIB work mode normally. 4. intialize the SIB TX_FIFO/RX_FIFO related register 5. enable the SIB by writing the 1 to SIB_ENA_REG. (If SIB is not used, SIB_ENA_REG can be

set to 0 to reduce the power consumption.) The sample code is showed as below. SIB use the internal IO_CLOCK as the clock source and the Audio data use SIB FIFO and the telecom data use USP3 FIFO. Audio and Telecom data use the flag on the SIB bus as the sample flag. Both Audio and Telecom data use the DMA to transfer data. #define PWRCLK_DMA_EN 0x00000004 #define PWRCLK_SP3_EN 0x00001000 #define RESET_SR_SP3_RST 0x00020000 #define USP3_SIB_MODE_SEL 0x400000 #define SIB_PORT_ENABLE 0x1

//reset and power up PWR_CLK_EN | = PWRCLK_SP3_EN; //SIB and USP3 share the same clock

signal PWR_CLK_EN | = PWRCLK_DMA_EN; //if DMA is used RESET_SR | = RESET_SR_SP3_RST; //SIB and USP3 share the same reset RESET_SR &= RESET_SR_SP3_RST; PWR_PIN_RELEASE=1; USP3_INT_STATUS = 0xffff0000; //clear all the interrupt of SIB //SIB module initialize SIB_CTRL = (0x03 << 17) | USP3_SIB_MODE_SEL; // the frequency of SIB

clock is 1/8 of IO_CLOCK //SIB FIFO initialize SIB_TX_DMA_IO_LEN = 0; SIB_RX_DMA_IO_LEN = 0; SIB_TXFIFO_CTRL = 0x1 | (0x04 << 2); // word SIB_RXFIFO_CTRL = 0x1 | (0x0c << 2); // word

SIB_TXFIFO_OP = 0x1; //reset the FIFO SIB_RXFIFO_OP = 0x1; //reset the FIFO SIB_TXFIFO_OP = 0x2; //start the FIFO SIB_RXFIFO_OP = 0x2; //start the FIFO //USP3 FIFO initialize



USP3_TX_DMA_IO_LEN = 0; USP3_RX_DMA_IO_LEN = 0; USP3_TXFIFO_CTRL = 0x1 | (0x04 << 2); // word USP3_RXFIFO_CTRL = 0x1 | (0x0c << 2); // word USP3_TXFIFO_OP = 0x1; //reset the FIFO USP3_RXFIFO_OP = 0x1; //reset the FIFO USP3_TXFIFO_OP = 0x2; //start the FIFO USP3_RXFIFO_OP = 0x2; //start the FIFO

//SIB bus enable SIB_ENA = SIB_PORT_ENABLE;



12.10 SIB Operations After the SIB module is initialized, Atlas™ can write or read the register data of the external SIB device, UCB1200/1300 etc. The interrupt of the UCB1200 can be connected to the GPIO of Atlas™. 12.10.1 Register Writing The operation step of register writing is showed as below

1. write the register address, register data, write flag to SIB_EXT_DATA regsiter. 2. the SIB logic will send data out to external device automatically. After it finishes, SIB logic will

set the SIB_WRITE_END bit in the reigster of SIB_STATUS to valid. 3. Software can poll SIB_WRITE_END bit after step 1. The SIB_WRITE_END bit is read only. If it

is valid, it means that the writing operation fnishes and software can start another register writing or reading. The SIB_WRITE_END will be cleared automatically after SIB_EXT_DATA is read or written.

12.10.2 Register Reading The operation step of register writing is showed as below

1. write the register address, read flag to SIB_EXT_DATA regsiter. 2. the SIB logic will send address and command out to external device and receive the data to be

read in the SIB_EXT_DATA at the same time automatically. After it finishes, SIB will set the SIB_READ_END bit in the regsiter of SIB_STATUS to valid.

3. Software should poll this bit after step1. the SIB_READ_END bit is read only. If it is valid, it means that the writing operation fnishes. Software can read the data out of the SIB_EXT_DATA. After the data is read, the SIB_READ_END will be clear automatically and software can start another register writing or reading.

12.10.3 Audio Data Transfer The DMA mode is usually used for the audio data transfering. The operations step below use the SIB FIFO for data transfering.

1. before you start audio data transfer, you must initialize the SIB module. 2. initialize the SIB TX_FIFO and RX_FIFO to. Be careful that both two FIFO’s should be set to

DMA mode, and then reset and start the two FIFO to prepare for data transfer. 3. configure all the audio related register of the external SIB device except the register bits of

AUD_IN_ENA or AUD_OUT_ENA in the audio control register with the address equal to 8 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA) 5. Set the RSC_DMA_MUX assign DMA CH6&CH7 to SIB RX_FIFO and TX_FIFO 6. Setup the DMA channel 6 and channel 7 related register in the DMA controller, such as the

DMA_CH6_XLEN, DMA_CH6_YLEN, DMA_CH6_CTRL, DMA_CH6_XLEN, DMA_CH6_YLEN, DMA_CH6_CTRL

7. Assign the memory address of the audio data to be transmitted to register of DMA_CH7_ADDR to start DMA transmitting, and assign the memory address of the memory block to store the external audio data to register of DMA_CH6_ADDR to start DMA receiving.

8. write 1 to both the AUD_IN_ENA and AUD_OUT_ENA bit to the audio contol register with address equal to 8, which will automatically start the both the SIB module and external device



to tranmsit and receive audio data on the SIB bus. The received data in the RX_FIFO will be read out by the DMA and the data written into the TX_FIFO by the DMA will be sent out by SIB automatically.

9. If the TX_FIFO/RX_FIFO DMA length register is not set to 0, after the data defined in the DMA length register has been transmitted/received, the DMA write/read will stop. Software can also use the interupt to monitor it.

10. If the TX_FIFO/RX_FIFO DMA length register is set to 0, and software want to finish the audio data transfer, it can write 0 to both the AUD_IN_ENA and AUD_OUT_ENA bit of audio control register, which will stop both side of SIB bus to stop the Audio data transfer.

12.10.4 Telecom Data Transfer The DMA mode is also used for the Telecom data transfering. The operations step below use the USP3 FIFO for data transfering. The whole procedure is similar to that of the Audio data.

1. before you start telecom data transfer, you must initialize the SIB module. 2. initialize the USP3 TX_FIFO and RX_FIFO. Be careful that both two FIFO’s should be set to

DMA mode, and then reset and start the two FIFO’s to prepare for data transfer. 3. configure all the telecom related register of the external SIB device except the register bits of

TEL_IN_ENA or TEL_OUT_ENA in the telecom contol register with the address equal to 6 4. Set the DMA_WIDTH register of the DMA controller (please refer to the DMA) 5. Set the RSC_DMA_MUX assign DMA CH9&CH10 to USP3 RX_FIFO and TX_FIFO 6. Setup the DMA channel 9 and channel 10 related register in the DMA controller, such as the

DMA_CH9_XLEN, DMA_CH9_YLEN, DMA_CH9_CTRL, DMA_CH10_XLEN, DMA_CH10_YLEN, DMA_CH10_CTRL

7. Assign the memory address of the telecom data to be transmitted to register of DMA_CH10_ADDR to start DMA transmitting, and assign the memory address of the memory block to store the external telecom data to register of DMA_CH9_ADDR to start DMA receiving.

8. write 1 to both the TEL_IN_ENA and TEL_OUT_ENA bit to the telecom contol register with address equal to 6, which will automatically start the both the SIB module and external device to tranmsit and receive telecom data on the SIB bus. The received data in the RX_FIFO will be read out by the DMA and the data written into the TX_FIFO by the DMA will be sent out by SIB automatically.

9. If the TX_FIFO/RX_FIFO DMA length register is not set to 0, after the data defined in the DMA length register has been transmitted/received, the DMA write/read will stop. Software can also use the interupt to monitor it.

10. If the TX_FIFO/RX_FIFO DMA length register is set to 0, and software want to finish the telecom data transfer, it can write 0 to both the TEL_IN_ENA and TEL_OUT_ENA bit of audio control register, which will stop both side of SIB bus to stop the telecom data transfer.

Audio data can select either SIB FIFO or USP3 FIFO as the data buffer, and then telecom data will use another one.



13 Audio CODEC Interface

13.1 Operation Overview The Audio CODEC interface can be used to connect to either AC’97 or I2S type CODEC. The CODEC interface share pins with USP1. Both AC’97 and I2S CODEC controller interface can support dual and single channel record and playback; For AC’97 CODEC controller, it can support 48KHz sample rate and VRA mode; For I2S interface, both the bit clock and frame rate are programmable, 512fs, 384fs and 256fs are all supported. The audio CODEC interface operation includes: 1. Audio CODEC controller initialization 2. AC’97 CODEC configuration

a) AC’97 audio CODEC initialization b) AC’97 register operation c) AC’97 record d) AC’97 playback

3. I2S CODEC configuration a) I2S dual-channel record and playback b) I2S single channel record and playback c) L3 mode implementation



13.2 AudioCODEC Controller Initialization Before configure the AC’97 or I2S interface, use needs to initialize the audio CODEC controller first. The audio CODEC controller initialization includes: 1. Program PWR_CLK_EN to provide clock to AtlasTM audio CODEC interface and DMA interface (the

audio data transfer can only be in DMA mode), and then give a software reset to audio CODEC interface; PWR_CLK_EN |= 0x100; // provide clock to CODEC interface PWR_CLK_EN |= 0x4; // provide clock to CODEC interface for (i=0;i<10;i++); RESET_SWR |= 0x100; // declare reset to CODEC for (i=0;i<10;i++); RESET_SWR &= ~ 0x100; //clear reset to CODEC

2. Program RSC_PIN_MUX to enable audio CODEC pin. Since audio CODEC is pin-muxed with USP1, if audio CODEC function is selected, the pin should be configured for audio CODEC purpose. RSC_PIN_MUX | = 0x8000;

3. Program the CODEC_SHARE register to select audio CODEC modes: AC’97 or I2S. If AC’97 CODEC controller is selected, bit 7 of CODEC_SHARE should be 1’b0; if I2S interface is selected, bit 7 of CODEC_SHARE register should be 1’b1.



13.3 AC’97 CODEC Configuration The AC’97 CODEC controller configuration includes: 1. AC’97 audio CODEC initialization The AC’97 audio CODEC needs to be activated to work firstly. The step is: 1) Initialize audio CODEC to be AC’97 interface. (13.2 section) 2) After AC’97 CODEC is powered up, AtlasTM needs to reset AC’97 audio CODEC by pulling down

reset pin of AC’97 audio CODEC for about 80ms. The hardware reset can be realized by AtlasTM GPIO or extended GPIO.

3) Wait for another 80ms; 4) Read CODEC_AC97_RTAGH register to check bit 7, if bit 7 is 1’b1 it indicates that AC’97 CODEC

has worked; if it keeps to be 1’b0 for 40us, it indicates AC’97 audio CODEC hasn’t work yet. Set bit 4 (WARM_WAKE) of CODEC_AC97_CONTROL for 2us, and check bit 7 of CODEC_AC97_RTAGH again, if it’s 1’b1 then AC’97 audio CODEC initialization is done; if it is 1’bo, then go back to step 2.

2. AC’97 control register operation AC’97 control register operation is realized through AC-Link slot 1 and slot 2 of the input and output frames. The register operation command is issued through output frame slot1 and slot2; the value of target register is returned in input frame slot2. Both the record channel and playback channel should be enabled. After the audio CODEC interface is configured as AC’97 format, when writing AC’97 control register, the step is:

1) Program CODEC_SHARE register to bring AC’97 DA channel out of idle mode (If DA_CHANNEL is already out of idle mode, there is no need to program the register again).

CODEC_SHARE & = ~0x40;

2) Set bit 5 of CODEC_AC97_CONTROL register to start AC’97; If AC’97 has been started, there is

no need to set the bit again. CODEC_AC97_CONTROL |= 0x20;

3) Program CODEC_AC97_COMMAND to set the register index and written data. CODEC_AC97_COMMAND = (register_value <<16) | (register_index <<8)

4) Set bit 15 to indicate the next output frame contains valid data; Set bit 14 and bit 13 of CODEC_AC97_CONTROL, the register index and write command will be issued to AC’97 audio CODEC in slot 1 and slot 2 of next output frame.

CODEC_AC97_CONTROL |= 0xE000;

5) Check the bit 14 and 13 (tag bit of slot 1 and slot 2) of CODEC_AC97_CONTROL to make sure that the command has been issued. The sample code for step 3 to 5 is:



CODEC_AC97_CMD = ((unsigned long) data << 16) | ((unsigned long) addr << 8);

CODEC_AC97_CTRL |= 0xe000; while(CODEC_AC97_CTRL & 0x4000);

When reading status from AC’97 audio CODEC, the step is:

1) Program CODEC_SHARE register to bring AC’97 controller DA and AD channel out of ilde mode (If they are already enabled, there is no need to set them again). CODEC_AC97_CONTROL & = ~0x60;

2) Set bit 5 of CODEC_AC97_CONTROL register to start AC’97; If AC’97 has already been started, there is no need to set the bit again. CODEC_AC97_CONTROL |= 0x20;

3) Program CODEC_AC97_COMMAND to set the register index and set bit 15 of CODEC_AC97_COMMAND register to indicate the read operation.

CODEC_AC97_COMMAND = (register_index <<8) | 0x8000;

4) Set bit 15 of CODEC_AC97_CONTROL to indicate that the next output frame is valid; Set bit 14 of CODEC_AC97_CONTROL, the read command will be issued to AC’97 audio CODEC in the slot1 of next output frame;

CODEC_AC97_CONTROL |= 0xC000;

5) Poll AC97_REG_RD register bit, when it’s asserted, it indicates the AC’97 audio CODEC has return the status data. Then write 1’b1 to AC97_REG_RD to clear the status

6) Read CODEC_AC97_STATUS register to get the value. register_value = (CODEC_AC97_STATUS && 0xFFFF0000) >> 16;

The sample code for step 3 to step 6 is:

CODEC_AC97_CMD = (0x0000ffff & (((unsigned long) addr | 0x80) << 8)); CODEC_AC97_CTRL |= 0xc000; while(CODEC_AC97REG_OK == 0x0); CODEC_AC97REG_OK = 0x01; data = (CODEC_AC97_STATUS & 0xFFFF0000) >> 16;

3. AC’97 record The following steps describe the procedures necessary for audio dual channel record program.

1) Initialize audio CODEC interface and select AC’97 mode (section 13.2); 2) Initialize external AC’97 audio CODEC. 3) Program AC’97 audio CODEC control register to set sample frequency, gain etc. 4) DMA audio record channel (DMA channel 6) initialization;

a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value.

b) Enable DMA interrupt; (Please refer to DMA interface for more information)



5) Initialize AtlasTM AC’97 controller interface;

a) Reset and initialize audio record FIFO; b) Program CODEC_SHARE register to enable AC’97 record channel;

The play channel may also be enabled for AC’97 codec register control. c) If interleave mode is selected, set bit 0 of CODEC_SHARE register When interleave mode is selected, in dual channel mode the 32-bit data is in L-R format. In normal mode, the 32-bit data is in R-L mode. d) Program CODEC_AC97_CONTROL register to select the left and right channel; If dual channel record mode is selected, both the left and right record channel of CODEC_AC97_CONTROL should be enabled. AC’97 controller interface receives data from input frame Slot3 and Slot4 for left and right channel respectively. In normal mode, the 32-bit audio data is saved in R-L format; when interlave mode is selected the 32-bit data is in L-R mode. CODEC_AC97_CONTROL |= 0x0C; In single channel record mode, when left channel is enabled, the left record channel of CODEC_AC97_CONTROL should be enabled and right record channel is disabled. AC’97 controller only receives data from input frame Slot3, the data from Slot4 is ignored. When right channel is enabled, the right record channel of CODEC_AC97_CONTROL should be enabled and left record channel is disabled. AC’97 controller only receives data from input frame Slot4, the data from Slot3 is ignored.

6) Start audio record FIFO. a) Set AC97_START bit to start AC97 interface; b) Start audio record FIFO;

CODEC_RX_FIFO_OP_REG = 0x01;

7) Instruct DMA audio record channel to run by programming DMA channel 6 start address register DMA_CH6_ADDR.

4. AC’97 audio play The following steps describe the procedures necessary for audio play:

1) Initialize AtlasTM audio CODEC controller 2) Initialize AC’97 audio CODEC

a) Reset AC’97 Codec; b) Program AC’97 Codec control register to set sample frequency, gain etc.

3) DMA audio play channel (DMA channel 7) initialization; a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in

loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value. b) DMA interrupt enable (Please refer to DMA interface for more information)

4) Configure AtlasTM AC’97 interface; a) Reset and audio play FIFO;

CODEC_TX_FIFO_OP_REG = 0x02;

b) Program CODEC_SHARE register to AC’97 play channel; When AC’97 codec status needs to be monitored, the AC’97 record channel must be enabled.



c) If interleave mode is selected, set bit 0 of CODEC_SHARE register When interleave mode is selected, in dual channel mode the 32-bit audio data is treated as L-R format. In normal mode, the 32-bit data is treated as R-L mode. d) Program CODEC_AC97_CONTROL register to enable the left or right channel. If dual channel play mode selected, both the left and right play channel of CODEC_AC97_CONTROL should be enabled. In normal mode, the 32-bit audio data is treated as R-L format, the high 16-bit is sent to AC’97 audio CODEC through output frame Slot 4 and low 16-bit is through output frame Slot3; In interlave mode the high 16-bit is for left playback channel and low 16-bit is for right play channel. In single channel play mode, when the left play channel of CODEC_AC97_CONTROL is enabled, the 32-bit digital audio data to be played is in L-L format representing 2 sample data. When right channel is enabled, the 32-bit data is in R-R format. e) Program CODEC_AC97_CONTROL register to set the tag to enable the AC-Link slots. Bit 15 (Frame valid) of CODEC_AC97_CONTROL register must be set no matter the audio play is in stereo or mono mode. It is used to indicate AC’97 audio CODEC that output frame is valid. If dual channel mode is selected, the bit 11 and 12 (output frame tag bit of slot 4 and 3) of CODEC_AC97_CONTROL register should be set. If left single channel is enabled, bit 12 (output frame tag of Slot 3) must be 1’b1; if bit 11 (output frame tag of Slot 4) is also set, the audio data is also played through right channel, in this case both the left and right channel play the same mono audio data stream. If bit 11 is 0, only left channel plays the audio stream. If right single channel is enabled, bit 11 (output frame tag of Slot 4) must be 1’b1; if bit 12 (output frame tag of Slot 3) is also set, the audio data is also played back through left channel, in this case both the left and right channel play the same mono audio data stream. If bit 12 is 1’b0, only right channel plays the audio stream.

5) Instruct DMA audio play channel to run by writing DMA channel 7 start address register. 6) Start audio playback FIFO; Set AC97_START bit to start AC’97 interface

CODEC_TX_FIFO_OP_REG = 0x01; CODEC_AC97_CTRL |= AC97_START;



13.4 I2S CODEC Configuration The following steps describe the procedures necessary for I2S audio record program

1) AtlasTM audio CODEC interface initialization and select the I2S interface; 2) Intialise AtlasTM I2S CODEC ctroller

a) Enable AtlasTM CKO b) Program CODEC_UDA_CONTROL to set I2S BIT_CLK frequency c) Program CODEC_UDA_CONTROL to set I2S word_select frequency The frequency relationship between CKO, BCK and WS is: fBCK = fIOCLOCK / 2(BCK_SET + 1); fWS = fBCK/2(WS_SET+1); fCKO = 512fws or 384fws or 256fws

In AtlasTM CKO is sourced from one of the two PLLs, and it has a fixed relationship with IOCLOCK.

3) DMA audio record channel (DMA channel 6) initialization; a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in

loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value. b) DMA interrupt enable (Please refer to DMA interface for more information)

4) Initialize external I2S audio CODEC through L3 interface. a) Hardware reset I2S CODEC through AltasTM GPIO or extended GPIO; b) Program I2S CODEC control register to set gain etc.

5) Initialize CODEC and I2S interface; a) Reset and initialize audio record FIFO; b) Program CODEC_SHARE register to enable UDA interface and UDA record channel. c) Program CODEC_UDA_CONTROL register to select the left and right data channel; If dual channel record mode is selected, both the left and right record channel of CODEC_UDA_CONTROL should be enabled. I2S interface receives data from both the left channel and right channel. In normal mode, the 32-bit audio data is saved in R-L format; when interlave mode is selected the 32-bit data is in L-R mode. In single channel record mode, when left channel is enabled, the left record channel of CODEC_UDA_CONTROL should be enabled and right record channel is disabled. I2S controller only receives data from left slot, the data from right slot is ignored. When right channel is enabled, the right record channel of CODEC_UDA_CONTROL should be enabled and left record channel is disabled. I2S controller only receives data from right channel, the data on left channel is ignored. d) Program CODEC_UDA_CONTROL register to enable the UDA left slots; e) Set UDA_START bit to start UDA interface;

6) Instruct DMA audio record channel to run, and start audio record FIFO.

The following steps describe the procedures necessary for audio play through I2S audio CODEC:

1) AtlasTM audio CODEC interface initialization and select the I2S interface; 2) Intialise AtlasTM I2S CODEC ctroller

a) Enable AtlasTM CKO b) Program CODEC_UDA_CONTROL to set I2S BIT_CLK frequency



c) Program CODEC_UDA_CONTROL to set I2S word_select frequency The frequency relationship between CKO, BCK and WS is: fBCK = fIOCLOCK / 2(BCK_SET + 1); fWS = fBCK/2(WS_SET+1); fCKO = 512fws or 384fws or 256fws

3) DMA audio play channel (DMA channel 7) initialization;

a) Program DMA channel x-length, Y-length and Width register to set transfer counter. When in loop mode, the DMA x-length will be 0, and Y-length must be a non-zero value.

b) DMA interrupt enable (Please refer to DMA interface for more information)

4) Initialize external I2S Codec through L3 interface by programming Atlas GPIO a) Reset I2S Codec; b) Program I2S Codec control register to set gain etc.

5) Initialize I2S interface; d) Reset and initialize audio play FIFO; e) Program CODEC_SHARE register to enable UDA interface and UDA play channel; f) Program CODEC_UDA_CONTROL register to enable the left and right channel. If dual channel play mode selected, both the left and right play channel of CODEC_UDA_CONTROL should be enabled. In normal mode, the 32-bit audio data is treated as R-L format, the high 16-bit is sent to I2S audio CODEC through output frame right Slot and low 16-bit is through output frame left slot; In interlave mode the high 16-bit is for left playback channel and low 16-bit is for right play channel. In single channel play mode, when the left play channel of CODEC_UDA_CONTROL is enabled, the 32-bit digital audio data to be played is in L-L format representing 2 sample data. When right channel is enabled, the 32-bit data is in R-R format. g) Program CODEC_UDA_CONTROL register to enable the UDA left and right slots. If dual channel mode is selected, the bit 30 and 31 (right and left slot enable signals) of CODEC_UDA_CONTROL register should be set. If left single channel is enabled, bit 31 (left slot enable) must be 1’b1; if bit 30 (right slot enable signal) is also set, the audio data is also played through right channel, in this case both the left and right channel play the same mono audio data stream. If bit 30 is 0, only left channel plays the audio stream. If right single channel is enabled, bit 30 (right slot enable) must be 1’b1; if bit 31 (left slot enable) is also set, the audio data is also played back through left channel, in this case both the left and right channel play the same mono audio data stream. If bit 31 is 1’b0, only right channel plays the audio stream.

6) Instruct DMA audio play channel to run and start audio playback FIFO; Set UDA_START bit to start UDA interface.



14 Camera Interface

14.1 Operation Overview In sensor control interface, support following operation mode: 1. Slave mode, external sensor provide VSYNC, HSYNC and PIXCLK to the Atlas™ processor. 2. Master mode, Atlas™ processor provides VSYNC, HSYNC and PIXCLK signal to the external

sensor. 3. VSYNC, HSYNC or PIXCLK can be inversed by the internal logic for generating the needed control

signal. 4. 10-bit pixel data can be shifted right or left to adapt the software operation. 5. There is an internal logic to remove the glitch signal in the pixel clock. 6. Capture the needed image with active region function. 7. Support abnormal interrupt, such as FIFO overflow. In I2C module, support following operation mode: 1. In master mode, support 7-bit SLAVE ID. 2. In master mode, support programmable I2C master clock frequency. 3. In master mode, support up to 4 bytes data transfer. 4. In slave mode, support 7-bit programmable slave ID. 5. In slave mode, support 2 bytes data transfer.



14.2 Initialize Operations 14.2.1 Initialize Camera Interface 14.2.1.1 Step-by-step register programming 1. Enable the camera interface, for it share some pins with data flash/SmartMedia interface. 2. Supply the clock to the camera interface. 3. Reset the camera interface. 4. Enable the camera interrupt. 14.2.1.2 Common examples of use Following code gives an example:

// Enable camera pins. PWR_PIN_RELEASE = 1; RSC_PIN_MUX |= 0x4000; // Enable clock of camera interface PWR_CLK_EN |= 0x80; // Reset camera interface RESET_SR |= 0x1000; RESET_SR &= (~0x1000); // Enable the camera interrupt. INT_RISC_MASK |= 0x00008000;

14.2.2 Camera Interrupt Operation 14.2.2.1 Step-by-step register programming 1. Check the INT_IRQ_PENDING register if this interrupt is trigged by the camera interface. 2. Disable the camera interface interrupt to avoid the interrupt generate repeatly. 3. Check the CAM_INT_CTRL register. 4. Set a flag to notify the main program which interrupt happens. 5. Clear the interrupt by setting the corresponding bit of CAM_INT_CTRL register. 6. Enable the camera interrupt again. 14.2.2.2 Common examples of use Following code are used in the interrupt processing program to process the camera interrupt.

// Check the interrupt source Int iStatus = INT_IRQ_PENDING; if (iStatus & 0x00008000) { // Disable the camera interrupt INT_RISC_MASK &= (~0x00008000); iStatus = CAM_INT_CTRL;

// Check which interrupt happens if (iStatus & 0x01) { // Clear the interrupt



CAM_INT_CTRL = 0x01; }

// Add similar code here to check other interrupts … // Enable the camera interrupt. INT_RISC_MASK |= 0x00008000; }



14.3 DMA Operations 14.3.1 Initialize DMA Interface 14.3.1.1 Step-by-step register programming 1. Supply the clock to DMA interface. 2. Enable the DMA interrupt. 3. Enable the DMA channel2 interrupt in DMA_INT_EN register. This channel is dedicated to camera

interface. 14.3.1.2 Common examples of use Following code gives an example:

// Enable clock of DMA interface PWR_CLK_EN |= 0x04; // Enable the DMA interrupt INT_RISC_MASK |= 0x02000000; // Enable DMA channel2 interrupt DMA_INT_EN |= 0x04;

14.3.2 DMA Interrupt Operation 14.3.2.1 Step-by-step register programming 1. Check the INT_IRQ_PENDING register if this interrupt is trigged by the DMA interface. 2. Disable the DMA interrupt to avoid the interrupt generate repeatly. 3. Check the DMA_CH_INT register. 4. If this interrupt is trigged by channel2, set a flag to notify the main program DMA is done. 5. Clear the interrupt by setting the bit2 of DMA_CH_INT register. 6. Enable the DMA interrupt again. 14.3.2.2 Common examples of use It is only DMA channel2 interrupt that need to be checked. Following code are used in the interrupt processing program to process the DMA channel2 interrupt.

// Check the interrupt source Int iStatus = INT_IRQ_PENDING; if (iStatus & 0x02000000) { // Disable the DMA interrupt INT_RISC_MASK &= (~0x02000000); iStatus = DMA_CH_INT;

// Check which interrupt happens if (iStatus & 0x04) { // Clear the interrupt.

DMA_CH_INT = 0x04; // Set a flag here such as following code. bDMADone = 1;



} // Enable the DMA interrupt again. INT_RISC_MASK |= 0x02000000; }

14.3.3 DMA operation 14.3.3.1 Step-by-step register programming Following registers must be set first. 1. Set the CAM_FIFO_LEVEL_CHK to adjust the priority of channel2. 2. Select a DMA width register and set it with the needed number. 3. Configure the DMA_CH2_XLEN and DMA_CH2_YLEN register. 4. Configure the control register, work in normal mode or burst mode, transmission direction and select

a width register. 5. Start the DMA channel2 operation by writing the DWORD sdram address to DMA_CH2_ADDR. 6. Wait for the DMA channel2 interrupt. 14.3.3.2 Common examples of use Following code gives an example base on following condition: Capture the 640*480 pixel data from external sensor and store it from the address 0x20000 using DMA width0 register. // Set the DMA_WIDTH0 register.

DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; // Set the YLEN, it equals to actual number - 1 DMA_CH2_YLEN = 480-1; // Set the DMA operation mode DMA_CH2_CTRL |= 0x0000; //normal DMA mode DMA_CH2_CTRL |= 0x0008; //burst DMA mode // Start dma channel2 operation, this data must be the DWORD address. DMA_CH2_ADDR = 0x20000/4;



14.4 Sensor Operations 14.4.1 Initialize Sensor Control Module 14.4.1.1 Step-by-step register programming 1. Write 0xFFFFFFFF to CAM_START, make active region out of possible range. 2. Write 0x00007FFF to CAM_YINT, avoid camera interface generate too many interrupts. 3. Set bit5 of CAM_CTRL register according the trigger type of sensor. 4. Enable the SENSOR_INT and FIFO_OVERFLOW in the CAM_INT_EN register. 5. Reset the FIFO before capture operation. 14.4.1.2 Common examples of use Following code gives an example:

CAM_YINT = 0x00007FFF; CAM_START = 0xFFFFFFFF; CAM_INT_EN |= 0x21;

14.4.2 Sensor Clock Operation 14.4.2.1 Step-by-step register programming Sensor clock can be provided by the CKO of Atlas™-1 except the external oscillator. If using CKO, following register must be configured. 1. Set the PWR_PLL2_CONFIG to select a need frequency. 2. Turn on the PLL2. 3. Set the PWR_CLK_RATIO to decide the ratio between CKO and PLL2 frequency. 4. Set the PWR_CLK_SWITCH to switch the CKO to PLL2. 5. Set the PWR_CLK_EN to enable the CKO output. 14.4.2.2 Common examples of use Following code gives an example provide a 12MHz CKO.

// Set the PLL2 to 48MHz PWR_PLL2_CONFIG = 0x44; // Turn on PLL2 PWR_CLK_CTRL |= 0x02; // Wait for PLL2 work normal for(i=1;i<=300;i++); // Select CKO = PLL2/4=48M/4=12M PWR_CLK_RATIO |= 0x20; // CKO switch to PLL2 PWR_CLK_SWITCH |= 0x80; for(i=1;i<=100;i++); // Enable CKO PWR_CLK_EN |= 0x10000;

14.4.3 Capture Image Operation



14.4.3.1 Step-by-step register programming 1. Set the CAM_DMA_LEN to the actual transfer byte number. This register can be used in debugging

process to check the actual received bytes. 2. Reset the FIFO through setting CAM_FIFO_OP. 3. Configure the DMA register according to actual needed. 4. Start the DMA operation. 5. Configure the camera register according to actual needed. 6. Start capturing process. 7. Wait for the DMA interrupt. 8. After receiving DMA interrupt, it means the receive picture has stored to SDRAM. 9. Clear the bit0 of CAM_FIFO_OP register after the DMA interrupt received. Otherwise FIFO will

overflow. 14.4.3.2 Common examples of use Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation.

// Set the CAM_DMA_LEN to 640*480*2, for each 10-bit pixel occupis 2 bytes; CAM_DMA_LEN = 648*480*2; // Reset the FIFO through setting CAM_FIFO_OP. CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01;

After receiving DMA interrupt, it means the receive picture has stored to SDRAM. 14.4.4 Slave Mode Operation 14.4.4.1 Step-by-step register programming 1. In this mode, PIXEL clock, HSYNC and VSYNC are generated by external sensor, so set bit8,9,10

of register CAM_CTRL to 0. 2. Capture the video image as 14.4.3 list. 14.4.4.2 Common examples of use Following example code are based on following conditions:



Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation.

// Set the CAM_CTRL register, select slave mode. CAM_CTRL &= (~0x0700); // Set the CAM_DMA_LEN to 640*480*2, for each pixel occupis 2 bytes; CAM_DMA_LEN = 648*480*2; // Reset the FIFO through setting CAM_FIFO_OP. CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01;

After receiving DMA interrupt, it means the receive picture has stored to SDRAM. 14.4.5 Pixel Data Shift Operation 14.4.5.1 Step-by-step register programming 1. Set the CAM_PIXEL_SHIFT to select the shift direction and shift number. 2. Capture the video image as 14.4.3 list. 14.4.5.2 Common examples of use Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA burst mode. We only need its high eight bit from its total 10-bit pixel data, so shift right 2 bits. 4 shifted pixel data will be combined to a DWORD data.

// Set the CAM_PIXEL_SHIFT. CAM_PIXEL_SHIFT = 2; // Set the CAM_DMA_LEN to 640*480; CAM_DMA_LEN = 640*480; // Reset the FIFO CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA channel2 DMA_WIDTH0 = 640/4; DMA_CH2_XLEN = 640/4; DMA_CH2_YLEN = 480-1; // Set the burst DMA mode. DMA_CH2_CTRL = 0x0008; // Start the DMA operation. DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image.



CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation. CAM_FIFO_OP |= 0x01;

After receiving DMA interrupt, it means the receive picture has stored to SDRAM. 14.4.6 Inverse Control Operation 14.4.6.1 Step-by-step register programming 1. In this mode, PIXCLK, HSYNC and VSYNC can be inversed separately, so set bit2 or bit3 or bit4 of

CAM_CTRL register according to system needs; 2. Capture the video image as 14.4.3 list. 14.4.6.2 Common examples of use Following example code are based on following conditions: Capture a (640,480) picture from (2,2) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. The PIXCLK, HSYNC and VSYNC are inversed, this function must cooperate with your sensor’s timing.

// Set the CAM_CTRL register. CAM_CTRL |= 0x001C; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, DMA_WIDTH0 = 640/2, DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1+2) << 16) + (640-1+2); CAM_YINT = 480-1+2; CAM_START = 0x00020002; // Start the capture operation CAM_FIFO_OP |= 0x01;

After receiving DMA interrupt, it means the receive picture has stored to SDRAM.

14.4.7 Sample Pixel Clock Operation 1. In this mode, if the pixel clock has some glitches, we can use sample function to decrease the

damage, so set bit7 of CAM_CTRL register. It must be sure that IOCLK frequency is at least 6 multiple of PIXCLK.

2. Capture the video image as 14.4.3 list. 14.4.7.1 Common examples of use



Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation.

// Set the CAM_CTRL register to enable this function. CAM_CTRL |= 0x0080; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO. CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2, and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation. CAM_FIFO_OP |= 0x01;


14.4.8 Master Mode Operation 1. In this mode, camera interface generate PIXCLK, HSYNC and VSYNC by itself, so set bit 8,9,10 of

CAM_CTRL register; 2. Capture the video image as 14.4.3 list. 14.4.8.1 Common examples of use Following example code are based on following conditions: Capture a (640,480) picture from (0,0) original point and store it to SDRAM from 0x20000 address, using DMA normal mode operation. Output pixel clock equals to 3MHz (suppose IOCLK equals to 30MHz), valid HSYNC width equals to 16 pixel clocks, valid VYSNC high period equals to 38 pixel clocks plus 1 HSYNC width, a valid line include 700 pixel clocks and a whole picture include 600 lines.

// Set the output VYSNC signal, 0x257 blank line + 0x1 active line = 600 lines CAM_VSYNC_CTRL = 0x02570001; // Set the output HSYNC signal, 0x2ac blank pixel clocks + 0x10 active pixel clocks = 700 pixel clocks CAM_HSYNC_CTRL = 0x02AC0010; // Set the output PIXCLK signal, (4+1)*2*output pixel clock frequency = IOCLK frequency. // Set the valid VSYNC high period equals to 38 pixel clock. CAM_PIXCLK_CTRL = 0x00240004; // Set CAM_CTRL register to enable the PIXCLK, HSYNC and VSYNC output. CAM_CTRL |= 0x0700; // Set the CAM_DMA_LEN to 640*480*2; CAM_DMA_LEN = 640*480*2; // Reset the FIFO



CAM_FIFO_OP |= 0x02; CAM_FIFO_OP &= (~0x02); // Set registers of DMA2 and start DMA operation. DMA_WIDTH0 = 640/2; DMA_CH2_XLEN = 640/2; DMA_CH2_YLEN = 480-1; DMA_CH2_CTRL = 0x0000; DMA_CH2_ADDR = 0x20000/4; // Set the active region of the image. CAM_END = ((480-1) << 16) + (640-1); CAM_YINT = 480-1; CAM_START = 0x00000000; // Start the capture operation CAM_FIFO_OP |= 0x01;




14.5 I2C Master Operations 14.5.1 Initialize Unit 14.5.1.1 Step-by-step register programming 1. Set bit6 of CAM_CTRL register to enable the I2C unit. 2. Enable I2C master interrupt in CAM_INT_EN register. 3. Set I2C clock period in CAM_I2C_MASTER_CLK_CTRL register. 14.5.1.2 Common examples of use Fowllowing example configures the I2C master clock period. Suppose IOCLK frequency = 33MHz and I2C master clock frequency = 100kHz, so the high period and low period of SCLK = 33M/ (2*100K) = 165 = 0xA5. CAM_CTRL |= 0x40; CAM_INT_EN |= 0x06;

CAM_I2C_MASTER_CLK_CTRL = 0x00A500A5; 14.5.2 Write n Bytes to External Device 14.5.2.1 Step-by-step register programming 1. Write n bytes (up to 4 bytes) register data to CAM_I2C_MASTER_OUT register. 2. Write slave ID, register number, and register address to CAM_I2C_MASTER_CTRL register. R/W

must be 0 for a write. 3. Wait for I2C interrupt. 4. If I2C success interrupt happens, set bit1 of CAM_INT_CTRL register to clear this interrupt and

transmission is ok. 5. If I2C fail interrupt happens, set bit2 of CAM_INT_CTRL register to clear this interrupt. You must

check your hardware connection and try it again from step1. 14.5.2.2 Common examples of use Following example code are based on following conditions:

• Write 1 byte data to a slave device • Slave device ID address = 0x33 (7b’0110011”) • Register address = 0xAA(8b’10101010”) • Data to write = 0xAC

// Set the register data CAM_I2C_MASTER_OUT = 0xAC; // Set the control register, transfer number(1byte, 2’b00)+slave address(0x33)+write bit(0)+register address(0xAA) CAM_I2C_MASTER_CTRL = 0x000066AA; Wait for I2C master success interrupt or fail interrupt.

If success interrupt happens, clear this interrupt and transmission is ok. Otherwise, if fail interrupt happens, you must check your hardware connection and try it again.



14.5.3 Read n Bytes from External Device 14.5.3.1 Step-by-step register programming 1. Write slave ID, register number and register address to CAM_I2C_MASTER_CTRL register. R/W

must be 1 for a read. 2. Wait for I2C master interrupt. 3. If I2C master success interrupt happens, set bit1 of CAM_INT_CTLR register to clear this interrupt. 4. Read register data from CAM_I2C_MASTER_IN register. 5. If I2C master fail interrupt happens, set bit2 of CAM_INT_CTRL register to clear this interrupt. You

must check your hardware connection and try it again from step1. 14.5.3.2 Common examples of use Following example code are based on following conditions: Read 2 byte data from an external I2C device. Slave device ID address = 0x33 Register address = 0xAA

// Set the control register, transfer number(2bytes, 2’b01)+slave address(0x33)+read bit(1)+register address(0xAA) CAM_I2C_MASTER_CTRL = 0x400067AA;

Waiting for I2C master success interrupt or fail interrupt. If success interrupt happens, Read data from CAM_I2C_MASTER_IN. Bit0—bit15 is the valid byte. Clear I2C master success interrupt bit. If fail_interrupt happens, you must check your hardware connection and try it again.



14.6 I2C Slave Operations 14.6.1 Initialize Unit 14.6.1.1 Step-by-step register programming During initializing process, following register must be set first: 1. Set bit6 of CAM_CTRL register to enable the I2C unit. 2. Enable I2C slave interrupt in CAM_INT_EN register. 3. Set the SLAVE ID to the CAM_I2C_SLAVE_CTRL register. 14.6.1.2 Common examples of use Following code gives an example. // Enable I2C module

CAM_CTRL |= 0x40; // Enable interrupt CAM_INT_EN |= 0x18; // Set slave ID (7’h4c) CAM_I2C_SLAVE_CTRL = 0x9800;

14.6.2 Normal Operation 14.6.2.1 Step-by-step register programming When I2C slave module received register address send from external I2C master device, it will generate DATA_REQ_INT interrupt to RISC, RISC must read CAM_I2C_SLAVE_ADDR register first, get the register address, then send the corresponding register data to CAM_I2C_SLAVE_CTRL register. When I2C slave module complete receive or transmit a complete register data, it will generate I2C_SLAVE_INT to notify RISC. RISC should read CAM_I2C_SLAVE_CTRL again, and overwrite the old register data with new data in CAM_I2C_SALVE_CTRL if bit8 of this register equals to 0. 14.6.2.2 Common examples of use Following example code are based on following conditions: Process register0x0b, suppose its default value = 0x7788. Slave ID of AtlasTM-1 is 7’h4C.

// Set the slave ID to I2C slave unit. CAM_I2C_SLAVE_CTRL = 0x9800; When receive DATA_REQ_INT, read CAM_I2C_SLAVE_ADDR register. Suppose it value equal to 0x0000980B. It means external master will process the register0b. // Write register data to CAM_I2C_SLAVE_CTRL register. CAM_I2C_SLAVE_CTRL = 0x7788980B;

After receiving I2C_SLAVE_INT, read CAM_I2C_SLAVE_CTRL register back. If bit8 of received data equals to 1, that means external device read register of AtlasTM-1 processor. Otherwise, external device write new data to AtlasTM-1 processor, suppose it value equal to 0x6677980B, overwrite register 0x0B data from 0x7788 to 0x6677.



14.7 Quick Reference Use following table as a quick reference sheet to set the DMA register when shift function is used. Suppose capture an (XSIZE, YSIZE) image. Table 10. Pixel Shift Number vs DMA Register Setting CAM_PIXEL_SHIFT DMA_CH2_XLEN DMA_CH2_YLEN DMA_WIDTH CAM_DMA_LEN 0x01, 0x00, 0x10~0x16

XSIZE/2 YSIZE-1 XSIZE/2 XSIZE*YSIZE*2

0x02~0x0x05 XSIZE/4 YSIZE-1 XSIZE/4 XSIZE*YSIZE 0x06~0x09 XSIZE/8 YSIZE-1 XSIZE/8 XSIZE*YSIZE/2



15 USB 1.1 Device Interface

15.1 Operation Overview The Atlas™ USB device is USB version 1.1 compatible. Knowledge of USB standard is helpful to developers. The specification is available at http://www.usb.org.



15.2 Initialization The USB device register space in Atlas™ is from 0x80040000. Offset 0x0~0x7c are USB core registers; 0x80~0x90 are USB interface registers; after 0xf00 are DMA FIFO control registers. Please refer to Atlas™ Development Manual for registers definition. All bit mask used in sample should be defined in head files. The initialization sequence is:

• Configure PLL2 (Make sure PLL1 already be effectived) PWR_PLL2_CONFIG = 0x44; PWR_CLK_CTRL |= 0x3; // turn on PLL2

• Enable USB clock.

PWR_CLK_EN |= PWRCLK_USB_EN;

• Enable interrupt controller INT_RISC_MASK |= INT_MASK_USB;

• Initialize USB interface wait counter (if IO clock more than 48MHz)

USB_WS = 0x68;

• Enable USB. USB_USBSTS = (USB_ENABLE | USB_INTF_MODE | USB_RST_DISABLE);

• Clear all interrupt status USB_INTSTS1 = 0xFF; USB_INTSTS3 = 0xFF; USB_INTSTS5 = 0xFF;

• Enable endpoint 0, reset and suspend interrupt USB_INTEN1 = USB_EP0_TX_RX_INT_MASK; USB_INTEN3 = USB_EP0_TX_RX_INT_MASK; USB_INTEN5 = USB_RST_INT_MASK | USB_SUS_INT_MASK;

• Enable USB endpoint 0. USB_EP0CTL = 0x1B;

• Enable 3.3v supply.

USB_USBSTS |= USB_SOFT_CONNECT; Please refer to charpter 6 for details of clocks and power manager operation



15.3 Control Transfer Endpoint 0(EP0) is configured as default control endpoint. During bus enumeration, the host read all the descripter tables through it to know information about the device. Here we just talking USB device read and write operation, developer should follw USB specification standard device requests to process the received command. EP0 read sequence:

• The host sends a SETUP command.

• Device generates an EP0 RX Interrupt.

• Select endpoint. USB_EPINDX = ep_num;

• Check EP0 status register received setup token bit.

if (USB_EP0STS & 0x04)

• Wait until the start of overwrite bit is cleared while (USB_EP0STS & USB_EP0_ST_OW);

• Set the end of overwrite bit

USB_EP0STS = USB_EP0_END_OW;

• Read the data into a buffer. data = USB_EPRXDAT;

• Check the start of overwrite bit and the end of overwrite bit.

if (USB_EP0STS & (USB_EP0_ST_OW | USB_EP0_END_OW))

• Set EP0 status register receive valid bit. USB_EP0STS = USB_EP0_RX_VALID;

• Clear EP0 contorl register stall bit after receving a setup pkt

USB_EP0CTL &= ~USB_EP0_STALL;

• Process SETUP command.

• Clear EP0 status register the setup packet status bit. USB_EP0STS = USB_EP0_RX_SETUP;

• Clear the EP0 RX interrupt bit and returns from the interrupt service routine.

EP0 write sequence:

• Device generates an EP0 TX Interrupt.


• Flush transmition FIFO. (if need)

USB_EP0CTL |= 0x10;

• Write the data into USB TX data register.



USB_EPTXDAT = data;

• Set EP0 control register bit2. USB_EP0CTL |= 0x20;

• Clears the EP0 TX interrupt bit and returns from the interrupt service routine.



15.4 I/O Operation Endpoint 1~3 (EP1~3) is programmable through firmware for interrupt or bulk or isochronous transfer. CPU programs endpoint TX/RX control register bit2 to set transfer type whenever SET CONFIGURATION command are executed. EP1~3 TX/RX Interrupt was enabled when device configured successfully. Following sequence for bulk in transfer:

• The host sends an IN command.

• Device generates an EP1~3 TX Interrupt.


• Flush and clear underflow or overflow. (if need)

USB_EPTXCTL |= USB_EP_FLUSH; USB_EPTXSTS |= (USB_EP_XFER_OF | USB_EP_XFER_UF);

• Check valid packet transmitted. USB_EPTXSTS;

• Write data to USB. USB_EPTXDAT = data;

• Set TX data valid bit. USB_EPTXCTL |= USB_EP_TX_RX_VALID;

• Clears the EP1~3 TX interrupt bit and returns from the interrupt service routine. Following sequence for bulk out transfer:

• The host sends a OUT command.

• Device generates an EP1~3 RX Interrupt.


• Flush and clear underflow or overflow. (if need) USB_EPRXCTL |= USB_EP_FLUSH; USB_EPRXSTS |= (USB_EP_XFER_OF | USB_EP_XFER_UF);

• Check valid packet received. USB_EPRXSTS;

• Get byte count for the data packet. pkt_len = USB_EPRXCNTL;

• Read data from USB. data = USB_EPRXDAT;

• Set RX data valid bit after read all data. USB_EPRXCTL |= USB_EP_TX_RX_VALID;



• Clears the EP1~3 RX interrupt bit and returns from the interrupt service routine.

For isochronous transfer, the sequence sames to bulk transfer except the interrupt event is SOF interrupt



15.5 DMA Operation Here we are talking about the DMA in Palm-2, which can be used for the block data transfer between Palm-2 and external USB device. This “block data transfer” is still belong to the I/O transfer in USB core (USB core do not support the DMA mode). To start a DMA transfer, the sequence is:

• Enable DMA interrupt INT_RISC_MASK |= INT_MASK_DMA_CTRL;

• Initialization USB device like before.

• Initialize the FIFO control registers USB_TX_DMA_IO_CTRL = 0x0; USB_TX_FIFO_LEVEL_CHK = 0x060504; USB_TX_FIFO_OP = 0x3; USB_RX_DMA_IO_CTRL = 0x2; USB_RX_FIFO_LEVEL_CHK = 0x060504; USB_RX_FIFO_OP = 0x3; • Select endpoint.

USB_EPINDX = ep_num;

• Set DMA control registers (XLEN, YLEN, CTRL, etc.) DMA_WIDTH0 = 0x100; (if doing 2-D DMA) DMA_CH1_XLEN = 0x100; DMA_CH1_YLEN = 0x1F; (if doing 2-D DMA) DMA_CH1_CTRL = 0x0C; DMA_WIDTH0 = 0x100; (if doing 2-D DMA) DMA_CH0_XLEN = 0x100; DMA_CH0_YLEN = 0x1F; (if doing 2-D DMA) DMA_CH0_CTRL = 0x08; • Set the DMA start address to start the DMA

DMA_CH1_ADDR = (iAddr >> 2);(if IN Token) DMA_CH0_ADDR = (iAddr >> 2);(if OUT Token)

• Reset the DMA FSM (if need) USB_CTRL = 0x01; USB_CTRL = 0x00;

• Set USB interface control registers. USB_CTRL = (dma_len << 8) | 0x02;(if IN Token) USB_CTRL = (dma_len << 8) | 0x06;(if OUT Token)

• Set USB BULK mode registers (if USB data flow is BULK). USB_BULK_DMA = 0x01;

• Wait until DMA finishes (interrupt from DMA controller)



• Set data valid bit (if USB data flow is ISO) USB_EPTXCTL |= USB_EP_TX_RX_VALID; (if IN Token) USB_EPRXCTL |= USB_EP_TX_RX_VALID; (if OUT Token)

• Clears the SOF interrupt bit and returns from the interrupt service routine. (if USB data flow is

ISO) For ISO transfer, length of each DMA operation cannot exceed 256 bytes. Please refer to charpter 9 for details of DMA operation.



15.6 Quick Reference Table 11. USB Device Endpoint Configuration

Endpoint Number

Transfer Type Packet Size FIFO Size

0 Control 8-byte 8-byte 1 Interrupt or bulk or isochronous 16-byte 32-byte x2 2 Interrupt or bulk or isochronous 64-byte 128-byte x2 3 Interrupt or bulk or isochronous 256-byte 512-byte x2



16 Host Port Interface

16.1 Operation Overview The Host Port is used when Atlas™ acts as a PCMCIA slave to an external host (such as a PDA or Notebook PC). The Host Port operations are compatible with PC Card Standard 2.1. And the Host Port has some registers that can be accessed by both Atlas™ and the external Host, e.g. the CIS1 and Function Configuration registers. The Atlas™ Host Port can store 4 sets of Function Configuration registers, which means the Atlas™ can act as up to 4 different functional PC Card. From the Atlas™’s point of view, there are two types of data transfer: I/O data transfer and DMA data transfer.

1 Card Information Structure (please refer to the PCMCIA standard)



16.2 Address Mapping The Host port register space in Atlas™ is from 0x8009_0000. Offset 0x0~0x3FF are CIS space; 0x400~0x53F are Function Configuration Registers; after 0x540 are other Host port control registers. For more details, please refer to the related section in Atlas™ Developer’s Manual. From the external PCMCIA host’s point of view, there are two separate address space: the Attribute Memory Window and I/O Window. The CIS is on the bottom of the Attribute Memory Window (starts from 0x0) while the Function Configuration Registers are starts from a base address defined in register CONFIG_BASE_ADDR. Each set of the Function Configuration Registers has a different base address. All the other Host port control registers can be accessed in the I/O Window (starts from I/O Base Address).



16.3 Initialization The initialization has two parts: one for the Atlas™, the other for the external PCMCIA host. For Atlas™, the initialization sequence is:

• Enable Host Port clock and pins #define PWRCLK_HOST_EN 0x00002000 PWR_PIN_RELEASE = 1; PWR_CLK_EN = PWRCLK_HOST_EN; RSC_PIN_MUX |= 0x10; // enable Host port

• Reset Host Port

#define RESET_SR_HOST_RST 0x00080000

RESET_SR = RESET_SR_HOST_RST; for(i = 0; i < 10; i++); RESET_SR = 0;

• Enable PCMCIA mode (HP_CONTROL)

#define HP_PCMCIA_ENABLE (0x01 << 1) HP_CONTROL = HP_PCMCIA_ENABLE;

• Reset the Host port (if needed) and Set the interrupt type (HP_CONFIG_OPTION_x)

//HP_CONFIG_STATUS_REG_0 #define PCMCIA_FUNC_ENABLE (0x01 << 0) #define PCMCIA_LEVEL_REQ (0x01 << 6) #define PCMCIA_SRESET (0x01 << 7) #define PCMCIA_CLR_SRESET (0x00 << 7) HP_CONFIG_OPTION_0 = PCMCIA_SRESET;

for(i = 0; i < 10; i++); HP_CONFIG_OPTION_0= PCMCIA_CLR_SRESET | PCMCIA_LEVEL_REQ;

• Initialize Wait Counter (HP_PCMCIA_WAIT) HP_PCMCIA_WAIT = 0x8;

• Set the ENDIAN mode HP_PCMCIA_ENDIAN = 0x3; // input/output is big-endian

• Activate one function of the four (for multiple function PC Card) (HP_PCMCIA_FUNC_ACTIVE)

//PCMCIA_FUNCTION_ACTIVE #define HP_PCMCIA_FUNC0_ACTIVE (0x01 << 0)

HP_PCMCIA_FUNC_ACTIVE = HP_PCMCIA_FUNC0_ACTIVE;



• Set the I/O Base address registers (HP_IO_BASE_LO & HP_IO_BASE_HI)

#define IO_WINDOW_START_ADDR 0x170 HP_IO_BASE_LO_0 = IO_WINDOW_START_ADDR & 0xff; HP_IO_BASE_HI_0 = (IO_WINDOW_START_ADDR >> 8) & 0xff;

• Set the base address for all four sets of Function Configuration Registers (HP_CONFIG_BASE_ADDRESS_x)

HP_CONFIG_BASE_ADDRESS_0 = 0x100; HP_CONFIG_BASE_ADDRESS_1 = 0x120; HP_CONFIG_BASE_ADDRESS_2 = 0x140; HP_CONFIG_BASE_ADDRESS_3 = 0x160;

• Configure CIS

#define _HOST_MODULE_BASE 0x80090000 #define TUPLE_LENGTH 98

// Tuple data constant array unsigned char test_tuple[128] = {

0x01, //Device Info Tuple 0x02, //Link = 2h

0x00, //Not a memory device 0xff, //Termination Byte

… };

int i; //set config base address to cis for(i = 0; i < TUPLE_LENGTH; i+=4) { *(unsigned *)(_HOST_MODULE_BASE + i) = *(unsigned *)(test_tuple + i); }

• Enable Host port interrupt (HP_INT_EN, HP_PCMCIA_INT_EN, and HP_CONFIG_INT_EN_x) //HP_INT_STATUS

#define HP_PCMCIA_RESET_INT_MASK (0x01 << 2) #define HP_PCMCIA_FUNC0_INT_MASK (0x01 << 3) #define HP_PCMCIA_INT_MASK (0x01 << 8) //HP_PCMCIA_INT_EN masks #define HP_PCMCIA_XSFER_INT (0x01 << 7) //HP_CONFIG_INT_EN masks #define HP_CONIG_INT (0x01 << 0)

HP_INT_EN |= HP_PCMCIA_INT_MASK | HP_PCMCIA_FUNC0_INT_MASK; HP_PCMCIA_INT_EN = HP_PCMCIA_XSFER_INT; HP_CONFIG_INT_EN_0 = HP_CONIG_INT;



For the external PCMCIA host, please refer to the PCMCIA host’s spec.



16.4 I/O & DMA Operation There is a 64x8 FIFO SRAM in the Host Port. All the data transfer are done throught this FIFO. The FIFO can be accessed by either RISC or DMA Controller (please refer to the FIFO section in Atlas™ Developer’s Manual). If RISC accesses the FIFO, the data transfer is in I/O mode; if the DMA Controller accesses the FIFO, then the data transfer is in DMA mode. The I/O mode is relatively straightforward. But the DMA mode needs some further explanation here. First of all, please do not confuse this DMA with the DMA mode in PCMCIA standard. Here we are talking about the DMA in Atlas™, which can be used for the block data transfer between Atlas™ and external PCMCIA host. This “block data transfer” is still belong to the I/O transfer in PCMCIA standard (the DMA mode of PCMCIA standard is not supported by Atlas™). To start a DMA transfer of Host Port in Atlas™, the sequence is:

• Enable DMA interrupt //Init DMA DMA_WIDTH0 = 0x80; DMA_WIDTH1 = 0x100; DMA_WIDTH2 = 0x200; DMA_WIDTH3 = 0x300; //set dma int enable for host port DMA_INT_EN = 0x800; //clear all dma interrupts DMA_CH_INT = 0xfff; • Set DMA control registers (XLEN, YLEN, CTRL, etc.) according to the transfer size in

HP_PCMCIA_TX_SIZE_HI & HP_PCMCIA_TX_SIZE_LO registers //set dma ch11 x_length DMA_CH11_XLEN = (HP_PCMCIA_TX_SIZE_LO | (HP_PCMCIA_TX_SIZE_HI << 8))/4; if ((HP_PCMCIA_TX_SIZE_LO & 0x3) != 0) DMA_CH11_XLEN += 1; //set dma ch11 y_length DMA_CH11_YLEN = 0; //set dma ch11 width = 0x80 (width0), dir = 0, and burst = 1 DMA_CH11_CTRL = ((0x1<<3) | (0x0<<2) | (0x0));

• Set the DMA start address to start the DMA (this start address can be set by the external host by programming the general-purpose data registers HP_PCMCIA_GENERIC_x). In the following example, the external host stores the DMA start address into the two of general-purpose data registers. So Atlas™ can set the DMA start address by reading those general-purpose data registers.

//start dma and ch11 start address DMA_CH11_ADDR = (HP_PCMCIA_GENERIC_0 | (HP_PCMCIA_GENERIC_1 << 8));

• Initialize the FIFO control registers //start sdram --> fifo --> host HP_DMA_IO_CTRL = 0x00; // DMA mode; write to fifo HP_FIFO_LEVEL_CHK = (0xc | (0x8 << 10) | (0x4 << 20));



HP_FIFO_OP = 0x02; // reset fifo HP_FIFO_OP = 0x01; // start fifo HP_FIFO_INT_EN = 0x07; // oflow|uflow|threshold

• Start the data transfer (HP_PCMCIA_TX_CTRL) HP_PCMCIA_TX_CTRL = 0x01; // start transfer

• Wait until DMA finishes (interrupt from DMA controller)

• Wait until data transfer finishes (HP_PCMCIA_STATUS) while (HP_PCMCIA_STATUS & 0x1);

• Reset the FIFO controller HP_FIFO_OP = 0x02 ; After that, the Host port is ready for the next DMA trasnfer.



16.5 Handshaking with Host The Atlas™ Host Port can communicate with the external host by two ways: polling and interrupt. Because some registers in the Host Port can be access by both Atlas™ and external host, these registers can be used for handshaking between the Atlas™ Host Port and the external host. The external host can poll the specific register bit of these registers to see if there is any change. Of course user needs to define a clear protocol of how to use these register for handshaking. Besides, Atlas™ Host Port and the external host can interrupt each other. The Atlas™ Host Port can interrupt the host by asserting the HIREQ_B signal (please refer to the Atlas™ Developer’s Maunal). And the host can interrup the Atlas™ in the following ways:

• By writing the HP_CONFIG_INDEX_x register. • By writing the HP_CONFIG_STATUS_x register. • By writing a 1’b1 to the bit7 of AT_PCMCIA_COMMAND register (TX_START). • By writing a 1’b1 to the bit6 of AT_PCMCIA_COMMAND register (EXT_INT).



17 Secure Disk (SD) / Multi-Media Card Interface (MMC)

17.1 Operation Overview Communication between SD interface and SD card is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit. The operation of SD interface is based on the reading and writing of SD interface registers. The SD interface accomplish the command by writing the data in registers, and get the responding and status by reading data from registers.



17.2 Internal Regsiter Programming Normally, the maximum data rate of the SD cards is 25Mbps and the IO clock of AltasTM is beyond 25M. So there are two different clocks in SD interface. The operation frequency of program is IO clock and the reading and writing clock of SD host internal register from address 0x00 to 0x7f is SD clock. If the program wants to write or read the SD host internal registers from address 0x00 to 0x7f by IO, the program need write or read the register first and wait the SDREG_RDY being 0x01. In SD interface, when the program read the SD host internal registers, the SD interface put the SDREG_RDY in the bit 16 of IO data. So user can distinguish the success reading by the bit 16 of IO data.



17.3 I/O Operation The bit 0 of SD_DMA_IO_CTRL specifies the IO or DMA mode of SD interface. The bit 1 of SD_DMA_IO_CTRL specifies the reading or writing status of SD interface. If SD_DMA_IO_CTRL is 0x01, the SD interface is in IO writing mode. Program can write data to SD Card by SD_DATA_BUFFERS. If SD_DMA_IO_CTRL is 0x03, the SD interface is in IO reading mode. Program can read data from SD Card by SD_DATA_BUFFERS.



17.4 DMA Operation If SD_DMA_IO_CTRL is 0x00, the SD interface will be in DMA writing mode. And if SD_DMA_IO_CTRL is 0x02, the SD interface will be in DMA reading mode. The DMA registers and FIFO registers should be set besides the SD_DMA_IO_CTRL register. DMA channel 8 is used for SD. The DMA_CH8_XLEN, DMA_CH8_YLEN are used to decide the number of DMA transfer.The DMA Y-length specifies the number of lines in DMA transfer. The number of the lines in DMA transfer is Y-Length + 1. The maximum number of line can be 2048. To set Y-length to 0 has the effect that doing 1-D DMA. The DMA X-length is in 32-bit D-word boundary. The value specifies the number of D-words transferred in each line. The maximum length is 2047 D-words. The DMA_CH8_CTRL specifies the width, direction and transfer mode of DMA operation. DMA_CH8_ADDR must be the last register to be set among all the DMA configuration registers. Set this register will start the DMA.

// DMA register DMA_CH8_XLEN = count/4; //dword DMA_CH8_YLEN = 0x0; DMA_CH8_CTRL = 0xc; //burst mode, sdram --> fifo, word DMA_CH8_ADDR = 0x10000;

The SD_DMA_IO_LEN specifies the length of data transfer. Because the width of reading and writing data is word in SD interface, the bit 0 of SD_FIFO_CTRL is set to 1. The FIFO will be reset before starting the data transfer operation. So the SD_FIFO_OP should be set 0x2 first and 0x1 next.

// FIFO register SD_DMA_IO_LEN = count/2; //word SD_FIFO_CTRL = 0x1; SD_FIFO_LEVEL_CHK = 0x3; SD_FIFO_OP = 0x2; SD_FIFO_OP = 0x1;

After DMA and FIFO register are set, the bit 0 of SD_DMA_IO_CTRL is cleared for selecting DMA mode. Then the SD interface will read or write data between DMA and FIFO. When the DMA finish the data transfer, the bit 0 of SD_INT_STATUS will be set 1. The program will set the bit 0 of SD_DMA_IO_CTRL for choosing IO mode.



17.5 Initialization The SD interface must be reset when it is used in first time. The reset register of AltasTM is RESET_SR. The corresponding bit of reset bit of SD is bit 21. The SD_CARD_SEL register is set to select corresponding SD card such as 0x1 for selecting card 0. The maximum data rate of the SD cards is 25Mbps and the IO clock of AltasTM is beyond 25M for example 90M. So the SD_CLK_RATE register must be set to provide the different devision of IO clock to work with the SD card. If the program wants to use the interrupt mode, the SD_INT_CNTL and the SD_INTERRUPT_MASK will be set correct value.



17.6 No Data Command/Response Transaction In the basic no data command/response transaction, the following registers and content are used:

• In the CMD register, the command code is written. • In the argument registers, the MSB and LSB arguments are updated. • In the CMD_DAT_CONT, next bits are updated:

o The format of the response is updated (Bits 0 & 1). o The DATA En is set to “0” (Bit 2). o The busy bit is set to “0” (Bit 7). o The initial bit is set to “0” (Bit 8) (If no initialize is required). o The NO_CMD bit is set to “0” (Bit 9)

After the CMD_DAT_CONT register is written, the application is required not to change the set of registers until the status register indicates that the command response has finished and the response is in the response FIFO for the application to read.



17.7 Single Block Operation 17.7.1 Single Block Write In the single block write command, the following registers are updated:

• In the BLOCK_LEN register, the number of bytes per block must be specified. • In the CMD register, the number of the command itself is updated. • In the MSB and LSB arguments registers, the address is updated. • In the CMD_DAT_CONT, next bits are updated:

o The format of response is updated to 01h (Bits 0 & 1). o The DATA EN is set to “1” (Bit 2). o The write read is set to “1” (Bit 3). o The stream block is set to “0” (Bit 4). o The multiple block is set to “0” (Bit 5). o The busy bit is set to “0” (Bit 7). o The initial bit is set to “0” (bit 8) (If no initialize is required). o The WB bit is set as required.

After receiving the response, the application checks the STATUS register to see whether the buffer is empty. If it is, the application writes to the buffer assigned to it and informs the host that the buffer is ready. At this point, the application waits until the SD Memory Card adapter sets the DATA_TRAN_DONE bit status to “1”.After receiving the DATA_TRAN_DONE signal, the application should check the STATUS register to see whether the data transfer has finished successfully or not. If the application wants to address a different card, it can send a select command to that card by sending a basic no data command/response transaction. If the application wants to address the same card, it must first check if the PRG_DONE bit is set to “1” in the STATUS register. By waiting for PRG_DONE, the application ensures that the busy is finished. 17.7.2 Single Block Read To operate the SD Memory Card adapter to perform a single block read, the application must first send the read command itself, such as the basic no data command response transaction, with some modifications:

• In the BLOCK_LEN register, the number of bytes per block must be specified. • In the CMD_DAT_CONT, next bits are updated:

o The format of response is updated to 01h (Bits 0 & 1). o The DATA En is set to “1” (Bit 2). o The write/read bit is set to “0” (Bit 3). o The stream block is set to “0” (Bit 4). o The multiple block is set to “0” (Bit 5). o The busy is set to “0” (Bit 7). o The initial bit is set to “0” (Bit 8) (If no initialize is required). o The WB bit is set as required.

After the application read the response from the response FIFO registers, it must wait for the DATA_TRAN_DONE signal in the status register, and then reads the data transfer FIFO buffer.



17.8 Multiple Block Operation 17.8.1 Multiple Block Write To operate the SD Memory Card adapter to perform a multiple block write, the application must first send the write command itself, such as the basic no data command response transaction, with some modifications:


o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to “1” (Bit 2). o The write/read is set to “1” (Bit 3). o The stream block is set to “0” (Bit 4). o The multiple block is set to “1” (Bit 5). o The busy bit is set to “0” (Bit 7). o The initial bit is set to “0” (Bit 8) (If no initialize is required).

After the CMD_DAT_CONT has been written, the application must wait for the bit END_CMD_RES. At this point, the application reads the response from the response FIFO. The application must wait for the EMPTY_FIFO signal in the status register. Then, data must be written to the data FIFO (256 words, 16 bit each) and the buffer ready is updated. The process of waiting for the EMPTY_FIFO signal, writing the FIFO and buffer ready is turned on is repeated until the last block. At the last block, the application also updates the stop transmission CMD before updating the buffer ready and while writing the buffer ready also writes the last buffer. The application must then wait for the signals DATA_TRAN_DONE.The application sends the stop transmission command as described in the section on the no data command/response transaction with the addition of the bit BUSY_BIT in the CMD_DAT_CONT it is set to “1”. After receiving the response the application waits for the end of the busy signal by waiting for the PROG_DONE signal in the status or sending the send status command to the card and checking the state of the card in the response. 17.8.2 Multiple Block Read To operate the SD Memory Card adapter to perform a multiple block read, the application must first send the read command itself, such as the basic no data command response transaction, with some modifications:


o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to “1” (Bit 2). o The write/read is set to “0” (Bit 3). o The stream block is set to “0” (Bit 4). o The multiple block is set to “1” (Bit 5). o The initial bit is set to “0” (Bit 8) (If no initialize is required).

After the CMD_DAT_CONT has been written, the application must wait for the bit END_CMD_RES. At this point, the application reads the response from the response FIFO. The application must wait for the FULL_FIFO signal in the status register. Then, data must be read from the data FIFO (256 words, 16 bit each). The process of waiting for the FULL_FIFO signal and reading the FIFO is repeated until the last block. Before the last block, the application informs the adapter that the next block is the last block in the BUF_RDY register. After the adapter from the card has received the last block, the adapter stops the clock. After the last data block is received, the application sends the stop transmission command.



17.8.3 Multiple Block Write Using Number Blocks To operate the SD Memory Card adapter to perform a multiple block write, the application must first send the write command itself, such as the basic no data command response transaction, with some modifications:


o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to “1” (Bit 2). o The write/read is set to “1” (Bit 3). o The stream block is set to “0” (Bit 4). o The multiple block is set to “1” (Bit 5). o The busy bit is set to “0” (Bit 7). o The initial bit is set to “0” (Bit 8) (If no initialize is required). o The NOB_ON bit is set to ‘1’ (bit 12).

After the CMD_DAT_CONT has been written, the application does exactly what it specified in the section of Multiple Block Write above, until the last block. At the last block, the application set the Buffer Ready and Last Buffer. The application waits for the end of the busy signal by waiting for the PROG_DONE signal in the status or sending the send status command to the card and checking the state of the card in the response. 17.8.4 Multiple Block Read Using number Blocks To operate the SD Memory Card adapter to perform a multiple block read, the application must first send the read command itself, such as the basic no data command response transaction, with some modifications:


o The format of response is updated to 01h (Bits 0 & 1). o DATA EN is set to “1” (Bit 2). o The write/read is set to “0” (Bit 3). o The stream block is set to “0” (Bit 4). o The multiple block is set to “1” (Bit 5). o The initial bit is set to “0” (Bit 8) (If no initialize is required). o The NOB_ON bit is set to ‘1’ (bit 12).

After the CMD_DAT_CONT has been written, the application must wait for the bit END_CMD_RES. At this point, the application reads the response from the response FIFO. The application must wait for the FULL_FIFO signal in the status register. Then, data must be read from the data FIFO (256 words, 16 bit each). The process of waiting for the FULL_FIFO signal and reading the FIFO is repeated until the last block. Before the last block, the application informs the adapter that the next block is the last block in the BUF_RDY register. After the adapter from the card has received the last block, the adapter stops the clock.



18 Nand Flash Memory Interface

18.1 Operation Overview The Atlas™ Nand flash controller support five types of data transfer: DMA read, DMA write, RISC read data from FIFO, RISC write data to FIFO, RISC directly read data from Nand flash controller’s data register. Normally we only use DMA to transfer data. RISC read/write data from FIFO is only used for debug purpose. When boot from Nand flash, we need two of them: DMA read, RISC directly read data register.

18.2 Initialization Some registers need not to be set before every operation. • WAIT_REG. This register need to be set if the IOCLK changes. Get timing characteristic from SmartMedia/DataFlash specification

tWP: WE# Pulse Width. Normally 25nS tRP: RD# Pulse Width. Normally 30nS tWH: WE# High Hold Time, Normally 15nS tREH: RD# High Hold Time, Normally 15nS tWB: WE# High to Busy. Normally 100nS tRB: Last RE# High to Busy(at sequential read). Normally 100nS IOCLK: MHz

WAIT_REG<3:0> = floor (tRP * IOCLK * 310− ) WAIT_REG<7:4> = floor (tWp * IOCLK * 310− ) WAIT_REG<11:8> = floor (MAX (tWB, tRB) * IOCLK * 310− ) WAIT_REG<12> = floor (MAX (tWH, tREH) * IOCLK * 310− )

• ADDRESS_NUM_REG. This register needs to be set according to the Nand Flash type.

When COMMAND ADDRESS FSM start, the Nand Flash interface first send COMMAND_REG<7:0> to DATAFLASH, then according to the value of this register, it will send LOW_ADDRESS_REG<31:0> and HIGH_ADDRESS_REG<7:0> to Nand Flash • PAGESIZE_REG. This register default value is 528, which is SmartMedia page size. Only

SAMSUNG’s more than 128MB Nand Flash page size is 2112 bytes

• DIRECT_READ. This register is used for NANDBOOT, after hardware reset, the value or this register is 1, and RISC can directly read data from SmartMedia. In normal read/write this register need to be set to 0.

18.3 I/O Operation RISC read/write data from FIFO directly. In this mode, RISC can wait for FIFO_THRESHOLD interrupt or check FIFO_STATUS_REG register before read data. 18.3.1 IO Read



1. Set DMA_IO_CTRL_REG to 5’b00011

2. If you want to use interrupt, then clear interrupt by write 4’b1111 to INT_STATUS_REG. And enable FIFO_THRESHOLD interrupt by setting INT_CTRL_REG to 4’b1000. And set FIFO_CTRL_REG to the number of bytes you want to read every read operation. If you want to use RISC check FIFO_STATUS_REG, then disable interrupt by setting INT_CTRL_REG to 0.

3. Write LOW_ADDRESS_REG and HIGH_ADDRESS_REG according to the address you want to

read.

4. Write Nand Flash read command to COMMAND_REG. This will make the interface to write command and address to Nand Flash.

5. Wait for FIFO_THRESHOLD interrupt or check FIFO_STATUS_REG register, and then read

FIFO_DATA_REG register. 6. Repeat step 5.

18.3.2 IO Write


2. If you want to use interrupt, then clear interrupt by write 4’b1111 to INT_STATUS_REG. And enable FIFO_THRESHOLD interrupt by setting INT_CTRL_REG to 4’b1000. And set FIFO_CTRL_REG to the number of bytes you want to read every read operation. If you want to use RISC check FIFO_STATUS_REG, then disable interrupt by setting INT_CTRL_REG to 0.

3. Write LOW_ADDRESS_REG and HIGH_ADDRESS_REG according to the address you want to

read.

4. Write Nand Flash sequential data input command to COMMAND_REG. This will make the interface to write command and address to Nand Flash.

5. Repeat this step until you have write all datas, or you have write one page data(currently one

page =528 bytes)


7. Clear interrupt by write 4’b1111 to INT_STATUS_REG. Set INT_CTRL_REG to 4’b0010 to enable COMMAND ADREESS DONE interrupt.

8. Write Nand Flash page program command to COMMAND_REG register

9. Wait for COMMAND ADDRESS DONE interrupt.

18.4 DMA Operation

1. Set DMA_IO_CTRL_REG to 5’b00110 for DMA read or 5’b00100 for DMA write.

2. Write LOW_ADDRESS_REG and HIGH_ADDRESS_REG according to the address you want to read.

3. Write DMA_IO_LEN_REG register and FIFO_LEVEL_CHK_REG register.



4. Clear interrupt by write 4’b1111 to INT_STATUS_REG. Set INT_CTRL_REG to 4’b0100 to enable DMA DONE interrupt.

5. Write Nand Flash read command (or sequential data input command) to COMMAND_REG

register. This will make the Nand Flash interface go into DMA transfer.

6. Wait for DMA DONE interrupt.

7. If this is DMA write operation, the following step is needed.

8. Clear interrupt by write 4’b1111 to INT_STATUS_REG. Set INT_CTRL_REG to 4’b0010 to enable COMMAND ADREESS DONE interrupt.

9. Write Nand Flash page program command to COMMAND_REG register

10. Wait for COMMAND ADDRESS DONE interrupt.

18.5 DMA read example DMA_CH_INT = 0x010; //clear DMA controller’s interrupt SMDF_DMA_IO_CTRL_REG =0x4; SMDF_ADD_NUM_REG = 3; //assume the Nand Flash is less than 64MBytes SMDF_LOW_ADDRESS_REG = (address>>1) & 0xFFFFFF00 + address & 0xFF; //delete address bit 9 SMDF_FIFO_LEVEL_CHK_REG = 0xC02004; //set FIFO check level SMDF_FIFO_OP_REG = 1; //start FIFO SMDF_DMA_IO_LEN_REG = 512; //read 512 bytes SMDF_COMMAND_REG = 0; DMA_CH4_CTRL = 0x8; //DMA burst read DMA_CH4_XLEN = 512>>2; DMA_CH4_ADDR = ((DWORD) ram_addr)>>2; While ((DMA_CH_INT & 0x010) ==0); //wait DMA controller interrupt SMDF_FIFO_OP_REG =2; //stop FIFO

18.6 DMA write example SMDF_INT_STATUS_REG = 0x4; //clear interrupt SMDF_INT_CTRL_REG = 0x4; //enable interrupt SMDF_DMA_IO_CTRL_REG =; SMDF_ADD_NUM_REG = 3; //assume the Nand Flash is less than 64MBytes SMDF_LOW_ADDRESS_REG = (address>>1) & 0xFFFFFF00 + address & 0xFF; //delete address bit 9 SMDF_FIFO_LEVEL_CHK_REG = 0x40200C; //set FIFO check level SMDF_FIFO_OP_REG = 1; //start FIFO SMDF_DMA_IO_LEN_REG = 528; //write 528 bytes SMDF_COMMAND_REG = 0x80; DMA_CH4_CTRL = 0xC; //DMA burst write



DMA_CH4_XLEN = 528>>2; DMA_CH4_ADDR = ((DWORD) ram_addr)>>2; While ((SMDF_INT_STATUS_REG &0x4)==0); //wait Nand Flash interface DMA interrupt SMDF_FIFO_OP_REG =2; //stop FIFO SMDF_INT_STATUS_REG = 2; //clear interrupt SMDF_INT_CTRL_REG = 2; //enable interrupt SMDF_DMA_IO_CTRL_REG = 0x10; //set to NO_READWRITE SMDF_ADD_NUM_REG = 0; //did not need address when program to Nand Flash SMDF_COMMAND_REG = 0x10; While ((SMDF_INT_STATUS_REG &0x2)==0); //wait Nand Flash interface COMMAND ADDRESS interrupt

18.7 NAND Boot-loader To enable a Nand Flash to boot, software needs the following steps,

1) Write a boot program, this is the same as boot from ROM. Generate “init.bin” file 2) Write a program to read “init.bin”, and then write to the first block of Nand Flash.

For Nand Flash, continue read in one page, read speed is 50 ns/byte, otherwise it will cost 10 us for one read, so it is better that software continue read from Nand Flash, this will improve boot speed about 200 times. The default setting for WAIT_REG register is 0x200, this setting is suitable for 30MHz IOCLK. Change this register for the real IOCLK. When boot, Nand Flash interface always sent four bytes addresses to Nand Flash, regardless what size the Nand Flash card is. Software can write ADD_NUM_REG register to charge this case, but this step will have no influence on reading performance.

Following is structure diagram of Nand boot.



ARM initprocess

Flash Controller'sglobal register init

process

ReadDevice ID

select firstNand Flash chip

This isvalid ID?

YES

NO

select nextNand Flash chip

search file"NK.BIN"

NO

find?

read "NK.BIN"and parse it

YES

lauch to WinCEstartup code

Figure 12. NAND Boot Flow Diagram

18.7.1 ARM Init Process When RISC boots up, it shadows Nand flash memory space to 0, read code directly from Nand flash. In this stage, RISC performs all the initialization required before branching to the main C application code.



It defines the ENTRY point, initializes the Stack Pointers for each mode, copies RO code and RW data from FLASH to RAM and zero-initializes the ZI data areas used by the C code, and jump to C_Entry.

18.7.2 Flash Controller’s global register init process

In this stage,

a) Enables the clock of Flash controller and DMA controller PWR_CLK_EN = 0x6;

b) Commit share hardware resources to Nand flash controller PWR_PIN_RELEASE = 1; ROM_NAND_FIFO_SELECT = 1;

RSC_PIN_MUX = SMDF_NAND_CS_0 | SMDF_NAND_CS_1 |SMDF_NAND_CS_2 | SMDF_NAND_CS_3 | SMDF_CKE_EN | SMDF_CSB_EN;

c) Enable DMA interrupt INT_RISC_MASK = INT_MASK_DMA_CTRL; INT_RISC_LEVEL = 0; d) Change Flash controller from boot read mode to normal read mode. In boot mode, ARM can

only directly read data from the controller’s register, in normal mode, ARM/DMA controller can only read data from FIFO SMDF_DIRECT_READ_REG = 0;

e) Disable Nand flash’s all interrupts SMDF_INT_CTRL_REG = 0;

f) Set Nand flash’s FIFO level check register. This is set for DMA burst read. SMDF_FIFO_LEVEL_CHK_REG = 0xC02004;

18.7.3 Read Device ID

In this stage, read device ID, compare it with the device ID table. If this is a valid device ID Set Nand flash controller’s register: ADDRESS_NUM_REG according to the flash type. More than 32M-byte flash need set to 4, less than 32M-byte need set to 3.

18.7.4 Search File “NK.BIN” Search from the last block to check whether it is a good block, if it is a good block, the “NK.BIN” is start from this block, else read next block. If reading 5 blocks and not find good block, there is no “NK.BIN” in this Nand Flash chip.

18.7.5 Read “NK.BIN” and Parse It There is 2 bytes in the page spare area to indicate the next block location, according this information read all the “NK.BIN” to SDRAM, then parse it. For detail Nand Boot specifacation, please read Nand Boot software document.



18.8 Special Notes • LOW_ADDRESS_REG and HIGH_ADDRESS_REG In SmartMedia specification, the address<8> is absence. So software driver needs to delete bit8 to form a new address. For example, original address is data<31:0>, software driver need write data<31:9> and data<7:0> to LOW_ADDRESS_REG. HIGH_ADDRESS_REG is needed only in SAMSUNG Nand Flash more than 256MB.



19 LCD Controller Interface

19.1 Operation Overview The Atlas™ graphic LCD controller is used for applications like: GPS Navigation/Telematics systems, PDAs and Smartphones. The Atlas™ LCD Controller supports two types of displays: • Active Display Mode Supports up to 65536 colors (16-bit). • Passive Monochrome Display Mode Supports up to 16 gray-scale levels. Depending on the type of panel used, the LCD Controller can be programmed to use 4-, 8-, or 16-pixel data output pins. In passive monochrome mode, the LCD Controller can drive S-STN or D-STN displays. The AC Bias pin functions as a switch signal for some passive displays to convert the liquid crystal drive waveform into AC. In active mode, the LCD Controller can drive TFT displays. The LCD's line clock pin functions as a horizontal sync (HSYNC) signal, the frame clock pin functions as a vertical sync (VSYNC) signal, and the AC Bias pin functions as an output enable (OE) signal. In active color mode, the LCD Controller can also be configured to provide RGB to YCrCb hardware conversion and interfaces to some NTSC/PAL video encoders to drive video monitors.

19.2 Initialization The LCD controller can be reset by four sources of resets. Please refer to Section 5.7 “Reset Controller Overview” for details. After hardware reset, the LCD controller is disabled, and the output pins are configured as GPIO pins or resource sharing pins. And after any type of reset, all LCD controller registers are reset to the default values shown in the LCD register definitions. If the LCD controller is being enabled for the first time after hardware reset, following registers must be programmed to enable the LCD controller: • Configure power manager clock enable register (PWR_CLK_EN) to enable LCD controller system

clock. See Developer’s Manual Section 5.6 “Power Manager” for details. • Configure resource sharing pin multiplex register (RSC_PIN_MUX) for LCD controller functionality.

See Developer’s Manual Section 5.8 “Resource Sharing Controller” for details. • Reset the LCD controller (RESET_SR), and set the relative interrupt registers for LCD controller

(such as INT_RISC_MASK/ INT_DSP_MASK and INT_RISC_LEVEL, see Developer’s Manual Section 5.3 “Interrupt Controller” for details, and LCD_INT_MASK, and so on), if needed

• Configure Timing Control Register (LCD_TIMCTRL) to set the LCD controller as master mode or slave mode, that is, set L_PCLK, L_LCLK or L_FCLK as outputs or inputs.

• Configure power manager pin release register (PWR_PIN_RELEASE) to release pins of peripherals (include LCD pins).

• Write color palette or grey palette (FRC sequence table) to the on-chip RAM of LCD controller for color or grey displays, if needed

• Program all of the LCD registers required except the DMA start registers (LCD_SCN_CUR_Y/ LCD_OSD_CUR_Y and LCD_SCN_ADDR/LCD_OSD_ADDR) and the Frame Valid bit (bit0 of DISPLAYMODE register), such as the active region registers, screen control registers, sync signal generation registers (only for master sync mode), and so on.

• Write 1 to DMA start registers (LCD_SCN_CUR_Y/LCD_OSD_CUR_Y and LCD_SCN_ADDR/ LCD_OSD_ADDR) to start the DMA



• Write 1 to the Frame Valid bit to output the valid image frame to data pins As L_PCLK, L_LCLK and L_FCLK can be configured as inputs or outputs, and after reset these signals are defaulted as outputs when LCD controller is enabled, the LCD_TIMCTRL register should be configured correctly before releasing pins of peripherals (PWR_PIN_RELEASE register) to avoid pin conflicts with external signals. When there is no pin conflict, the LCD_TIMCTRL register can also be configured after PWR_PIN_RELEASE register’s configuration. The Frame Valid bit control the internal counters for internal valid signals, and can not be asserted too earlier before the DMA starts (otherwise, the FIFOs will underflow). So for safety, you may assert the Frame Valid bit after the DMA starts. For LCD controller interrupt, there are two levels of interrupts (one is in the level of Atlas™-1Interrupt Controller, the other is in the level of LCD controller). To enable the LCD controller interrupts, both the two levels of interrupts must be enabled. Following is a typical 8-bit/pixel master mode configuration example for the 240 x 320 TFT LCD panel.

#define PWRCLK_LCD_EN 0x00000008 #define INT_MASK_LCD_CTRL 0x01000000 #define RESET_SR_LCD_RST 0x00000020 PWR_CLK_EN |= PWRCLK_LCD_EN; /* Enable LCD controller system clock */ RSC_PIN_MUX |= 0x1; /* Enable LDD<15:8> as the LCD data pins */ PWR_PIN_RELEASE = 0x1; /* Release the peripheral pins including LCD

pins */ /* Initiate interrupt controller for LCD controller */ INT_RISC_MASK |= INT_MASK_LCD_CTRL; /* Enable LCD interrupt in the

level of Interrupt Controller */ /* LCD controller software reset */ RESET_SR |= RESET_SR_LCD_RST; /* Reset declare */ RESET_SR &= ~( RESET_SR_LCD_RST); /* Reset clear */ LCD_OSC_RATIO = 0x1006; /* Pixel clock is 1/7 sysclk. If system clock

is 42MHz, pixel clock is 6MHz */ Write_palette ( ); /* Fill in 256 color palette for 8-bit per pixel

mode */ /* SYNC_GEN (LCD_HSYNC_PERIOD, LCD_HSYNC_WIDTH, LCD_VSYNC_PERIOD, LCD_VSYNC_WIDTH) */ /* HSYNC period is 290, HSYNC pulse width is 9 pixels; VSYNC period is

332, VSYNC pulse width is 2 lines */ SYNC_GEN (288, 8, 332, 0x802); /* SCN_REGION (LCD_SCN_HSTART, LCD_SCN_VSTART, LCD_SCN_HEND,

LCD_SCN_VEND) */ /* Set to display a 240x320 image, 267-28 = 239, 328-8 = 320 */ SCN_REGION (28, 8, 267, 328); LCD_BLANK = 0x01000000; /* Set blank value to all zero */ LCD_TIMCTRL = 0x52; /* Master mode Syncs and Pixclk */ LCD_DISPLAYMODE = 0x212; /* little endian, 8-bit per pixel, 5:6:5

output, Frame Valid =0 */



/* Configure the FIFO High, Middle, Low Threshold */ LCD_SCNFIFO = 0x183858; /* DMA_SETUP (LCD_SCN_XSIZE, LCD_SCN_YSIZE, LCD_SCN_SKIP, LCD_SCNFIFO_SUPPRESS, LCD_SCNBASE) */ /* Line size is 15 4-DWORD bursts = 15*4*4 = 240 pixels (for 8bit/pixel

mode), 320 lines, the DMA base address is 0x800000, continuous screen DMA */ DMA_SETUP (14, 319, 0x10, 0x0, 0x88000000); /* Start screen DMA channel */ LCD_SCN_CUR_Y = 0x1; LCD_SCN_ADDR = 0x1; LCD_DISPLAYMODE |= 0x1; /* Frame Valid =1 */

19.3 DMA Operation The LCD controller loads picture data of the frame buffer into the FIFOs on a demand basis using LCD's own DMA controller. It has two DMA channels: one is for screen/main path channel, and the other is for OSD/second path channel. It supports two types of DMA: single DMA and continuous DMA. Continuous DMA will automatically start next DMA after the first DMA ends. Thus, after the first DMA starts, the LCD controller will continuously load frame data without software controls. Continuous DMA is used to support for many general LCD displays. Single DMA can be used to load frame data only when the frame picture is updated (for example, when Atlas™-1 is connected with some Hitachi LCD modules such as TX06D12VM1CAA). As fewer data are loaded, it can save the bus bandwidth and the power a lot. To start a DMA transfer in Atlas™-1 LCD controller, the sequence is: • Enable DMA interrupt for single DMA (for continuous DMA, you may not enable the DMA interrupt) • Initialize the FIFO control registers, you may change the default value • Configure DMA control registers (LCD_SCN_XSIZE, LCD_SCN_YSIZE, LCD_SCN_SKIP,

LCD_SCNFIFO_SUPPRESS, and LCD_SCNBASE for screen/main channel, and the similar registers for OSD/second channel)

• Configure the two registers as 1 (LCD_SCN_CUR_Y/LCD_OSD_CUR_Y and LCD_SCN_ADDR/ LCD_OSD_ADDR) to start the DMA (screen/main or OSD/second)

For single DMA, wait until DMA finishes (that is, wait for DMA interrupt from DMA controller), and after that, the LCD controller is ready for the next DMA transfer. Following is an example for single screen DMA configuration.

#define INT_MASK_LCD_CTRL 0x01000000 #define SCN_DMA_MASK 0x02

INT_RISC_MASK |= INT_MASK_LCD_CTRL; /* Enable LCD interrupt in the

level of Interrupt Controller */ LCD_INT_MASK |= SCN_DMA_MASK; /* Enable screen DMA interrupt in the level of LCD Controller */

/* Configure the FIFO High, Middle, Low Threshold, and select the other method of request generation */

LCD_SCNFIFO = 0x1183858;



/* Screen DMA channel set up */ LCD_SCN_XSIZE = 29; /* Line size is 30 4-DWORD bursts, for 16bit/pixel

mode, it’s 240 (30x4x2) pixels. */ LCD_SCN_YSIZE = 119; /* This DMA includes 120 Lines */ LCD_SCN_SKIP = 0x10; /* The DMA address generator skips 16 Bytes

between lines of DMA, as the DMA unit supported is a burst, therefore it means that the beginning of the second line is continuous with the ending of the first line. */

LCD_SCNFIFO_SUPPRESS = 0x0; /* If there aren’t any DWORDs to be suppressed, set this register as 0x0 */

LCD_SCNBASE = 0x8000000; /* Single DMA, the DMA base address is 0x800000, pixel offset is 0. */

/* Start screen DMA channel */ LCD_SCN_CUR_Y = 0x1; LCD_SCN_ADDR = 0x1;

This DMA channel will transfer 120 x 30 x 4 DWORDs data every one time. Therefore, different pixel depths and different resolutions will lead to different DMA configurations. Generally, for a DMA transfer of M pixels/Line x N Lines data block with the pixel depth of D bits/pixel, XSIZE and YSIZE are decided by following equations:

XSIZE = (M x D)/(4 x 32) – 1 YSIZE = N – 1

Obviously, XSIZE and YSIZE must be interger. And if the XSIZE and the YSIZE are non-interger when computed by these two equations, multiple lines can be combined as one DMA line to make the XSIZE as interger. In addition, when pixel offset is non-zero, XSIZE will be increased by 1, and the SUPPRESS register should also be configured. Please refer to FIFO write suppress registers in Developer’s Manual Section 9.5.4 for details.

19.4 Configuration Comparison for Different Mode In general, even for different LCD displays or different modes, there are many common registers need to configure. Following is a list for that.

• Write color or grey palette to the on-chip RAM of LCD controller for color or monochrome displays, if needed

• Set the Screen Active Region Registers of the display • When in master pixclk mode, set the proper divider ratio (LCD_OSC_RATIO), and in master

sync mode, set Sync Signal Generation Registers • Set timing control register (LCD_TIMCTRL), display mode/format register

(LCD_DISPLAYMODE), and some other Screen Control Registers according to different display modes

• Set FIFO Control Registers and DMA Registers For overlay mode, OSD active region registers, OSD palette registers and the OSD channel DMA registers should also be configured. For YUV output mode, YUV output registers should also be configured. For 2bit or 4bit per pixel monochrome passive mode, as frame rate control is used to generate different grey scales, FRC registers should be configured. And the grey palette should also be configured as dithering sequence table for FRC. For passive mode, generally the alternate HSYNC and the alternate VSYNC should be selected for correct display, and the LCD_FMOD should also be configured and adjusted to get better quality for many monochrome STN displays. For 16bit per pixel color mode, the image data bypass the color palette, and directly output to LCD pins, thus the palette needn’t be configured.



The differences between master mode and slave mode are shown in the follwing table:

Table 12. Differences between Master and Slave Mode Registers Master Mode Slave Mode

LCD_TIMCTRL Register

PCLK_IO = 1 (default) HSYNC_IO = 1 (default) VSYNC_IO = 1 (default)

PCLK_IO = 0 HSYNC_IO = 0 VSYNC_IO = 0

LCD_OSC_RATIO Register

For master pixel clock, this register should be configured to obtain the pixel clock from the system clock.

For slave pixel clock, this register needs not to be configured.

Sync Signal generation Registers

Should be configured according to the LCD display requirements.

Need not to be configured.

Note that the pixel clock and the sync signals can be configured as master or slave mode independently.

19.5 Palette The palette in the LCD controller is a 256 x 18bit RAM. And this palette can be used as color palette or grey palette of dithering sequence for FRC. 19.5.1 Color Palette When the image data are 4bit or 8bit per pixel, the 4bit or 8bit data are directly as the index of palette entries. Basically, this color palette should be matched with the one that is provided for the image data. For example, if the image data is got from WINDOWS, then the color palette in the LCD controller should be matched with the palette that WINDOWS provides. For the 4bit/pixel data, the bottom 16 entries are used, and for the 8bit/pixel data, all the 256 entries are used. 19.5.2 Grey Palette of FRC Sequence The grey palette is a 16 x 32bit FRC sequence table that is located in the 256 x 18bit RAM (256 entries). Thus the FRC can support up to 16 grey scales. For 4bit/pixel mode, bits <15:0> of entry 0 and entry 16 combine as 32 bits for one gray color, and bits <15:0> of entry 1 and entry 17 as another gray color, and so on. And for 2bit/pixel mode, only entry 0~3 and entry 16~19 are used. The FRC is actually a time-based dithering, which is to turn each pixel on or off in a certain period of time to create the perception of different intensities. For every pixel, the sequence repeats itself every 32 frames. Higher 0 to 1 transition frequency within 32 frames will result in better picture quality. Following is a FRC sequence table recommended.

Table 13. FRC Sequence Table Example Index Entry (16 + Index) Entry (Index) Frequency Intensity 0000 0000,0000,0000,0000 0000,0000,0000,0000 0/32 0/32 0001 0000,0001,0000,0001 0000,0001,0000,0001 4/32 4/32 0010 0000,1000,0010,0001 0000,1000,0010,0001 6/32 6/32 0011 0001,0001,0001,0001 0001,0001,0001,0001 8/32 8/32 0100 0001,0010,0100,1001 0001,0010,0100,1001 10/32 10/32 0101 0010,0101,0010,0101 0010,0101,0010,0101 12/32 12/32 0110 0010,1001,0100,1010 0101,0010,1001,0101 13/32 13/32 0111 0010,1010,0101,0101 0010,1010,0101,0101 14/32 14/32 1000 0010,1010,1010,1010 0101,0101,0101,0101 15/32 15/32



1001 0101,0101,0101,0101 0101,0101,0101,0101 16/32 16/32 1010 0101,0101,0101,0101 1010,1010,1010,1011 15/32 17/32 1011 0101,0101,1010,1011 0101,0101,1010,1011 14/32 18/32 1100 0101,1011,0101,1011 0101,1011,0101,1011 12/32 20/32 1101 0110,1101,1011,0111 0110,1101,1011,0111 10/32 22/32 1110 0111,0111,0111,0111 0111,0111,0111,0111 8/32 24/32 1111 1111,1111,1111,1111 1111,1111,1111,1111 0/32 32/32

19.6 Special Register Configuration 19.6.1 Pixel Clock Divider The LCD controller provides a clock divider for pixel clock. The divide ratio is equal to DIV_RATIO+1. Pixel clock can be obtained from the system clock divided by this ratio:

PixelClock = SystemClock/(DIV_RATIO+1) The system clock is the same as the RISC clock with programmable frequency. The valid range of DIV_RATIO value is 1~1023 (0 is illegal), thus the valid range of divide ratio is 2~1024. When the divide ratio is odd (that is, DIV_RATIO is even), HALF_DUTY bit can be used to control the divided clock as half duty cycle. When HALF_DUTY = 0 (non-half duty cycle), the pulse width difference between the high pulse and the low pulse is one system clock period. And HALF_DUTY bit has no effect when the divide ratio is even (that is, DIV_RATIO is odd). The pixel clock frequency should be adjusted to satisfy the required frame refresh rate. The refresh rate depends on many factors such as the HSYNC period, the VSYNC period, the pixel clock frequency, and the different modes (single or dual panel modes, monochrome or color mode). Different display manufacturers require different frame refresh rate depending on the physical characteristics of the display. 19.6.2 FIFO Request Watermark Control There are two FIFOs (Screen FIFO and OSD FIFO) for temporarily storing the image data loaded from memory in the LCD controller. Two methods of DMA requests generation are supported. The first or normal method is better used in real time environment as this method will generate DMA requests scatteredly, and every request will be deasserted after a few bursts are received. While the second method (selected when REQ_SEL=1) will generate DMA requests more centralized, and every request will be deaserted after more bursts are obtained. As the switching among different memory access masters will waste some memory bus bandwidth, centralized request method will save the bandwidth than the normal method. In addition, as there are some delays between request generation and data reception in memory controller, margins should be given to avoid FIFO underflow or overflow when set the high request watermark or the low request watermark. Don’t set the high request watermark far below 0x10, and the low request watermark far beyond 0x70. Please also refer to the Developer’s Manual Section 9.5.4 “FIFO control registers” for details.

19.7 Power Sequence / Back Light Control for LCD Displays Many LCD panels need proper power sequence for normal display. In Atlas™-1, we can use some GPIOs or external logic to implement the power sequence. Generally, if two GPIOs are required (named as ENV1 and ENV2), in panel power-up sequence, ENV1 is asserted first, and ENV2 is asserted last, while in panel power-down sequence, ENV2 is de-asserted first, and ENV1 is de-asserted last. For more details, please refer to the actual LCD panel datasheet. And back light control is also needed for almost all LCD displays, GPIO or external logic can also be used for the back light control signal.



20 Revision History

REVISION DATE DESCRIPTION AUTHOR 0.1 3/27/03 Prepare a bare-bone of the programming

guide Hongyu Zhang

0.2 4/8/03 Added detail for Clocks & Power Manager, Camera, SD, and USB

Hongyu Zhang, Yu Li, Jinfeng Zhan, and Xianshi Cui

0.3 4/8/03 Added details for LCD controller Hongyu Zhang and Xiaoyi Qing

0.4 4/9/03 Added details for RSC, DMA controller, PCMCIA, Extension Port, USP, CODEC, Host Port, and LCD controller

Hongyu Zhang, Jun Mo, Lianxue Xiong, Peng Yong, and Xiaoyi Qin

0.5 4/10/03 Added details for RISC Interface, DSP Interface, Memory Interface, and GPIO

Hongyu Zhang, Jun Mo and Qingyi Sheng

0.6 4/15/03 Added more details for LCD controller and NAND Flash controller

Hongyu Zhang, Xiaoyi Qin, and Tiefeng Liu

Atlas Programming Guide Preli

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