ATG for SSFs in Combinatorial Circuitszebpe83/teaching/test/lec3.pdfATG for SSFs in Combinatorial...

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ATG for SSFs in Combinatorial Circuits

Traian Pop Sorin [email protected] [email protected]

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Outline

eneration

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ATG for SSFs in Combinatorial CircuitsTraian Pop, Sorin Manolache

Introduction

Deterministic Test Generation

❚ Fault-Oriented ATG

❚ Fault Independent ATG

Random Test Generation

❚ Combined Deterministic and Random Test G

ATG Systems

Conclusions

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Introduction

Tes

Ge


ting

❚ off-line

❚ edge-pin

❚ stored-pattern

❚ full comparison of the output results

neral problems for TG:

❚ the cost of generating the test

❚ the quality of the generated test

❚ the cost of applying the test

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ic Test Generation

Tests(Test stimuli + Correct response)

dataDiagnostic

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Determinist

manual / automatic

fault-oriented / fault-independent

Circuitmodel

Faultuniverse

ATG

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Fault-Oriented ATG

by a fault model

imarytputs

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Pro


targeted at certain fault within a fault universe given

blems:❚ fault activation

❚ error propagation

f s-a-v

Primaryinputs

Prou

N

x

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iented ATG (cont’d)

the value of a gate are reached)

1

0

1

D

D

0/0

0/1

1/0

1/1

v/v f

err1

err1

non-controlling value

Fauout

Err

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Fault-Or

lt activ ation: line-justification (recursively justifyingput by values of the gate inputs until primary inputs

or pr opagation:

composite logic values

reduced to a set of line-justification problems

01

x11

0x

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D1 D

j

e = 1m = Do = 1

l = 0 p = D

c = 1j = 0 k = 0

o = 0

a = 1 b = 1

c = 0 k = 0

Initial implications

To justify n = 1

Contradiction

Implications

To justify n = 1

To justify o = 1

g = Df = 1n = 1

d = 1

Fan

Cir

.


Fault-Orout-free circuits:

cuits with fanout:

ab

cde

11

0x0

g

f s-a-0D0

h

i

x

i = 1

h = 1

o = 1

Decisions

ab

cd

efg

s-a-1x

n

m

l

k

ji

o p

h

..

.

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LURE

SS

Sobe

en


Fault-Or

lve()ginif( Imply_and_check() = FAILURE) then return FAIif (error at PO and all lines are justified)

then return SUCCESSif (error can’t be propagated to a PO)

then return FAILUREselect an unsolved problemrepeat

beginselect one untried way to solve itif (Solve() = SUCCESS) then return SUCCE

enduntil all ways to solve it have been triedreturn FAILURE

d

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01x1

xD

D-fro■ u

■ b

J-fr o■ k

Minim■ m

■ g

■ re

■ e


Fault-Orntier:

sed during error propagation process (D-drive)

ecomes void if no error can be propagated to a PO

ntier:eeps track of unjustified lines

izing the number of incorrect decisions:aximum implications principle

lobal implications

versing incorrect decisions

rror-propagation look-ahead

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) = FAILURE) then return FAILUREen beginid) then return FAILURE

an untried gate (G) from D-frontiertrolling value of Gc to every input of G with value x() = SUCCESS) then return SUCCESS

om D-frontier have been tried

en return SUCCESSJ-frontier

of G

put (j) of G with value x, assign c to j SUCCESS) then return SUCCESS

re specified

Alg

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Fault-Ororithms:

the D algorithm

the 9-V algorithm

single-path sensitization

PODEM

FAN

etc.

D-alg()begin

if( Imply_and_check(if (error not at PO) th

if(D-frontier = vorepeat

beginselect c = conassignif (D-alg

enduntil all gates frreturn FAILURE

endif (J-frontier = void) thselect a gate (G) fromc = controlling value repeat

beginselect an inif (Solve() =

enduntil all inputs of G areturn FAILURE

end

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o a value

error from a line to a PO

1

Pri■

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Me■

■

Co■

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Fault-Ornciples used for decisions:attack the most difficult problem first

try the easiest solution first

asures:controllability: the relative difficulty of setting a line t

observability: the relative difficulty of propagating an

st functions:distance-based functions

recursive cost functions

fanout-based cost functions

C0 l( ) min C0 i( ){ } f l –+=C1 l( ) C1 i( ){ }∑ f l 1–+=

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lt-Independent ATG

f SSFs without targeting

critical values on the gate inputs

mplete specification)

Goind

Cri

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■

! cr


Fau

al: to produce a set of tests that detect a large set oividual faults

tical-path TG algorithm:

select a PO and assign it a critical value

recursively justify any critical value on a gate output by

itical values are used instead of primitive values (co

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ndent ATG (cont’d)

p to detect SSFs

rting from already existing ones

ctable faults

Cri■

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Fau■

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Fault-Indepe

tical-path TG for circuits with reconvergent fanout:conflicts

self-masking

multiple-path sensitization

overlap among PO cones

lt-oriented TG vs. Fault-independent TG:fault-oriented TG needs an additional simulation ste

using critical-path TG, new tests can be generated sta

fault-independent algorithms cannot identify undete

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m Test Generation

etect as many faults as

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pos


Rando

do not target a particular fault

random test vectors are applied and one hopes to d

sible

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Comparison

need for test vector stor-

han deterministically gen-

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a

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e


advantages:

❚ low test generation cost

❚ test vectors usually generated on-the-fly (no

ge)

disadvantages:

❚ long test sequence (approx. 10 times longer t

rated tests)

❚ high test application cost

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Quality Measures

ssible faults after applying N

bility to detect fault f after

e most difficult to detect

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ran

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app

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fau


test quality – t N – the probability to detect all po

dom tests

N-step detection probability of f – d fN – the proba

lying N random tests

detection quality – d N – the probability to detect th

lt after applying N random tests

dN = min f dfN

tN < dN

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Test Length (1)

ce should be in order to

probability c, then they

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ach

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will


usually, one is interested in how long a test sequen

ieve a detection quality (test quality) of c

simulation too expensive

if N tests detect the most difficult to detect fault with

detect another fault with a probability ≥ c

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Test Length (2)

vectors

f

ty among the SSFs in the

mber of faults with detection

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dN ≥ c, N = ?

df1 = |Tf| / 2

n, for uniformly distributed input test

Tf – the set of test vectors that detect the fault

dmin = min f df1, the lowest detection probabili

circuit

1 – (1 – dmin )N ≥ c

N ≥ ceil(ln(1 – c) / ln(1 – d min ))

tN ≥ c, N = ?

N ≥ ceil((ln(1 – c) – ln(k)) / ln(1 – d min )), k – nuprobability d min ≤ d ≤ 2dmin

dmin has to be determined

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dmin

f G being 1

)cuits, otherwise expo-

f fixed probabilities ⇒ lin-

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nen

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ear


dmin ≥ 1 / 2n ⇒ exhaustive testing

the probability to detect l s-a-0 = the probability o

there may be several paths to propagate the error

dmin ≥ P(Gk = 1) (max?P(l = 1) is computed in linear time for fanout-free cir

tial

probability intervals and cuts can be used instead o

time

1l

1 0

G

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Difficult Faults

e a lower bound, d L

with d f ≤ dL, the difficult

t or fanout branch)

e difficult fault becomes

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fau

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eas


sometimes N max is bounded (fixed) (testing time)

having a desired detection quality c, one can deduc

then the circuit has to be checked if there are faults

lts

among checkpoint faults (checkpoint = primary inpu

if found, then modify the circuit in such a way that th

ier to detect (design for testability)

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uted Test Vectors

optimization goals (cov-

s, gathers statistical data

n the pdf of future test

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era

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abo

vec


Non-Uniformly Distrib

turned out to be better for some circuits for various

ge, testing cost, cost of DFT modifications)

research for computing the pdf of the test vectors

adaptive RTG , monitors the test generation proces

ut the most successful test vectors and adjusts the

tors

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inistic/Random TG

m Testing)

10

enerated tests will have A = 1

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Combined Determ

RAPS (Random Path Sensitization)

SMART (Sensitizing Method for Algorithmic Rando

0

0x

x1

x 1

half of g

A

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ATG Systems

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requirements:

❚ fault coverage ↑

❚ test generation cost ↓

❚ test set size ↓

should it collapse faults?

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Systems Structure

ling? */ is important */

PI */

rep

unt

rep

unt


ATG

eatGenerate_test(t);fault simulate tv = value(t)if acceptable(v) then add t to the testil endphase1();

/* what about test schedu/* redundancy elimination

eatselect a new target fault f /* better one close to the try to generate a new test t for fif successful

add f to the testfault simulate fdiscard the faults detected by f

fiil endphase2();

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est Set Compaction

nal faults are detected

nal fault to be tested

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T

static compaction

01x 011 0100x10x0 0x0 001x01 x01

dynamic compaction

❚ try to set the unspecified PIs such that additio

❚ biggest problem is the selection of the additio

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Other TG Methods

the simultaneous ena-

e complicated, derived

re tested before (design

me with its gate level

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blin

■

fr

fo

m


algebraic – impractical

extensions for tristate logic – problem: how to avoid

g of multiple bus drivers

TG for module-level circuits

❚ modules assumed to be fault free

❚ propagation and justification procedures mor

om the module’s function

❚ if the modules are not fault free, either they a

r testability) or after by replacing one module at a ti

odel

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