ATA6562/63 High-Speed CAN Transceiver with Standby...

ATA6562/3High-Speed CAN Transceiver with Standby Mode

Features• Fully ISO 11898-2, ISO 11898-2: 2016 and

SAE J2962-2 Compliant• CAN FD Ready• Communication Speed up to 5 Mbps• Low Electromagnetic Emission (EME) and High

Electromagnetic Immunity (EMI)• Differential Receiver with Wide Common Mode

Range• ATA6562: Silent Mode• Remote Wake-Up Capability via CAN Bus -

Wake-Up on Pattern (WUP), as Specified in ISO 11898-2: 2016, 3.8 µs Activity Filter Time

• Functional Behavior Predictable under All Supply Conditions

• Transceiver Disengages from the Bus When Not Powered Up

• RXD Recessive Clamping Detection• High Electrostatic Discharge (ESD) Handling

Capability on the Bus Pins• Bus Pins Protected Against Transients in

Automotive Environments• Transmit Data (TXD) Dominant Time-Out

Function• Undervoltage Detection on VCC and VIO Pins• CANH/CANL Short-Circuit and Overtemperature

Protected• Fulfills the OEM “Hardware Requirements for LIN,

CAN and FlexRay Interfaces in Automotive Appli-cations, Rev. 1.3"

• Qualified According to AEC-Q100 and AEC-Q006• Two Ambient Temperature Grades Available:

- ATA6562-GAQW1, ATA6563-GAQW1, ATA6562-GBQW1 and ATA6563-GBQW1 up to Tamb = +125°C

- ATA6562-GAQW0, ATA6563-GAQW0, ATA6562-GBQW0 and ATA6563-GBQW0 up to Tamb = +150°C

• Packages: SOIC8, VDFN8 with Wettable Flanks (Moisture Sensitivity Level 1)

ApplicationsClassical CAN and CAN FD networks in Automotive,Industrial, Aerospace, Medical and Consumerapplications.

General DescriptionThe ATA6562/ATA6563 is a high-speed CANtransceiver that provides an interface between acontroller area network (CAN) protocol controller andthe physical two-wire CAN bus. The transceiver is designed for high-speed (up to5 Mbps) CAN applications in the automotive industry,providing differential transmit and receive capability to(a microcontroller with) a CAN protocol controller. Itoffers improved electromagnetic compatibility (EMC)and electrostatic discharge (ESD) performance, as wellas features such as:• Ideal passive behavior to the CAN bus when the

supply voltage is off• Direct interfacing to microcontrollers with supply

voltages from 3V to 5V (ATA6563)Three operating modes together with the dedicatedfail-safe features make the ATA6562/ATA6563 anexcellent choice for all types of high-speed CANnetworks, especially in nodes requiring low-powermode with wake-up capability via the CAN bus.

Package Types

ATA6563 3 x 3 VDFN* with wettable flanks

ATA6562SOIC

VCC

GND

RXD

CANH

CANL

1

2

34

8

7

65 NSIL

STBYTXD

ATA6563SOIC

VCC

GND

RXD

CANH

CANL

1

2

34

8

7

65 VIO

STBYTXD

ATA65623 x 3 VDFN* with wettable flanks

VCC

GND

RXD

CANH

CANL

NSIL

STBY TXD 1

234

8

765

*Includes Exposed Thermal Pad (EP); see Table 1-2.

VCC

GND

RXD

CANH

CANL

VIO

STBYTXD 1

234

8

765

2017-2020 Microchip Technology Inc. DS20005790D-page 1

ATA6562/3
ATA6562/ATA6563 Family Members
Device VIO Pin NSIL Grade 0 Grade 1 VDFN8 SOIC8 DescriptionATA6562-GAQW0 X X X Standby mode and Silent mode ATA6562-GAQW1 X X X Standby mode and Silent mode ATA6562-GBQW0 X X X Standby mode and Silent mode ATA6562-GBQW1 X X X Standby mode and Silent modeATA6563-GAQW0 X X X Standby mode, VIO - pin for

compatibility with 3.3V and 5V microcontroller

ATA6563-GAQW1 X X X Standby mode, VIO - pin for compatibility with 3.3V and 5V microcontroller

ATA6563-GBQW0 X X X Standby mode, VIO-pin for compatibility with 3.3V and 5V microcontroller

ATA6563-GBQW1 X X X Standby mode, VIO - pin for compatibility with 3.3V and 5V microcontroller

Note: For ordering information, see the Product Identification System section.

DS20005790D-page 2 2017-2020 Microchip Technology Inc.

ATA6562/3
Functional Block Diagram
Notes: 1. Pin 5: ATA6563: VIO ATA6562: NSIL (the VIO line and the VCC line are internally connected) 2. HSC: High-speed comparator 3. WUC: Wake-up comparator

TemperatureProtection

TXDTime-Out-

Timer

Control Unit

MUX

Slope Control and

Driver

Wake-upFilter

CANH

CANL

TXD

GND

V

RXD

STBY

V

NSIL

VIO(1)

VIO(1)

VIO(

VCC

HSC(2)

WUC(3)

VIO(1)

1

8

4

2

6

7

35(1)

5(1)


ATA6562/3
1.0 FUNCTIONAL DESCRIPTIONThe ATA6562/ATA6563 is a stand-alone dualhigh-speed CAN transceiver compliant with theISO 11898-2, ISO 11898-2: 2016, ISO 11898-5 andSAE J2962-2 CAN standards. It provides a very lowcurrent consumption in Standby mode and wake-upcapability via the CAN bus. There are two versionsavailable, only differing in the function of pin 5:• ATA6562: The pin 5 is the control input for Silent
mode NSIL, allowing the ATA6562 to only receive data but not send data via the bus. The output driver stage is disabled. The VIO line and the VCC line are internally connected, this sets the signal levels of the TXD, RXD, STBY, and NSIL pins to levels compatible with 5V microcontrollers.

• ATA6563: The pin 5 is the VIO pin and should be connected to the microcontroller supply voltage. This allows direct interfacing to microcontrollers with supply voltages down to 3V and adjusts the signal levels of the TXD, RXD, and STBY pins to the I/O levels of the microcontroller. The I/O ports are supplied by the VIO pin.

1.1 Operating ModesEach of the transceivers supports three operatingmodes: Unpowered, Standby and Normal. TheATA6562 additionally has the Silent mode. Thesemodes can be selected via the STBY and NSIL pin.See Figure 1-1 and Table 1-1 for a description of theoperating modes.

FIGURE 1-1: OPERATING MODES

1.1.1 NORMAL MODEA low level on the STBY pin together with a high levelon pin TXD selects the Normal mode. In this mode thetransceiver is able to transmit and receive data via the

CANH and CANL bus lines (see Functional BlockDiagram). The output driver stage is active and drivesdata from the TXD input to the CAN bus. Thehigh-speed comparator (HSC) converts the analog

Note: For the ATA6563 NSIL is internally set to “1”.

UnpoweredMode

StandbyMode

VCC < Vuvd(VCC)VCC < Vuvd(VCC)

SilentMode

VCC > Vuvd(VCC)VCC < Vuvd(VCC)

STBY = 1

STBY = 0 and(NSIL = 0 or

TXD = 0)

NormalMode

STBY = 0 andNSIL = 1 and TXD = 1 and

Error = 0

STBY = 1

NSIL = 1 and TXD = 1 and Error = 0

NSIL = 0 or Error = 1

ATA6562

UnpoweredMode

StandbyMode

VCC < Vuvd(VCC) or VIO < Vuvd(VIO)

SilentMode *

STBY = 1

STBY = 0 andTXD = 0

NormalMode

STBY = 0 andTXD = 1 and

Error = 0

STBY = 1

TXD = 1 and Error = 0

Error = 1

ATA6563



VCC > Vuvd(VCC) or VIO > Vuvd(VIO)

* Silent ode is externally not accessible

TABLE 1-1: OPERATING MODES

ModeInputs Outputs

STBY NSIL PIN TXD CAN Driver Pin RXDUnpowered X(3) X(3) X(3) Recessive Recessive

Standby HIGH X(3) X(3) Recessive Active(4)

Silent (only for ATA6562) LOW LOW X(3) Recessive Active(1)

Normal LOW HIGH(2) LOW Dominant LOWLOW HIGH(2) HIGH Recessive HIGH

Note 1: LOW if the CAN bus is dominant, HIGH if the CAN bus is recessive.2: Internally pulled up if not bonded out.3: Irrelevant4: Reflects the bus only for wake-up


ATA6562/3
data on the bus lines into digital data which is output topin RXD. The bus biasing is set to VVCC/2 and theundervoltage monitoring of VCC is active. The slope of the output signals on the bus lines iscontrolled and optimized in a way that guarantees thelowest possible electromagnetic emission (EME).To switch the device in normal operating mode, set theSTBY pin to low and the TXD pin to high (see Table 1-1and Figure 1-2). The STBY pin provides a pull-upresistor to VIO, thus ensuring a defined level if the pinis open.
Please note that the device cannot enter Normal modeas long as TXD is at ground level.The switching into Normal mode is depicted in thefollowing two figures.

FIGURE 1-2: SWITCHING FROM STANDBY MODE TO NORMAL MODE (NSIL = HIGH)

FIGURE 1-3: SWITCHING FROM SILENT MODE TO NORMAL MODE

1.1.2 SILENT MODE (ONLY WITH THE ATA6562)

A low level on the NSIL pin (available on pin 5) and onthe STBY pin selects Silent mode. This receive-only

mode can be used to test the connection of the busmedium. In Silent mode the ATA6562 can still receivedata from the bus, but the transmitter is disabled andtherefore no data can be sent to the CAN bus. The buspins are released to recessive state. All other IC


ATA6562/3
functions, including the high-speed comparator (HSC),continue to operate as they do in Normal mode. Silentmode can be used to prevent a faulty CAN controllerfrom disrupting all network communications.
1.1.3 STANDBY MODEA high level on the STBY pin selects Standby mode. Inthis mode the transceiver is not able to transmit orcorrectly receive data via the bus lines. The transmitterand the high-speed comparator (HSC) are switched offto reduce current consumption. For ATA6562 only: In the event the NSIL input pin is setto low in Standby mode, the internal pull-up resistorcauses an additional quiescent current from VIO toGND. Microchip recommends setting the NSIL pin tohigh in Standby mode.

1.1.3.1 Remote Wake-up via the CAN BusIn Standby mode the bus lines are biased to ground toreduce current consumption to a minimum. TheATA6562/ATA6563 monitors the bus lines for a valid

wake-up pattern as specified in the ISO 11898-2: 2016.This filtering helps to avoid spurious wake-up events,which would be triggered by scenarios such as adominant clamped bus or by a dominant phase due tonoise, spikes on the bus, automotive transients or EMI.The wake-up pattern consists of at least twoconsecutive dominant bus levels for a duration of atleast tFilter, each separated by a recessive bus levelwith a duration of at least tFilter. Dominant or recessivebus levels shorter than tFilter are always being ignored.The complete dominant-recessive-dominant pattern asshown in Figure 1-4, must be received within the buswake-up time-out time tWake to be recognized as a validwake-up pattern. Otherwise, the internal wake-up logicis reset and then the complete wake-up pattern mustbe retransmitted to trigger a wake-up event. Pin RXDremains at high level until a valid wake-up event hasbeen detected.During Normal mode, at a VCC undervoltage conditionor when the complete wake-up pattern is not receivedwithin tWake, no wake-up is signalled at the RXD pin.

FIGURE 1-4: TIMING OF THE BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE

When a valid CAN wake-up pattern is detected on thebus, the RXD pin switches to low to signal a wake-uprequest. A transition to Normal mode is not triggereduntil the STBY pin is forced back to low by the micro-controller.

1.2 Fail-safe Features

1.2.1 TXD DOMINANT TIME-OUT FUNCTION

A TXD dominant time-out timer is started when theTXD pin is set to low. If the low state on the TXD pinpersists for longer than tto(dom)TXD, the transmitter isdisabled, releasing the bus lines to recessive state.This function prevents a hardware and/or software

application failure from driving the bus lines to apermanent dominant state (blocking all networkcommunications). The TXD dominant time-out timer isreset when the the TXD pin is set to high. If the lowstate on the TXD pin was longer than tto(dom)TXD, thenthe TXD pin has to be set to high longer 4 µs in order toreset the TXD dominant time-out timer..

1.2.2 INTERNAL PULL-UP STRUCTURE AT THE TXD AND STBY INPUT PINS

The TXD and STBY pins have an internal pull-up toVIO. This ensures a safe, defined state in case one orboth pins are left floating. Pull-up currents flow in these


ATA6562/3
pins in all states, meaning all pins should be in highstate during Standby mode to minimize the currentconsumption.
1.2.3 UNDERVOLTAGE DETECTION ON PIN VCC

If VVCC or VVIO drops below its undervoltage detectionlevels (Vuvd(VCC) and Vuvd(VIO))(see Section 2.0,Electrical Characteristics), the transceiver switches offand disengages from the bus until VVCC and VVIO hasrecovered. The low-power wake-up comparator is onlyswitched off during a VCC and VIO undervoltage. Thelogic state of the STBY pin is ignored until the VVCCvoltage or VVIO voltage has recovered.

1.2.4 BUS WAKE UP ONLY AT DEDICATED WAKE-UP PATTERN

Due to the implementation of the wake-up filtering theATA6562/ATA6563 does not wake-up when the bus isin a long dominant phase, it only wakes up at adedicated wake-up pattern as specified in the ISO11898-2: 2016. This means for a valid wake-up at least

two consecutive dominant bus levels for a duration ofat least tFilter, each separated by a recessive bus levelwith a duration of at least tFilter must be received via thebus. Dominant or recessive bus levels shorter thantFilter are always being ignored. The completedominant-recessive-dominant pattern as shown inFigure 1-4, must be received within the bus wake-uptime-out time tWake to be recognized as a valid wake-uppattern. This filtering leads to a higher robustnessagainst EMI and transients and reduces therefore therisk of an unwanted bus wake- up significantly.

1.2.5 OVERTEMPERATURE PROTECTION

The output drivers are protected againstovertemperature conditions. If the junction temperatureexceeds the shutdown junction temperature, TJsd, theoutput drivers are disabled until the junctiontemperature drops below TJsd and pin TXD is at highlevel again. The TXD condition ensures that outputdriver oscillations due to temperature drift are avoided.

FIGURE 1-5: RELEASE OF TRANSMISSION AFTER OVERTEMPERATURE CONDITION

1.2.6 SHORT-CIRCUIT PROTECTION OF THE BUS PINS

The CANH and CANL bus outputs are short-circuitprotected, either against GND or a positive supplyvoltage. A current-limiting circuit protects thetransceiver against damage. If the device is heating up

due to a continuous short on CANH or CANL, theinternal overtemperature protection switches the bustransmitter off.

FailureOvertemp

GND

TXD

Overtemperature

R D R

t

t

t

OT

BUS VDIFF(CANH-CANL)

VIO

R DD

t

t

RXDVIO

GND


ATA6562/3
1.2.7 RXD RECESSIVE CLAMPINGThis fail-safe feature prevents the controller fromsending data on the bus if its RXD is clamped to HIGH(e.g., recessive). That is, if the RXD pin cannotsignalize a dominant bus condition because it is e.g,shorted to VCC, the transmitter withinATA6562/ATA6563 is disabled to avoid possible datacollisions on the bus. In Normal and Silent mode (onlyATA6562), the device permanently compares the state
of the high-speed comparator (HSC) with the state ofthe RXD pin. If the HSC indicates a dominant bus statefor more than tRC_det without the RXD pin doing thesame, a recessive clamping situation is detected andthe transceiver is forced into Silent mode. ThisFail-safe mode is released by either entering Standbyor Unpowered mode or if the RXD pin is showing adominant (e.g., low) level again.

FIGURE 1-6: RXD RECESSIVE CLAMPING DETECTION

1.3 Pin Description The descriptions of the pins are listed in Table 1-2.

TABLE 1-2: PIN FUNCTION TABLEATA6562 ATA6563

Pin Name DescriptionSOIC8 VDFN8 SOIC8 VDFN8

1 1 1 1 TXD Transmit data input

2 2 2 2 GND Ground1 supply3 3 3 3 VCC Supply voltage4 4 4 4 RXD Receive data output; reads out data from the bus lines— — 5 5 VIO Supply voltage for I/O level adapter5 5 — — NSIL Silent mode control input (low active);6 6 6 6 CANL Low-level CAN bus line7 7 7 7 CANH High-level CAN bus line8 8 8 8 STBY Standby mode control input— 9 — 9 EP Exposed Thermal Pad: Heat slug, internally connected to the

GND pin.


ATA6562/3
1.4 Typical Application
Typical Application ATA6562

Typical Application ATA6563

Note: For VDFN8 package: EP (heatslug) must always be connected to GND.

Microcontroller ATA6562

VDD

GND

GND

1

2

3

4

NSIL

STBY8 7

6

5

TXD

RXD

CANH

CANL

CANH

CANL

BAT

VCC

100 nF

22 µF(1)

5V12V+

GND

(1) The size of this capacitor depends on the used external voltage regulator

Note: For VDFN8 package: EP (heatslug) must always be connected to GND.

Microcontroller ATA6563

VDD

GND

GND

1

2

3

4

7

6

5

TXD

RXD

CANH

CANL

CANH

CANL

BAT

VCC

100 nF 22 µF(1)

3.3V12V

+

GND

(1) The size of this capacitor depends on the used external voltage regulator

STBY8

VIO

100 nF

5V12V


ATA6562/3
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)

DC Voltage at CANH, CANL (VCANH, VCANL) ................................................................................................–27 to +42VTransient Voltage at CANH, CANL (according to ISO 7637 part 2) (VCANH, VCANL) .................................–150 to +100VMax. differential bus voltage (VDiff) ..................................................................................................................–5 to +18VDC voltage on all other pins (VX) .................................................................................................................–0.3 to +5.5VESD according to IBEE CAN EMC - Test specification following IEC 61000-4-2 — Pin CANH, CANL ..................±8 kVESD (HBM following STM5.1 with 1.5 kΩ/100 pF) - Pins CANH, CANL to GND.................................................... ±6 kVComponent Level ESD (HBM according to ANSI/ESD STM5.1, JESD22-A114, AEC-Q100 (002) .........................±4 kV CDM ESD STM 5.3.1 ..............................................................................................................................................±750VESD machine model AEC-Q100-RevF(003) ...........................................................................................................±200VVirtual Junction Temperature (TvJ) .............................................................................................................–40 to +175°CStorage Temperature Range (Tstg) .........................................................................................................-55°C to +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at those or any other conditions above those indicated inthe operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periodsmay affect device reliability.

TABLE 2-1: ELECTRICAL CHARACTERISTICSElectrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units ConditionsSupply, Pin VCCSupply Voltage VVCC 4.5 — 5.5 VSupply Current in Silent Mode

IVCC_sil 1.9 2.5 3.2 mA Silent mode, VTXD = VVIO

Supply Current in Normal Mode

IVCC_rec 2 — 5 mA recessive, VTXD = VVIO IVCC_dom 30 50 70 mA dominant, VTXD = 0V IVCC_short — — 85 mA short between CANH and

CANL(Note 1)Supply Current in Standby Mode

IVCC_STBY — — 12 µA VCC = VIO,VTXD = VNSIL = VVIO

IVCC_STBY — 7 — µA Ta = 25°C (Note 3)Undervoltage Detection Threshold on Pin VCC

Vuvd(VCC) 2.75 — 4.5 V

I/O Level Adapter Supply, Pin VIO (only with the ATA6563)Supply voltage on pin VIO VVIO 2.8 — 5.5 VSupply current on pin VIO IVIO_rec 10 80 250 µA Normal and Silent mode

recessive, VTXD = VVIOIVIO_dom 50 350 500 µA Normal and Silent mode

dominant, VTXD = 0VIVIO_STBY — — 1 µA Standby mode

Note 1: 100% correlation tested2: Characterized on samples3: Design parameter


ATA6562/3

Undervoltage detectionthreshold on pin VIO

Vuvd(VIO) 1.3 — 2.7 V

Mode Control Input, Pin NSIL and STBYHigh-level Input Voltage VIH 0.7VVIO — VVIO+0.3 VLow-level Input Voltage VIL –0.3 — 0.3VVIO VPull- up Resistor to VCC Rpu 75 125 175 kΩ VSTBY = 0V, VNSIL = 0VHigh-level Leakage Current IL –2 — +2 µA VSTBY = VVIO, VNSIL = VVIOCAN Transmit Data Input, Pin TXDHigh-level Input Voltage VIH 0.7VVIO — VVIO+0.3 VLow-level Input Voltage VIL –0.3 — 0.3VVIO VPull-up Resistor to VCC RTXD 20 35 50 kΩ VTXD = 0V High-level Leakage Current ITXD –2 — +2 µA Normal mode, VTXD = VVIO Input Capacitance CTXD — 5 10 pF Note 3CAN Receive Data Output, Pin RXDHigh-level Output Current IOH –8 — –1 mA Normal mode,

VRXD = VVIO – 0.4V, VVIO = VVCC

Low-level Output Current, Bus Dominant

IOL 2 — 12 mA Normal mode, VRXD = 0.4V, bus dominant

Bus Lines, Pins CANH and CANLSingle Ended Dominant Output Voltage

VO(dom) 2.75 3.5 4.5 V VTXD = 0V, t < tto(dom)TXDRL = 50Ω to 65Ωpin CANH (Note 1)

0.5 1.5 2.25 V VTXD = 0V, t < tto(dom)TXDRL = 50Ω to 65Ωpin CANL (Note 1)

Transmitter Voltage Symmetry

VSym 0.9 1.0 1.1 VSym = (VCANH + VCANL) / VVCC,Split Termination, RL = 2 x 30, CSplit = 4.7 nF (Note 3)

Bus Differential Output Voltage

VDiff 1.5 — 3 V VTXD = 0V, t < tto(dom)TXDRL = 45Ω to 65Ω

1.5 — 3.3 V RL = 70Ω (Note 3)1.5 — 5 V RL = 2240Ω (Note 3)–50 — +50 mV Normal and Silent mode:

VVCC = 4.75V to 5.25VVTXD = VVIO, recessive, no load

–200 — +200 mV Standby mode:VVCC = 4.75V to 5.25VVTXD = VVIO, recessive, no load

Single Ended Recessive Output Voltage

VO(rec) 2 0.5* VVCC

3 V Normal and Silent mode, VTXD = VVIO, no load

VO(rec) –0.1 — +0.1 V Standby mode,VTXD = VVIO, no load

TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units Conditions



ATA6562/3

Differential Receiver Threshold Voltage

Vth(RX)dif 0.5 0.7 0.9 V Normal and Silent mode (HSC), Vcm(CAN) = –27V to +27V

Vth(RX)dif 0.4 0.7 1.1 V Standby mode (WUC),Vcm(CAN) = –27V to +27V(Note 1)

Differential Receiver Hysteresis Voltage

Vhys(RX)dif 50 120 200 mV Normal and Silent mode (HSC), Vcm(CAN) = –27V to +27V (Note 1)

Dominant Output Current IIO(dom) –75 — –35 mA VTXD = 0V, t < tto(dom)TXD,VVCC = 5Vpin CANH, VCANH = –5V

35 — 75 mA VTXD = 0V, t < tto(dom)TXD,VVCC = 5Vpin CANL, VCANL = +40V

Recessive Output Current IIO(rec) –5 — +5 mA Normal and Silent mode,VTXD = VVIO, no load,VCANH = VCANL = –27V to +32V

Leakage Current IIO(leak) –5 0 +5 µA VVCC = VVIO = 0V, VCANH = VCANL = 5V

IIO(leak) –5 0 +5 µA VCC = VIO connected to GND with R = 47kΩ VCANH = VCANL = 5V(Note 3)

Input Resistance Ri 9 15 28 kΩ VCANH = VCANL = 4VRi 9 15 28 kΩ –2V ≤ VCANH ≤ +7V,

–2V ≤ VCANL ≤ +7V(Note 3)Input Resistance Deviation ΔRi –1 0 +1 % Between CANH and CANL

VCANH = VCANL = 4V (Note 1)ΔRi –1 0 +1 % Between CANH and CANL

–2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3)

Differential Input Resistance Ri(dif) 18 30 56 kΩ VCANH = VCANL = 4V (Note 1)Ri(dif) 18 30 56 kΩ –2V ≤ VCANH ≤ +7V,

–2V ≤ VCANL ≤ +7V (Note 3)Common-mode Input Capacitance

Ci(cm) — — 20 pF f = 500 kHz, CANH and CANL referred to GND (Note 3)

Differential Input Capaci-tance

Ci(dif) — — 10 pF f = 500kHz, between CANH and CANL (Note 3)

Differential Bus Voltage Range for RECESSIVE State Detection

VDiff_rec –3 — +0.5 V Normal and Silent mode (HSC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3)

VDiff_rec –3 — +0.4 V Standby mode (WUC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V(Note 3)





ATA6562/3

Differential Bus Voltage Range for DOMINANT State Detection

VDiff_dom 0.9 — 8.0 V Normal and Silent mode (HSC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3)

VDiff_dom 1.15 — 8.0 V Standby mode (WUC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3)

Transceiver Timing, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3Delay Time from TXD to Bus Dominant

td(TXD-busdom) 40 — 130 ns Normal mode (Note 2)

Delay Time from TXD to Bus Recessive

td(TXD-busrec) 40 — 130 ns Normal mode (Note 2)

Delay Time from Bus Dominant to RXD

td(busdom-RXD) 20 — 100 ns Normal mode (Note 2)

Delay Time from Bus Recessive to RXD

td(busrec-RXD) 20 — 100 ns Normal mode (Note 2)

Propagation Delay from TXD to RXD

tPD(TXD-RXD) 40 — 210 ns Normal mode, Rising edge at pin TXD RL = 60Ω, CL = 100 pF

40 — 200 ns Normal mode, Falling edge at pin TXDRL = 60Ω, CL = 100 pF

tPD(TXD-RXD) — — 300 ns Normal mode, Rising edge at pin TXDRL = 150Ω, CL = 100 pF (Note 3)

— — 300 ns Normal mode, Falling edge at pin TXDRL = 150Ω, CL = 100pF (Note 3)

TXD Dominant Time-Out Time

tto(dom)TXD 0.8 — 3 ms VTXD = 0V, Normal mode

Bus Wake-up Time-Out Time tWake 0.8 — 3 ms Standby modeMin. Dominant/Recessive Bus Wake-up Time

tFilter 0.5 3 3.8 µs Standby mode

Delay Time for Standby Mode to Normal Mode Tran-sition

tdel(stby-norm) — — 47 µs Falling edge at pin STBY

Delay Time for Normal Mode to Standby Mode Transition

tdel(norm-stby) — — 5 µs Rising edge at pin STBY (Note 3)

Delay time for Normal modeto Silent mode transition

tdel(norm-sil) — — 10 µs Falling edge at pin NSILSTBY = LOW (Note 3)

Delay time for Silent mode toNormal mode transition

tdel(sil-norm) — — 10 µs Rising edge at pin NSILSTBY = LOW (Note 3)





ATA6562/3

Delay time for Silent mode toStandby mode transition

tdel(sil-stby) — — 5 µs Rising edge at pin STBYNSIL = LOW (Note 3)

Delay time for Standby modeto Silent mode transition

tdel(stby-sil) — — 47 µs Rising edge at pin STBYNSIL = LOW (Note 3)

Debouncing Time for Recessive Clamping State Detection

tRC_det — 90 — ns V(CANH-CANL) > 900mVRXD = high (Note 3)

Transceiver Timing for higher Bit Rates, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3Recessive Bit Time on Pin RXD

tBit(RXD) 400 — 550 ns Normal mode, tBit(TXD) = 500 nsRL = 60, CL = 100 pF (Note 1)

120 — 220 ns Normal mode, tBit(TXD) = 200 nsRL = 60, CL = 100 pF

Recessive Bit Time on the Bus

tBit(Bus) 435 — 530 ns Normal mode, tBit(TXD) = 500 nsRL = 60, CL = 100 pF (Note 1)

155 — 210 ns Normal mode, tBit(TXD) = 200 nsRL = 60, CL = 100 pF

Receiver Timing Symmetry ΔtRec –65 — +40 ns Normal mode, tBit(TXD) = 500 nsΔtRec = tBit(RXD)–tBit(Bus)RL = 60, CL = 100 pF (Note 1)

–45 — +15 ns Normal mode, tBit(TXD) = 200 nsΔtRec = tBit(RXD)–tBit(Bus)RL = 60, CL = 100 pF




TABLE 2-2: TEMPERATURE SPECIFICATIONSParameters Sym. Min. Typ. Max. Units

Thermal Characteristics SOIC8Thermal resistance Virtual Junction to Ambient RthvJA — 145 — K/WThermal Shutdown of the Bus DriversATA6562-GAQW1, ATA6563-GAQW1 (Grade 1) TVJsd 150 — 195 °CATA6562-GAQW0, ATA6563-GAQW0 (Grade 0) TVJsd 170 — 195 °CThermal Shutdown Hysteresis TvJsd_hys — 15 — °CThermal Characteristics VDFN8Thermal Resistance Virtual Junction to Heat Slug RthvJC — 10 — K/WThermal Resistance Virtual Junction to Ambient, where Heat Slug is soldered to PCB according to JEDEC

RthvJA — 50 — K/W

Thermal Shutdown of the Bus DriversATA6562-GBQW1, ATA6563-GBQW1 (Grade 1) TVJsd 150 — 195 °CATA6562-GBQW0, ATA6563-GBQW0 (Grade 0) TVJsd 170 — 195 °CThermal Shutdown Hysteresis TvJsd_hys — 15 — °C


ATA6562/3
FIGURE 2-1: TIMING TEST CIRCUIT FOR THE ATA6562/3 CAN TRANSCEIVER
FIGURE 2-2: CAN TRANSCEIVER TIMING DIAGRAM 1

TXD

CANH

HIGH

LOW

HIGH

recessive

LOW

dominant

0.9V

0.5V

CANL

RXD

VDiff

td(TXD-busdom) td(TXD-busrec)

td(busdom-RXD)

tPD(TXD-RXD) tPD(TXD-RXD)

td(busrec-RXD)

0.7 VIO0.3 V


ATA6562/3
FIGURE 2-3: CAN TRANSCEIVER TIMING DIAGRAM 2

ATA6562/3
3.0 PACKAGING INFORMATION
Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

8-Lead SOIC ExampleATA6562 Grade 0

721ATA6562H1729256

ExampleATA6562 Grade 1

721ATA65621729256


721ATA6563H1729256


721ATA65631729256


ATA6562/3

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

8-Lead 3 X 3 mm VDFN ExampleATA6562 Grade 0

6562H 256


6562 256


6563H 256


6563 256


ATA6562/3

0.25 C A–B D

CSEATING

PLANE

TOP VIEW

SIDE VIEW

VIEW A–A

0.10 C

0.10 C

Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2

8X

For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging

Note:

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

1 2

N

h

h

A1

A2A

A

B

e

D

E

E2

E12

E1

NOTE 5

NOTE 5

NX b

0.10 C A–B2X

H 0.23

(L1)L

R0.13

R0.13

VIEW C

SEE VIEW C

NOTE 1

D

0.10 C A–B2X

0.10 C A–B2X


ATA6562/3

Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2



Note:

Foot Angle 0° - 8°

15°-5°Mold Draft Angle Bottom15°-5°Mold Draft Angle Top0.51-0.31bLead Width0.25-0.17cLead Thickness

1.27-0.40LFoot Length0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length3.90 BSCE1Molded Package Width6.00 BSCEOverall Width

0.25-0.10A1Standoff--1.25A2Molded Package Thickness

1.75--AOverall Height1.27 BSCePitch

8NNumber of PinsMAXNOMMINDimension Limits

MILLIMETERSUnits

protrusions shall not exceed 0.15mm per side.3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

REF: Reference Dimension, usually without tolerance, for information purposes only.BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. § Significant Characteristic

4. Dimensioning and tolerancing per ASME Y14.5M

Notes:

§

Footprint L1 1.04 REF

5. Datums A & B to be determined at Datum H.


ATA6562/3

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2057-SN Rev F

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:Dimensioning and tolerancing per ASME Y14.5M1.


Note:

Dimension LimitsUnits

CContact Pad SpacingContact Pitch

MILLIMETERS

1.27 BSCMIN

EMAX

5.40

Contact Pad Length (X8)Contact Pad Width (X8)

Y1X1

1.550.60

NOM

E

X1

C

Y1

SILK SCREEN



ATA6562/3

BA

0.10 C

0.10 C

0.10 C A B0.05 C

(DATUM B)(DATUM A)

CSEATING

PLANE

1 2

N

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

0.10 C A B

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-21358 Rev B Sheet 1 of 2

2X

8X


Note:

8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks

D

E

NOTE 1

(A3)

AA1

1 2

N

D2

E2

NOTE 1

L

K

e

8X b

A

A


ATA6562/3

Microchip Technology Drawing C04-21358 Rev B Sheet 2 of 2

Number of Terminals

Overall Height

Terminal Width

Overall Width

Terminal Length

Exposed Pad Width

Terminal Thickness

Pitch

Standoff

UnitsDimension Limits

A1A

bE2

A3

e

L

E

N0.65 BSC

0.203 REF

1.50

0.350.25

0.800.00

0.300.40

1.60

0.850.03

3.00 BSC

MILLIMETERSMIN NOM

8

1.70

0.450.35

0.900.05

MAX

K -0.20 -

REF: Reference Dimension, usually without tolerance, for information purposes only.BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1.2.3.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.Package is saw singulatedDimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]


Note:

With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks

Overall LengthExposed Pad Length

DD2 2.30

3.00 BSC2.40 2.50

A4

E3

SECTION A–A

PARTIALLYPLATED

Wettable Flank Step Cut Depth A4 0.10 0.13 0.15E3 -- 0.04Wettable Flank Step Cut Width


ATA6562/3

RECOMMENDED LAND PATTERN

Dimension LimitsUnits

Optional Center Pad WidthOptional Center Pad Length

Contact Pitch

Y2X2

2.501.70

MILLIMETERS

0.65 BSCMIN

EMAX

Contact Pad Length (X8)Contact Pad Width (X8)

Y1X1

0.800.35

Microchip Technology Drawing C04-23358 Rev B

NOM

8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]

1 2

8

CContact Pad Spacing 3.00

Contact Pad to Center Pad (X8) G1 0.20

Thermal Via Diameter VThermal Via Pitch EV

0.331.20

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss duringreflow process

1.

2.


Note:

With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks

C

E

X1

Y1

Y2

EV

ØV

G1

SILK SCREEN

EVX2

Pin 1 Index Chamfer CH 0.20Contact Pad to Contact Pad (X6) G2 0.20

G2

CH


ATA6562/3
APPENDIX A: REVISION HISTORY
Revision D (June 2020)The following is the list of modifications:1. Updated parameter “Supply Current in Silent

Mode” in Table 2-1: Electrical Characteristics.2. Added test conditions at several parameters in

Table 2-1: Electrical Characteristics.3. Added parameter “Bus Differential Output Volt-

age” in Standby mode in Table 2-1: ElectricalCharacteristics.

4. Updated Package Marking Information

Revision C (August 2019)The following is the list of modifications:1. Updated TABLE 2-2: “Temperature Specifica-

tions”.2. Added test conditions at several parameters in

TABLE 2-1: “Electrical Characteristics”.

Revision B (August 2017)The following is the list of modifications:1. Added new devices ATA6562-GBQW0 and

ATA6563-GBQW0 and updated the relatedinformation across the document.

2. Updated Features section.3. Updated ATA6562/ATA6563 Family Members

section.4. Updated Table 2-2: Temperature Specifica-

tions.5. Updated Package Marking Information6. Updated Product Identification System section.7. Various typographical edits.

Revision A (June 2017)• Original Release of this Document.• This document replaces Atmel - 9389C-

11/16ATA6562/ATA6563


ATA6562/ATA6563
NOTES:

ATA6562/3
PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:a) ATA6562-GAQW0: ATA6562, 8-Lead SOIC,

Tape and Reel, Packageaccording to RoHS,Temperature Grade 0

b) ATA6562-GAQW1: ATA6562, 8-Lead SOIC, Tape and Reel, Package according to RoHS, Temperature Grade 1

c) ATA6562-GBQW0: ATA6562, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 0

d) ATA6562-GBQW1: ATA6562, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 1

e) ATA6563-GAQW0: ATA6563, 8-Lead SOIC, Tape and Reel, Packageaccording to RoHS,Temperature Grade 0

f) ATA6563-GAQW1: ATA6563, 8-Lead SOIC, Tape and Reel, Package according to RoHS, Temperature Grade 1

f) ATA6563-GBQW0: ATA6563, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 0

g ATA6563-GBQW1: ATA6563, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 1

PART NO. X

Package directivesDevice

Device: ATA6562: High-speed CAN Transceiver with Standby and Silent Mode CAN FD Ready

ATA6563: High-speed CAN Transceiver with Standby Mode and VIO-pin CAN FD Ready

Package: GA = 8-Lead SOICGB = 8-Lead VDFN

Tape and Reel Option:

Q = 330 mm diameter Tape and Reel

Package directives classification:

W = Package according to RoHS(2)

Temperature Range:

0 = Temperature Grade 0 (-40°C to +150°C)1 = Temperature Grade 1 (-40°C to +125°C)

XX

Package

X

TemperatureRange

[X](1)

Tape and ReelOption classification

Note 1: Tape and Reel identifier only appears in thecatalog part number description. Thisidentifier is used for ordering purposes and isnot printed on the device package. Check withyour Microchip Sales Office for packageavailability with the Tape and Reel option.

2: RoHS compliant, Maximum concentrationvalue of 0.09% (900 ppm) for Bromine (Br)and Chlorine (Cl) and less than 0.15% (1500ppm) total Bromine (Br) and Chlorine (Cl) inany homogeneous material. Maximumconcentration value of 0.09% (900 ppm) forAntimony (Sb) in any homogeneous material.


ATA6562/3
NOTES:

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2017-2020 Microchip Technology Inc.

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

TrademarksThe Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies.

© 2020, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-6283-5

DS20005790D-page 29

www.microchip.com/quality

www.microchip.com/quality


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