AT94 Training 2001Slide 1 Configurable SRAM 8 Bit RISC MCU AT40K FPGA Monolithic SRAM Based FPSLIC...

AT94 Training 2001Slide 1

Configurable SRAM

8 Bit RISC MCUAT40K FPGA

Monolithic SRAM Based FPSLIC

20 MIPS* - 8bit RISC MCU

Up to 36K bytes of SRAM

From 5K Up to 40K gates FPGA

*30 MIPS version available Q4 2001


Configurable SRAM

SRAM interface

AVR/AT40

K inte

rface

FPSLIC Embedded Blocks

• Software configurable interface between blocks already implemented• Pre-implemented Interface blocks save 2000-5000 FPGA gates

AT40K FPGA8 Bit RISC MCU


Designer Defined Program and Data SRAM Allocation

10K* Words Instruction (x 16)

PROG. SRAM Fixed

4K B

yte

for D

ata

• Memory partition is user defined during development• Easy to trade-off Program and data SRAM

* 2K Words (x16) for FPSLIC (AT94K05)

2K x

8

2K x

8

2K x

8

2K x

8

2Kx

8

2K x

8

Designer Allocated Memory


8 Bit RISC MCU

I/O select[15:0]

R/W

Data[7:0]

Int[15:0]

AT40K FPGA

02Data[7:0]

W

Internal I/O space and Interrupts

I/Oselect[0]

Write:ldi r16,0x00 ldi r17,0x02out FISCR,r16 ; I/O select 0out FISUA,r17 ; r17 data on the bus


Data SRAM (DPRAM)4K byte up to 16Kbyte

AVR-Add

[15:

0]

Avr-D

ata[

7:0]

AVR-R/W

AVR-Clk

8 Bit RISC MCU

FPG

A-Add

[15:

0]

FPGA-R/W

FPGA-Clk

FPGA-Dat

a[7:

0]

AT40K FPGA

Internal Data SRAM Access

True Dual Port AccessAVR can disable writing from FPGA


AT40K FPGA8 Bit RISC MCU

GCLK5(internal)

AVR System Clk

GCLK 1,2,3,4,7,8 (External)

FPSLIC Clocking

AVR System ClkHigh Frequency

AVR System Clk32 KHz Osc

AVR System Clk

Timer Clk

WD Clk

GCLK6 (internal)


"0"

"0"

FPGA Internal Clocking Scheme

• Individual Clock per sector column• Clock and Clock BAR at sector boundary• Column Clock can be any one of 8 Global

clocks• Clock from Column Clock or Express Bus• 4 Fast Clocks (2 per side for PCI spec)• Low power tie-off (lower power!)• Clock skew <1ns guaranteed

>> Can reduce power by >50% !


FPSLIC Reducing Power consumption

MCU MEM

ASIC/FPGA

Most of power usedin I/O pads

Discrete Solution Monolithic Solution

MEM

MCU FPGA

Power is reduced by more than 50%• Standby <100uA• Active 2-3mA/MHz

Power is Reduced by 50%+


Configurable SRAM

8 Bit RISC MCUAT40K FPGA

FPSLIC Resets

(Internal)• Watchdog reset AVR only• FPSLIC Software reset with SFTCR bit

FPSLIC Reset Pin

(External)

AVR Reset Pinsoftware defined

(External)FPGA Logic Reset (any I/O)

(External)


RSA3

DESSoftw

are

Applicat

ion

Data/

Keys

8 Bit RISC MCU

X[7:0]

Y[7:0]

Z[7:0]

D[7:0]

write

32 bits

X

Y

Z

RSA3

DES

FPSLIC - Partial Reconfiguration using AVR

CacheLogicTM

• Hardware implemented for the AVR to control partial reconfiguration• Enable Hardware context switching


SRAM

8 Bit RISC MCU

Configura

tor

2 Wire Protocol

SRAM

2 Wire

FPSLIC- CONFIGURATION ( Mode 0)

• Automatic download after power up --> FPGA bitstream/AVR code and data/System register• EEPROM configuration memory can be updated by FPSLIC itself• Extra system parameters can be stored in remaining EEPROM

AT40K FPGA AT40K FPGA Configuration

Reprogrammed

SRAM CONFIGURED

AT40K FPGACONFIGURED


Initial AVR-FPSLIC Family• 5K, 10K and 40K gate AT40K FPGA options• High performance AVR microcontroller• 2 UARTs, watch-dog timer, programmable timer, interrupt• Configuration, 2-wire interface, glue logic

Device Samples FPGAGates

FreeRAMTM

SRAMFPGA

I/OProgram/Data

SRAMFPSLIC Q3/01 5K 2048

bitsupto96

4K-16K Bytes/4K-16K Bytes

AT94K10AL Q3/01 10K 4096bits

Upto192

20K –32K Bytes/4K-16K Bytes

AT94K40AL Q3/01 40K 18432bits

Upto384

20K –32K Bytes/4K-16K Bytes


FPSLIC Applications• Wireless and Portable systems

• Low power. Stand-by Idd < 100uA. Active <100mA.• Space saving BGA packaging technology• Reconfigurability (on the fly, remote)• Secure FPSLIC for sensitive applications

• PDAs and PCMCIA (PCCARD)• Cell phone accessories• Digital cameras• Portable audio• Smartcard readers• Wireless security/access systems• Portable instrumentation• Medical instrumentation• Toll Tags• Irrigation systems/remote monitoring

Features:


FPSLIC Applications • Wireline and fixed systems

• High performance 20 MIPS @ 25MHz• Remote updates (reconfigurability)• Very flexible architecture - platform product• Space saving BGA packages• Low power. Stand-by Idd < 100uA. Active <100mA• Secure FPSLIC for sensitive applications

• Home networking / Internet appliance

• Base stations for Wireless systems

• Networking and Telecom line-cards

• Test equipment

• Point of Sale terminals

• Wired security/access systems

• Industrial control and fixed instrumentation

• Image processing systems

Features :


AT40KxxAL

Low $Avail: Now

AT40KxxAL

Low $Avail: Now

2000 2001 2002 2003

Fea

ture

s

AT40KxxAV

Low $

AT40KxxAV

Low $

3.3V 0.35u

ASIC FPSLICTM /Embeddable FPGA core

ASCPs Available now

ASIC FPSLICTM /Embeddable FPGA core

ASCPs Available now

AT40K with RISC uCAVRTM FPSLICTM

AT40K with RISC uCAVRTM FPSLICTM

AT40KxxAX

Low $

AT40KxxAX

Low $1.8V 0.12u

AT40K with ARMARM FPSLICTM

AT40K with ARMARM FPSLICTM

Atmel Programmable SLi Roadmap

1.8V 0.18u


FPSLIC™ System Designer ™ Software Tools


FPSLIC™ Design Tools

Complete IDS7 FPGA Software• Place & route, floorplanning, timing analysis, etc.

• Leonardo Spectrum Synthesis Compiler• VHDL & Verilog entry (FPSLIC version)

• ModelSim hardware simulator (FPSLIC version)

• AVR Studio• Design & debugging• Instruction set simulator• Assembler

FPGA

Co-Verification

AVR

• Co-verification• PC-based: Windows 95/98/NT/ME/2000• Powered by Mentor Graphics (FPSLIC version)


Modelsim for Simulation

$10K value

Exemplar’s Leonardo for Synthesis

$10K value

Co-verification powered by Mentor

$50K value

AVR Studio for Debug

FPGA IDS for Layout

FPSLIC™ Software System Designer


System Designer

Features:

• Design Manager• Environment management• Part Selection Manager• Co-Verification launcher• Launch FPGA/uC tools• Device Dependent Methodology Manager• Controls System Flow• Bitstream Utilities• Download Utilities• Extensive interactive help• Intuitive and easy to learn


Release to

Manufacturing

System design without Co-verification

Iteration Loop

1 to 3 Months

HardwareDevelopment

SoftwareDevelopment

SystemIntegration

PhysicalImplementation


PhysicalImplementation

System design with co-verification

HardwareDevelopment

SoftwareDevelopment

Release to

Manufacturing

SystemIntegration

System Designer

Iteration Loop 1 to 3 Hours

Co-Verification


Co-Verification Software Backplane

SW SimulationAVR Studio

HDL SimulationModelSim

Co-Verification* Software

API

Instruction-Set Simulator

–Complete Instruction Set– Interrupt–Reset– Instruction Timing

ModelSim

Interface

Bus Interface Model

–Peripherals

–Bus Cycle Timing

–Controllers

API

MTIModelSimSimulator

*FPSLIC Co-Verification S/W is powered by Mentor Graphics


Bitstream Generation

• Can generate a complete bitstream (AVR and FPGA) or can generate an AVR only or FPGA only bitstream for faster debugging

• Output file can be directly downloaded to FPSLIC or used on industry standard 3rd part programmers


System Control Register Settings• Everything is programmable in FPSLIC

• System Designer gives you control over internal device settings

• 64 bits are used for configuring operating Modes

– Configuration control– Memory protections and partitioning– Dual pin configuration– I/O drive configuration– Clock selection


Design Tools

ATDS94KSW1 - $995 Annual Subscription

or

ATDS94KSW2 - $2495 Purchase Price

ATDM94KSW2 - $495 Annual Maintenance

System Designer

AT94 Training 2001Slide 1 Configurable SRAM 8 Bit RISC MCU AT40K FPGA Monolithic SRAM Based FPSLIC...

Documents

Transcript of AT94 Training 2001Slide 1 Configurable SRAM 8 Bit RISC MCU AT40K FPGA Monolithic SRAM Based FPSLIC...