AT90CAN32 AT90CAN64 AT90CAN128Note: 1. Details on section 19.4.3 on page 242. Rev....

Rev. 7679H–CAN–08/08

8-bit Microcontroller with32K/64K/128K Bytes ofISP FlashandCAN Controller

AT90CAN32AT90CAN64AT90CAN128

Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers + Peripheral Control Registers– Fully Static Operation– Up to 16 MIPS Throughput at 16 MHz– On-chip 2-cycle Multiplier

• Non volatile Program and Data Memories– 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128)

• Endurance: 10,000 Write/Erase Cycles– Optional Boot Code Section with Independent Lock Bits

• Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes• In-System Programming by On-Chip Boot Program (CAN, UART, ...)• True Read-While-Write Operation

– 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128)– 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128)– Up to 64K Bytes Optional External Memory Space– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface– Boundary-scan Capabilities According to the JTAG Standard– Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits– Extensive On-chip Debug Support

• CAN Controller 2.0A & 2.0B - ISO 16845 Certified (1)– 15 Full Message Objects with Separate Identifier Tags and Masks– Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes– 1Mbits/s Maximum Transfer Rate at 8 MHz– Time stamping, TTC & Listening Mode (Spying or Autobaud)

• Peripheral Features– Programmable Watchdog Timer with On-chip Oscillator– 8-bit Synchronous Timer/Counter-0

• 10-bit Prescaler• External Event Counter• Output Compare or 8-bit PWM Output

– 8-bit Asynchronous Timer/Counter-2• 10-bit Prescaler• External Event Counter• Output Compare or 8-Bit PWM Output• 32Khz Oscillator for RTC Operation

– Dual 16-bit Synchronous Timer/Counters-1 & 3 • 10-bit Prescaler• Input Capture with Noise Canceler• External Event Counter• 3-Output Compare or 16-Bit PWM Output• Output Compare Modulation

– 8-channel, 10-bit SAR ADC• 8 Single-ended Channels• 7 Differential Channels• 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x

– On-chip Analog Comparator– Byte-oriented Two-wire Serial Interface– Dual Programmable Serial USART– Master/Slave SPI Serial Interface

• Programming Flash (Hardware ISP)• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated RC Oscillator– 8 External Interrupt Sources– 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby– Software Selectable Clock Frequency– Global Pull-up Disable

• I/O and Packages– 53 Programmable I/O Lines– 64-lead TQFP and 64-lead QFN

• Operating Voltages: 2.7 - 5.5V• Operating temperature: Industrial (-40°C to +85°C)• Maximum Frequency: 8 MHz at 2.7V, 16 MHz at 4.5VNote: 1. Details on section 19.4.3 on page 242.

1. Description

1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They dif-fer only in memory sizes as shown in Table 1-1.

1.2 Part DescriptionThe AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle, theAT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the systemdesigner to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.

The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Pro-grammable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN con-troller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differ-ential input stage with programmable gain, a programmable Watchdog Timer with InternalOscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used foraccessing the On-chip Debug system and programming and five software selectable power sav-ing modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports andinterrupt system to continue functioning. The Power-down mode saves the register contents butfreezes the Oscillator, disabling all other chip functions until the next interrupt or HardwareReset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stopsthe CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noiseduring ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while therest of the device is sleeping. This allows very fast start-up combined with low powerconsumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serialinterface, by a conventional nonvolatile memory programmer, or by an On-chip Boot programrunning on the AVR core. The boot program can use any interface to download the applicationprogram in the application Flash memory. Software in the Boot Flash section will continue to runwhile the Application Flash section is updated, providing true Read-While-Write operation. By

Table 1-1. Memory Size Summary

Device Flash EEPROM RAM

AT90CAN32 32K Bytes 1K Byte 2K Bytes

AT90CAN64 64K Bytes 2K Bytes 4K Bytes

AT90CAN128 128K Bytes 4K Byte 4K Bytes

27679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible andcost effective solution to many embedded control applications.

The AT90CAN32/64/128 AVR is supported with a full suite of program and system developmenttools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-tors, and evaluation kits.

1.3 Disclaimer Typical values contained in this datasheet are based on simulations and characterization ofother AVR microcontrollers manufactured on the same process technology. Min and Max valueswill be available after the device is characterized.

37679H–CAN–08/08

1.4 Block Diagram

Figure 1-1. Block Diagram

PROGRAMCOUNTER

STACKPOINTER

PROGRAMFLASH

MCU CONTROLREGISTER

SRAM

GENERALPURPOSE

REGISTERS

INSTRUCTIONREGISTER

TIMER/COUNTERS

INSTRUCTIONDECODER

DATA DIR.REG. PORTB

DATA DIR.REG. PORTE

DATA DIR.REG. PORTA

DATA DIR.REG. PORTD

DATA REGISTERPORTB

DATA REGISTERPORTE

DATA REGISTERPORTA

DATA REGISTERPORTD

INTERRUPTUNIT

EEPROM

SPIUSART0

STATUSREGISTER

Z

Y

X

ALU

PORTB DRIVERSPORTE DRIVERS

PORTA DRIVERSPORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB7 - PB0PE7 - PE0

PA7 - PA0PF7 - PF0

RE

SE

T

VCC

AGND

GND

AREF

XTA

L1

XTA

L2

CONTROLLINES

+ -

AN

ALO

GC

OM

PAR

ATO

R

PC7 - PC0

INTERNALOSCILLATOR

WATCHDOGTIMER

8-BIT DATA BUS

AVCC

USART1

TIMING ANDCONTROL

OSCILLATOR

OSCILLATOR

CALIB. OSC

DATA DIR.REG. PORTC

DATA REGISTERPORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMINGLOGIC

BOUNDARY- SCAN

DATA DIR.REG. PORTF

DATA REGISTERPORTF

ADC

POR - BODRESET

PD7 - PD0

DATA DIR.REG. PORTG

DATA REG.PORTG

PORTG DRIVERS

PG4 - PG0

TWO-WIRE SERIALINTERFACE

CAN� CONTROLLER

47679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

1.5 Pin Configurations

Figure 1-2. Pinout AT90CAN32/64/128 - TQFP

PC0 (A8)

VC

C

GN

D

PF0

(AD

C0)

PF7

(AD

C7

/ TD

I)

PF1

(AD

C1)

PF2

(AD

C2)

PF3

(AD

C3)

PF4

(AD

C4

/ TC

K)

PF5

(AD

C5

/ TM

S)

PF6

(AD

C6

/ TD

O)

AR

EF

GN

D

AV

CC

17

61 60

18

59

20

58

19 21

57

22

56

23

55

24

54

25

53

26

52

27

51

2928

50 49323130

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC2A) PB4

(OC

0A /

OC

1C) P

B7

(TO

SC

2 )

PG

3

(OC1B) PB6

(TO

SC

1 )

PG

4

(OC1A) PB5

PC1 (A9)

(T0)

PD

7

PC2 (A10)

PC3 (A11)

PC4 (A12)

PC5 (A13)

PC6 (A14)

PC7 (A15 / CLKO)

PA7 (AD7)

PG2 (ALE)

PA6 (AD6)

PA5 (AD5)

PA4 (AD4)

PA3 (AD3)

PA

0 (A

D0)

PA

1 (A

D1)

PA

2 (A

D2)

(RX

CA

N /

T1) P

D6

(TX

CA

N /

XC

K1)

PD

5

(IC

P1)

PD

4

(TX

D1

/ IN

T3) P

D3

(RX

D1

/ IN

T2) P

D2

(SD

A /

INT1

) PD

1

(SC

L / I

NT0

) PD

0

XTA

L1

XTA

L2

RE

SE

T

GN

D

VC

C

PG1 (RD)

PG0 (WR)

2

3

1

4

5

6

7

8

9

10

11

12

13

14

16

15

64 63 6247

46

48

45

44

43

42

41

40

39

38

37

36

35

33

34

(2)

(2)

NC = Do not connect (May be used in future devices)(1)

Timer2 Oscillator(2)

NC(1)

(64-lead TQFP top view)

INDEX CORNER

57679H–CAN–08/08

Figure 1-3. Pinout AT90CAN32/64/128 - QFN

Note: The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

1.6 Pin Descriptions

1.6.1 VCCDigital supply voltage.

1.6.2 GNDGround.

NC = Do not connect (May be used in future devices)(1)

Timer2 Oscillator(2)

PC0 (A8) V

CC

GN

D

PF0

(AD

C0)

PF7

(AD

C7

/ TD

I)

PF1

(AD

C1)

PF2

(AD

C2)

PF3

(AD

C3)

PF4

(AD

C4

/ TC

K)

PF5

(AD

C5

/ TM

S)

PF6

(AD

C6

/ TD

O)

AR

EF

GN

D

AV

CC

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC2A) PB4

(OC

0A /

OC

1C) P

B7

(TO

SC

2 )

PG

3

(OC1B) PB6

(TO

SC

1 )

PG

4

(OC1A) PB5

PC1 (A9)

(T0)

PD

7

PC2 (A10)

PC3 (A11)

PC4 (A12)

PC5 (A13)

PC6 (A14)

PC7 (A15 / CLKO)

PA7 (AD7)

PG2 (ALE)

PA6 (AD6)

PA5 (AD5)

PA4 (AD4)

PA3 (AD3)

PA

0 (A

D0)

PA

1 (A

D1)

PA

2 (A

D2)

(RX

CA

N /

T1) P

D6

(TX

CA

N /

XC

K1)

PD

5

(IC

P1)

PD

4

(TX

D1

/ IN

T3) P

D3

(RX

D1

/ IN

T2) P

D2

(SD

A /

INT1

) PD

1

(SC

L / I

NT0

) PD

0

XTA

L1

XTA

L2

RE

SE

T

GN

D

VC

C

PG1 (RD)

PG0 (WR)

2

3

1

4

5

6

7

8

9

10

11

12

13

14

16 33

15

47

46

48

45

44

43

42

41

40

39

38

37

36

35

34

(2)

(2)

NC(1)

17 18 2019 21 22 23 24 25 26 27 2928 323130

52 51 50 4964 63 62 5361 60 59 58 57 56 55 54

(64-lead QFN top view)

INDEX CORNER

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AT90CAN32/64/128

AT90CAN32/64/128

1.6.3 Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort A output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port A pins that are externally pulled low will source current if the pull-upresistors are activated. The Port A pins are tri-stated when a reset condition becomes active,even if the clock is not running.

Port A also serves the functions of various special features of the AT90CAN32/64/128 as listedon page 74.

1.6.4 Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.

Port B also serves the functions of various special features of the AT90CAN32/64/128 as listedon page 76.

1.6.5 Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort C output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.

Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page78.

1.6.6 Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.

Port D also serves the functions of various special features of the AT90CAN32/64/128 as listedon page 80.

1.6.7 Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort E output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port E pins that are externally pulled low will source current if the pull-upresistors are activated. The Port E pins are tri-stated when a reset condition becomes active,even if the clock is not running.

Port E also serves the functions of various special features of the AT90CAN32/64/128 as listedon page 83.

1.6.8 Port F (PF7..PF0)Port F serves as the analog inputs to the A/D Converter.

77679H–CAN–08/08

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pinscan provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-metrical drive characteristics with both high sink and source capability. As inputs, Port F pinsthat are externally pulled low will source current if the pull-up resistors are activated. The Port Fpins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

1.6.9 Port G (PG4..PG0)Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G outputbuffers have symmetrical drive characteristics with both high sink and source capability. Asinputs, Port G pins that are externally pulled low will source current if the pull-up resistors areactivated. The Port G pins are tri-stated when a reset condition becomes active, even if the clockis not running.

Port G also serves the functions of various special features of the AT90CAN32/64/128 as listedon page 88.

1.6.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate areset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteedto generate a reset. The I/O ports of the AVR are immediately reset to their initial state even ifthe clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128.

1.6.11 XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

1.6.12 XTAL2Output from the inverting Oscillator amplifier.

1.6.13 AVCCAVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCCthrough a low-pass filter.

1.6.14 AREFThis is the analog reference pin for the A/D Converter.

2. About Code Examples This documentation contains simple code examples that briefly show how to use various parts ofthe device. These code examples assume that the part specific header file is included beforecompilation. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.

87679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

3. AVR CPU Core

3.1 IntroductionThis section discusses the AVR core architecture in general. The main function of the CPU coreis to ensure correct program execution. The CPU must therefore be able to access memories,perform calculations, control peripherals, and handle interrupts.

3.2 Architectural Overview

Figure 3-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – withseparate memories and buses for program and data. Instructions in the program memory areexecuted with a single level pipelining. While one instruction is being executed, the next instruc-tion is pre-fetched from the program memory. This concept enables instructions to be executedin every clock cycle. The program memory is In-System Reprogrammable Flash memory.

FlashProgramMemory

InstructionRegister

InstructionDecoder

ProgramCounter

Control Lines

32 x 8GeneralPurpose

Registrers

ALU

Statusand Control

I/O Lines

EEPROM

Data Bus 8-bit

DataSRAM

Dire

ct A

ddre

ssin

g

Indi

rect

Add

ress

ing

InterruptUnit

SPIUnit

WatchdogTimer

AnalogComparator

I/O Module 2

I/O Module1

I/O Module n

97679H–CAN–08/08

The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing – enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up tables in Flash program memory. Theseadded function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant anda register. Single register operations can also be executed in the ALU. After an arithmetic opera-tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able todirectly address the whole address space. Most AVR instructions have a single 16-bit word for-mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and theApplication Program section. Both sections have dedicated Lock bits for write and read/writeprotection. The SPM (Store Program Memory) instruction that writes into the Application Flashmemory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on theStack. The Stack is effectively allocated in the general data SRAM, and consequently the Stacksize is only limited by the total SRAM size and the usage of the SRAM. All user programs mustinitialize the SP in the Reset routine (before subroutines or interrupts are executed). The StackPointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessedthrough the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional GlobalInterrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in theInterrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-tion. The lower the Interrupt Vector address, the higher is the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the DataSpace locations following those of the Register File, 0x20 - 0x5F. In addition, theAT90CAN32/64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only theST/STS/STD and LD/LDS/LDD instructions can be used.

3.3 ALU – Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general purposeworking registers. Within a single clock cycle, arithmetic operations between general purposeregisters or between a register and an immediate are executed. The ALU operations are dividedinto three main categories – arithmetic, logical, and bit-functions. Some implementations of thearchitecture also provide a powerful multiplier supporting both signed/unsigned multiplicationand fractional format. See the “Instruction Set Summary” section for a detailed description.

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AT90CAN32/64/128

AT90CAN32/64/128

3.4 Status RegisterThe Status Register contains information about the result of the most recently executed arith-metic instruction. This information can be used for altering program flow in order to performconditional operations. Note that the Status Register is updated after all ALU operations, asspecified in the Instruction Set Reference. This will in many cases remove the need for using thededicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restoredwhen returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set to enabled the interrupts. The individual interruptenable control is then performed in separate control registers. If the Global Interrupt EnableRegister is cleared, none of the interrupts are enabled independent of the individual interruptenable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set bythe RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared bythe application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-nation for the operated bit. A bit from a register in the Register File can be copied into T by theBST instruction, and a bit in T can be copied into a bit in a register in the Register File by theBLD instruction.

• Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is usefulin BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ VThe S-bit is always an EXCLUSIVE OR between the negative flag N and the Two’s ComplementOverflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “InstructionSet Description” for detailed information.

Bit 7 6 5 4 3 2 1 0

I T H S V N Z C SREGRead/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

117679H–CAN–08/08

• Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.

3.5 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achievethe required performance and flexibility, the following input/output schemes are supported by theRegister File:

• One 8-bit output operand and one 8-bit result input• Two 8-bit output operands and one 8-bit result input• Two 8-bit output operands and one 16-bit result input• One 16-bit output operand and one 16-bit result input

Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 3-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, andmost of them are single cycle instructions.

As shown in Figure 3-2, each register is also assigned a data memory address, mapping themdirectly into the first 32 locations of the user Data Space. Although not being physically imple-mented as SRAM locations, this memory organization provides great flexibility in access of theregisters, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

3.5.1 The X-register, Y-register, and Z-registerThe registers R26..R31 have some added functions to their general purpose usage. These reg-isters are 16-bit address pointers for indirect addressing of the data space. The three indirectaddress registers X, Y, and Z are defined as described in Figure 3-3.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

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AT90CAN32/64/128

AT90CAN32/64/128

Figure 3-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the instruction set reference for details).

3.5.2 Extended Z-pointer Register for ELPM/SPM – RAMPZ

• Bits 7..1 – Res: Reserved BitsThese bits are reserved for future use and will always read as zero. For compatibility with futuredevices, be sure to write to write them to zero.

• Bit 0 – RAMPZ0: Extended RAM Page Z-pointerThe RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-pointer. As the AT90CAN32/64/128 does not support more than 64K of SRAM memory, this reg-ister is used only to select which page in the program memory is accessed when the ELPM/SPMinstruction is used. The different settings of the RAMPZ0 bit have the following effects:

– AT90CAN32 and AT90CAN64: RAMPZ0 exists as register bit but it is not used forprogram memory addressing.

– AT90CAN128: RAMPZ0 exists as register bit and it is used for program memoryaddressing.

Figure 3-4. The Z-pointer used by ELPM and SPM

Note: LPM (different of ELPM) is never affected by the RAMPZ setting.

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

Bit 7 6 5 4 3 2 1 0

– – – – – – – RAMPZ0 RAMPZRead/Write R R R R R R R R/W


RAMPZ0 = 0: Program memory address 0x0000 - 0x7FFF (lower 64K bytes) is accessed byELPM/SPM

RAMPZ0 = 1: Program memory address 0x8000 - 0xFFFF (higher 64K bytes) is accessed byELPM/SPM

RAMPZ ZH ZL

7Bit (Individually) 0 7 0 7 0

23Bit (Z-pointer) 16 15 8 7 0

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3.6 Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for storingreturn addresses after interrupts and subroutine calls. The Stack Pointer Register always pointsto the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-tions to lower memory locations. This implies that a Stack PUSH command decreases the StackPointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and InterruptStacks are located. This Stack space in the data SRAM must be defined by the program beforeany subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set topoint above 0xFF. The Stack Pointer is decremented by one when data is pushed onto the Stackwith the PUSH instruction, and it is decremented by two when the return address is pushed ontothe Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data ispopped from the Stack with the POP instruction, and it is incremented by two when data ispopped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number ofbits actually used is implementation dependent. Note that the data space in some implementa-tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Registerwill not be present.

3.7 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The AVRCPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for thechip. No internal clock division is used.

Figure 3-5 shows the parallel instruction fetches and instruction executions enabled by the Har-vard architecture and the fast-access Register File concept. This is the basic pipelining conceptto obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,functions per clocks, and functions per power-unit.

Figure 3-5. The Parallel Instruction Fetches and Instruction Executions

Bit 15 14 13 12 11 10 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPHSP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W


0 0 0 0 0 0 0 0

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd Instruction Execute

3rd Instruction Fetch3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

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AT90CAN32/64/128

AT90CAN32/64/128

Figure 3-6 shows the internal timing concept for the Register File. In a single clock cycle an ALUoperation using two register operands is executed, and the result is stored back to the destina-tion register.

Figure 3-6. Single Cycle ALU Operation

3.8 Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the separate ResetVector each have a separate program vector in the program memory space. All interrupts areassigned individual enable bits which must be written logic one together with the Global InterruptEnable bit in the Status Register in order to enable the interrupt. Depending on the ProgramCounter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12are programmed. This feature improves software security. See the section “Memory Program-ming” on page 336 for details.

The lowest addresses in the program memory space are by default defined as the Reset andInterrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 60. The list alsodetermines the priority levels of the different interrupts. The lower the address the higher is thepriority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSELbit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information.The Reset Vector can also be moved to the start of the Boot Flash section by programming theBOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page321.

3.8.1 Interrupt BehaviorWhen an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabledinterrupts can then interrupt the current interrupt routine. The I-bit is automatically set when aReturn from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets theinterrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vectorin order to execute the interrupt handling routine, and hardware clears the corresponding inter-rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to becleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is clearedby software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enablebit is cleared, the corresponding interrupt flag(s) will be set and remembered until the GlobalInterrupt Enable bit is set, and will then be executed by order of priority.

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

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The second type of interrupts will trigger as long as the interrupt condition is present. Theseinterrupts do not necessarily have interrupt flags. If the interrupt condition disappears before theinterrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute onemore instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, norrestored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with theCLI instruction. The following example shows how this can be used to avoid interrupts during thetimed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any pending interrupts, as shown in this example.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1

AT90CAN32/64/128

3.8.2 Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-mum. After four clock cycles the program vector address for the actual interrupt handling routineis executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. Ifan interrupt occurs during execution of a multi-cycle instruction, this instruction is completedbefore the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interruptexecution response time is increased by four clock cycles. This increase comes in addition to thestart-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clockcycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer isincremented by two, and the I-bit in SREG is set.

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4. MemoriesThis section describes the different memories in the AT90CAN32/64/128. The AVR architecturehas two main memory spaces, the Data Memory and the Program Memory space. In addition,the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three memoryspaces are linear and regular.

Notes: 1. Byte address.2. Word (16-bit) address.

4.1 In-System Reprogrammable Flash Program Memory The AT90CAN32/64/128 contains On-chip In-System Reprogrammable Flash memory for pro-gram storage (see “Flash size”). Since all AVR instructions are 16 or 32 bits wide, the Flash isorganized as 16 bits wide. For software security, the Flash Program memory space is dividedinto two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 wri te/erase cycles. TheAT90CAN32/64/128 Program Counter (PC) address the program memory locations. The opera-tion of Boot Program section and associated Boot Lock bits for software protection are describedin detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 321. “MemoryProgramming” on page 336 contains a detailed description on Flash data serial downloadingusing the SPI pins or the JTAG interface.

Table 4-1. Memory Mapping.Memory Mnemonic AT90CAN32 AT90CAN64 AT90CAN128

Flash

Size Flash size 32 K bytes 64 K bytes 128 K bytesStart Address - 0x00000

End Address Flash end0x07FFF(1)

0x3FFF(2)0x0FFFF(1)

0x7FFF(2)0x1FFFF(1)

0xFFFF(2)

32 Registers

Size - 32 bytesStart Address - 0x0000End Address - 0x001F

I/ORegisters

Size - 64 bytesStart Address - 0x0020End Address - 0x005F

Ext I/ORegisters

Size - 160 bytesStart Address - 0x0060End Address - 0x00FF

InternalSRAM

Size ISRAM size 2 K bytes 4 K bytes 4 K bytesStart Address ISRAM start 0x0100End Address ISRAM end 0x08FF 0x10FF 0x10FF

ExternalMemory

Size XMem size 0-64 K bytesStart Address XMem start 0x0900 0x1100 0x1100End Address XMem end 0xFFFF

EEPROM

Size E2 size 1 K bytes 2 K bytes 4 K bytesStart Address - 0x0000End Address E2 end 0x03FF 0x07FF 0x0FFF

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AT90CAN32/64/128

Constant tables can be allocated within the entire program memory address space (see theLPM – Load Program Memory and ELPM – Extended Load Program Memory instructiondescription).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-ing” on page 14.

Figure 4-1. Program Memory Map

4.2 SRAM Data MemoryFigure 4-2 shows how the AT90CAN32/64/128 SRAM Memory is organized.

The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can besupported within the 64 locations reserved in the Opcode for the IN and OUT instructions. Forthe Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can beused.

The lower data memory locations address both the Register File, the I/O memory, Extended I/Omemory, and the internal data SRAM. The first 32 locations address the Register File, the next64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the nextlocations address the internal data SRAM (see “ISRAM size”).

An optional external data SRAM can be used with the AT90CAN32/64/128. This SRAM willoccupy an area in the remaining address locations in the 64K address space. This area starts atthe address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAMoccupies the lowest bytes, so when using 64 KB (65,536 bytes) of External Memory,“XMem size” bytes of External Memory are available. See “External Memory Interface” on page27 for details on how to take advantage of the external memory map.

0x0000

Flash end

Program Memory

Application Flash Section

Boot Flash Section

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4.2.1 SRAM Data AccessWhen the addresses accessing the SRAM memory space exceeds the internal data memorylocations, the external data SRAM is accessed using the same instructions as for the internaldata memory access. When the internal data memories are accessed, the read and write strobepins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation isenabled by setting the SRE bit in the XMCRA Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of theinternal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POPtake one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutinecalls and returns take three clock cycles extra because the two-byte program counter is pushedand popped, and external memory access does not take advantage of the internal pipe-linememory access. When external SRAM interface is used with wait-state, one-byte externalaccess takes two, three, or four additional clock cycles for one, two, and three wait-statesrespectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cyclesmore than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the RegisterFile, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address givenby the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, andthe “ISRAM size” bytes of internal data SRAM in the AT90CAN32/64/128 are all accessiblethrough all these addressing modes. The Register File is described in “General Purpose Regis-ter File” on page 12.

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AT90CAN32/64/128

AT90CAN32/64/128

Figure 4-2. Data Memory Map

4.2.2 SRAM Data Access TimesThis section describes the general access timing concepts for internal memory access. Theinternal data SRAM access is performed in two clkCPU cycles as described in Figure 4-3.

Figure 4-3. On-chip Data SRAM Access Cycles

32 Registers64 I/O Registers

Internal SRAM(ISRAM size)

0x0000 - 0x001F 0x0020 - 0x005F

XMem start ISRAM end

0xFFFF

0x0060 - 0x00FF

Data Memory

External SRAM(XMem size)

160 Ext I/O Reg.ISRAM start

clk

WR

RD

Data

Data

Address Address valid

T1 T2 T3

Compute AddressR

ead

Writ

e

CPU

Memory Access Instruction Next Instruction

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4.3 EEPROM Data MemoryThe AT90CAN32/64/128 contains EEPROM memory (see “E2 size”). It is organized as a sepa-rate data space, in which single bytes can be read and written. The EEPROM has an enduranceof at least 100,000 write/erase cycles. The access between the EEPROM and the CPU isdescribed in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-ister, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see“SPI Serial Programming Overview” on page 348, “JTAG Programming Overview” on page 352,and “Parallel Programming Overview” on page 339 respectively.

4.3.1 EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 4-2. A self-timing function, however,lets the user software detect when the next byte can be written. If the user code contains instruc-tions that write the EEPROM, some precautions must be taken. In heavily filtered powersupplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for someperiod of time to run at a voltage lower than specified as minimum for the clock frequency used.See “Preventing EEPROM Corruption” on page 26.for details on how to avoid problems in thesesituations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction isexecuted. When the EEPROM is written, the CPU is halted for two clock cycles before the nextinstruction is executed.

4.3.2 The EEPROM Address Registers – EEARH and EEARL

• Bits 15..12 – Reserved BitsThese bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.

• Bits 11..0 – EEAR11..0: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in theEEPROM space (see “E2 size”). The EEPROM data bytes are addressed linearly between 0and “E2 end”. The initial value of EEAR is undefined. A proper value must be written before theEEPROM may be accessed.

– AT90CAN32: EEAR11 & EEAR10 exist as register bit but they are not used for addressing.

– AT90CAN64: EEAR11 exists as register bit but it is not used for addressing.

Bit 15 14 13 12 11 10 9 8

– – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARHEEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7 6 5 4 3 2 1 0

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X X X X

X X X X X X X X

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AT90CAN32/64/128

4.3.3 The EEPROM Data Register – EEDR

• Bits 7..0 – EEDR7.0: EEPROM DataFor the EEPROM write operation, the EEDR Register contains the data to be written to theEEPROM in the address given by the EEAR Register. For the EEPROM read operation, theEEDR contains the data read out from the EEPROM at the address given by EEAR.

4.3.4 The EEPROM Control Register – EECR

• Bits 7..4 – Reserved BitsThese bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. WritingEERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM atthe selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE hasbeen written to one by software, hardware clears the bit to zero after four clock cycles. See thedescription of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When addressand data are correctly set up, the EEWE bit must be written to one to write the value into theEEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-erwise no EEPROM write takes place. The following procedure should be followed when writingthe EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Mem-

ory Control and Status Register) becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The softwaremust check that the Flash programming is completed before initiating a new EEPROM write.Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program theFlash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Bit 7 6 5 4 3 2 1 0

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDRRead/Write R/W R/W R/W R/W R/W R/W R/W R/W


Bit 7 6 5 4 3 2 1 0

– – – – EERIE EEMWE EEWE EERE EECRRead/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 X 0

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Support – Read-While-Write Self-Programming” on page 321 for details about Bootprogramming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since theEEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM isinterrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing theinterrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag clearedduring all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correctaddress is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger theEEPROM read. The EEPROM read access takes one instruction, and the requested data isavailable immediately. When the EEPROM is read, the CPU is halted for four cycles before thenext instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is inprogress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 4-2 lists the typical pro-gramming time for EEPROM access from the CPU.

Table 4-2. EEPROM Programming Time.

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU) 67 584 8.5 ms

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AT90CAN32/64/128

AT90CAN32/64/128

The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo-bally) so that no interrupts will occur during execution of these functions. The examples alsoassume that no Flash Boot Loader is present in the software. If such code is present, theEEPROM write function must also wait for any ongoing SPM command to finish.


EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write (unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1

The next code examples show assembly and C functions for reading the EEPROM. The exam-ples assume that interrupts are controlled so that no interrupts will occur during execution ofthese functions.

4.3.5 Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage istoo low for the CPU and the EEPROM to operate properly. These issues are the same as forboard level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This canbe done by enabling the internal Brown-out Detector (BOD). If the detection level of the internalBOD does not match the needed detection level, an external low VCC reset Protection circuit canbe used. If a reset occurs while a write operation is in progress, the write operation will be com-pleted provided that the power supply voltage is sufficient.


EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1

AT90CAN32/64/128

4.4 I/O MemoryThe I/O space definition of the AT90CAN32/64/128 is shown in “Register Summary” on page405.

All AT90CAN32/64/128 I/Os and peripherals are placed in the I/O space. All I/O locations maybe accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the32 general purpose working registers and the I/O space. I/O registers within the address range0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, thevalue of single bits can be checked by using the SBIS and SBIC instructions. Refer to theinstruction set section for more details. When using the I/O specific commands IN and OUT, theI/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space usingLD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is acomplex microcontroller with more peripheral units than can be supported within the 64 locationreserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most otherAVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore beused on registers containing such status flags. The CBI and SBI instructions work with registers0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

4.5 External Memory InterfaceWith all the features the External Memory Interface provides, it is well suited to operate as aninterface to memory devices such as External SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are:

• Four different wait-state settings (including no wait-state).• Independent wait-state setting for different extErnal Memory sectors (configurable sector

size).• The number of bits dedicated to address high byte is selectable.• Bus keepers on data lines to minimize current consumption (optional).

4.5.1 OverviewWhen the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAMbecomes available using the dedicated External Memory pins (see Figure 1-2 on page 5 or Fig-ure 1-3 on page 6, Table 9-3 on page 74, Table 9-9 on page 78, and Table 9-21 on page 88).The memory configuration is shown in Figure 4-4.

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Figure 4-4. External Memory with Sector Select

4.5.2 Using the External Memory InterfaceThe interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus.• A15:8: High-order address bus (configurable number of bits).• ALE: Address latch enable.• RD: Read strobe.• WR: Write strobe.

The control bits for the External Memory Interface are located in two registers, the ExternalMemory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the datadirection registers that corresponds to the ports dedicated to the XMEM interface. For detailsabout the port override, see the alternate functions in section “I/O-Ports” on page 66. The XMEMinterface will auto-detect whether an access is internal or external. If the access is external, theXMEM interface will output address, data, and the control signals on the ports according to Fig-ure 4-6 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low,there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interfaceis enabled, also an internal access will cause activity on address, data and ALE ports, but theRD and WR strobes will not toggle during internal access. When the External Memory Interfaceis disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-face is disabled, the address space above the internal SRAM boundary is not mapped into theinternal SRAM. Figure 4-5 illustrates how to connect an external SRAM to the AVR using anoctal latch (typically “74x573” or equivalent) which is transparent when G is high.

0x0000

ISRAM end

External Memory(0-64K x 8)

0xFFFF

Internal memory

SRL[2..0]

SRW11SRW10

SRW01SRW00

Lower sector

Upper sector

XMem start

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AT90CAN32/64/128

AT90CAN32/64/128

4.5.3 Address Latch RequirementsDue to the high-speed operation of the XRAM interface, the address latch must be selected withcare for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-tions above these frequencies, the typical old style 74HC series latch becomes inadequate. TheExternal Memory Interface is designed in compliance to the 74AHC series latch. However, mostlatches can be used as long they comply with the main timing parameters. The main parametersfor the address latch are:

• D to Q propagation delay (tPD).• Data setup time before G low (tSU).• Data (address) hold time after G low (TH).

The External Memory Interface is designed to guaranty minimum address hold time after G isasserted low of th = 5 ns. Refer to tLAXX_LD / tLLAXX_ST in Table 26-7 through Table 26-14 of Sec-tion 26.9 on page 375. The D-to-Q propagation delay (tPD) must be taken into considerationwhen calculating the access time requirement of the external component. The data setup timebefore G low (tSU) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring delay(dependent on the capacitive load).

Figure 4-5. External SRAM Connected to the AVR

4.5.4 Pull-up and Bus-keeperThe pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written toone. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups bywriting the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-abled and enabled in software as described in “External Memory Control Register B – XMCRB”on page 33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on theAD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.

4.5.5 TimingExternal Memory devices have different timing requirements. To meet these requirements, theAT90CAN32/64/128 XMEM interface provides four different wait-states as shown in Table 4-4. Itis important to consider the timing specification of the External Memory device before selectingthe wait-state. The most important parameters are the access time for the external memorycompared to the set-up requirement of the AT90CAN32/64/128. The access time for the Exter-nal Memory is defined to be the time from receiving the chip select/address until the data of this

D[7:0]

A[7:0]

A[15:8]

RDWR

SRAM

D Q

G

AD7:0

ALE

A15:8RDWR

AVR

297679H–CAN–08/08

address actually is driven on the bus. The access time cannot exceed the time from the ALEpulse must be asserted low until data is stable during a read sequence (see tLLRL+ tRLRH - tDVRHin Table 26-7 through Table 26-14). The different wait-states are set up in software. As an addi-tional feature, it is possible to divide the external memory space in two sectors with individualwait-state settings. This makes it possible to connect two different memory devices with differenttiming requirements to the same XMEM interface. For XMEM interface timing details, pleaserefer to Table 26-7 through Table 26-14 and Figure 26-6 to Figure 26-9 in the “External DataMemory Characteristics” on page 375.

Note that the XMEM interface is asynchronous and that the waveforms in the following figuresare related to the internal system clock. The skew between the internal and external clock(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-quently, the XMEM interface is not suited for synchronous operation.

Figure 4-6. External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

Figure 4-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

ALE

T1 T2 T3

Writ

eR

ead

WR

T4

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

RD

DA7:0 (XMBK = 0) DataPrev. data Address

DataPrev. data AddressDA7:0 (XMBK = 1)

System Clock (CLKCPU)

XXXXX XXXXXXXX

ALE

T1 T2 T3

Writ

eR

ead

WR

T5



RD




T4

307679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).





ALE

T1 T2 T3

Writ

eR

ead

WR

T6



RD




T4 T5

ALE

T1 T2 T3

Writ

eR

ead

WR

T7



RD




T4 T5 T6

317679H–CAN–08/08

4.5.6 External Memory Control Register A – XMCRA

• Bit 7 – SRE: External SRAM/XMEM EnableWriting SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pindirection settings in the respective data direction registers. Writing SRE to zero, disables theExternal Memory Interface and the normal pin and data direction settings are used. Note thatwhen the XMEM interface is disabled, the address space above the internal SRAM boundary isnot mapped into the internal SRAM.

• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector LimitIt is possible to configure different wait-states for different External Memory addresses. Theexternal memory address space can be divided in two sectors that have separate wait-state bits.The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 4-3 and Figure 4-4. Bydefault, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory addressspace is treated as one sector. When the entire SRAM address space is configured as one sec-tor, the wait-states are configured by the SRW11 and SRW10 bits.

Note: 1. See Table 4-1 on page 18 for “XMem start” setting.

Bit 7 6 5 4 3 2 1 0

SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 XMCRARead/Write R/W R/W R/W R/W R/W R/W R/W R/W


Table 4-3. Sector limits with different settings of SRL2..0

SRL2 SRL1 SRL0 Sector Addressing

0 0 0Lower sector N/A

Upper sector “XMem start”(1) - 0xFFFF

0 0 1Lower sector “XMem start”(1) - 0x1FFF

Upper sector 0x2000 - 0xFFFF








Upper sector 0xA000 - 0xFFFF

1 1 0Lower sector “XMem start”(1) - 0xBFFF

Upper sector 0xC000 - 0xFFFF

1 1 1Lower sector “XMem start”(1) - 0xDFFF

Upper sector 0xE000 - 0xFFFF

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AT90CAN32/64/128

AT90CAN32/64/128

• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper SectorThe SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-nal memory address space, see Table 4-4.

• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower SectorThe SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-nal memory address space, see Table 4-4.

Note: 1. n = 0 or 1 (lower/upper sector).For further details of the timing and wait-states of the External Memory Interface, see Figures 4-6 through Figures 4-9 for how the setting of the SRW bits affects the timing.

4.5.7 External Memory Control Register B – XMCRB

• Bit 7– XMBK: External Memory Bus-keeper EnableWriting XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper isenabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwisebe tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, soeven if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK isone.

• Bit 6..4 – Reserved BitsThese are reserved bits and will always read as zero. When writing to this address location,write these bits to zero for compatibility with future devices.

• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High MaskWhen the External Memory is enabled, all Port C pins are default used for the high address byte.If the full address space is not required to access the External Memory, some, or all, Port C pinscan be released for normal Port Pin function as described in Table 4-5. As described in “Usingall 64KB Locations of External Memory” on page 35, it is possible to use the XMMn bits toaccess all 64KB locations of the External Memory.

Table 4-4. Wait States(1)

SRWn1 SRWn0 Wait States

0 0 No wait-states

0 1 Wait one cycle during read/write strobe

1 0 Wait two cycles during read/write strobe

1 1 Wait two cycles during read/write and wait one cycle before driving out new address

Bit 7 6 5 4 3 2 1 0

XMBK – – – – XMM2 XMM1 XMM0 XMCRBRead/Write R/W R R R R R/W R/W R/W


337679H–CAN–08/08

4.5.8 Using all Locations of External Memory Smaller than 64 KBSince the external memory is mapped after the internal memory as shown in Figure 4-4, theexternal memory is not addressed when addressing the first “ISRAM size” bytes of data space. Itmay appear that the first “ISRAM size” bytes of the external memory are inaccessible (externalmemory addresses 0x0000 to “ISRAM end”). However, when connecting an external memorysmaller than 64 KB, for example 32 KB, these locations are easily accessed simply by address-ing from address 0x8000 to “ISRAM end + 0x8000”. Since the External Memory Address bit A15is not connected to the external memory, addresses 0x8000 to “ISRAM end + 0x8000” willappear as addresses 0x0000 to “ISRAM end” for the external memory. Addressing aboveaddress “ISRAM end + 0x8000” is not recommended, since this will address an external mem-ory location that is already accessed by another (lower) address. To the Application software,the external 32 KB memory will appear as one linear 32 KB address space from “XMem start” to“XMem start + 0x8000”. This is illustrated in Figure 4-10.

Figure 4-10. Address Map with 32 KB External Memory

Table 4-5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins

0 0 0 8 (Full External Memory Space) None

0 0 1 7 PC7

0 1 0 6 PC7 .. PC6

0 1 1 5 PC7 .. PC5

1 0 0 4 PC7 .. PC4

1 0 1 3 PC7 .. PC3

1 1 0 2 PC7 .. PC2

1 1 1 No Address high bits Full Port C

(Unused)

Internal Memory0x0000

XMem startISRAM end

0xFFFF

AVR Memory Map

External Memory

0x80000x7FFF

XMem start + 0x8000ISRAM end + 0x8000

External 32K SRAM (Size=0x8000)

0x7FFF

0x0000

XMem start ISRAM end

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AT90CAN32/64/128

AT90CAN32/64/128

4.5.9 Using all 64KB Locations of External MemorySince the External Memory is mapped after the Internal Memory as shown in Figure 4-4, only(64K-(“ISRAM size”+256)) bytes of External Memory is available by default (address space0x0000 to “ISRAM end” is reserved for internal memory). However, it is possible to take advan-tage of the entire External Memory by masking the higher address bits to zero. This can be doneby using the XMMn bits and control by software the most significant bits of the address. By set-ting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation,the Memory Interface will address 0x0000 - 0x1FFF. See the following code examples.

Note: 1. The example code assumes that the part specific header file is included.Care must be exercised using this option as most of the memory is masked away.

Assembly Code Example(1)

; OFFSET is defined to 0x2000 to ensure; external memory access; Configure Port C (address high byte) to; output 0x00 when the pins are released; for normal Port Pin operation

ldi r16, 0xFFout DDRC, r16ldi r16, 0x00out PORTC, r16; release PC7:5ldi r16, (1

4.6 General Purpose I/O RegistersThe AT90CAN32/64/128 contains three General Purpose I/O Registers. These registers can beused for storing any information, and they are particularly useful for storing global variables andstatus flags.

The General Purpose I/O Register 0, within the address range 0x00 - 0x1F, is directly bit-acces-sible using the SBI, CBI, SBIS, and SBIC instructions.

4.6.1 General Purpose I/O Register 0 – GPIOR0



Bit 7 6 5 4 3 2 1 0

GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 GPIOR0Read/Write R/W R/W R/W R/W R/W R/W R/W R/W


Bit 7 6 5 4 3 2 1 0



Bit 7 6 5 4 3 2 1 0



367679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

5. System Clock

5.1 Clock Systems and their DistributionFigure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocksneed not be active at a given time. In order to reduce power consumption, the clocks to unusedmodules can be halted by using different sleep modes, as described in “Power Management andSleep Modes” on page 46. The clock systems are detailed below.

Figure 5-1. Clock Distribution

5.1.1 CPU Clock – clkCPUThe CPU clock is routed to parts of the system concerned with operation of the AVR core.Examples of such modules are the General Purpose Register File, the Status Register and thedata memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performinggeneral operations and calculations.

5.1.2 I/O Clock – clkI/OThe I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, CAN,USART. The I/O clock is also used by the External Interrupt module, but note that some externalinterrupts are detected by asynchronous logic, allowing such interrupts to be detected even if theI/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro-nously when clkI/O is halted, enabling TWI address reception in all sleep modes.

5.1.3 Flash Clock – clkFLASHThe Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-taneously with the CPU clock.

General I/OModules

CANController CPU Core RAM

clkI/O

clkASY

AVR ClockControl Unit

clkCPU

Flash andEEPROM

clkFLASH

Source clock

Watchdog Timer

WatchdogOscillator

Reset Logic

Prescaler

ClockMultiplexerMultiplexer

CKOUT Fuse

CLKO

Watchdog clock

Calibrated RCOscillator

Timer/Counter2OscillatorExternal Clock

CrystalOscillator

Low-frequencyCrystal OscillatorExternal Clock

ADC

clkADC

AsynchronousTimer/Counter2

Timer/Counter2

TOSC2 XTAL2TOSC1 XTAL1

377679H–CAN–08/08

5.1.4 Asynchronous Timer Clock – clkASYThe Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directlyfrom an external clock or an external 32 kHz clock crystal. The dedicated clock domain allowsusing this Timer/Counter as a real-time counter even when the device is in sleep mode.

5.1.5 ADC Clock – clkADCThe ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocksin order to reduce noise generated by digital circuitry. This gives more accurate ADC conversionresults.

5.2 Clock SourcesThe device has the following clock source options, selectable by Flash Fuse bits as shownbelow. The clock from the selected source is input to the AVR clock generator, and routed to theappropriate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPUwakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU startsfrom reset, there is an additional delay allowing the power to reach a stable level before startingnormal operation. The Watchdog Oscillator is used for timing this real-time part of the start-uptime. The number of WDT Oscillator cycles used for each time-out is shown in Table 5-2. Thefrequency of the Watchdog Oscillator is voltage dependent as shown in “AT90CAN32/64/128Typical Characteristics” on page 384.

5.3 Default Clock SourceThe device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The defaultclock source setting is the Internal RC Oscillator with longest start-up time and an initial systemclock prescaling of 8. This default setting ensures that all users can make their desired clocksource setting using an In-System or Parallel programmer.

Table 5-1. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000

External Low-frequency Crystal 0111 - 0100

Calibrated Internal RC Oscillator 0010

External Clock 0000

Reserved 0011, 0001

Table 5-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K (65,536)

387679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

5.4 Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-figured for use as an On-chip Oscillator, as shown in Figure 5-2. Either a quartz crystal or aceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of thecapacitors depends on the crystal or resonator in use, the amount of stray capacitance, and theelectromagnetic noise of the environment. Some initial guidelines for choosing capacitors foruse with crystals are given in Table 5-3. For ceramic resonators, the capacitor values given bythe manufacturer should be used. For more information on how to choose capacitors and otherdetails on Oscillator operation, refer to the Multi-purpose Oscillator Application Note.

Figure 5-2. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific frequencyrange. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5-3.

Note: 1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table5-4.

Table 5-3. Crystal Oscillator Operating Modes

CKSEL3..1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF)

100(1) 0.4 - 0.9 12 - 22

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 16.0 12 - 22

XTAL2

XTAL1

GND

C2

C1

397679H–CAN–08/08

Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre-quency of the device, and if frequency stability at start-up is not important for the application.

5.5 Low-frequency Crystal OscillatorTo use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystalOscillator must be selected by setting the CKSEL Fuses to “0100”, “0101”, “0110”, or “0111”.The crystal should be connected as shown in Figure 5-3.

Figure 5-3. Low-frequency Crystal Oscillator Connections

12-22 pF capacitors may be necessary if the parasitic impedance (pads, wires & PCB) is verylow.

Table 5-4. Start-up Times for the Oscillator Clock Selection

CKSEL0 SUT1..0Start-up Time from Power-down and

Power-save

Additional Delay from Reset (VCC = 5.0V)

Recommended Usage

0 00 258 CK(1) 14 CK + 4.1 ms Ceramic resonator, fast rising power

0 01 258 CK(1) 14 CK + 65 ms Ceramic resonator, slowly rising power

0 10 1K CK(2) 14 CK Ceramic resonator, BOD enabled

0 11 1K CK(2) 14 CK + 4.1 ms Ceramic resonator, fast rising power

1 00 1K CK(2) 14 CK + 65 ms Ceramic resonator, slowly rising power

1 01 16K CK 14 CK Crystal Oscillator, BOD enabled

1 10 16K CK 14 CK + 4.1 ms Crystal Oscillator, fast rising power

1 11 16K CK 14 CK + 65 ms Crystal Oscillator, slowly rising power

XTAL2

XTAL1

GND

12 - 22 pF

12 - 22 pF

32.768 KHz

407679H–CAN–08/08

AT90CAN32/64/128

AT90CAN32/64/128

When this Oscillator is selected, start-up times are determined by the SUT1..0 fuses as shown inTable 5-5 and CKSEL1..0 fuses as shown in Table 5-6.

Note: 1. These options should only be used if frequency stability at start-up is not important for the application

5.6 Calibrated Internal RC OscillatorThe calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominalvalue at 3V and 25°C. If 8 MHz frequency exceeds the specification of the device (depends onVCC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 dur-ing start-up. The device is shipped with the CKDIV8 Fuse programmed. See “System ClockPrescaler” on page 44. for more details. This clock may be selected as the system clock by pro-gramming the CKSEL Fuses as shown in Table 5-7. If selected, it will operate with no externalcomponents. During reset, hardware loads the calibration byte into the OSCCAL Register andthereby automatically calibrates the RC Oscillator. At 5V and 25°C, this calibration gives a fre-quency within ± 10% of the nominal frequency. Using calibration methods as described inapplication notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at anygiven VCC and temperature. When this Oscillator is used as the chip clock, the Watchdog Oscil-lator will still be used for the Watchdog Timer and for the Reset Time-out. For more informationon the pre-programmed calibration value, see the section “Calibration Byte” on page 339.

Note: 1. The device is shipped with this option selected.

Table 5-5. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 14 CK Fast rising power or BOD enabled

01 14 CK + 4.1 ms Slowly rising power

10 14 CK + 65 ms Stable frequency at start-up

11 Reserved

Table 5-6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL3..0 Start-up Time from Power-down and Power-save Recommended Usage

0100(1) 1K CK

0101 32K CK Stable frequency at start-up

0110(1) 1K CK

0111 32K CK Stable frequency at start-up

Table 5-7. Internal Calibrated RC Oscillator Operating Modes(1)

CKSEL3..0 Nominal Frequency

0010 8.0 MHz

417679H–CAN–08/08

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown inTable 5-8.

Note: 1. The device is shipped with this option selected.

5.6.1 Oscillator Calibration Register – OSCCAL

• Bit 7 – Reserved BitThis bit is reserved for future use.

• Bits 6..0 – CAL6..0: Oscillator Calibration ValueWriting the calibration byte to this address will trim the internal Oscillator to remove process vari-ations from the Oscillator frequency. This is done automatically during Chip Reset. WhenOSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this regis-ter will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives thehighest available frequency. The calibrated Oscillator is used to time EEPROM and Flashaccess. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal fre-quency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended forcalibration to 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 5-9.

5.7 External ClockTo drive the device from an external clock source, XTAL1 should be driven as shown in Figure5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Table 5-8. Start-up times for the internal calibrated RC Oscillator clock selection

SUT1..0 Start-up Time from Power-down and Power-saveAdditional Delay from

Reset (VCC = 5.0V)Recommended Usage

00 6 CK 14 CK BOD enabled

01 6 CK 14 CK + 4.1 ms Fast rising power

10(1) 6 CK 14 CK + 65 ms Slowly rising power

11 Reserved

Bit 7 6 5 4 3 2 1 0

– CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCALRead/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0

Table 5-9. Internal RC Oscillator Frequency Range.

OSCCAL Value Min Frequency

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