At-Speed Test Considering Deep Submicron Effects...At-Speed Test Considering Deep Submicron Effects...
Transcript of At-Speed Test Considering Deep Submicron Effects...At-Speed Test Considering Deep Submicron Effects...
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At-Speed Test Considering Deep Submicron Effects
D. M. H. WalkerDept. of Computer Science
Texas A&M [email protected]
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Integrated Circuit Testing
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IC Test – What’s Going On
DUT(DeviceUnderTest)
TestGeneration
ATE(Automatic
TestEquipment)
TestPatterns
Go/No Go(Failure Details)
Stimulus
Response
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Types of Tests for Digital Circuits
• Functional– Apply tests according to spec– Random patterns
• Structural– Verify structures in place– Use a fault model
• Test speed– Slow - boolean tests – find short/open– Fast - at-speed tests – find extra delay
• Focus in this talk is at-speed structural test
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0.1
1
10
100
2005 2010 2015 2020Year
Cost/Xistor
(μcents)
Test Cost Must Fall Fast
• Test cost/transistor must follow Moore’s Law
ITRS2005, Cost-Perf MPU
Need 100xtransistortest cost
reduction!
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But …
• Test cell cost not following Moore’s Law– Already using DFT tester or old ATE– Handler and probe card cost not scaling– High-speed I/Os cost more
Must reduce test time• Parallel testing running out of gas
Must reduce test time per transistor– Constant test time per chip
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Reducing Test Time Per Transistor
• Less time, more transistors ⇒ must wiggle more wires in less time
Higher power dissipation• But… tests/transistor rising to cope
with DSM
Even higher power dissipation
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But … Max Power/Transistor is Falling
10
100
1000
2005 2010 2015 2020
Year
nW/xistor
ITRS2005, Cost-Perf MPU
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Future Digital Test All About Power?
• Fraction of chip that can be fired up at one time is decreasing– Mission-mode power constraints– Test supply noise– Test thermal limits– Limits intra-die test parallelism
• How to screen most defects per Joule?
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Eliminate Wasted Energy
• Useless transitions– Scan power– Unnecessary capture power– Much research/commercial activity
• Low-odds test patterns– Luck – tails of BIST, WRP– Shotgun blasts – N-detect, DOREME,
TARO, …
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Squeeze Chip Harder Instead
• IDDQ
• MINVDD
• …
• Small Delay Defect– KLPG
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Our Delay Test Research
• Defect-Based Delay test ATPG considering:– Resistive shorts and opens– Process variation– Capacitive crosstalk– Temperature gradients– Power supply noise– Power dissipation
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Kitchen Sink Fault Model
Spot Defect Process Variation
LocalDelay Fault
GlobalDelay Fault
CombinedDelay Fault
FunctionalFailure
ReliabilityHazard
Noise
Supply Temp
Crosstalk
Intra-Die
Die-to-Die
Litho
Have we forgotten anything?
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Target Realistic Defects
Resistive OpenMadge et al
Resistive ShortStanojevic et al
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But…
• Fault population too large
• Limited fault model accuracy
• Limited fab data
• Limited calibration time, cost
• Fault model must be abstract enough for fortuitous detection of unmodeled faults– “The vectors do the work, not the fault
model” – J. H. Patel
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Our Approach
• Test K longest rising/falling paths through each gate/line (KLPG)– Targets resistive shorts and opens– Larger K deals with delay uncertainty
• Supply noise• Process variation• Delay modeling errors• Crosstalk
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K Longest Paths Per Gate (KLPG)
• CodGen ATPG developed at Texas A&M– CodSim fault simulator
• Tests K longest paths through each gate/line
• Detects small defects on each gate/line– Covers all transition faults
• Needs circuit delay information (SDF)
• May produce more patterns than TF test
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Apply KLPG to Industrial Designs
KLPG Test Generator
TetraMAX/FastScandofile/procfile/library
Hierarchical Verilog Design
K
Test Data
….010001100001....
Test Sequence……Load patternPulse clock......
Same inputs as TF test generation
Tester
sdf
CPU Time:~3x TF test generation
Memory:400 MB/1M gates
Only 0’s & 1’s are different from TF ATPG outputs
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Transition fault test10 ns
KLPG-1 test11 ns
180 nm / 40k gates / full scan / 2.3k scan cells
Chips are Slower Using KLPG Test
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Cleaner Shmoo
Transition Fault KLPG
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KLPG Silicon Experiment
• TI ASIC design– 738K gates (597K gates in 250 MHz clock
domain)– 130 nm technology– 5 clock domains (highest 250 MHz)– 8 scan chains, 14 963 muxed D flip-flops in
250 MHz domain• 24 devices marginally pass regular TF test
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KLPG Test Results
KLPG unique detects
Up to 3% delay decrease seen in KLPG-1
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Dynamic Compaction
Test Set Compaction• Static Compaction
– Performed after test generation• Dynamic Compaction
– Performed during test generation– Classic method good for stuck-at tests but not
suitable for path delay tests
Develop dynamic compaction for KLPG tests
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Dynamic Compaction Approach
Vector pair and NAs (Xs) for Path2
V3XX
1X
X0
XX
I1
I2
I3
I4
I5
I6
O1
O2
O3
O4
O5
O6
xx
x xx Path2
x
B
x
x
O2
O3
O6
O5
Vector pair and NAs for Path1 & 2
V4I1
I2
I3
I4
I5
I6
O1
O4
Path1
1X
00
XX
Ax
x
x xx Path2
x
B
x
x
Vector pair and NAs (circles) for Path1
V2 V1I1
I2
I3
I4
I5
I6
O1
O2
O3
O4
O5
O6
Path1
XX
11
0X
X1
XX
1X
X1
00
X1
XXA
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Test Size (KLPG-1 vs. Transition)
RobustNon-
robustLong
TFTotal
Comm. TF
289 6 7 302 231
24 4 0 28 68
425 41 1 467 365
249 134 70 453 528
1192 452 103 1747 1900
619 687 493 1799 2537
4406 1688 550 6644 1445
s15850
s35932
s38417
s38584
chip1
chip2a
chip3
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Constant Power Dissipation
• Constant power ⇒ ~linear temperature rise• Easy to characterize
– Know temperature for each pattern• Adjust test timing for each pattern
– Circuit slows down as temperature rises– 35-55% delay increase for 100°C rise in 65 nm
• Reorder patterns for constant power dissipation
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s38417 Results
5000000
6000000
7000000
8000000
9000000
10000000
11000000
12000000
13000000
14000000
15000000
1 11 21 31 41 51 61 71 81 91
Group #
Shift
Pow
er
Initial PowerFinal Power
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Conclusions
• Demonstrated KLPG on industrial designs– Modest test data volume increase– Affordable ATPG time increase
• Demonstrated constant power reordering
• Not discussed: supply noise model demonstrated on industrial design
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Questions?