Asynchronous SAR ADC: Past, Present and...
Transcript of Asynchronous SAR ADC: Past, Present and...
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Asynchronous SAR ADC: Past,
Present and Beyond
Mike Shuo-Wei Chen
University of Southern California
MWSCAS 2014
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Roles of ADCs
• Responsibility of ADC is increasing more BW, more dynamic range
• Potentially simplify analog pre-conditioning circuits
• Reconfigurable system imposes more weights on ADC
spec/cost of ADC?
IF Sampling, except IF is becoming RF
Direct RF Sampling
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Who is driving higher speed?
• Low Medium resolution (6bit) with 10-100 GS/s
High speed optical links, instrumentations.
• High Medium resolution (10bit), with 100MS/s to
a few GS/s.
Radars, Commercial Communications, or
wideband radios, such as 60GHz, UWB, SDR,
Cognitive radio.
Power efficiency is a key issue!
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Why possible now?
• Cost of such ADCs used to be intimidating, bounded by Walden wall.
• CMOS technology provides tremendous opportunity.
• Circuit designers enjoy inventing and polishing ADC architectures.
Given the resolution, speed and power efficiency advanced by orders of magnitude over the past decade
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Walden’s ADC Survey
Robert Walden, “Analog-to-Digital Converter Survey and Analysis”, Journal of
selected area in communications, 1999.
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Optimal ADC Architecture?
• Architecture that promotes mostly digital operation
so it scales with CMOS technology
• No high precision analog requirement
• Tolerate low voltage design
• Take advantage of device speed
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ADC Architecture Overview
VrefD
eco
de
rVin
CLK
Vin
De
co
de
r
CLK
DAC
S/H
ADC DAC
+
Stage
1
Stage
N
Stage i
Flash Pipeline SAR
Complexity
Conv. time 7
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Successive Approximation (SAR) Algorithm
• Binary
searching.
• N-bit resolution
requires N
comparisons, i.e.
1 bit per cycle.
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Typical SAR Logic
• N-bit SAR requires at least N+1 cycles.
• Typically, a fast clock is used to divide the time into S/H, and N bit comparison.
• DAC and SAR logic change reference levels.
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DAC Implementation
• Capacitor array to perform sampling and
charge redistribution fast and low
power. This is most commonly used.
• However, other DAC implementations are
possible, such as resistor ladder network
or capacitor-resistor hybrid version.
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Sampling Phase
• Sampling on the capacitive DAC.
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First MSB comparison
• All capacitors are connected to Vcm.
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Second MSB Comparison
• If Vin > 0… The rest of bit conversions
follows.
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Why SAR?
1. Mostly digital components good for
technology scaling
2. No linear, high precision amplification is
required fast, low power
3. Minimal hardware 1 comparator is needed
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Evolving Ecosystem
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SAR ADC in the past 10 years
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Limitation of Synchronous SAR
• Cost
– No redundant comparison
– High-speed internal clock
• Speed limitation
– Worst-case cycle time
– Margin for clock jitter
MSB MSB-1 LSB
Synchronous
Conversion Phase
Tracking
Phase Sampling Instants
MSB-2
Jitter
Internal
CLK
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MSB MSB-1 MSB-2 LSB
Sampling Instants
Tracking
PhaseAsynchronous
Conversion Phase
Gnd
Vref
Vref
Vref
VrefVin
'1'
'0'
'1' Full
Scale
Conversion Time
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85
21
Asynchronous SAR ADC Concept
)ln(ID
FS
m
cmpV
V
g
Ct
t cm
p
VID
M. S.W. Chen, R. Brodersen, “A 6b 600MS/s 5.3mW
Asynchronous ADC in 0.13µm CMOS,” ISSCC 06. Still uniform sampling… 18
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How much time can it save?
• Conv. time between sync. and async. SAR,
assuming regenerative comparator is used.
• It varies with residue voltage profile
Best case
Worst case
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Best Case
• Peak input value yields larger Vres pattern
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Worst Case (I)
• Input with alternative polarity smaller
magnitude
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Worst Case (II)
• As N increases, it approaches ½, same as the
best case!
• Note that: Since there is no synchronous clock
uncertainty, more saving is possible! Actual time
saving depends on input signal characteristics. 22
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Ready
Generator
SR
Latch
Non-Binary
Capacitor
Network
Switch
Logic
&
Bit
Caches
Pulse
Generator
Sequencer
(Multi-Phase CLK)
iCLK0
iCLK6
Vin
Clk0
Clk1
bit0
bit6
SRAM
Vref+
Vref-
2-phase
clock
generation
First Asynchronous SAR ADC
Prototype
Asynchronous digital circuits
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Vb
VinVip
Qn Qp
eq
strobe strobe2a
2aeq
Qp
Qn
Ready
Dynamic Comparator
• Dynamic to save power and generate ready signal
• Reset switches for fast recovery
• Ready signal is generated by NAND gate!
regenerative latch pre-amplifier
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Metastable Issue
NAND gate
threshold
'1' '0' '0' '1' '0' '0'
'1' '1'
large vid moderate
vid
vid~0
(metastable
)
Ready
Signal
Cmp
Outputs
VFS
If a comparison is stuck, SAR conversion won’t be complete!
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Sampling Network
• Series capacitor bank reduces input cap loading
and settling time (C-2C network if α=β=2)
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Die Micrograph
240 µm
250 µ
m1.4 mm
1.7
4 m
m
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Single Async. SAR ADC
• Resolution naturally tradeoffs with sampling rate!
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Single Async. SAR w/ RF Input
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Dual Async. SAR ADCs
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Performance Summary
Technology 0.13-mm 6M CMOS
Package Chip-on-board
Resolution 6 bits
Sampling rate 300-500 MS/s for single ADC
(600M-1GS/s for dual)
Supply voltage 1.2 V
Input 3dB BW > 4 GHz
Peak SNDR 34 dB (fs = 600MS/s for dual ADC)
INL/DNL 0.5 / -0.5 LSB
Power
Analog 1.2mW
Total (dual ADC):
5.3mW Digital 3.2mW
Clock 0.9mW
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Comparison with SOA in 2006
• High-speed (>10MS/s, 6-10b) ADCs from ISSCC (00’-05’)
ENOB
s 2F
Total_PW
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• Constant field scaling (W,L,Vdd ↓ 1/S)
FOM (joule/conversion step) ↓ 1/S2
Technology Scaling
Ttrack Tcomp Tdig
RCH~1/S 1/fT~1/S RC~1/S
Panalog Pclk Pdig
IV~1/S fCV2~[1/S-1/S2] fCV2~1/S2
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Asynchronous SAR Advantages
• Asynchronous SAR architecture breaks
the speed limit of conventional
synchronous design methodology.
• Clock generation requirement is
significantly relaxed.
• It was just the starting point… many
variations can be introduced potentially.
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What’s next?
1. Higher resolution approaching KT/C
limit regime?
2. Higher speed 1-100 GS/s sampling
rate possible?
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Higher Resolution Extension
DAC
Asynchronous
SAR Logic
VINGPassive
DAC
Asynchronous
SAR Logic
VIN
• Traditional Asynchronous SAR
• Proposed Passive Gained Asynchronous SAR
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• Key highlights
Proposed Passive Gained SAR
DAC
Asynchronous
SAR Logic
VIN
𝐃𝐎𝐔𝐓
VN,Comp
VN,Comp
GPassive
Input referred
Noise
GPassive
1. Passive amplifier(Power-less) ► Comparator noise spec.
2. Redundant SAR operation ► Non-linear distortion
due to parasitic Cap.
3. Passively amplified signal ► Comparison time
4. Embedding amplifier into DAC ► DAC settling time
► Full-scaled amplifying O
1
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Mike Chen’s IC Group
• Key highlights
Proposed Passive Gain SAR
DAC
Asynchronous
SAR Logic
VIN
𝐃𝐎𝐔𝐓
VN,Comp
VN,Comp
GPassive
Input referred
Noise
GPassive
1. Passive amplifier(Power-less) ► Comparator noise spec.
2. Redundant SAR operation ► Non-linear distortion
due to parasitic Cap.
3. Passively amplified signal ► Comparison time
4. Embedding amplifier into DAC ► DAC settling time
► Full-scaled amplifying O
2 Converged to
common mode
at the final
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Mike Chen’s IC Group
• Key highlights
Proposed Passive Gain SAR
DAC
Asynchronous
SAR Logic
VIN
𝐃𝐎𝐔𝐓
VN,Comp
VN,Comp
GPassive
Input referred
Noise
GPassive
1. Passive amplifier(Power-less) ► Comparator noise spec.
2. Redundant SAR operation ► Non-linear distortion
due to parasitic Cap.
3. Passively amplified signal ► Comparison time
4. Embedding amplifier into DAC ► DAC settling time
► Full-scaled amplifying O
3 xGPassive
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Mike Chen’s IC Group
• Key highlights
Proposed Passive Gain SAR
DAC
Asynchronous
SAR Logic
VIN
𝐃𝐎𝐔𝐓
VN,Comp
VN,Comp
GPassive
Input referred
Noise
GPassive
1. Passive amplifier(Power-less) ► Comparator noise spec.
2. Redundant SAR operation ► Non-linear distortion
due to parasitic Cap.
3. Passively amplified signal ► Comparison time
4. Embedding GPassive into DAC ► DAC settling time
► Rail-to-rail input swing √
4
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Embedded Passive Gain Operation
VIN
CS1 CS2
CS1 CS2
CS MS1 MS2
Passive
Gain
Split Capacitor
(Double Sampling)
Stacked Capacitor
(Amplification)
-2VIN
-
+
-
+
+
-
+
-
CS
2
CS
2
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Controlling only CS/2 during SAR operation
► DAC response speed
VIN
CS1 CS2
CS1 CS2
CS MS1 MS2
Passive
Gain
-2VIN -2VIN+Vtune
Vtune
SAR
Operation
Subsequent
SAR operation
Embedded Passive Gain Operation
Split Capacitor
(Double Sampling)
Stacked Capacitor
(Amplification)
+
- -
+
+
- -
+
CS
2
CS
2
C-DAC
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VOUT VIN
Voltage Over-range Issue
Φ1
Φ1’
Φ2
Φ2
CS1 Φ1
Φ1’
Φ1 : Sampling VIN to CS1 & CS2 Φ1’
Φ2 Φ2 : Charge Redistribution
Φ1
VX
VIN
+ –
+ –
VIN 0 VX 0 VOUT 0
CS2
- VFS/2
+VFS/2
- VFS/2
+VFS/2
- VFS/2
+VFS/2
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Mike Chen’s IC Group
Voltage Over-range Issue
VIN Φ1
Φ1’
Φ2
Φ2
CS1 Φ1
Φ1’
VOUT
Φ1 : Sampling VIN to CS1 & CS2 Φ1’
Φ2 Φ2 : Charge Redistribution
Φ1
VX
VIN
+ –
+ –
VX 0 VOUT 0 VIN
- VFS/2
0
+VFS/2
Not properly
Turned off
Rail-to-rail
Input Swing [X]
CS2
- VFS/2
+VFS/2
- VFS/2
+VFS/2
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Mike Chen’s IC Group
Proposed Level Shifting
• Procedures
(1) MSB decision by using CS2
(2) Performing Level shifting
VIN Φ1
Φ1’
Φ2
Φ2
CS1
CS2
Φ1
Φ1’
VOUT VX
VIN
+ –
+ –
Comparator
Level Shifting
Circuit
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Mike Chen’s IC Group
Level Shift Up [MSB>0]
0
Level shift up
x2
VIN
CASE – I : VIN = [ -VFS/2, 0 ]
VFS/2
VFS/2
CBAT
CS2
VIN Φ1
Φ3
CS1
Φ1’
Φ1’
+ –
+ –
Φ3
Φ3
VOUT
Comp.
MSB (=D[1]) Φ2
Φ1’
Φ2
Φ1
Φ3 doubled
[MSB-1]
Decision range
Performing at once
VIN
Φ1
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Mike Chen’s IC Group
Level Shift Down [MSB<0]
CASE – II : VIN = [ 0, VFS/2 ]
Level shift down VFS/2
0
VFS/2
VIN
[MSB-1]
Decision range
CBAT
CS2
VIN Φ1
Φ3
CS1
Φ1’
Φ1’
+ –
+ –
Φ3
Φ3
VOUT
Comp.
MSB (=D[1]) Φ2
x2
Performing at once
VIN
Φ1
Φ1’
Φ2
Φ1
Φ3 doubled
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Mike Chen’s IC Group
VOUT
VOUT VIN
VY
+ VFS/2
- VFS/2
VX 0 0 0 0
• Allowing rail-to-rail input signal swing
Free of Voltage Clipping
CBAT
CS2
VIN Φ1
Φ3
CS1
Φ1’
Φ1’
+ –
+ –
Φ3
Φ3
Comp.
Φ2
VIN Φ1
VX
VY
+ VFS/2
- VFS/2
+ VFS/2
- VFS/2
+ VFS/2
- VFS/2
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Mike Chen’s IC Group
Subsequent SAR Operation
CBAT
CS2
VIN
CS1
D[1]
VIN
• CS1 consists of non-binary weighted Cap arrays.
VREF
Asynchronous
SAR Logic
D[2:12]
Φ1’
Φ2 Φ1’
12
𝐕𝐃𝐀𝐂 = 𝐃𝐎𝐔𝐓[𝒊]
𝐑𝐱[𝒊]𝒊∙ 𝑽𝑹𝑬𝑭
𝟏𝟐
𝒊=𝟐
VOUT
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Mike Chen’s IC Group
KT/C Noise Analysis
VIN
Passive
Gain
- 2VIN±VBAT
CBAT
VBAT
CBAT
𝐒𝐍𝐑𝐢 ≝𝑽𝐈𝐍𝑲𝑻𝐂𝒔
Signal Amplitude: 2VIN
RMS V[ KT/C Noise ] : 𝟐𝑲𝑻
𝐂𝒔
SNRO = SNRi
Selecting large size of CBAT
(SNR drops due to CBAT) < 0.5dB
+
-
+
-
-
+
-
+
CBAT
Sampling Phase Amplifying Phase
• Sufficiently large sized CBAT to prevent SNR degradation
CS
2
CS
2
CS
2
CS
2
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Mike Chen’s IC Group
CKRS
CKRS
CKRS
CKRSVINNVINP
VO1N VO1P
VO2PVO2N
CKAMP
CKAMP
CKAMP
VOUTP VOUTN
1st Stage 2nd Stage
Latch
S2
S1
Equalize Amplify
CKAMP
CKRS
S1 :S2 :
ON OFFON ON
S1 >> S2
MP1 MP2
MP3 MP4 MP5 MP6
MN1 MN2 MN3 MN4
MN5 MN6
IS1 IS2
VDD
R1 R2
• Dual sized switches ► Fast Reset (S1)
► Amplifying (S2)
Comparator
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Mike Chen’s IC Group
DAC
Delay T time-out
Asynchronous SAR logic
CKRS
Vdata_ready
SW_CTRL CKAMP, CKRS
Earlier arrived pulse
detected
Vtime-out
VINP
VINN
Sampling Clock
Time-out Scheme
• Forcing the advancement of asynchronous
conversion if comparator is stuck.
Normal Operation Loop
Time-out operation Loop
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Mike Chen’s IC Group
…
SCLK
Env_Conv
Vdata_ready
CKAmp
Vtime-out
…
…
…
Vcomp
Comparator’s
threshold level
1st
Time-out
detect
2nd 3rd
4th Nth
T time-out
T Conv
Code 1 0 1 1 0
• Vtime-out forces next conversion (Ttime-out designed for worst case)
Time-out Timing Diagram
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Mike Chen’s IC Group
260um
280u
m
CDACP
(CS1)
Bootstrap
SW
CDACN
(CS1)
Async.
SAR Logic
CBAT
CS2 CS2
Co
mp
ara
tor
Decimator
CBAT
• Active Area: 280μm X 260μm
Chip Micrograph
J. Nam, D. Chiong, M. S.W. Chen, “A 95-MS/s 11-bit 1.36-mW Asynchronous SAR
ADC with Embedded Passive Gain in 65nm CMOS”, CICC 2013.
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Mike Chen’s IC Group
Static Performance
+1.0
-1.0
0.0
0 2047 [CODE]
+1.0
-1.0
0.0
[LS
B]
DNL (+0.70/-0.84 LSB)
INL (+0.79/-0.84 LSB)
[LS
B]
0 2047 [CODE]
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Mike Chen’s IC Group
-120
-80
-40
0
0 32
3 fS
32
4 fS
32
2 fS
32
fS
Po
wer
(dB
)
SNDR = 63.1 dB
SFDR = 75.2 dB
fIN = 1.0 MHz, fS = 95 MHz
ENOB = 10.2
HD2 HD3 HD5
After Radix Calibration*
Normalized Frequency (ADC output decimated by 4x)
Dynamic Performance
-120
-80
-40
0
032
3 fS
32
4 fS
32
2 fS
32
fS
50
60
70
80
0 10M 50M30M 40M20M
Po
we
r (d
B) SNDR = 63.1 dB
SFDR = 75.2 dB
fIN = 1.0 MHz, fS = 95 MHz
ENOB = 10.2
Normalized Frequency
Po
we
r (d
B)
Input Frequency (Hz)
SFDR
SNDR
HD2 HD3 HD5
fS = 95 MHz
(ADC output decimated by 4x)
57.8 dB
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ADC Topology Asynchronous SAR
with Passive Gain
fsampling 95-MS/s
Resolution 11-bit
Signal Bandwidth 47.5 MHz
Supply (V) 1.1 V
SFDR (dB) 75.2 dB
SNDR (dB) 63.1 dB
Power (mW) 1.36 mW
Area (mm2) 0.073 mm2
Process (nm) 65 nm CMOS
FoM 22 fJ/conv.-step @ Nyquist
14 fJ/conv.-step @ Low Freq.
Performance Summary
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Mike Chen’s IC Group
Filtering with > 10.0 ENOB, > 10MS/s
fsample
Comparison to prior art F
oM
[fJ
/ste
p]
• Achieves the lowest FoM among recently published ADCs
( >10ENOB, > 10MS/s )
ISSCC 1997-2013
VLSI 1997-2013
0.0
20.0
40.0
60.0
80.0
20M 40M 60M 80M 100M 0
This work
10.2 ENOB
(@ Nyquist)
(@ Low Freq.)
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Mike Chen’s IC Group
Higher Speed Extension
• What if higher speed is demanded?
1. Unrolled comparators
2. Asynchronous DAC settling
3. Multi-bit/cycle
4. Pipelining
5. Time interleaving
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Mike Chen’s IC Group
Unrolled Comparators
• Unroll the comparators No comparator reset
No DAC settling
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Mike Chen’s IC Group
Unrolled Asynchronous SAR
G. Van der Plas, et al, “A 150 MS/s 133 uW 7 bit ADC in 90 nm Digital CMOS
“, JSSC, 2008
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Mike Chen’s IC Group
Asynchronous DAC Settling
• DAC settling can also be asynchronous
R. Kapusta, et al., “A 14b 80MS/s SAR ADC with 73.6dB
SNDR in 65nm CMOS,“ ISSCC 2013.
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Mike Chen’s IC Group
Multi-bit/cycle Conversion
- Fewer cycles
required for
conversion
- Time-to-digital
converter can
assist bit
comparison
But…
-Give away the
offset tolerance
-Opportunities for
calibration
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Mike Chen’s IC Group
Pipelining
• Residue voltage is available on capacitor
network for free
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Mike Chen’s IC Group
Time Interleaving
• Sampling rate scale
proportionally to the
number of interleaved
channels
• Calibration is required
for inter-channel
mismatch
• Relaxed clock
distribution
• For example:
8bit 56GS/s
320 of 175MS/s SAR
(Fujitsu)
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Mike Chen’s IC Group
90GS/s 8bit with 64x Time Interleave
• Two comparators ping pong in two consecutive
conversions implemented in 32nm SOI
66
L. Kull, et al., “A 90GS/s 8b 667mW 64x Interleaved
SAR ADC in 32nm Digital SOI CMOS,” ISSCC 14.
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Mike Chen’s IC Group
Family of Asynchronous SAR
• High-speed (>10MS/s, 5-10b) ADCs from ISSCC (00’-10’)
• Asynchronous SAR has been widely adopted since 2006.
• Benefit from technology scaling!
ENOB
s 2F
Total_PW
Family of Async. Enabled ADC
Latest: 8b, 90GS/s,
200 fJ/conv-step
ISSCC 2014
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Mike Chen’s IC Group
Future Asynchronous SAR
• The trend is going towards 1-100GS/s ADC.
• Power efficiency is going towards the order of 1-10
fJ/conv-step.
ENOB
s 2F
Total_PW
Latest: 8b, 90GS/s,
200 fJ/conv-step
ISSCC 2014
68 Future Breakthroughs!
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Mike Chen’s IC Group
Conclusion
• Low-power, high-speed ADCs are in great needs. New opportunities and breakthroughs are expected in accelerated rate.
• Asynchronous SAR ADC architecture provides power efficient platform for achieving this goal. The record high-speed (90GS/s) ADC also leverages this topology.
• More variations of asynchronous SAR ADC architecture will come from all of you!
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Mike Chen’s IC Group
Acknowledgements
• All PhD students involved in these
projects: Jaewon Nam, Praveen Sharma
and David Chiong.
• ONR for funding supports.
70