Asynchronous Pipelined Ring Interconnection for SoC Final Presentation One semester project, Spring...

Asynchronous Pipelined Asynchronous Pipelined Ring Interconnection for Ring Interconnection for

SoCSoCFinal PresentationFinal Presentation

One semester project, Spring 2005One semester project, Spring 2005

Supervisor: Nitzan MironSupervisor: Nitzan Miron

Students: Ziv Zeev ShwaitserStudents: Ziv Zeev ShwaitserChen DamishianChen Damishian

Based on the article:Based on the article:““SELF-TIMED COMMUNICATION PLATFORM FOR SELF-TIMED COMMUNICATION PLATFORM FOR

SYSTEM-ON-CHIP DESIGN”SYSTEM-ON-CHIP DESIGN”Pasi Liljeberg, Juha Plosila, and Jouni Isoaho Pasi Liljeberg, Juha Plosila, and Jouni Isoaho

Electronics and Communication Systems Dept. of Electronics and Communication Systems Dept. of Information Technology University of Turku, FinlandInformation Technology University of Turku, Finland

AgendaAgenda

• Presenting the system.Presenting the system.– Preface.Preface.– Project purposes.Project purposes.– The system architecture.The system architecture.

• Implementation steps.Implementation steps.– Implementing the processing elements in VHDL.Implementing the processing elements in VHDL.– Simulating the system in Modelsim.Simulating the system in Modelsim.– Defining the system in EDK.Defining the system in EDK.

• System architecture.System architecture.• Implementing protocols.Implementing protocols.• Implementing the code.Implementing the code.

• Debugging the system.Debugging the system.• Simulation results.Simulation results.• Summary.Summary.

Presenting the systemPresenting the system

• The system is The system is implemented using an implemented using an Asynchronous Asynchronous Pipelined Ring Pipelined Ring Interconnection that Interconnection that was designed in the was designed in the VLSI lab.VLSI lab.

• Each processing Each processing element works in a element works in a different clock domain, different clock domain, and the and the synchronization is done synchronization is done using asynchronous using asynchronous transfer stages.transfer stages.

Presenting the systemPresenting the system• Each transfer stage has three pipe stages.Each transfer stage has three pipe stages.

– The request from the bus is accepted in the The request from the bus is accepted in the Input Control unit.Input Control unit.

– The request is transferred to the processing The request is transferred to the processing element or to the next transfer stage, element or to the next transfer stage, according to the address, in the Forward according to the address, in the Forward Control unit.Control unit.

– The request from the previous transfer stage The request from the previous transfer stage or from the processing element is transferred or from the processing element is transferred to the bus in the Output Control unit.to the bus in the Output Control unit.

BUS

BUS

HOST


• The purposes of the project are:The purposes of the project are:1) Design a system that is composed of 1) Design a system that is composed of

different processing elements.different processing elements.

2) Implement the system using the 2) Implement the system using the Asynchronous Pipelined Ring Asynchronous Pipelined Ring Interconnection system.Interconnection system.

3) Synthesize the system on an FPGA card.3) Synthesize the system on an FPGA card.

4) Debug the system and check its 4) Debug the system and check its feasibility.feasibility.


• The proposed system is a calculator with a stack architecture.The proposed system is a calculator with a stack architecture.– The data and the operations are presented in a postfix order.The data and the operations are presented in a postfix order.

• ((1 + 2) * 3) will be represented as (1 2 + 3 *).((1 + 2) * 3) will be represented as (1 2 + 3 *).

• The input can be a number or an opcode.The input can be a number or an opcode.• When a number is received, it is pushed to the stack.When a number is received, it is pushed to the stack.• When an opcode is received, its arguments are popped from the When an opcode is received, its arguments are popped from the

stack, and its result is pushed to the stack.stack, and its result is pushed to the stack.• For example, for the input 1 2 +.For example, for the input 1 2 +.

At first, the stack is empty.The first argument is written to the stack

1

The second argument is written to the stack

2

The arguments for the operation are popped from the stackThe result of the operation is pushed to the stack

3


• The system is composed of five processing elements:The system is composed of five processing elements:– Stack.Stack.– Memory.Memory.– ALU.ALU.– Input.Input.– Output.Output.

• Each processing element has a different address in the ring.Each processing element has a different address in the ring.• The data bus width was chosen to be 80 bits, which are divided The data bus width was chosen to be 80 bits, which are divided

according to the following:according to the following:

DataDataOpcodeOpcodeSource Source addressaddress

DestinatioDestination addressn address

79:4879:4847:3247:3231:1631:1615:015:0


• The Stack:The Stack:– Performs POP, PUSH and CLEAR operation.Performs POP, PUSH and CLEAR operation.

• The Memory:The Memory:– Upon a LOAD, performs:Upon a LOAD, performs:

• PUSH(Memory[POP]).PUSH(Memory[POP]).– Upon a STORE, performs:Upon a STORE, performs:

• POP(Addr).POP(Addr).• POP(Data).POP(Data).• Memory[Addr] <= Data.Memory[Addr] <= Data.

• The ALU performs the following operation:The ALU performs the following operation:– PUSH(POP OP POP).PUSH(POP OP POP).

• The following error conditions cause an abort of the operation, The following error conditions cause an abort of the operation, followed by an indication to the user:followed by an indication to the user:– Stack empty (or not enough elements in the Stack).Stack empty (or not enough elements in the Stack).– Operation error (Memory address not in range, division by 0).Operation error (Memory address not in range, division by 0).– Stack full.Stack full.


• The Input:The Input:– Gets requests from the plb bus, and transfers Gets requests from the plb bus, and transfers

them to the appropriate processing element.them to the appropriate processing element.– Gets an indication from the Output, that a Gets an indication from the Output, that a

request has finished, and another request can request has finished, and another request can be processed.be processed.

• The Output:The Output:– Gets results from the processing elements, Gets results from the processing elements,

and returns them on the plb bus.and returns them on the plb bus.– Gets results, and sends indication to the Input, Gets results, and sends indication to the Input,

that a request has finished, and another that a request has finished, and another request can be processed.request can be processed.


• For example: 1 2 + 5 store.For example: 1 2 + 5 store.

InputBus

Output

StackMemory

ALU

• For example: For example: 11 2 + 5 store. 2 + 5 store.

1 & PUSH & OUTPUT & STACK

1 & SUCCESS &

STACK & OUTPUT

1 & NEXT & OUTPUT &

INPUT


• For example: For example: 11 2 + 5 store. 2 + 5 store.

InputBus

Output

StackMemory

ALU

• For example: For example: 11 22 + 5 store. + 5 store.


2 & SUCCESS &

STACK & OUTPUT

2 & NEXT & OUTPUT &

INPUT


• For example: For example: 11 22 + 5 store. + 5 store.

InputBus

Output

StackMemory

ALU

• For example: For example: 11 22 ++ 5 store. 5 store.

0 & PLUS & OUTPUT &

ALU

2 & POP & ALU & STACK

2 & SUCCESS &

STACK & ALU

1 & SUCCESS &

STACK & ALU

3 & PUSH & ALU & STACK

3 & SUCCESS &

STACK & ALU

3 & (SUCCESS PLUS) & ALU &

OUTPUT

3 & NEXT & OUTPUT &

INPUT


• For example: For example: 11 22 ++ 5 store. 5 store.

InputBus

Output

StackMemory

ALU

• For example: For example: 11 22 ++ 55 store. store.


5 & SUCCESS &

STACK & OUTPUT

5 & NEXT & OUTPUT &

INPUT


• For example: For example: 11 22 ++ 55 store. store.

InputBus

Output

StackMemory

ALU

• For example: For example: 11 22 ++ 55 storestore..

0 & STORE & OUTPUT & MEMORY

2 & POP & MEMORY &

STACK

5 & SUCCESS &

STACK & MEMORY

3 & SUCCESS &

STACK & MEMORY

3 & (SUCCESS STORE) &

MEMORY & OUTPUT

3 & NEXT & OUTPUT &

INPUT

• For example: For example: 11 22 ++ 55 storestore..

AgendaAgenda




• Debugging the system.Debugging the system.• Simulation results.Simulation results.• SummarySummary

Implementation stepsImplementation steps

• The files in VHDL were imported The files in VHDL were imported to HDL Designer. to HDL Designer.

• The Ring was built from five The Ring was built from five transfer stage elements. Each transfer stage elements. Each transfer stage element was transfer stage element was assigned a different address.assigned a different address.

• Each processing element was Each processing element was implemented using graphical implemented using graphical views such as flow diagrams or views such as flow diagrams or state machines.state machines.

Simulation with ModelsimSimulation with ModelsimDifferent

clock domain

Output

Memory

ALU

Stack

Input PUSHSTORE

Simulation with ModelsimSimulation with Modelsim

Since the interconnection ring is asynchronous, the

data is transferred immediately from one

transfer stage to the other.

Defining the system in EDKDefining the system in EDK• The system is composed of The system is composed of

two buses:two buses:– One bus, the PLB (Processor One bus, the PLB (Processor

Local Bus) is faster, and Local Bus) is faster, and closer to the PPC.closer to the PPC.• On which the PPC and the On which the PPC and the

instruction controller are instruction controller are located.located.

– The other, the OPB (On board The other, the OPB (On board Peripheral Bus) is slower, and Peripheral Bus) is slower, and farther from the PPC.farther from the PPC.• On which the IO peripherals On which the IO peripherals

are located.are located.– The two busses are The two busses are

connected through a bridge connected through a bridge (plb2opb).(plb2opb).

• The Asynchronous The Asynchronous Pipelined Ring system is Pipelined Ring system is located on the PLB.located on the PLB.

Defining the system in EDKDefining the system in EDK

• The system was allocated The system was allocated addresses on the PLB bus.addresses on the PLB bus.– A 32 bit write to address 0x000 A 32 bit write to address 0x000

means a number that should be means a number that should be pushed to the Stack.pushed to the Stack.

– A 16 bit write to address 0x010 A 16 bit write to address 0x010 means an opcode that needs to means an opcode that needs to be executed (Such as POP, be executed (Such as POP, LOAD, STORE, ‘+’, etc).LOAD, STORE, ‘+’, etc).

– A 32 bit read from address A 32 bit read from address 0x020 means getting the result 0x020 means getting the result of the previous operation.of the previous operation.

– A 16 bit read from address A 16 bit read from address 0x030 means getting the 0x030 means getting the returned error code of the returned error code of the previous operation.previous operation.

Implementing protocolsImplementing protocols

• To implement To implement the interface the interface with the PLB, with the PLB, we have used we have used the EDK tool the EDK tool to generate to generate an instance an instance of an IPIF of an IPIF unit, with unit, with which our which our system can system can communicate communicate easily.easily.

Implementing protocolsImplementing protocols• The IPIF protocol The IPIF protocol

with the IP was with the IP was implemented implemented according to the according to the specifications.specifications.

Implementing the codeImplementing the code

DIP Switches – Used to enter a

number between 0 and

255.

• The code was written in C.The code was written in C.• The code reads requests The code reads requests

from the user, sends them from the user, sends them to the system, and returns to the system, and returns results to the user.results to the user.

Push button – The input is a number to be pushed to

the Stack.

Push button – The input is an opcode,

which should be sent to the appropriate

element.

Push button – used to end the program.

Serial port – used to send the

results to the user, through

hyper terminal.

LCD screen – used to display

the project information.

AgendaAgenda





Debugging the systemDebugging the system

• The resource allocation problem.The resource allocation problem.

• Adding buffers.Adding buffers.

• Synchronizing two different clock Synchronizing two different clock domains.domains.

The resource allocation The resource allocation problemproblem• The first project files could not fit into The first project files could not fit into

the card.the card.• Analysis of the problem led to the Analysis of the problem led to the

conclusion that the problem was with conclusion that the problem was with a conversion function from a conversion function from std_logic_vector to integer.std_logic_vector to integer.

Adding buffersAdding buffers

• The first checking of the system gave different The first checking of the system gave different results than the results in the simulation.results than the results in the simulation.

• The first suspicion was about the validity of the The first suspicion was about the validity of the data in respect to the time the request arrives.data in respect to the time the request arrives.


• The synthesis took off the buffers, for not being essential The synthesis took off the buffers, for not being essential logically.logically.

• The way to overcome this limitation was to create a buffer The way to overcome this limitation was to create a buffer with enable bits, whose enable bits come from a register with enable bits, whose enable bits come from a register that can contain different results (And not considered that can contain different results (And not considered constant according to the synthesis tool, even though it constant according to the synthesis tool, even though it remains 1 throughout the simulation).remains 1 throughout the simulation).


• An alternative solution to the problem that is delay An alternative solution to the problem that is delay independent is to use dual rail representation for the data.independent is to use dual rail representation for the data.

• This would require additional logic for request valid This would require additional logic for request valid indication.indication.

• This would also double the registers.This would also double the registers.• For the above reasons, this solution was abandoned.For the above reasons, this solution was abandoned.

CC DoneDoneORORbitbit00

OORR

bitbit11

ORORbitbitnn

bit mbit m

bit 1bit 1

ackack

AA BB

Synchronizing two different clock Synchronizing two different clock domainsdomains• Some combinations of clock frequencies gave unpredicted Some combinations of clock frequencies gave unpredicted

results.results.• The problem was the lack of synchronization between two The problem was the lack of synchronization between two

synchronous elements, which operate in a different clock synchronous elements, which operate in a different clock domain.domain.– The user_logic (clk_100) and the Input.The user_logic (clk_100) and the Input.– The user_logic (clk_100) and the Output.The user_logic (clk_100) and the Output.

Input

Output

• The solution: Adding a pair of FF at The solution: Adding a pair of FF at each input.each input.

Synchronizing two different clock Synchronizing two different clock domainsdomains

AgendaAgenda





Simulation resultsSimulation results

Input: Output:

AgendaAgenda





SummarySummary

• We enjoyed working on this project, We enjoyed working on this project, and we learned a lot.and we learned a lot.

• We gained experience in:We gained experience in:– VHDL design and simulation.VHDL design and simulation.– Design of a system on an FPGA card, Design of a system on an FPGA card,

and the synthesis flow.and the synthesis flow.– Debug of a complicated system.Debug of a complicated system.– Debug of an asynchronous logic on an Debug of an asynchronous logic on an

FPGA.FPGA.

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