ASYNCHRONOUS mode. 1 · 1 1 8-bits B2 B1 Baud rate factor 0 0 SYNC MODE 0 1 1 times TxC or RxC 1 0...

Unit-IV

Peripheral Interfacing

1. Architecture and Working of 8251 USART or SCI

Intel 8251 is called USART (Universal Synchronous Asynchronous Receiver Transmitter)

or PCI[Programmable Communication Interface].

Architecture :

Data Bus Buffer :

8-bit bidirectional Data bus connected to the Data bus of 8085 microprocessor or 8051

microcontroller

Data word , Control Word or Command Word , Status Word are transferred through this

buffer.

Read/Write Control Logic :

Allows CPU to read DATA WORD and STATUS WORD of 8251.

INTEL 8251 STATUS WORD

DSR [Data Set Ready] bit = 1 , Indicates MODEM is ready to accept data from or

transmit data to CPU

SYNDET/BRKDET = 1 , Indicates SYNC characters are received from MODEM device during

SYNCHRONOUS mode ; Indicates BREAK in the data stream during reception in

ASYNCHRONOUS mode.

FE [Framing Error] bit = 1 , Indicates when a STOP bit is not present in the character during

transmission/reception.

OE [Overrun Error] bit = 1 , Indicates the character in the RECEIVE BUFFER has been

OVERWRITTEN by a new character before the CPU has read the older one.

PE[Parity Error] bit = 1 , Indicates the parity in the characters at the transmitted end and

received end are different.

TxEMPTY [Transmitter EMPTY]bit = 1 , Indicates the transmit buffer has finished transmission

of the loaded data and is EMPTY.

RxRDY [Receiver READY] bit = 1 , Indicates the RECEIVE BUFFER has got a new character to

be read by CPU.

TxRDY [Transmitter READY] bit = 1 , Indicates the TRANSMIT BUFFER is ready to accept a

new character from CPU.

Allows CPU to write DATA WORD and CONTROL WORD into 8251. 8251 has two types of

CONTROL WORDS : (i) COMMAND WORD (ii) MODE INSTRUCTION WORD.

INTEL 8251 COMMAND or CONTROL WORD

EH[Enable Hunt Mode]bit = 1 , Searches[HUNTs] for SYNC characters during reception

of characters from a peripheral device.

IR [Internal Reset] bit = 1 , Resets command word to mode instruction word.

RTS[Request To Send] bit = 1 , Indicates that CPU is ready to accept the data from

Modem.

ER [Error Reset]bit = 1 , Resets the ERROR FLAG bits such as FE , PE , OE in the 8251

Status Word.

SBRK[Send Break Character] bit = 1 , Indicates that there is BREAK during

TRANSMISSION of assembled data characters from Transmit Buffer.

RxE[Receiver Enable] bit = 1 , Receiver Section is Enabled for Reception of data

characters from MODEM.

DTR[Data Terminal Ready] bit = 1 , Indicates that CPU is ready to transfer data to

Modem or receive data from Modem.

TxEn[Transmitter Enable ] bit = 1 , Transmitter Section is enabled for reception of data

characters from CPU.

INTEL 8251 MODE INSTRUCTION WORD

S2 S1 Number of Stop-

bits

0 0 INVALID Stop

bit

0 1 1 Stop bit

1 0 1.5 Stop bit

1 1 2 Stop bits

EP [ EVEN PARITY GENERATION CHECK] bit = 1 , EVEN PARITY CHARACTER

GENERATED ; 0 = ODD PARITY GENERATED.

PEN[PARITY ENABLE] bit = 1 , Enable PARITY GENERATION.

L2 L1 Character Length[Number of bits per

character]

0 0 5-bits

0 1 6-bits

1 0 7-bits

1 1 8-bits

B2 B1 Baud rate factor

0 0 SYNC MODE

0 1 1 times TxC or

RxC

1 0 16 times TxC or

RxC

1 1 64 times TxC or

RxC

Allows the CPU to enable or disable 8251.

Allows CPU to make reset all the internal components of 8251.

Modem Control Logic :

Provides set of handshaking signals for allowing the CPU to communicate with the

MODEM.

When not used for communication with MODEM , DSR[Data Set Ready] signal functions as

1-bit input port , RTS and DTR signal functions as 1-bit output port.

Transmitter Section :

Contains Transmit Buffer and Transmission Control Logic.

Transmit Buffer:

The Transmit Buffer is a Parallel In Serial Out(PISO) Shift register , that converts the

parallel data input of CPU into serial data output.

Data is transmitted out of the buffer on the falling edge of TRANSMITTER CLOCK (i.e.

𝑇𝑥𝐶 ). Data Transmission occurs only if 𝐶𝑇𝑆 [Clear To Send] signal is activated.

Transmission Control Logic :

Indicates CPU whether Transmit Buffer is ready to accept a new data from CPU

Indicates CPU whether Transmit Buffer has finished OFF-LOADING the data to MODEM.

On signaling this , if the CPU does’nt load the data byte into the buffer , the control logic

starts transmitting SYNC characters on TxD line.

Provides the clock required for the Transmit Buffer to SHIFT OUT the loaded data. Under

Synchronous operation , the baud rate is equal to Transmitter clock frequency. Under

Asynchronous operation , the baud rate is equal to 1 (or)1/16 times (or) 1/64 times the

Transmitter clock frequency.

Receiver Section :

Contains Receive Buffer and Reception Control Logic.

Receive Buffer :

The Receive Buffer is a Serial In Parallel Out (SIPO) shift register , that converts the serial

data input of a peripheral device into a parallel data output.

Data is received into the buffer on the rising edge of RECEIVER CLOCK (i.e. 𝑅𝑥𝐶 ).

Reception Control Logic :

Ensures an invalid Start Bit does’nt occur after a LINE BREAK condition.

Ensures VALID START BIT is not corrupted by a TRANSIENT NOISE.

Ensures STOP BIT occurs at the end of a BYTE.

Indicates to the CPU whether Receive Buffer has got any new character to be read by CPU.

For Asynchronous or Synchronous mode, for 8251 to set RxRDY , the receiver must be

enabled and a character must be assembled and transferred to the Data Output

Register[connected to CPU]

Provides the clock required for the Receive Buffer to SHIFT IN the data. Under

Synchronous operation , the baud rate is equal to Receiver clock frequency. Under

Asynchronous operation , the baud rate is equal to 1 (or)1/16 times (or) 1/64 times the

Receiver clock frequency.

Operating Modes :

SYNCHRONOUS TRANSMISSION and RECEPTION :

DATA FORMAT DURING SYNCHRONOUS COMMUNICATION

Synchronous Transmission :

The TxD lines remains continuously HIGH till the TRANSMIT BUFFER receives FIRST

SYNC CHARACTER from CPU.

The FIRST SYNCH CHARACTER gets transmitted out of TxD , when the CPU activates the

CTS[Clear To Send] signal.

The DATA consisting of SYNCH CHARACTERS + DATA CHARACTERS are transmitted at

the same rate as TxC during its falling edge.

If the TRANSMIT BUFFER does’nt receive a subsequent character from CPU before it

becomes EMPTY , 8251 informs TxEMPTY signal to the CPU and starts sending SYNC

CHARACTERS through TxD line. The TxEMPTY signal is deactivated , when the

TRANSMIT BUFFER has received character for next transmission from CPU.

Synchronous Reception :

The RxD pin is sampled on the rising edge of RxC for ensuring whether 1 or 2 SYNC

characters have been received into RECEIVE BUFFER. This process is called HUNTING.

Once SYNC characters are detected , the SYNDET pin is set high. If parity is programmed ,

the SYNDET will be set at the middle of PARITY bit. These set of above operations are

called INTERNAL SYNCHRONIZATION.

In case of external synchronization , the SYNDET pin is SET high by MODEM. The

SYNDET pin is then reset after one RxC cycle.

Parity Error and Overrun error are checked. The SYNDET Flip-Flop is Reset , when

STATUS word is read by CPU.

ASYNCHRONOUS TRANSMISSION and RECEPTION:

DATA FORMAT DURING ASYNCHRONOUS COMMUNICATION

Asynchronous Transmission :

Data character is sent by CPU to TRANSMIT BUFFER.

8251 forms an appropriate DATA FRAME consisting of START BIT + DATA BITS +

PARITY BIT + STOP BIT.

The data frame is then transmitted at a rate equals to 1 (or) 1/16 (or) 1/64 of TxC on its

falling edge.

When no data bits is loaded into TRANSMIT BUFFER , the TxD pin becomes high and 8251

starts sending out BREAK characters indicating a BREAK in transmission.

Asynchronous Reception:

The RxD line is checked twice for VALID START BIT when a falling edge occurs on it.

A bit counters starts detecting the CENTRE POSITIONS in DATA BIT , PARITY BIT , and

STOP BIT.

Data and Parity Bits are sampled on the RISING EDGE of RxC.

Once the STOP BIT occurs during reception , it indicates the END of RECEPTION. The

character is assembled in RECEIVE BUFFER and RxRDY signal is activated to CPU to

indicate it has DATA BITS READY to be READ.

During Asynchronous RECEPTION Parity Error , Framing Error and Overrun Error are

checked and appropriate FLAGS are set on its occurrence.

I/O MAPPED I/O INTERFACING OF INTEL 8251 to 8085 MICROPROCESSOR :

2. Architecture and Working of Intel 8255 PPI or PCI

INTEL 8255 is called PROGRAMMABLE PERIPHERAL INTERFACE [PPI} (or) PARALLEL

COMMUNICATION INTERFACE (PCI)

Architecture :

Data Bus Buffer :


microcontroller


buffer.


Allows CPU to read DATA WORD and STATUS WORD of 8255. There are two types of

STATUS WORD based on the MODE of OPERATION.

MODE 1 STATUS WORD for INPUT CONFIGURATION.

MODE 1 STATUS WORD for OUTPUT CONFIGURATION

GROUP A refers to 8-bits of PORT A + Upper 4-bits of PORT C.

GROUP B refers to 8-bits of PORT B + Lower 4-bits of PORT C.

MODE 2 STATUS WORD

Allows CPU to write DATA WORD and CONTROL WORD into 8255. There are two types of

CONTROL WORDS in 8255 : (i) MODE DEFINITION (ii) BIT SET/RESET CONTROL.

INTEL 8255 CONTROL WORD

D7 = 1 , I/O mode ; 0 = BIT SET/RESET mode.

D6 – D3 = GROUP- A CONTROL BITS [ GROUP A can function in MODE 0 , 1, 2]

D6 D5 D4 D3 Meaning

0 0 1 1 MODE 0 , PORT A and PC7-PC4

acts as INPUT PORT

0 1 MODE 1 , PORT A and PC7-PC4

acts as INPUT PORT

1 X MODE 2 , PORT A and PC7-PC4

acts as INPUT PORT

0 0 1 0 MODE 0 , PORT A acts as INPUT

PORT and PC7-PC4 acts as

OUTPUT PORT

0 1 MODE 1 , PORT A acts as INPUT


OUTPUT PORT

1 X MODE 2 , PORT A acts as INPUT


OUTPUT PORT

0 0 0 1 MODE 0 , PORT A acts as

OUTPUT PORT and PC7-PC4 acts

as INTPUT PORT

0 1 MODE 1 , PORT A acts as


as INTPUT PORT

1 X MODE 2 , PORT A acts as


as INTPUT PORT

0 0 0 0 MODE 0 , PORT A and PC7-PC4

acts as OUTPUT PORT

0 1 MODE 1 , PORT A and PC7-PC4

acts as OUTPUT PORT

1 X MODE 2 , PORT A and PC7-PC4

acts as OUTPUT PORT

D4 control PORT A BITS ; D3 controls PC7-PC4 bits ; D6 D5 controls the OPERATING

MODE for GROUP-A ;

A PORT BIT having “1” in it acts as INPUT PORT and a PORT BIT having “0” in it acts as

OUTPUT PORT.

D2-D0 = GROUP B CONTROL BITS [GROUP B can function in MODE 0 ,1]

D2 D1 D0 Meaning

0 1 1 MODE 0 , PORT B and PC3-PC0 acts as INPUT

PORT

1 0 MODE 0 , PORT B acts as INPUT PORT and PC3-

PC0 acts as OUTPUT PORT

0 1 MODE 0 , PORT B acts as OUTPUT PORT and

PC3-PC0 acts as INPUT PORT

0 0 MODE 0 , PORT B and PC3-PC0 acts as OUTPUT

PORT

1 1 1 MODE 1 , PORT B and PC3-PC0 acts as INPUT

PORT

1 0 MODE 1 , PORT B acts as INPUT PORT and PC3-

PC0 acts as OUTPUT PORT

0 1 MODE 1 , PORT B acts as OUTPUT PORT and

PC3-PC0 acts as INPUT PORT

0 0 MODE 1 , PORT B and PC3-PC0 acts as OUTPUT

PORT.

8255 BIT/RESET MODE CONTROL WORD

D7 = 0 , BIT SET/RESET MODE SELECTED.

D6-D4 = XXX[Don’t Care] . This indicates that PORT-A is not used in this mode.

D3-D1 = PORT C bit selection

D3 D2 D1 Meaning

0 0 0 PORT C0 selected








D0 = To set or reset a bit selected using D3-D1 ; 1 = SET , 0 = RESET

Allows CPU to enable or disable 8255.

Allows CPU to reset internal components of 8255.

Issues control signals to GROUP-A and GROUP B CONTROL LOGIC.

GROUP-A and GROUP-B CONTROL LOGIC:

Based upon the commands received from READ/WRITE CONTROL LOGIC , these two

appropriate program their associated ports in their respective operating modes.

GROUP A refers to 8-bits of PORT A + Upper 4-bits of PORT C.[PC7-PC4]

GROUP B refers to 8-bits of PORT B + Lower 4-bits of PORT C. [PC3-PC0]

PORT A, B,C:

Three 8-bit I/O ports of 8255.

PORT C functionally separated into two 4-bit ports. [i.e PORT C Upper and Port C Lower]

PORT A contains : 8-bit INPUT LATCH + 8-bit OUTPUT LATCH + 8-bit OUTPUT

BUFFER

PORT B contains : 8-bit INPUT LATCH + 8-bit INPUT BUFFER + 8-bit OUTPUT LATCH +

8-bit OUTPUT BUFFER

Port C contains : 8-bit INPUT BUFFER + 8-bit OUTPUT LATCH + 8-bit OUTPUT

BUFFER

Operating Modes :

Mode 0 [Basic I/O Mode]:

In this mode , GROUP A and GROUP B acts either as INPUT ports and/or as OUTPUT ports

No handshaking signals are involved in this mode.

Data is simply written into or read from a specified PORT.

Mode 1[ Strobed I/O Mode] :

In this mode , PORT A of GROUP A and PORT B of GROUP B acts either as INPUT port

and/or as OUTPUT port .

Separate 3-bits of PORT C serves as HANDSHAKING SIGNALs for PORT A and PORT B.

Remaining 2-bits of PORT C serve as I/O port for PORT A.

HANDSHAKING SIGNALS of MODE 1 when PORT A and PORT B functions as INPUT

PORT :

𝑆𝑇𝐵𝐴 /𝑆𝑇𝐵𝐵

– When activated , DATA from Input Device is loaded into the INPUT

LATCHES of PORT-A and PORT B.

𝐼𝐵𝐹𝐴 /𝐼𝐵𝐹𝐵 - Acknowledgement from the PORTs to the INPUT DEVICE after data have been

loaded into their respective latches. Set by STB signal and reset by RD signal.

𝐼𝑁𝑇𝑅𝐴 /𝐼𝑁𝑇𝑅𝐵 – Interrupts to indicate CPU that INPUT DEVICE has loaded into the INPUT

LATCHES of PORT A and PORT B.

HANDSHAKING SIGNALS of MODE 1 when PORT A and PORT B functions as OUTPUT

PORT :

𝑂𝐵𝐹𝐴 /𝑂𝐵𝐹𝐵 - When activated , DATA from CPU is loaded into the OUTPUT LATCHES of

PORT A and PORT B.

𝐴𝐶𝐾𝐴 /𝐴𝐶𝐾𝐵

- Acknowledgement from the PORTs to the CPU after data have been loaded into

their respective latches.

𝐼𝑁𝑇𝑅𝐴 /𝐼𝑁𝑇𝑅𝐵 - Interrupts to indicate CPU that OUTPUT DEVICE has accepted data loaded

in the OUTPUT LATCHES of PORT A and PORT B.

Mode 2 [Strobed Bidirectional I/O]:

In this mode , PORT A of GROUP A acts as INPUT port and OUTPUT port.

PORT C generates handshaking signals required for carrying out communication in this

mode. 5 bits of PORT C are used for handshaking purpose. Remaining 3-bits serves as

normal I/O ports.

HANDSHAKING SIGNALS for MODE 2 when PORT A is acting as I/O PORT:

𝑆𝑇𝐵𝐴 – When activated , DATA from Input Device is loaded into the INPUT LATCH of

PORT-A

𝐼𝐵𝐹𝐴 - Acknowledgement from the PORT A to the INPUT DEVICE after data have been

loaded into its latch. Set by STB signal and reset by RD signal.

𝐼𝑁𝑇𝑅𝐴 - Interrupts to indicate CPU that INPUT DEVICE has loaded into the INPUT LATCH

of PORT A during input mode ; Interrupts to indicate CPU that OUTPUT DEVICE has

accepted data loaded in the OUTPUT LATCHES of PORT A during output mode

𝑂𝐵𝐹𝐴 - When activated , DATA from CPU is loaded into the OUTPUT LATCH of PORT A .

𝐴𝐶𝐾𝐴 - Acknowledgement from the PORT A to the CPU after data have been loaded into its

OUTPUT LATCH.

I/O MAPPED I/O INTERFACING OF 8255 WITH INTEL 8085 MICROPROCESSOR :

3. Architecture and Working of 8253/54 PIT

INTEL 8253/54 is called PROGRAMMABLE INTERRUPT TIMER /COUNTER.

Data Bus Buffer :


microcontroller.


buffer.

Read/Write Control Logic:

Allows CPU to read DATA WORD and CONTENTS of COUNTER of 8253. The CONTENTS

of COUNTER can be READ either by STOPPING the COUNTER or while it is RUNNING.

Allows CPU to write DATA WORD and CONTROL WORD into 8253.

SC 1 , SC 0 – Counter Selection Bits

SC 1 SC 0 COUNTER

SELECTED

0 0 COUNTER 0

0 1 COUNTER 1

1 0 COUNTER 2

1 1 ILLEGAL

RL1 , RL0 – COUNTER READ/WRITE bits

RL 1 RL 0 Meaning

0 0 Selected Counter’s current value latched into a STORAGE

REGISTER , while the COUNTER is running

0 1 Read/Load(Write) MSB from or into a SELECTED

COUNTER by STOPPING it.

1 0 Read/Load(Write) MSB from or into a SELECTED

COUNTER by STOPPING it.

1 1 Read/Load(Write) MSB first followed by LSB of the

selected COUNTER by STOPPING it.

M2 – M0 = OPERATING MODE SELECTION BITS

M2 M1 M0 MODE

0 0 0 MODE 0 :Interrupt on Terminal Count

0 0 1 MODE 1 : Programmable or Retrriggerable One SHOT

or MONOSTABLE MULTIVIBRATOR.

0 1 0 MODE 2: RATE GENERATOR or DIVIDE-BY-N

COUNTER

0 1 1 MODE 3 : SQUARE WAVE RATE GENERATOR

1 0 0 MODE 4 : SOFTWARE TRIGGERED STROBE

1 0 1 MODE 5: HARDWARE TRIGGERED STROBE

BCD – Type of value to be counted by a selected COUNTER

BCD Type of Value to be counted

0 Binary Counter counting from

FFFFH to 0000H

1 BCD Counter counting from

999910 to 000010 [i.e. 4 decade]

One Decade refers to powers of 10 (i.e. 10X where X – a positive integer such as

1,2,3….)

Allows the CPU to control the MODE of OPERATION of the COUNTERS.

Allows the CPU to control the format of value a COUNTER has to count (Binary or BCD).

Allows the CPU to select the COUNTER.

COUNTER 0 , 1, 2 :

Each counter consist of 16-bit PRESETTABLE SYNCHRONOUS DOWN COUNTERS.

The counter can count either in BINARY or BCD.

The COUNTER can be read either by STOPPING the counter or by LATCHING it in a

STORAGE REGISTER when RUNNING.

Each COUNTER is independent of other.

OPERATION :

MODE 0 : (INTERRUPT ON TERMINAL COUNT)

MODE 0 is selected via CONTROL WORD REGISTER and loaded into a SELECTED

COUNTER.

COUNT value is loaded into the SELECTED COUNTER.

The selected COUNTER’s OUTPUT pin goes low and the counter value starts to

decrement.

Once 0[Terminal or Final] is reached , the selected COUNTER’s OUTPUT pin goes high

and remains at the same state till MODE SELECTION or NEW COUNT IS LOADED

INTO THE SELECTED COUNTER.

MODE 1: (PROGRAMMABLE ONE SHOT or RETRIGGERABLE ONE-SHOT or

MONOSTABLE MULTIVIBRATOR MODE)


COUNTER.


The selected COUNTER’s OUTPUT pin goes low ON THE RISING EDGE OF GATE

INPUT and the counter value starts to decrement.

Once TERMINAL or FINAL COUNT is reached , the selected COUNTER’s OUTPUT pin

goes high.

MODE 2 : (RATE GENERATOR or DIVIDE-BY-N COUNTER or FREQUENCY DIVIDER

MODE)


COUNTER.


The selected COUNTER’s OUTPUT pin goes HIGH ON THE RISING EDGE OF GATE


Once PENULTIMATE value is reached , the selected COUNTER’s OUTPUT pin goes low

and remains in the state till the INITIAL VALUE is loaded into the COUNTER.

The PERIOD FROM ONE OUTPUT PULSE TO SUBSEQUENT OUTPUT PULSE

EQUALS THE NUMBER OF COUNTS IN THE INPUT REGISTER.

If a COUNTER is reloaded between OUTPUT PULSES , present period will not be affected

but subsequent period reflects the new value.

MODE 3:[SQUARE WAVE RATE GENERATOR MODE]

This mode of operation depends upon the type of COUNT VALUE (EVEN or ODD

NUMBER) loaded into COUNTER.


COUNTER.


If the COUNT is ODD NUMBER , the COUNTER’s OUTPUT will be high for (N+1)/2

COUNTS and low for (N-1)/2 COUNTS.

If the COUNT is EVEN NUMBER , the COUNTER’s OUTPUT will be high N/2 COUNTS

and low for remaining N/2 COUNTS. [N – COUNT VALUE LOADED INTO a SELECTED

COUNTER]

MODE 4 : (SOFTWARE TRIGGERED STROBE MODE)


COUNTER.


The selected COUNTER’s OUTPUT pin goes HIGH WHEN GATE INPUT goes HIGH and

the counter value starts to decrement.


goes low for one clock period and then becomes HIGH.

The COUNTER’s operation can be disabled by making GATE INPUT low.

MODE 5: (HARDWARE TRIGGERED STROBE MODE)


COUNTER.


The selected COUNTER’s OUTPUT pin goes HIGH on the RISING EDGE OF GATE



goes low for one clock period and then becomes HIGH.

The COUNTER’s operation can be disabled by making GATE INPUT low.

I/O MAPPED I/O INTERFACING of 8253 with 8085 MICROPROCESSOR :

4. Architecture and Working of 8259 PIC

INTEL 8259 is called PROGRAMMABLE INTERRUPT CONTROLLER.

Architecture :

Data Bus Buffer :


microcontroller.


buffer.


Allows CPU to write DATA WORD and CONTROL WORD into 8259. There are two types of

CONTROL WORDS or COMMAND WORDS associated with 8259. They are

ICW(Initialization Command Word) and OCW (Operation Command Word).

There are four types of ICWs. They are :

ICW 1

A7-A5 = Lower order address bits of INTERRUPT VECTOR ADDRESS.

LTIM = 1 , 8259 operates in POSITIVE Level Triggered Interrupt Mode ; 0 , 8259 operates

in RISING Edge Triggered Interrupt Mode.

ADI [ADDress Interval] =1, [CALL ADDRESS INTERVAL of 4 BYTES i.e. TWO

SUBSEQUENT CALL ADDRESSES have a DIFFERENCE of 4 BYTES]. In this case , A4-

A0 inserted by 8259 while A15-A5 provided by CPU.

= 0 , [CALL ADDRESS INTERVAL of 8 BYTES i.e. TWO

SUBSEQUENT CALL ADDRESSES have a DIFFERENCE of 8]. In this case , A5-A0

inserted by 8259 while A15-A6 provided by CPU.

SNGL [SINGLE] = 1, No SLAVE 8259s connected to given MASTER 8259.

IC4 = 1 , ICW 4 will be issued.

ICW 2

A15-A8 = Higher order address bits of INTERRUPT VECTOR ADDRESS for 8085

microprocessor

ICW 3 for MASTER DEVICE

S7-S0 = 1 when present in any of the bits indicate a SLAVE has been attached to the

corresponding INTERRUPT REQUEST INPUT.

= 0 when present in any of the bits indicate NO SLAVE has been attached to the

corresponding INTERRUPT REQUEST INPUT.

ICW 3 for SLAVE DEVICE

ID2 ID1 ID0 Slave

Number

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

To a given MASTER 8259 upto 8 SLAVE 8259 devices can be attached.

ICW 4

SFNM = 1 , SPECIALLY FULLY NESTED MODE. ; 0 = NOT SPECIALLY FULLY

NESTED MODE

BUF M/S Type of Mode

0 X Non-Buffered Mode

1 0 Buffered Mode/Slave

1 1 Buffered

Mode/Master

AEOI = 1 ,Automatic End Of Interrupt ; 0 , Normal End Of Interrupt

μPM = 1 , 8080/8085 MODE ; 0 = 8086/8088 MODE.

There are three types of OCW. They are :

OCW 1

M7-M0 = 1 when present in any of the bits indicate the corresponding INTERRUPT REQUEST is

BLOCKED ; 0 when present in any of the bits indicate the corresponding INTERRUPT REQUEST

is ALLOWED.

OCW 2

R(Rotate) SL

(Select

Level)

EOI Type of Mode

0 0 0 Don’t Rotate during AUTOMATIC

EOI mode

1 0 0 Rotate during AUTOMATIC EOI

mode

0 0 1 Non-Specific EOI mode

0 1 1 Specific EOI mode

1 0 1 Rotate on Non-Specific EOI mode

1 1 1 Rotate on Specific EOI mode

1 1 0 Set Priority Command

0 1 0 No Operation

L2 L1 L0 INTERRUPT REQUEST

NUMBER

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

OCW 3

ESMM SMM Meaning

0 X No Action

1 0 Read Interrupt Request Register on next read

pulse

1 1 Read Interrupt Service Register on next read

pulse

P = 1 , Issue POLL Command ; 0 = Don’t Issue POLL Command

RR RIS Meaning

0 X No Action

1 0 Reset Special Mask Mode

1 1 Set Special Mask Mode

Allows CPU to read DATA WORD and STATUS of INTERRUPT REQUEST REGISTER ,

INTERRUPT MASK REGISTER , IN SERVICE REGISTER from 8259.

Allows CPU to enable and disable 8259.

Forwards a selected interrupt request to microprocessor or microcontroller.

CASCADE BUFFER and COMPARATOR :

Allows a MASTER 8259 to select a SLAVE 8259.

The CAS2-CAS0 lines of the MASTER acts as CHIP SELECT signals of desired SLAVE

8259.

A master 8259 can handle upto 64 interrupt request or 8 slave 8259s.

Stores and Compares the IDs of all 8259s used in the system.

When a SLAVE 8259 sends an INTERRUPT REQUEST to MASTER 8259 through the

connected INTERRUPT REQUEST line , the MASTER 8259 forwards it to the CPU. The

CPU in-turn sends an acknowledgement signal back to MASTER 8259 to release the

INTERRUPT VECTOR ADDRESS. On receiving the acknowledgement , the MASTER

enables the REQUESTING SLAVE to release the 2nd and 3rd bytes of INTERRUPT VECTOR

ADDRESS.

INTERRUPT REQUEST REGISTER : (IRR)

8-bit register which holds the set ACTIVE and INACTIVE INTERRUPT REQUEST i.e.

INTERRUPT REQUESTs that are waiting for SERVICE

D7 D6 D5 D4 D3 D2 D1 D0

IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

A value of “1” in any one of the bit indicates that corresponding INTERRUPT REQUEST

(IR) is active and a value of “0” indicates the corresponding INTERRUPT REQUEST is

INACTIVE.

INTERRUPT MASK REGISTER : (IMR)

8-bit register which holds the STATUS of ENABLED and DISABLED INTERRUPT

REQUEST LINES.

STATUS of MASKED INTERRUPT REQUEST lines can be known from OCW 1.

IN-SERVICE REGISTER : (ISR)

8-bit register which holds the STATUS of INTERRUPT REQUESTs that is CURRENTLY in

SERVICE.

PRIORITY RESOLVER :

A 8:3 priority encoder circuit which resolves conflict among the interrupts by assigning

PRIORITY to the INTERRUPTS. By default , IR 0 is taken as HIGHEST PRIORITY

REQUEST and IR 7 is taken as LOWEST PRIORITY REQUEST. The priority of the

INTERRUPT REQUEST can be altered by programming OCW 2.

I/O MAPPED I/O INTERFACING of 8259 with 8085 Microprocessor :

5. Architecture and Working of 8237 DMA Controller

Architecture :

Data Bus Buffer :


microcontroller.

Data word , Control Word or Command Word , Status Word , Word Count , MSB of

address , Temporary Register Data are transferred through this buffer.

Address Bus Buffer :

In Idle Cycle , they are used by CPU to read or write into a selected register.

In Active Cycle , they are the lower 4-bit address for DMA operation.

Control Logic :

Consist of three control blocks : (i) Timing Control block (ii) Program Command Control

Block (iii) Priority Encoder block.

The Timing Control Block generates INTERNAL and EXTERNAL CONTROL signals for

8237.

The Program Command Control Block Decodes various commands given by CPU to 8237

before servicing a DMA request. It also decodes MODE CONTROL WORD , to select the

type of DMA transfer during servicing.

The Priority Encoder Block resolves the priority between DMA channels requesting service

simultaneously.

Internal Register :

There are 12 registers of various width present in 8237. They are :

Current Address Register and Current Word Register :

Current Address Register is a 16-bit register that holds the address used during a DMA

transfer. The address gets incremented or decremented after each transfer.

Current Word Register is a 16-bit register that holds the NUMBER of DMA

transfers[WORD COUNT] to be performed. The count value gets decremented after each

data transfer.

Base Address Register and Base Word Count Register :

Base Address Register is a 16-bit register that holds the initial value of address loaded in

Current Address Register ; Reinitializes the Current Address Register to its initial value

during AUTO-INITIALIZATION.

Base Word Count Register is a 16-bit register that holds the initial value of NUMBER of

TRANSFERS loaded in the Current Word Register ; Reinitializes the Current Address

Register to its initial value during AUTO-INITIALIZATION.

Request Register :

Holds the DMA request bit associated with each channel. There are totally 4 DMA channels.

The value of the register is controlled by software and is reset to 0000H upon generation of a

TERMINAL COUNT command or external EOP (End Of Process).

Command Register :

D7 = DMA acknowledgement signal can be programmed ACTIVE LOW[0] or ACTIVE HIGH[1] to

indicate the REQUESTED PERIPHERAL that DMA cycle has been granted.

D6 – DMA REQUEST signal can be programmed ACTIVE LOW[0] or ACTIVE HIGH [1] to indicate

a PERIPHERAL is requesting 8237 for a DMA TRANSFER.

D5 – LATE WRITE [0] or EXTENDED WRITE [1] selection bit.

D4 – Fixed PRIORITY [0] or Rotating Priority [1] selection bit.

D3 – Normal Timing [0] or Compressed Timing [1] selection bit.

D2 – DMA Controller Enable [0] or DMA Controller Disable [1] selection bit.

D1 – Channel 0 address hold ENABLE [0] or Channel 0 address hold DISABLE [1]

D0 – Memory to Memory Transfer ENABLE [1] or Memory to Memory Transfer DISABLE [0]

Mode Register :

D7 D6 Mode Selection

0 0 Demand Mode

0 1 Single Mode

1 0 Block Mode

1 1 Cascade Mode

D5 = 0 , Address Increment Select ; 1 , Address Decrement Select

D4 = 0 , Auto-initialize Disable ; 1 , Auto-Initialize Enable

D3 D2 Action

0 0 Verify Transfer

0 1 Write Transfer

1 0 Read Transfer

D1 D0 Channel

Selection

0 0 0

0 1 1

1 0 2

1 1 3

Mask Register :

The mask register holds bits for disabling the channels that are making request. Each channel can

be individually masked [disabled] from making requests.

D7-D3 = X [ Don’t Care ]

D2 = 0 Clear Mask ; 1 , Set Mask

D1 D0 Channel

Selection

0 0 Channel 0

Masked

0 1 Channel 1

Masked

1 0 Channel 2

Masked

1 1 Channel 3

Masked

Status Register :

The Status Register contains information about the channels whose requests are pending and the

channels which have reached their programmed TERMINAL COUNT(FINAL VALUE).

D7 = 1 , Request from Channel 3 is pending




D3 = 1 , Channel 3 has reached Terminal Count

D2 = 1, Channel 2 has reached Terminal Count

D1 = 1, Channel 1 has reached Terminal Count

Temporary Register :

The Temporary register holds the last byte transferred during a PREVIOUS MEMORY-MEMORY

transfer operation.

Operating Modes :

(i) Idle Cycle :

In this mode , no channel has a request activated in them.

8237 therefore samples each CHANNEL’s REQUEST line in each CLOCK cycle to

determine if any channel is requesting DMA service.

(ii) Active Cycle :

This mode is categorized into four sub modes. They are

Single Transfer Mode

Block Transfer Mode

Demand Transfer Mode

Cascade Mode

SINGLE TRANSFER MODE or CYCLE STEALING MODE :

Only 1 BYTE is transferred between memory and I/O devices through DMAC.

DMAC sends HOLD signal to microprocessor. On receiving acknowledgement signal

(HLDA) from microprocessor , DMAC gains control of the processor’s system bus and

EXECUTES ONLY ONE DMA CYCLE.

After transferring one byte , DMAC disables HOLD signal and enters into slave mode. Then

processor gains control of its system bus and executes next machine cycle.

BURST or BLOCK TRANSFER DMA MODE :

≥ 2 BYTES are transferred between memory and I/O devices through DMAC.

DMAC sends HOLD signal to microprocessor. On receiving acknowledgement signal (HLDA)

from microprocessor , DMAC gains control of the processor’s system bus and EXECUTES

ONE DMA CYCLE.

After transferring one byte , DMAC increments memory address , decrements counter and

transfers next byte.

The number of DMAC machine cycles depends on number of bytes to be transferred to the

microprocessor.

After transferring all data bytes , DMAC disables HOLD signal and enters into slave mode. .

Then processor gains control of its system bus and executes next machine cycle.

TRANSPARENT or HIDDEN DMA TRANSFER MODE :

Processor executes some states during which it releases its system bus.

DMAC transfers data between memory and I/O devices during these states. This operation

is known to the microprocessor.

An extra logic is required to determine when does the processor releases its system bus.

6. Architecture and Working of 8279 PKDI

Data Bus Buffer :


microcontroller.


buffer.

I/O Control :

Controls the data bus buffer of 8279. When A0 is 0 , data from the internal data bus flows in

the data bus buffer. When A0 is 1 , COMMAND WORD is transferred from CPU to 8279 or

STATUS WORD is transferred from 8279 to CPU.

Control and Timing Registers :

Store the keyboard and display modes and other operating conditions programmed by the

CPU.

The command sent by the CPU is latched onto the appropriate control register on the rising

edge of WR signal.

The different types of control registers are as follows :

KEYBOARD /DISPLAY COMMAND WORD:

KEYBOARD MODES

K K K MODE

0 0 0 Encoded Scan , 2-Key Lockout

0 1 0 Encoded Scan , N-key rollover

0 0 1 Decoded Scan , 2 Key Lockout

0 1 1 Decoded Scan , N-Key rollover

DISPLAY MODE

D D MODE

0 0 8 BYTES CHARACTER

DISPLAY – LEFT ENTRY


DISPLAY – RIGHT ENTRY


DISPLAY – LEFT ENTRY


DISPLAY – RIGHT ENTRY

PROGRAM CLOCK COMMAND WORD :

PPPPP varies from 2 (00010) to 31 (11111). This command word is used for dividing the

external clock signal by an integer varying from 2 to 31 in order to derive 100 kHz which in

turn is used for deriving scan and debounce times.

READ FIFO/SENSOR RAM COMMAND WORD :

In the FIFO RAM mode , the 8279 provides data to the CPU in the order it was entered into

the FIFO RAM.

In the SENSOR RAM MODE , the bits AAA is used for selecting a location [row] of SENSOR

RAM. To move from one address to another address of SENSOR RAM , the AI(Auto

Increment) bit is set to 1.

READ DISPLAY RAM COMMAND WORD :

The bits AAAA is used for selecting a location[row] of DISPLAY RAM. To move from one

address to another address of SENSOR RAM AFTER EACH READ OPERATION , the

AI(Auto Increment) bit is set to 1.

WRITE DISPLAY RAM COMMAND WORD :

The bits AAAA is used for selecting a location[row] of DISPLAY RAM. To move from one

address to another address of SENSOR RAM AFTER EACH WRITE OPERATION , the

AI(Auto Increment) bit is set to 1.

DISPLAY WRITE INHIBIT/BLANKING COMMAND WORD :

The IW (Inhibit Write) bits is used for preventing the altering of contents of DISPLAY RAM

OUTPUTS.

The BL [BLANK] bits is used for displaying BLANKING CODE at the DISPLAY RAM

OUTPUTS (All 0s or 20H or All 1s) whichever is specified in the CLEAR COMMAND.

CLEAR COMMAND WORD:

CD bits is used for displaying BLANKING CODE at the DISPLAY RAM OUTPUTS(All 0s or

20H or All 1s).

CF bits is used for disabling the IRQ(INTERRUPT REQUEST LINE) of FIFO RAM and reset

the SENSOR RAM location to 0.

CA bits is used for combining the operations of CD and CF bits. It also RESYNCHRONIZES

INTERNAL TIMING CHAIN.

END INTERRUPT / ERROR MODE SET COMMAND WORD :

For the SENSOR MATRIX MODE , this command word allows DATA to be WRITTEN INTO

SENSOR RAM by disabling IRQ line , which might have gone HIGH due to CHANGE IN

SENSOR VALUE.

For N-KEY ROLLOVER MODE , the E-bit(Error bit) is used for determining whether TWO

KEYS ARE PRESSED SIMULTANEOUSLY during SINGLE DEBOUNCE operation. If

occurred , E-bit is SET to 1.

Timing Control :

Consist of chain of counters that performs DIVIDE-BY-N operation in order to derive 100

kHz signal required for the operation of various internal components of 8279.

SCAN SECTION :

The scan section consist of a SCAN COUNTER that operates in two modes :

ENCODED MODE : In this mode , the output of the counter varies from 0000 to 1111.

These values are externally decoded by a 4:16 active high decoder circuit to generate SCAN

lines.

DECODED MODE : In this mode , the least significant two bits of the SCAN COUNTER

output are internally decoded by a 2:4 active low decoder circuit to generate SCAN lines

KEYBOARD SECTION :

The keyboard section consist of the following components :

RETURN BUFFER:

In SCANNED KEYBOARD and SENSOR MATRIX MODE , the contents of 8 return lines

(RL7 – RL0) are latched onto the RETURN BUFFER for each ROW SCAN.

In STROBED INPUT MODE , the contents of 8 return lines (RL7 – RL0) are transferred to

the FIFO RAM on the RISING EDGE of CNTL/STB pulse.

KEYBOARD DEBOUNCE AND CONTROL :

The main purpose of this block is to check whether a key remains in the pressed condition

for 10 ms and accordingly store the ADDRESS of the KEY + STATUS of SHIFT Key +

STATUS of CONTROL Key in the FIFO RAM.

FIFO / SENSOR RAM :

It acts as FIFO RAM in SCANNED KEYBOARD and STROBED INPUT MODES for

holding ROW of a keyboard matrix.

It acts as SENSOR RAM for holding ROW of a SENSOR MATRIX.

FIFO/SENSOR RAM STATUS :

This logic keeps track of whether FIFO or SENSOR RAM has become FULL or EMPTY.

When FULL , the logic sends an IRQ(Interrupt Request) to the CPU that keycode or sensor

status is available to be read.

DISPLAY SECTION :

The display section consist of the following components :

DISPLAY RAM:

It holds codes for the digits to be displayed. In decoded mode , 8279 uses FIRST 4

LOCATIONS of for 4 digit display . In encoded mode , 8279 uses first 8 locations for 8 digit

display and all 16 locations for 16 digits display.

DISPLAY ADDRESS REGISTER:

It holds the address of the DISPLAY RAM where a BYTE or SCAN COUNT VALUE is

stored. The address locations of DISPLAY RAM can be accessed sequentially by selecting

AUTO-INCREMENT option.

DISPLAY REGISTERS:

They hold the BIT PATTERNS for the characters to be displayed. The contents of display

registers A and B can be blanked and inhibited individually.

Operating Modes :

8279 operates in 3 Input modes and 2 output(Display) modes . The 3 input modes are as

follows:

Scanned Keyboard

Scanned Sensor Matrix

Strobed Input

Scanned Keyboard Mode is further sub-divided into four modes depending on

o Number of Scan Lines available and accordingly type of keyboard that can be

interfaced to 8279. (Encoded Scan and Decoded Scan Mode)

o Type of KEY DEPRESSION reading technique. (N-Key Rollover and 2-Key Lockout )

In Encoded Scan Mode , the 3 scan lines (SL2 – SL0) lines are externally decoded to provide

8 scan lines , thereby allowing 8 × 8 matrix keyboard. In Decoded Scan Mode , the 2 scan

lines (SL1 , SL0 ) are internally decoded to provide 4 scan lines , thereby allowing 4 × 8

matrix keyboard.

In 2-Key Lockout method , whenever a key is pressed the debounce logic checks for any

other key press during next two scans. If there is no key press detected , the debounce logic

assumes it to be a single key press and stores the corresponding keycode into the FIFO

RAM. As soon as a memory location of FIFO RAM is filled , the IRQ signal is set to indicate

CPU for the data to be read.

In N-key Rollover Method , whenever a key is pressed the debounce logic checks

whether the same key is in pressed during next two scans. If the key is still in the pressed

condition , the corresponding keycode is stored into the FIFO RAM. As soon as a memory

location of FIFO RAM is filled , the IRQ signal is set to indicate CPU for the data to be read

In Scanned Sensor Matrix Mode , a sensor matrix is connected to the SENSOR RAM.

Each row of the RAM represents a row in the SENSOR MATRIX. After storing the status of

a row in the sensor matrix into a SENSOR RAM location , any change in the sensor value is

checked. If present , the “S” bit (Sensor Closure) is set in the STATUS register and the IRQ

signal is set to indicate CPU for the data to be read. In encoded mode , size of sensor matrix

is 8 × 4 and in decoded mode , size of sensor matrix is 4 × 4.

In Strobed Input Mode , the DATA at the return lines are stored into the FIFO RAM

locations at the rising edge of CNTL/STB lines(Strobe or Control Lines).

In Left Entry or Type Writer Mode , the characters are displayed from LEFT to RIGHT.

Address 0 of Display RAM corresponds to LEFT MOST CHARACTER to be displayed and

Address 15 of Display RAM corresponds to RIGHT MOST CHARACTER to be displayed.

The locations of the Display RAM can be sequentially accessed by setting the AUTO-

INCREMENT bit.

In Right Entry or Calculator Mode , the characters are displayed from RIGHT to LEFT.

Address 0 of Display RAM corresponds to RIGHT MOST CHARACTER to be displayed and

Address 15 of Display RAM corresponds to LEFT MOST CHARACTER to be displayed.

I/O mapped I/O Interfacing of 8279 with 8085 Microprocessor:

ASYNCHRONOUS mode. 1 · 1 1 8-bits B2 B1 Baud rate factor 0 0 SYNC MODE 0 1 1 times TxC or RxC 1 0...

Documents

Transcript of ASYNCHRONOUS mode. 1 · 1 1 8-bits B2 B1 Baud rate factor 0 0 SYNC MODE 0 1 1 times TxC or RxC 1 0...