Asynchronous Asynchronous MachinesMachines

Asynchronous Asynchronous MachinesMachines

• Used slides from Mitch Thornton and Prof. Hintz

Reduce States

State Assignment

Flip-Flop or Latch Selection

Feedback Model for Asynchronous Sequential Networks

CombinationalLogicCircuit

n m

Present StateVariables, yi

Input Variables, X Output Variables, Z

xi

y1

s

1

zi

Next StateVariables, yi

y1

ysys

Asynchronous FSMAsynchronous FSMAsynchronous FSMAsynchronous FSM

Fundamental Mode Assumption– Only one input can change at a time

• Analysis too complicated if multiple inputs are allowed to change simultaneously

– Circuit must be allowed to settle to its final value before an input is allowed to change

• Behavior is unpredictable (nondeterministic) if circuit not allowed to settle

Asynch. Design DifficultiesAsynch. Design Difficulties

Delay in Feedback Path– Not reproducible from implementation to

implementation– Variable

• may be temperature or electrical parameter dependent within the same device

– Analog• not known exactly

Tell my stories how I worked with asynchronous machines in

1968

Stable StateStable State

• PS = present state• NS = next state• PS = NS = Stability

– Machine may pass through none or more intermediate states on the way to a stable state

– Desired behavior since only time delay separates PS from NS

• Oscillation– Machine never stabilizes in a single state

RacesRacesRacesRaces• A Race Occurs in a Transition From One

State to the Next When More Than One Next State Variables Changes in Response to a Change in an Input

• Slight Environment Differences Can Cause Different State Transitions to Occur– Supply voltage– Temperature, etc.

RacesRaces

01

10

11 00

PS

desired NS

if Y1 changes first

if Y2 changes first

Types of RacesTypes of Races

• Non-Critical– Machine stabilizes in desired state, but may

transition through other states on the way

• Critical– Machine does not stabilize in the desired state

RacesRaces

01

10

11 00

PS

desired NS

non- critical race

if Y1 changes first

if Y2 changes first

critical race

00

Asynchronous FSM BenefitsAsynchronous FSM Benefits

• Fastest FSM• Economical

– No need for clock generator

• Output Changes When Signals Change, Not When Clock Occurs

• Data Can Be Passed Between Two Circuits Which Are Not Synchronized

• In some technologies, like quantum, clock is just not possible to exist, no clocks in live organisms.

Asynchronous FSM ExampleAsynchronous FSM Example

next

statepresent

statey1

y2

input

Next State VariablesNext State Variables

12

2212

2211

2211211

,,

,,

yxy

yxyyyxY

yxyyxyx

yxyyxyxyyxY

You can analyze this machine at home

Asynchronous State TablesAsynchronous State TablesAsynchronous State TablesAsynchronous State Tables

States are either Stable or Unstable.

Stable states encircled with symbol. Present

stateNext state, output

x=0 x=1

Q0 Q0,0 Q1,0

Q1 Q2,0 Q1,0

Q2 Q2,0 Q3,1

Q3 Q0, 0 Q3,1

Oscillations occur if all states are unstable for an input value.

Total State is a pair (x, Qi)

Constraints on Asynchronous Constraints on Asynchronous NetworksNetworks

Constraints on Asynchronous Constraints on Asynchronous NetworksNetworks

If the next input change occurs before the previous ones effects are fed back to the input, the machine may not function correctly.

Thus, constraints are needed to insure proper operation.

Fundamental Mode – Input changes only when the machine is in a stable state.

Normal Fundamental Mode – A single input change occurring when the machine is in a stable state produces a single output change.

Example 8.4Example 8.4Example 8.4Example 8.4

Present state

Input x1,x2

00 01 11 10

Q0 Q0,01 Q0,01 Q0,00 Q1,00

Q1 Q1,10 Q0,10 Q0,10 Q1,10

Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.

Find state table for network

z1z2

Example 8.5Example 8.5Example 8.5Example 8.5

Present state

Input x1,x2

00 01 11 10

Q0[\ =00 Q2 Q3 Q0 Q1

Q1 = 01 Q1 Q0 Q0 Q1

Q2 = 11 Q0 Q0 Q0 Q0

Q3 = 10 Q3 Q3 Q0 Q0

Analyze circuit with fundamental model

State Code

y1,y2

Q0 00

Q1 01

Q2 11

Q3 10

Ask student to do this analysis

Example 8.5 Example 8.5

Present state

Input x1,x2

00 01 11 10

Q0 Q2 Q3 Q0 Q1

Q1 Q1 Q0 Q0 Q1

Q2 Q0 Q0 Q0 Q0

Q3 Q3 Q3 Q0 Q0

State Code

y1,y2

Q0 00

Q1 01

Q2 11

Q3 10

Analyze circuit without fundamental mode

Example 8.6Example 8.6Example 8.6Example 8.6Design the network for the given state table using SR-latches

Use state

assignmentPresent

stateNext state, output

x=0 x=1

Q0 Q0,0 Q1,0

Q1 Q2,0 Q1,0

Q2 Q2,0 Q3,1

Q3 Q0, 0 Q3,1

State Code

y1,y2

Q0 00

Q1 01

Q2 11

Q3 10

Example 8.6 (Continued)Example 8.6 (Continued)Use S when state variable must change from 0 to 1Use R when state variable must change from 1 to 0

Use s when state variable remains 1Use r when state variable remains 0

Example 8.7 – D Flip-FlopExample 8.7 – D Flip-FlopExample 8.7 – D Flip-FlopExample 8.7 – D Flip-Flop

Present state

Input x1,x2

00 01 11 10

Q0 Q0 Q1 Q0 Q0

Q1 Q0 Q1 Q2 Q2

Q2 Q3 Q2 Q2 Q2

Q3 Q3 Q2 Q0 Q0

Design the circuit from the state table using SR-latches

Example 8.8Example 8.8Example 8.8Example 8.8Derive the state table from the circuit

1’s where Set and (present state is 1 and not R)

y1,y2 Present state

Input x1,x2

00 01 11 10

00 Q0 Q0 Q1 Q0 Q0

01 Q1 Q0 Q1 Q1 Q2

11 Q2 Q0 Q2 Q3 Q2

10 Q3 Q0 Q0 Q3 Q3

Example 8.8 (Continued)Example 8.8 (Continued)

Race Conditions - Example 8.9Race Conditions - Example 8.9Race Conditions - Example 8.9Race Conditions - Example 8.9Race Condition – when two or more variable change at a time

Critical Race – final state dependent on order in which the state variables change

Present state

Input x1,x2

00 01 11 10

Q0 Q1 Q0 Q0 Q3

Q1 Q1 Q1 Q1 Q3

Q2 Q2 Q1 Q2 Q3

Q3 Q1 Q1 Q0 Q3

State Code

y1,y2

Q0 00

Q1 01

Q2 11

Q3 10

Present state

y1,y2 Input x1,x2

00 01 11 10

Q0 00 01 00 00 10

Q1 01 01 01 01 10

Q2 11 11 01 11 10

Q3 10 01 01 00 10

Input x1,x2 10 00

10, 00, 01 ok

10, 11, 01 not ok.

Avoiding RaceAvoiding Race

Present state

Input x1,x2

00 01 11 10

Q0 Q1 Q0 Q0 Q3

Q1 Q1 Q1 Q1 Q3

Q2 Q2 Q1 Q2 Q3

Q3 Q1 Q1 Q0 Q3

Q3

Q1

Q2

Q0

State Adjacency DiagramState Adjacency Diagram

Impossible to have hamming distance of 1 between all adjacent states. Must add states.

Table from previous

page

Asynchronous Machine Asynchronous Machine HazardsHazards

Asynchronous Machine Asynchronous Machine HazardsHazards

Steady-State Hazards – Occurs when a sequential network goes to an erroneous state due to gate delay.

Present state

y1,y2 Input x1,x2

00 01 11 10

Q0 00 01 00 00 10

Q1 01 01 01 01 10

Q2 11 11 01 11 10

Q3 10 01 01 00 10y2 = x1x2 + x2 y2+ x1y1

y1= x1x2 + x1 y1y2+ x2 y1y2

Static-1 Hazard

In (01, Q1) consider input change (00) (01)

Steady-State HazardsSteady-State HazardsSteady-State HazardsSteady-State Hazards

y2 = x1x2 + x2 y2+ x1y1 + x1 y2

y1= x1x2 + x1 y1y2+ x2 y1y2

Elimination of Static-1 Hazard

Hazard Example Feedback Sequential Implementation

Hazard Example Feedback Sequential Implementation

Maps resulting from State Table 8.5, Example 8.7

Essential HazardEssential HazardEssential HazardEssential Hazard•Essential Hazard –

•Erroneous sequential operation that cannot be cannot be eliminated without eliminated without controlling delayscontrolling delays in the circuit.

•Not affected by elimination of combinational logic hazards.

Essential Hazard ExampleEssential Hazard Example

Present state

Input x

0 1

Q0 = 00 Q0 Q3

Q1 = 01 Q0 Q1

Q2= 11 Q2 Q1

Q3 = 10 Q2 Q3

Slow

Starting in stable state Q2 with input 0 1

Caused by multiple paths for x

Students should complete this example in class, Students should complete this example in class, on Friday or at homeon Friday or at home