Assignment-3 Support Files
7
Main Decoder Control outputs State (Name) PCWrite MemWrite IRWrite RegWrite ALUSrcA Branch IorD MemtoReg RegDst ALUSrcB[1 PCSrc[1:0 ALUOp[1:0 FSM Control Word 0 (Fetch) 1 0 1 0 0 0 0 0 0 01 00 00 0x5010 1 (Decode) 0 0 0 0 0 0 0 0 0 11 00 00 0x0030 2 (MemAdr) 0 0 0 0 1 0 0 0 0 10 00 00 0x0420 3 (MemRd) 0 0 0 0 0 0 1 0 0 00 00 00 0x0100 4 (MemWB) 0 0 0 1 0 0 0 1 0 00 00 00 0x0880 5 (MemWr) 0 1 0 0 0 0 1 0 0 00 00 00 0x2100 6 (RtypeEx) 0 0 0 0 1 0 0 0 0 00 00 10 0x0402 7 (RtypeWB) 0 0 0 1 0 0 0 0 1 00 00 00 0x0840 8 (BeqEx) 0 0 0 0 1 1 0 0 0 00 01 01 0x0605 9 (AddiEx) 0 0 0 0 1 0 0 0 0 10 00 00 0x0420 10 (AddiWB) 0 0 0 1 0 0 0 0 0 00 00 00 0x0800 11 (JEx) 1 0 0 0 0 0 0 0 0 00 10 00 0x4008 Table 1 Expected Instruction Trace Cycle Reset PC Instr (FSM) state SrcA SrcB ALUResul t Zero 1 1 00 0 0 00 04 04 0 2 0 04 addi 20080042 1 04 108 10C 0 3 0 04 addi 20080042 9 00 42 42 0 4 0 04 addi 20080042 10 04 00 04 0
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MIPS
Transcript of Assignment-3 Support Files
Main Decoder Control outputs
State
(Name)PCWriteMemWriteIRWriteRegWriteALUSrcABranchIorDMemtoRegRegDstALUSrcB[1:0]PCSrc[1:0]ALUOp[1:0]FSM Control Word
0 (Fetch)1010000000100000x5010
1 (Decode)0000000001100000x0030
2 (MemAdr)0000100001000000x0420
3 (MemRd)0000001000000000x0100
4 (MemWB)0001000100000000x0880
5 (MemWr)0100001000000000x2100
6 (RtypeEx)0000100000000100x0402
7 (RtypeWB)0001000010000000x0840
8 (BeqEx)0000110000001010x0605
9 (AddiEx)0000100001000000x0420
10 (AddiWB)0001000000000000x0800
11 (JEx)1000000000010000x4008
Table 1
Expected Instruction Trace
CycleResetPCInstr(FSM) stateSrcASrcBALUResultZero
1100000004040
2004addi
2008004210410810C0
3004addi
2008004290042420
4004addi
20080042100400040
5004addi
2008004200404080
6008j
0800000810820280
7008j
08000008110800080
8020j
0800000802004240
9024beq
1000fff9124FFFF
FFE4080
10024beq
1000fff980000001
11008beq
1000fff9008040C0
1200Caddi
2009000410C101C0
1300Caddi
2009000490004040
1400Caddi
20090004100C000C0
1500C2009000400C04100
160100109502211000014088000140980
1701001095022642043E0
180100109502271004140
19010sub
0109502201004140
200140148582511400016094000160A80
210140148582563E427E0
220140148582571442560
23014014858250144180
24018sw
ac0b002c118B0C80
25018ac0b002c2002C2C0
26018ac0b002c5187E960
27018ac0b002c018041C0
2801Clw
8d2c002811CA0BC0
2901C8dc2c0028204282C0
3001C8dc2c002831C001C0
3101Clw
8d2c002841C001C0
3201Clw
8d2c002801C04200
33020j
080000071201C3C0
34020j
08000007112000200
3501Cj
0800000701C04200
36020j
080000071201C3C0
37020j
08000007112000200
Table 2Verilog Code
`timescale 100us/1ps
module alu_32_bit(input [31:0]a,input [31:0]b,input [2:0]sel,output [31:0]y,output z,output ov);
wire [31:0]b1;
assign b1=(sel[2])?(~b):b;
assign d=(sel==3'd6)?1'b1:1'b0;
wire [31:0]ornot;
wire [31:0]andnot;
wire [31:0]c;
wire [31:0]slt_equater;
addersub AA1(a,b1,d,c);
ornot AA2(a,b1,ornot);
andnot AA3(a,b1,andnot);
slt_equater AA4(a,b1,slt_equater);
assign z=~(|y);
assign ov=y[31]^ y[30]^ y[29];
assign y=((~sel[0])&(~sel[1]))?andnot:((sel[0])&(~sel[1]))?ornot:((~sel[0])&(sel[1]))?c:slt_equater;
endmodule
module addersub (input [31:0] a, input[31:0] b, input d,output [31:0] c1);
wire[31:0] c2;
wire c3,c4;
assign {c3,c2}=a+b;
assign {c4,c1}=c2+d;
endmodule
module ornot (input [31:0] a, input [31:0] b, output [31:0] ornot);
assign ornot=a | b;
endmodule
module andnot (input [31:0] a, input [31:0] b, output [31:0] andnot);
assign andnot= a & b;
endmodule
module slt_equater (input [31:0] a, input [31:0] b, output [31:0] slt_equater);
wire cry;
wire [31:0] c1;
assign {cry,c1}=a+(b+1);
assign slt_equater = 00000000000000000000000000000000 + c1[31];
endmodule
module MIPS_MC(input clk, input reset,output reg [31:0]PC, output [31:0] ALUResult);
reg [31:0] Instr;
wire IorD,PCWrite,PCWriteCond,MemtoReg,MemWrite,MemRead,IRWrite, RegDst, RegWrite;
wire [1:0] ALUOp,PCSource;
wire [2:0] ALUControl;
wire [1:0]ALUSrcB;
wire [1:0]PCSrc;
wire [31:0] writefromdata1;
wire [31:0]readfromdata1;
wire [31:0]readfromdata2;
wire [4:0]Rd;
reg [31:0]A;
reg [31:0]B;
wire [31:0]PC_out;
wire [31:0]SrcA;
wire [31:0]SrcB;
wire [31:0]Sign_extend_data;
reg [31:0]ALUOut;
wire Zero;
wire [31:0]Address;
wire [31:0] WriteData;
wire [31:0] ReadData;
wire [31:0]PCplus4;
wire [31:0]In_4=32'd4;
wire [31:0] Shift32bit_left_2_out_branch;
wire [27:0] Shift_left_2_out_jump;
wire [31:0] PCBranch;
wire [31:0]PC_out_Branch_or_PCplus4;
wire [31:0]PCJump;
wire out;
wire PCen;
wire [31:0]RD;
wire [14:0]FSM_COntrol_Word;
wire [31:0]instrctnmemaddr;
reg [31:0]memdatareg;
wire ALUSrcA;
always@(posedge clk)
begin
if(reset)
PCRd
Register_File R_F(clk,reset, Instr[25:21], Instr[20:16], Rd , writefromdata1,RegWrite,readfromdata1, readfromdata2);
assign SrcA=(ALUSrcA)?A:PC;
assign Sign_extend_data = {Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15:0]};
assign SrcB=((ALUSrcB==2'b00)?B:((ALUSrcB==2'b01)?32'd4:((ALUSrcB==2'b10)?Sign_extend_data:Shift32bit_left_2_out_branch)));
ALUCntrlUnit A_U(ALUOp,Instr[5:0],ALUControl);
alu_32_bit alu(SrcA, SrcB, ALUControl, ALUResult, Zero, Ov);
assign writefromdata1=(MemtoReg)?memdatareg:ALUOut;
endmodule
module Shift32bit_left_2(input [31:0] Sign_extend_data,output [31:0] Shift32bit_left_2_out_branch);
assign Shift32bit_left_2_out_branch={Sign_extend_data[29:0],2'b00};
endmodule
module Shift26bit_left_2(input [25:0] Jump_data_in ,output [27:0] Shift_left_2_out_jump);
assign Shift_left_2_out_jump={Jump_data_in[25:0],2'b00};
endmodule
module Add(input [31:0] a, input[31:0] b,output [31:0] c);
assign c=a+b;
endmodule
