Assgn Ques

2
Group 1 1. Explain the operation of Master slave JK flipflop. 2. Design a MOD-72 synchronous counter using positive edge triggered JK flip (with Active low clear and Preset Logic). Group 2 3. Draw the Internal Block diagram 8086 microprocessor and explain the functionality of each blocks 4. Design a MOD-30 synchronous counter using positive edge triggered JK flip (with Active low clear and Preset Logic). Group 3 5. List down the various addressing modes of 8086 and explain each of them with example. 6. Design an 8 bit serial in serial out shift register using D flip flops. Group 4 7. Implement a logic circuit for BCD to 7 segment decoding (Hint: Use K- map for generating simplified boolean expression for segments a to g) 8. (i) Explain the operation of a JK flip flop. (ii) Implement a D flip flop using JK flip flop. Group 5 9. Minimize the expression, Z = f(A,B,C) = + B + AB + AC Using K-map method. 10. Design a Mod-32 Updown counter using JK flipflop. Group 6 11. Explain functionality of D flip-flop, JK flip-flop, SR flipflop using truth table. 12. Design a 4 bit parallel in serial out shift register. Input named ‘Load’ and ‘shift’ must be used in the circuit.

description

DSMP

Transcript of Assgn Ques

Group 1

1. Explain the operation of Master slave JK flipflop.2. Design a MOD-72 synchronous counter using positive edge triggered JK flip (with Active low clear and Preset Logic).

Group 2

3. Draw the Internal Block diagram 8086 microprocessor and explain the functionality of each blocks

4. Design a MOD-30 synchronous counter using positive edge triggered JK flip (with Active low clear and Preset Logic).

Group 35. List down the various addressing modes of 8086 and explain each of them with example.

6. Design an 8 bit serial in serial out shift register using D flip flops.

Group 4

7. Implement a logic circuit for BCD to 7 segment decoding (Hint: Use K- map for generating simplified boolean expression for segments a to g)

8. (i) Explain the operation of a JK flip flop.

(ii) Implement a D flip flop using JK flip flop.

Group 5

9. Minimize the expression, Z = f(A,B,C) =+B + AB+ AC Using K-map method.10. Design a Mod-32 Updown counter using JK flipflop.Group 6

11. Explain functionality of D flip-flop, JK flip-flop, SR flipflop using truth table.12. Design a 4 bit parallel in serial out shift register. Input named Load and shift must be used in the circuit.

(i)If Load = 1 new parallel Data must be loaded to registers.

(ii) If shift = 1 data should be shifted out

(iii) If load = shift = 0, then register should maintain previous data.

Group 7

13. Explain the operation of full adder, half adder, half subtractor and full subtractor using the logic circuits and Truth table and draw the circuits with(i)NAND only (ii) NOR gates only.

14. Design an XOR gate using 4:1 multiplexer.