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    IL2450 - System Level Validation

    Tutorial

    Introduction To Assertions

    V. 2.0 April 10, 2008

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    Purpose of the tutorial

    This tutorial focuses on assertions and on how to use them in theIncisiveenvironment.

    Introduction

    Assertions are used to make assumptions while coding a design. The simulator tests those assumptions

    and generates results for every assertion. Assertions can be placed in a separate file or embedded

    directly in the source code. Assertions are actively monitored during simulation. Assertions are like any

    other design object: they can be probed and displayed in the navigator, waveform and other simulation

    debugging windows in SimVision. SimVisionprovides also some extra features for assertions like the

    Assertion Browser, where the current state of the assertion can be displayed during simulation, as well

    as the failure counts.

    Enabling assertions in simulation

    1 Create a directory for this project. Move to this directory, then download (using wgetor some other

    method) the file assertion.vfrom the course website. It is a very simple file in which signals are driven

    and one assertion is present. Please take your time to read through the file carefully until you

    understand it in every detail. StartNCLaunchand make a new project in the directory.

    2 When you compile the file assertion.vyou will have to activate support for assertions. To do that,

    right click on the filename in the file browser. Right-click on it, select NCVlog. In the popup window,

    select Advanced Options Assertions Enable assertion language processing, as shown in the

    following window:

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    Note that it would be possible to define assertions in an external file. This is an useful feature, but will

    not be discussed in this tutorial.

    Click OK in the Verilog Compiler Advanced Options window, then click OK again to launch the

    compilation.

    Once the compilation is done, you can elaborate the compiled object. Right-click on the snapshot

    obtained from elaboration and select NCSim...Accept the defaults in the popup window to run the

    simulation in GUI mode.

    Probing assertions in SimVision

    To monitor assertions in the SimVisionwaveform window for debugging, you need to probe them. Note

    that failures are reported every time, whether an assertion is probed or not. When an assertion is

    probed, a database is automatically created to store the information.

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    1 To create an assertion probe, right click on the assertion CHECK_REQ_WHEN_GNTin the signal

    list (you may first need to select the moduleEXPER_assertin the design browser) and select Create

    Probe.... Alternatively, it is possible to select the assertion in the design browser and select Simulation

    Create Probe...in theNCLaunchmenu. In either case, a popup window similar to the one in the

    following figure will pop up:

    You do not need to enter any name for the probe. Be sure that assertions is selected in the Probe these

    dropdown list.

    Set theRecord assertion asoption to State probe (it should be the default).

    To be able to view the probe in the waveform window, be sure that theAdd to waveform displaybutton

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    is activated.

    Click OKto confirm and exit the window.

    2 Run the simulation. The simulation will run until the assertion fails, at 22 ns. A message in the

    console will then be outputted and the simulation will stop. Go the waveform window. The state of the

    assertion should now be probed and the value of the assertion should be displayed. You can click again

    the Run button (or select Simulation Run in the menu) to make the simulation continue. The

    simulation will stop again when the assertion fails again. Resume the simulation once again and the

    simulation will run until the $finishstatement is encountered at time 13 ns.

    Take a look at the waveform window. The state of the assertion is monitored. Assertions can assume 5

    different states:

    Inactive: There are no matches of the sequence/conditions described by the assertion at the

    moment.

    Active: The first expression (or the first expressions) of the condition is (or are) satisfied, and

    the assertion has still not finished and not failed.

    Finished: The specified condition for the assertion has evaluated to true.

    Failed: The specified condition for the assertion has evaluated to false.

    Disabled: The assertion has been disabled by an assertion disable command or some other

    external control.

    Take your time to check whether the values taken by the assertion correspond to your expectations.

    3 Close the waveform window. In the design browser, right click on the assertion and select Create

    probe...again. This time, select to record the assertion as Failure Event in the popup window. Keep

    default values for the other parameters. Run the simulation again (remember to resume simulation each

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    time it gets stopped by a failed assertion). Check the waveforms in the waveform browser. As you can

    see, at each time instant the probe corresponds to the number of failed assertions that have occurred

    before that time instant, the value of the probe is incremented by one unit each time the assertion fails,

    as shown in the following window:

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    4 The last probe option is to create transaction probes. As you did before, create a new probe for the

    assertion. In the Create Probewindow, choose to record the assertion as transaction.

    Note that all the commands you are giving through the GUI can also be given by typing commands on

    the console. You can check the console to see the commands that are given whenever you give a

    command from the GUI. Giving commands from the console can be very useful because console

    commands can be inserted in scripts to automatize the process. Note also that you can see more than

    one probe for each assertion in the waveform window: it is possible to have all the different types of

    probes for the assertions in the same waveform window.

    When you record assertions as transactions, the waveform window shows the assertions as it does with

    transactions. The beginning of the transaction corresponds to the first cycle in which the enabling

    condition becomes true. The end of the transaction shows when the assertion finished or failed. In

    addition, Transaction Explorer can be used to search for specific transaction data.

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    Assertion browser

    SimVision contains an Assertion Browser for monitoring assertions.

    1 Breakpoints can be triggered by assertions. To set a breakpoint on an assertion from the GUI, right-

    click on the assertion in the design browser, and select break on change. When the simulation is

    running, it will stop each time there is a change in the assertion state. If you select the assertion in the

    design browser and you select Simulation Set Breakpoint Assertion...it is possible to select more

    advanced options for the conditions triggering the breakpoint, but this will not be covered in this

    tutorial.

    2 To open the assertion browser, select Windows New Assertion browserfrom any SimVision

    window. The Assertion browser will pop up. The assertions in your design will be displayed. You

    should see something similar to this window:

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    Different information on the assertions is diplayed in the Assertion Browser. This can be personalized,

    but, by default, the following information is reported:

    The TotalandDisplayedlines show values associated with the current state of the assertions.

    TheAssertion Namecolumn shows the label or property name assigned to the assertion.

    TheModulecolumn shows the name of the module where the assertion is defined.

    TheInstancecolumn shows the name of the instance in which the assertion is located.

    The Current Statecolumn shows the current state of the assertion, which can be inactive, active,

    finished, failed or disabled.

    The Checkedcolumn shows one of the following:

    The number of cycles in which the property reached a state in which failure became

    possible.

    The number of active cycles plus a disabled indicator.

    A neverindicator to show that the transaction has never been active.

    A disabledindicator to show that the assertion has been disabled from the beginning.

    The Finished Countcolumn counts the number of times the assertion finished.

    The Failed Countcolumn counts the number of times the assertion failed.

    3 Reset and run the simulation. It will stop when the state of the assertion will first change, at 6 ns.

    Note that the color of the assertion in the assertion browser changes according to its state.

    4Right-click on the assertion and select describe. A report on the assertion will be outputted to the

    console. In this order, the following information will be reported:

    The assertion name

    The current state of the assertion

    The state transitions that are logged and the name of the asserttion log file

    Whether error counting is on or off

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    Assertion information display

    Information regarding the assertions can be displayed also by issuing commands on the console.

    5 The describe command can be accesses by console by issuing the command describe, which takes

    as argument the name of the assertion that has to be described:

    ncsim describe EXPER_assert.CHEK_REQ_WHEN_GNT

    Try to issue this command in the console and check the output.

    6 Another command which you can use from the console is the command value, which also takes as

    argument the name of one assertion. Issuing:

    ncsim value EXPER_assert.CHEK_REQ_WHEN_GNT

    will output to the console the state of the assertion.

    7 The command assertions can be used to display and manage assertions. Issuing:

    ncsim assertion -summary

    will display a summary of the assertions in the design, as shown in the following figure:

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    8 Issue the command:

    ncsim assertion -strict on

    By default, the strictoption is off. By issuing the command, you turned it on. When the strictoption is

    on, counting of vacuous pass conditions and of simultaneous finish and fail conditions is activated.

    Also, action blocks are run also on vacuous pass conditions. Assertions' summary changes when this

    option is activated. However, since there are no vacuous passes and no simultaneous finish and fail

    conditions in our example, the behaviour of the simulator will not change when the option is on. You

    can turn it off by issuing:

    ncsim assertion -strict off

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    Assertions in the other SimVision windows

    Assertions and their properties can be monitored in the different SimVision debugging windows.

    1- Open the Assertion Browser, double-click on the assertion. The Source Browser will pop up, as

    shown in the following figure:

    2 When you move the cursor over an assertion name in the Source Browser, the assertion name and its

    current value are displayed over the source code. If you have more than one assertion in your design,

    you can select in the menu SelectAssertions, and all the assertions will be selected.

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    3 The register window can be used to view assertions and monitor the values during the simulation.

    Select Windows New Design Browser from the menu of any SimVision window. A register

    window will pop up, You can expand and use the mini design browser hidden at the left border of the

    window to select the assertion you want to monitor. Click on the module name in the upper part of the

    mini design browser, then click on the assertion name in the bottom part of the same window and the

    assertion will be added to the register window. Run the simulation and you will see the state of theassertion change:

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    4 The Trace Signals sidebar can be used to trace a failing assertion or a signal back to its source. To

    open the Trace Signals sidebar, right-click on an assertion and select Trace Driving Logic. The Trace

    Signals sidebar will pop out. In the toolbar it is possible to see the signals driving the assertion.