Assembly and Packaging (Part 1) - Personal webpages at...

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TFE4180 Semiconductor Manufacturing Technology

Assembly and Packaging (Part 1)Chapter 20 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda

Saroj Kumar Patra,TFE4180 Semiconductor Technology,

Norwegian University of Science and Technology ( NTNU )

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Objectives

• Describe the general trends and design constraints ofassembly and packaging.

• State and discuss the traditional assembly methods.

• Describe the different traditional packaging options.


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• Final assembly and packaging, the back-end of the IC manufacturing process

• Two distinct processes


Introduction

4 Traditional Final Assembly and Packaging Process (Encapsulation)

Wafer test and sort

Wire bond

Die Separation

Plastic packaging Final packaging and test

Die Attach


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Four Important Functions of IC Packaging

1. Protection from environment and handling damage2. Interconnections for signals into and out of the chip3. Physical support of the chip4. Heat dissipation


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Quad flat pack(QFP)

Leadless chip carrier(LCC)

Plastic leaded chip carrier(PLCC)

Dual in-line package(DIP)

Thin small outline package(TSOP)

Single in-line package(SIP)


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Design Constraints for IC Packaging


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Levels of IC Packaging

Main electronics assembly board

2nd level packaging: Printed circuit board (PCB) assembly

1st level packaging: IC-packaging

Final product assembly: Final assembly of circuit boards into system

Metal leads for mounting onto printed circuit board

Pins

Pins are inserted into holes then soldered on rear of PCB.

Surface mount chips are soldered

on top of copper pads

ont the PCB.

Edge connector plugs into main system

PCB subassembly

Leads


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Traditional Assembly


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Four Steps of Traditional Assembly

• Backgrind• Die separation• Die attach• Wire bonding


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Backgrind

Rotating and oscillating spindle

Wafer on rotating chuck

Downforce

Table rotates only during indexing of wafers


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Advantages of Thinning Wafers

• Thinner wafers are easier to dice into chips• Improved thermal dissipation• Reduces thermal stresses in thin ULSI packages• Thinner chips reduce the size profile and weight of

the final IC package


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Wafer

Stage

Blade

Die Separation


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Die AttachDieLeadLead Frame

Plastic DIP

http://www.youtube.com/watch?v=syMdS02P3_w

- Selected die is attached- Automated process


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Different Methods of Die Attaching

• Epoxy attach• Eutectic Au-Si attach• Glass frit attach

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Epoxy Attach

Chip

Epoxy

Lead Frame


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Eutectic Au-Si Attach

Silicon

Gold Film

Gold/Silicon eutectic alloy

Lead Frame


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Glass Frit Attach

Mixture of silver and glass particles suspended in an organic medium


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Wire Bonding

Electrical connection from chip surface to inner lead terminal

http://www.youtube.com/watch?v=VwOEQodkBrY


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Wire Connection Between Bonding Pad and Lead Frame

Moulding compound

LeadframeBonding pad

Die

Bond wire

Pin Tip


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Different Methods of Wire Bonding

• Thermocompression bonding

• Ultrasonic bonding

• Thermosonic ball bonding

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Thermocompression Wedge Bonding

Lead-terminal

Wedge bondDevice Bond pad

Heat

Pressure


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Ultrasonic Bonding

Wire

Wedge tool

(1)

Tool moves upward

Wire fed

(3)

Ultrasonic energy

Pressure

Lead Frame

(4)

Tool moves upward

Wire Breaks

(5)

(2)

Al bonding pad

Ultrasonic energy

Pressure

Die


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Ball Bonding

(2)

H2 TorchBall

(1)

Gold WireCapillary tool

(5)

Pressure and heat

Lead Frame

(6)

Tool moves upward

Wire Breaks at the bond

Bonding ball onpad

Pressure + Ultrasonic energy

Die

(3)

Tool moves upWire Fed

Die(4)


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Comparison Among Methods

Al, AuAuYes100-150 oCLowBall bonding

Al, AuAu, AlYes25 oCLowUltrasonic

Al, AuAu,No300-500 oCHighThermo Compression

PadWireUltrasonic energyTemperaturePressureType


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Wirebond Quality Measuring

• Visual inspection

• Pull test


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Visual Inspection

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Wire broken Wire missing Ball short circuit

• Used to detect wirebonding failures


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Pull Test

TerminalDevice

Chip under test

Hook

Holder

• Quantitative assessment of wirebond quality


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Traditional Packaging

• Metal packaging

• Plastic packaging

• Ceramic packaging


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Metal Packaging• Was common in early history of Semiconductor industry

• Still used today in special cases

Die

Gold‐plated header

Wirebonds

Leads


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Transistor Outline (TO) Type Metal Package

Used for packaging this type of devices:

• Semiconductor lasers, solid-state lasers with a diode pumping • Photodetectors, matrix photodetectors (CCD, FPA) • X-Ray detectors• Transistors, operational amplifiers, etc.

Voltage regulatorin TO3 package [2]

Laser diodein TO39 package [1]


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Plastic Packaging• Industry mainstay since its introduction• Highly popular due to:

o flexibility of the lead shape (gull-wings, J-leads, PIH) o high volume production techniques

DieLeadframe

Tie bar

Tie bar removallines

Leadframe [3]


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Packaging procedure• Molding • Deflashing• Component lead forming• Lead finish


Plastic Packaging

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Plastic Dual In-Line Package (DIP)A type of through-hole mount package with lead pins protruding from both sides of the package.

Used for packaging this type of devices:

Microcontrollers, logic elements, memory, operational amplifiers, buffers, optocouplers, timers, signal generators, etc.

DIP20 package [4] DIP6 package [5]


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Single In-Line Package (SIP)

A single row of leads protruding from the bottom of its body.

SIP's are often used in packaging:• networks of multiple resistors• single on chip amplifier solutions• voltage regulators

Power controller in SIP package [6]

Audio power amplifier in SIP package [7]

Resistor network in SIP package [8]


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TSOP with Gull Wings

• Low profile• Tight lead spacing• High pin count• Used for surface mount

TSOPs are often used in packaging memory modules (SRAM, Flash memory, FSRAM and E2PROM)

SDRAM [9] DRAM [10]

TSOP - Thin Small Outline PackageGull Wings – shape of the pins


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QFP with Gull Wing andSurface Mount Leads

• QFP – Quad Flat Pack

• Socketing such packages is rare and through-hole mounting is not possible.

• Used for packaging memory, processors, controllers, ASIC, DSP, etc.

80‐pin Microprocessor in TQFP package [12]

TQFP ‐ Thermally Enhancedpackage [11]


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PLCC with J-Leads

• PLCC - Plastic Leaded Chip Carrier

• Used for surface mount

• Used for packaging memory, processors, controllers, ASIC, DSP

EEPROM from ALTERA [13]

PAL from TIin 28 pin package [14]


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Leadless Chip Carrier (LCC)

LCC from Tektronics [15]

• Used for packaging CMOS image sensors, MEMS,crystal oscillator filters, antenna switch modules

• Available in plastic and ceramic packaging


40 Ceramic PackagingUsed for the state of the art devices that require:• maximum reliability • high-power• hermetic seal

Two main methods of ceramic packaging: • Refractory ceramic (used for high performance IC packaging)• Laminated ceramic (low cost approach used to create CerDIP package)

CPGA [16]

OpAmp from AD in CerDIP package for use in harsh environment [17]


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g{tÇ~ lÉâ


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References[1] http://www.thorlabs.com/images/large/21973‐lrg.jpg[2] http://media.digikey.com/photos/Texas%20Instr%20Photos/296‐TO‐3‐8.jpg[3] http://www.ue.com.hk/index.php/SOIC_%28Small_Outline_Integrated_Circuit_Packages%29[4] http://www.chinaicmart.com/uploadfile/ic‐doc/261‐20‐DIP.jpg[5] http://media.digikey.com/photos/Fairchild%20Semi%20Photos/46‐6‐DIP%20WHITE.jpg[6] http://www.infineon.com/cms/en/corporate/press/news/releases/2009/INFXX200906‐063.html[7] http://sjostromaudio.com/pages/hifi‐projects/36‐hifi‐projects/82‐qrp01‐the‐gainclone‐high‐performance‐power‐

amplifier?showall=1[8] http://www.emartee.com/product/41417/Resistor%20Network%2010K%20OHM%209P%208RES%20SIP[9] http://rocky.digikey.com/weblib/Micron/Web%20photos/557‐86‐TSOP.jpg[10] http://s.eeweb.com/resized/images/remote/http_s.eeweb.com/quizzes/2011/02/22/dram‐tsop‐

1298440075_500_327.png[11] http://www.analog.com/en/technical‐library/packages/qfp‐quad‐flat‐pack/tqfp‐thermally‐enhanced/index.html[12] http://en.wikipedia.org/wiki/File:PIC18F8720.jpg[13] http://ca.digikey.com/1/1/1042179‐ic‐max‐7000‐cpld‐64‐68‐plcc‐epm7064lc68‐15.html[14] http://media.digikey.com/photos/Texas%20Instr%20Photos/296‐28‐PLCC.jpg[15] http://component‐solutions.tek.com/services/ic‐packaging/packaging‐tech/#leadless‐chip‐carrier[16] http://www.interfacebus.com/ic‐package‐Ceramic‐PGA‐package‐dimensions.html[17] http://www.analog.com/en/technical‐library/packages/dip‐dual‐inline‐package/cerdip‐side‐or‐bottom‐

brazed/index.html


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