ASP-DACAsia and South Pacific DesignAutomation Conference 1999

January 18 - 21, 1999Hong Kong Convention and Exhibition

CenterWanchai, Hong Kong

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ASP-DAC99:Cover PageFront MatterTable of ContentsSession Index

Author Index

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Proceedings of theASP-DAC ’99

Asia and South Pacific Design Automation Conference1999

January 18-21, 1999Hong Kong Convention and Exhibition Centre

Wanchai, Hong Kong

Sponsors

IEEE Hong Kong SectionComputer Chapter andCAS/COM Chapter

Hong Kong Institute ofEngineers (ElectronicsDivision)

City University of Hong Kong

The Chinese University ofHong Kong

The Hong Kong University ofScience & Technology

The University of Hong Kong

In cooperation with

ACM SIGDA

Supporters

In Technical Cooperation withDesign Automation Conference

In Cooperation with

Chinese Institute of Electronics,

Hong Kong Computer Society,

Hong Kong Productivity Council,and

Institute of Electronics, Informationand Communication Engineers

Donors

K C Wong EducationFoundation (to providefinancial support to conferenceparticipants from the mainlandof China),

Cadence Design Systems AsiaLtd,

Hewlett Packard Hong KongLtd,

Sun Microsystems of CaliforniaLtd and Automated Systems(HK) Ltd

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Additional copies may be ordered from:

IEEE Order Dept.Hoes LaneP.O. Box 1331Piscataway, NJ 08854, U.S.A.

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permittedto photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume thatcarry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid throughCopyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint orrepublication permission, write to IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, P.O. Box1331, Piscataway, NJ 08855-1331. All rights reserved. Copyright1999 by the Institute of Electrical andElectronics Engineers, Inc.

IEEE Catalog Number 99EX198ISBN 0-7803-5012-X (Softbound Edition)ISBN 0-7803-5013-8 (Microfiche Edition)ISBN 0-7803-5014-6 (CD-ROM Edition)Library of Congress: 98-86104

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ASP-DAC’99 Organizing Committee

General Co-Chairs

Richard M. M. ChenCity University of Hong Kong

Secretary

Andrew M. LayfieldCity University of Hong Kong

Qian-Ling ZhangFudan University, Shanghai

Anthony S. S. FongCity University of Hong Kong

Vice General Chair

C. K. WongThe Chinese University of HongKong

Tutorial Co-Chairs

Philip H. W. LeongThe Chinese University of HongKong

Technical Programme Co-Chairs

Philip C. H. ChanThe Hong Kong University ofScience and Technology

Jack PoonMotorola Semicconductors HongKong Ltd.

Xian-Long HongTsinghua University, Beijing

Tony T.K. LeeThe Chinese University of HongKong

Masao YanagisawaWaseda University

Hiroaki KuniedaTokyo Institute of Technology

Finance Co-Chairs

Angus K. M. WuCity University of Hong Kong

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Finance Co-Chairs

Kevin J. ChenCity University of Hong Kong

Exhibition Chair

Wai-On LawMotorola Semiconductors HongKong Ltd.

Publication Chair

David Y. L. WuThe Chinese University of HongKong

Industrial Sponsorship Chair

Anthony S. S. FongCity University of Hong Kong

Publicity Chair

Howard C. LuongThe Hong Kong University ofScience and Technology

Design Contest Co-Chairs

Chi-Ying TsuiThe Hong Kong University ofScience and Technology

Registration Chair

Hei WongCity University of Hong Kong

Ryota KasaiNTT System Electronics Labs

Local Arrangement Chair

Oliver C. S. ChoyThe Chinese University of HongKong

Other O. C. Members

S. T. LaiHua Ko Electronic Co., Ltd., HongKong

International Liaison Chair

Paul Y. S. ChengThe University of Hong Kong

C. K. TangTelecom Technology Centre, HongKong

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P. F. TsuiVocational Training Council,Hong Kong

K. Y. TongThe Hong Kong PolytechnicUniversity

Mike W. T. WongThe Hong Kong PolytechnicUniversity

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International Advisory Committee ChairOmar Wing

The Chinese University of Hong Kong (retired)

International Advisory CommitteeMembers

Raul CamposanoSynopsys, USA

Francis Y. L. ChinThe University of Hong Kong

Tokinori KozawaSTARC, Tokyo

San-Li LiTsinghua University, Beijing

Steve Youn-Long LinTsing Hua University, Hsinchu

Isao ShirakawaEngineering Osaka University

Alexander L StempkovskyRussian Academy of Sciences

Regional Representatives

Zhenmin ChaiChinese Academy of Sciences, Beijing

Jacob KatzenelsonIsrael Institute of Technology, Haifa

Tohei KonoSinorex(Japan) Limited, Tokyo

Chong-Min KyungKorea Advanced Institute of Science & Tech.,Taejon

Hon-Wai LeongNational University of Singapore

Steve Youn-Long LinTsing Hua University, Hsinchu

Eric LindbergTechnical University of Denmark

Mahesh MehendaleTexas Instruments, Bangalore

Tsuneo NakataFujitsu Laboratories Ltd., Kawasaki

Anatoly I.PetrenkoUkrainian Academy of Engineering Sciences

Wolfgang RosenstielUniversitaet Tuebingen, Germany

David SkellernMacquarie University, Sydney

Ting-Ao TangFudan University, Shanghai

Xue-Ren ZhengSouth China University of Technology,Guangzhou

ASP-DAC’99 Secretariat

c/o Prof. Philip ChanDepartment of Electrical and Electronic Engineering

The Hong Kong University of Science and TechnologyClear Water Bay, Kowloon, Hong Kong

Fax: (852) 2358-1485Email: eepchan@ust.hkASP-DAC’99 Website

http://www.ee.ust.hk/ASPDAC99

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ASP-DAC Steering Committee

Chair

Tatsuo OhtsukiDepartment of Electronics, Information &Communication EngineeringWaseda University3-4-1 Okubo, Shinjuku Tokyo 169, JapanTel: +81-3-5286-3387Fax: +81-3-3203-9184E-mail:ohtsuki@ohtsuki.comm.waseda.ac.jp

Philip ChanThe Hong Kong University ofScience and Technology

Vice Chair

Fumiyasu HiroseCadence Design Systems, JapanE-mail: hirose@cadence.com

IEICE TGCAS Chair

Akinori NishiharaTokyoInstitute of Technology

Secretary

Tsuneo NakataFujitsu Laboratories Ltd.E-mail: nakata@flab.fujitsu.co.jp

IEICE TGVLD Chair

Hitoshi KitazawaNTT Corporation

ASP-DAC ’99 General Chair

Tokinori KozawaSemiconductor Technology AcademicResearch Center (STARC)

IEICE TGICD Chair

Gensuke GotoFujitsu Laboratories Ltd.

ASP-DAC ’99 Secretary

Toshihiro HattoriHitachi Ltd.

IPSJ SIGDA Chair

Kenji YoshidaToshiba Corporation

ASP-DAC ’99 Technical Program Co-Chairs

Shuji TsukiyamaChuo University

JIPC Representative

Kunihiro AsadaUniversity of Tokyo

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ACM SIGDA Representative

Nikil DuttUniversity of California at Irvine

Chong-Min KyungKorea Advanced Institute of Scienceand Technology

IEEE CAS Representative

Graham R. HellestrandUniversity of New South Wales

Hon-Wai LeongNational University of Singapore

DAC Representative

Basant R. ChawlaLucent Technologies

Youn-Long Steve LinTsing Hua University, Hsin-Chu

EDA Technofair Chair

Yoshitada FujinamiNEC Corporation

Sunil D. SherlekarSilicon Automation Systems (India)Pvt. Ltd.

EIAJ EDA TC Representative

Sagoro HazamaFujitsu Limited

David SkellernMacquarie University

International Members

Xian-Long HongTsinghua University, Beijing

Omar WingThe Chinese University of HongKong(retired)

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Ellen J. YoffaIBM Corporation Nobuaki Kawato

Fujitsu Laboratories of America

Qianling ZhangFudan University, Shanghai

Shigeo KuninobuMatsushita Electric Industrial Co.,Ltd.

Advisory Members (Industries)

Kazuyuki HirakawaOki Electric Industry Co., Ltd.

Masami MasuyamaSeiko Instruments Inc.

Eisaburo IwamotoSony Corporation

Shin’ichi MuraiMitsubishi Electric Corporation

Takashi KambeSharp Corporation

Fusao WadaZuken Inc.

Osamu KaratsuAdvanced TelecommunicationResearch Institute International

Kenji YoshidaToshiba Corporation

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Takeshi YoshimuraNEC Corporation

Yoshikazu MiyanagaHokkaido University

Advisory Members (Academia)

Toshiro AkinoKinki University

Yukihiro NakamuraKyoto University

Hideo FujiwaraNara Institute of Science andTechnology

Hidetoshi OnoderaKyoto University

Masaharu ImaiOsaka University

Tsutomu SasaoKyushu Institute of Technology

Michitaka KameyamaTohoku University Isao Shirakawa

Osaka University

Hiroaki KuniedaTokyo Institute of Technology Kazuhiro Ueda

Shibaura Institute of Technology

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Shin’ichi WakabayashiHiroshima University

Masao Yanagisawa (formerly Sato)Waseda University

Hiroto YasuuraKyushu University

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Welcome to ASP-DAC’99

The 1999 Asia South Pacific Design Automation Conference, or ASP-DAC’99, is the fourth in a series ofannual international conferences on Design Automation(DA) in this region. For the first time, it is held outsideof Japan, in Hong Kong.

Hong Kong is a Special Administrative Region of China. Under the policy of “one country two systems”,all of the circumstances which have contributed to Hong Kong’s success in the past such as low taxes, freetrade, and rule of law, have continued unaltered. What has changed is the new awareness of the importance ofadvanced technology in the economic development of Hong Kong. Indeed, the government has recently setaside HK$5 billion to support and to encourage new initiatives in technology research and development.

Asia is one of the hottest silicon areas in the world. It has become a significant center of VLSI productionand design. Thus it is most appropriate, and it is a privilege, to hold the ASP-DAC'99 in Hong Kong this year.It provides an opportunity for experts and practicing engineers to exchange ideas and to learn about the latestdevelopments in DA and in integrated circuits and systems design, which are the subjects of the conference.

Four internationally renowned experts in this field will present keynote speeches at this Conference. Theyare Professor Hitoshi Watanabe, Dean of Faculty of Engineering at Soka University; Dr Chi-Foon Chan,President and Chief Operating Officer of Synopsys; Dr Robert Yung, Director of Intel China Research Center;and Dr Dipender Saluja, Vice President of Engineering & Services of Cadence Design System. Their topicsinclude key areas of DA technology of general interest and the microprocessor technology for the 21st Century.

Our Technical Program Committee, led by Co-Chairs Professors Philip Chan, Xian-Long Hong andHiroaki Kunieda, has assembled an excellent technical program consisting of keynote addresses, oral andposter paper presentations, embedded tutorials, panel discussion and university design contest. A number ofinvited speakers will give presentations in their expert areas.

The Tutorial Program Co-Chairs have arranged three full-day tutorials on Monday, the first day of theConference. An Exhibition of EDA software and hardware platform is organized by the Hong KongProductivity Council in conjunction with the Organizing Committee. This exhibition will be held at conferencevenue during the conference period. Another EDA Techno Fair will be held in Japan by the end of January1999.

We would like to acknowledge financial sponsorship of IEEE, ACM, HKIE and the universities in HongKong, the support of the Steering Committee, the advice of the International Advisory Committee, and thededicated work of our Organizing Committee members. We also want to thank members of the RegionalRepresentatives for their assistance. We are greatly indebted to our Steering Committee Chair Professor TatsuoOhtsuki and International Advisory Committee Chair Professor Omar Wing for their valuable guidance, adviceand support during the past 22 months.

We welcome your participation at ASP-DAC’99 and sincerely hope that you will enjoy the Conference programand activities during your stay in Hong Kong.

Richard M. M. Chen and Qian-Ling ZhangGeneral Co-ChairsASP-DAC’99 OC

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Welcome to ASP-DAC’99 Exhibition

Date: January 18 (Monday) - 21 (Thursday), 1999Show hours: 10:00 AM – 5:00 PMVenue: Room 401, Hong Kong Convention and Exhibition Centre,

1 Harbour Road, Wanchai, Hong KongAdmission: Free of charge (registration is required at the exhibition

entrance)Managed by: Hong Kong Productivity Council

On behalf of the ASPDAC’99 Organizing Committee, I would like to invite you to attend theASPDAC’99 Exhibition, which will be held in conjunction with the ASPDAC’99Conference. Exhibitors will include companies involved in EDA tools, systems, related-products, and services, as well as local universities showing their EDA programs, systems andrelated achievements. The objectives are to promote the latest EDA technologies andproducts, to provide the latest information, and to provide an opportunity for the attendingelectronic design professionals and researchers to exchange ideas. Through the exhibitionand the conference, we hope to contribute to the development and the growth of the EDA andelectronic designs in Asia and South Pacific Region, which is the fastest growing region ofthe semiconductor industry.

Wai-On LawChair, ExhibitionASPDAC’99 Organizing Committee

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Invitation to ASP-DAC 2000

ASP-DAC 2000 is the fifth in a series of annual international conferences on DesignAutomation to be held in Asia and South Pacific region. It will be held in PacificoYokohama, Yokohama, Japan, during January 25 - 28, 2000.

Asia and the South Pacific Region is one of the hottest silicon areas in the world in thesense that the amount of VLSI production is rapidly growing. Thus the conference aims atproviding the Asian and South Pacific CAD/DA and Design community with opportunities ofestablishing leading edge research not only on specific design concepts but also on newaspects of approaches to integrated design concepts. Emphasized in the ASP-DAC 2000 will be more interaction between DA community anddesigners’ community, which is essential to overcome the so-called "Design Crisis". Wewould like to welcome submissions on the wider range of design issues, including designpractices/experiences themselves, as well as novel algorithms or tools, from system leveldown to physical and TCAD levels. Also, we continue the University LSI DesignContest to encourage academic education/research of LSI design implementations. EDA TechnoFair 2000, the premier Japanese EDA exhibition, will also be collocated withthe ASP-DAC 2000. Exhibitors included will be leading edge EDA vendors and ASICvendors, as well as universities who will demonstratetheir research/education results. On behalf of the ASP-DAC 2000 Organizing Committee, it is my pleasure to invite ASP-DAC 2000 participants and other researchers, designers and professionals in our technicalfields to submit papers and design to ASP-DAC 2000. For the conference, University LSIDesign Contest and paper submission details, please visit our web site athttp://www.jesa.or.jp/ASPDAC/ We look forward to having your participation.

Kenji YoshidaGeneral Chair, ASP-DAC 2000

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ASP-DAC’99 Technical Program Committee

Co-Chairs

Philip C. H. ChanThe Hong Kong University of Science andTechnology

Xian-Long HongTsinghua University, Beijing

Hiroaki KuniedaTokyo Institute of Technology

Members

Raul CamposanoSynopsys

Richard M. M. ChenCity University of Hong Kong

Oliver C. S. ChoyThe Chinese University of Hong Kong

Jason CongUCLA

Anthony S. S. FongCity University of Hong Kong

Jing-Yang JouChiao Tung University, Hsinchu

Andrew KahngUCLA

Ryota KasaiNTT System Electronics Labs

Chong-Min KyungKAIST

Wai On LawMotorola, HK

Mike LeeAvanti! Corporation

Philip H. W. LeongThe Chinese University of Hong Kong

Howard LuongThe Hong Kong University of Science andTechnology

Mahesh MehendaleTexas Instruments, Bangalore

Sudhakar MudduSilicon Graphics

Massoud PedramUniversity of Southern California

Wolfgang RosenstielUniversitaet Tuebingen

Pushan TangFudan University

C. Y. TsuiThe Hong Kong University of Science andTechnology

Omar WingThe Chinese University of Hong Kong (retired)

C. K. WongThe Chinese University of Hong Kong

Hei WongCity University of Hong Kong

Mike W. T. WongThe Hong Kong PolytechnicUniversity

Allen C. H. WuTsing Hua University, Hsinchu

Angus K. M. WuCity University of Hong Kong

David Y. L. WuThe Chinese University of Hong Kong

Hongxi XueTsinghua University, Beijing

Zhilian YangTsinghua University, Beijing

Kenneth YunUniversity of California, San Diego

Qian-Ling ZhangFudan University

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Best Paper Award Candidates

Asia and South Pacific Design Automation Conference 1999(ASP-DAC’99)

3A.1 Reduced-Order Modelling of Time-Varying SystemsJaijeet Roychowdhury

3A.2 Analysing Forced Oscillators with Multiple Time ScalesOnuttom Narayan, Jaijeet Roychowdhury

4A.2 Enhancing the Efficiency of Reduction of Large RC networks by PoleAnalysis via Congruence TransformationsHui Zheng, Wenjun Zhang, Lilin Tian, Zhilian Yang

6A.1 Design Method of MTCMOS Power Switch for Low-Voltage High-SpeedLSIsShin’ichiro Mutoh, Satosh Shigematsu, Yoshinori Gotoh, Shinsuke Konaka

7B.2 Optimal Wire Shape with Consideration of Coupling Capacitance underElmore Delay ModelYouxin Gao, D. F. Wong

7B.3 New Multilevel and Hierarchical Algorithms for Layout Density ControlAndrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky

7B.4 Function Smoothing with Applications to VLSI LayoutRoss Baldick, Andrew B. Kahng, Andrew Kennings, Igor L. Markov

11B.3 Combining GAs and Symbolic Methods for High Quality Tests of SequentialCircuitsMartin Keim, Nicole Drechsler, Bernd Becker

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ASP-DAC’99 University LSI Design ContestCommittee

Co-Chairs

Ryota KasaiNTT System Electronics Labs

Chi-ying TsuiThe Hong Kong University of Science and Technology

Members

Kwok-ying TongThe Hong Kong Polytechnic University

Akinori NishiharaTokyo Institute of Technology

Hidetoshi OnoderaKyoto University

Howard LuongThe Hong Kong University of Science and Technology

Hiroaki HirataKyoto Institute of Technology

Toshio KondoNTT System Electronics Labs.

Hideharu AmanoKeio University

Neil WesteMacquarie University

C.P. RavikumarIndia Institute of Technology, Delhi

Oliver Chiu-sing ChoyThe Chinese University ofHong Kong

Angus K. M. WuCity University, Hong Kong

Mike LeeAvanti! Corporation

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University LSI Design Contest SummaryEight designs were submitted from three countries, Japan, Korea and Indonesia. Statistics in terms ofthe application areas, and design methodologies are summarized as follows:

Application Area Design MethodologyCountry Number ofSubmission A D M C F/C G/A

Japan 2 0 1 1 0 2 0Korea 5 3 1 1 0 4 1

Indonesia 1 0 0 0 1 1 0

A: Analog or A/D Mixed Signal; D: DSP/Multimedia Application; M: Microprocessor;C: Custom Application; F/C: Full Custom or Cell-based; G/A: Gate Array

The submitted designs were reviewed by the members of the Design Contest Committee. After thereview, seven designs were selected and one design was rejected. From the selected designs, theDesign Contest Committee decided to confer an Outstanding Design Award and a Special FeatureAward to two specific designs, which are summarized as follows.

Outstanding Design Award

“A 16-bit DSP and System for Baseband/Voiceband Processing of IS-136 Cellular Telephony”

Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim,Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim,

Sang Jin Byun, Bae Sung Kwon, and Beomsup Kim

Department of Electrical Engineering,Korea Advanced Institute of Science and Technology, Taejon, Korea

(Digital Signal Processor, Full Custom Design)

Special Feature Award

“Motion Estimator LSI for MPEG2 High Level Standard”

Li, Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, and Hiroaki Kunieda

Department of Electrical and Electronics Engineering,Tokyo Institute of Technology, Tokyo, Japan

(Digital Signal Processor, Full Custom Design)

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Table of Contents

Organizing Committee...................................................................................................................iii

International Advisory Committee ................................................................................................. vi

Steering Committee ......................................................................................................................vii

Welcome to ASP-DAC'99.............................................................................................................xii

Welcome to ASP-DAC’99 Exhibition ..........................................................................................xiii

Invitation to ASP-DAC 2000 ....................................................................................................... xiv

Technical Program Committee...................................................................................................... xv

Best Paper Award Candidates ...................................................................................................... xvi

University LSI Design Contest Committee .................................................................................. xvii

University LSI Design Contest Summary ...................................................................................xviii

Session 1Keynote Speech 1

Chair: O. Wing

Session 2AAnalog CAD

Chair: O. WingCo-Chair: H. Yang

2A.1 Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits forHierarchical Symbolic AnalysisXiang-Dong Tan and C.-J. Richard Shi ........................................................................................... 1

2A.2 Symmetry Detection for Automatic Analog Layout RecyclingYoucef Bourai and C.-J. Richard Shi .............................................................................................. 5

2A.3 An SA-Based Nonlinear Function Synthesizer for Linear Analog IntegratedCircuitsHuazhong Yang, Rong Luo, Hui Wang and Runsheng Liu................................................................ 9

Session 2BPhysical Design 1 – Floorplanning

Chair: C. K. WongCo-Chair: X. Hong

2B.1 Relaxed Simulated Tempering for VLSI Floorplan DesignsJason Cong, Tianming Kong, Dongmin Xu, Faming Liang and Jun S. Liu..................................... 13

2B.2 Slicing Floorplans with Boundary ConstraintF. Y. Young and D. F. Wong ......................................................................................................... 17

2B.3 Design and Optimization of Power/Ground Network for Cell-Based VLSIs withMacro CellsXiaohai Wu, Changge Qiao and Xianlong Hong............................................................................ 21

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Session 2CDesign Contest

Chair: C. Y. TsuiCo-Chair: R. Kasai

2C. 1 An 8b 52 MHz Double-Channel CMOS A/D Converter for High-Speed DataCommunicationsJu-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee and Yong Jee............................................... 25

2C.2 A 10b 50 MHz CMOS A/D Converter for High-Speed Video ApplicationsByeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee and Sang-Won Yoon...................................... 29

2C.3 The Design of Delay Insensitive Asynchronous 16-bit MicroprocessorByung-Soo Choi, Dong-Wook Lee and Dong-Ik Lee ...................................................................... 33

2C.4 An LSI Implementation of an Adaptive Genetic Algorithm with On-the-FlyCrossover Operator SelectionShin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto,Yoshikatsu Nakayama and Koichi Hatta........................................................................................ 37

2C.5 Motion Estimator LSI for MPEG2 High Level StandardLi Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek and Hiroaki Kunieda............................ 41

2C.6 A Single-Chip CMOS CCD Camera Interface Circuit with Digitally ControlledAGCJin-Kug Lee, Dong-Young Chang, Geun-Soon Kang and Seung-Hoon Lee..................................... 45

2C.7 16-bit DSP and System for Baseband / Voiceband Processing of IS-136 CellularTelephonyTae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee,Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Jin Byun, Bae Sung Kwonand Beomsup Kim......................................................................................................................... 49

Session 3ACircuit Simulation 1

Chair: R. M. M. ChenCo-Chair: H. Yang

3A.1 Reduced-Order Modelling of Time-Varying SystemsJaijeet Roychowdhury ................................................................................................................... 53

3A.2 Analysing Forced Oscillators with Multiple Time ScalesOnuttom Narayan and Jaijeet Roychowdhury................................................................................ 57

3A.3 Waveform Relaxation of Linear Integral-Differential Equations for CircuitSimulationYao-Lin Jiang and Omar Wing...................................................................................................... 61

3A.4 A New Technique to Exploit Frequency Domain Latency in Harmonic BalanceSimulatorsM. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, K. K. Gullapalli and B.J. Mulvaney .................................................................................................................................. 65

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Session 3BPhysical Design 2 – Partitioning

Chair: A. B. KahngCo-Chair: C. K. Wong

3B.1 An Efficient Two-Level Partitioning Algorithm for VLSI CircuitsJong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai and Jan-Ming Ho .......................................... 69

3B.2 An Efficient Iterative Improvement Technique for VLSI Circuit PartitioningUsing Hybrid Bucket StructuresC. K. Eem and J. W. Chong........................................................................................................... 73

3B.3 A Clustering Based Linear Ordering Algorithm for K-Way SpectralPartitioningShiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin and Ting Ting Hwang ...................................... 77

3B.4 Faster and Better Spectral Algorithms for Multi-Way PartitioningJan-Yang Chang, Yu-Chen Liu and Ting-Chi Wang....................................................................... 81

Session 3CEDA Roadmap

Chair: Y. Furui

Session 4ACircuit Simulation 2

Chair: H. YangCo-Chair: R. M. M. Chen

4A.1 VCO Jitter Simulation and Its Comparison With MeasurementMasayuki Takahashi, Kimihiro Ogawa and Kenneth S. Kundert .................................................... 85

4A.2 Enhancing the Efficiency of Reduction of Large RC networks by Pole Analysisvia Congruence TransformationsHui Zheng, Wenjun Zhang, Lilin Tian and Zhilian Yang ................................................................ 89

4A.3 The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSIInterconnect CapacitanceJinsong Hou, Zeyi Wang and Xianlong Hong ................................................................................ 93

Session 4BPhysical Design 3 – Interconnection

Chair: J. CongCo-Chair: C. K. Wong

4B.1 Interconnect Delay Estimation Models for Synthesis and Design PlanningJason Cong and David Zhigang Pan ............................................................................................. 97

4B.2 An Analytical Delay Model for SRAM-Based FPGA InterconnectionsFeng Zhou, Zhijun Huang, Jiarong Tong and Pushan Tang ......................................................... 101

4B.3 Timing-Driven Bipartitioning with Replication Using Iterative QuadraticProgrammingShihliang Ou and Massoud Pedram ............................................................................................ 105

4C Embedded Tutorial:An Integrated Battery-Hardware Model for Portable ElectronicsMassoud Pedram, Chi-Ying Tsui and Qing Wu............................................................................ 109

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Session 5AKeynote Speech 2

Chair: P. Chan

Session 6ACircuit 1 - Low-power/High-speed

Chair: R. KasaiCo-Chair: P. Leong

6A.1 Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIsShin'ichiro Mutoh, Satosh Shigematsu, Yoshinori Gotoh and Shinsuke Konaka ............................ 113

6A.2 A New Single-Clock Flip-Flop for Half-Swing ClockingYoung-Su Kwon, Bong-il Park, In-Cheol Park and Chong-Min Kyung ......................................... 117

6A.3 Optimal Evaluation Clocking of Self-Resetting Domino PipelinesKenneth Y. Yun and Ayoob E. Dooply.......................................................................................... 121

6A.4 Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level DelayInsertionTomoyuki Yoda, Atsushi Takahashi and Yoji Kajitani .................................................................. 125

Session 6BPhysical Design 4 - Analog, Noise

Chair: X. HongCo-Chair: D. Y. L. Wu

6B.1 A Performance-Driven I/O Pin Routing AlgorithmDongsheng Wang, Ping Zhang, Chung-Kuan Cheng and Arunabha Sen ...................................... 129

6B.2 An Automatic Router for the Pin Grid Array PackageShuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen and Chia-Chun Tsai ....................................... 133

6B.3 Crosstalk Reduction by Transistor SizingTong Xiao and Malgorzata Marek-Sadowska .............................................................................. 137

6B.4 A Technology-Independent Methodology of Placement Generation for AnalogCircuitWai-chee Wong, Philip C. H. Chan and Wai-On Law .................................................................. 141

Session 6CDA for Electronic Packages

Chair: G. Choksi

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Session 6DPoster Session

6D.1 Technology Mapping for Low PowerChingwei Yeh, Chin-Chao Chang and Jinn-Shyan Wang ............................................................. 145

6D.2 An Efficient Approach to Constrained Via Minimization for Two-Layer VLSIRoutingMaolin Tan, Karmran Eshraghian and Hon Nin Cheung ............................................................. 149

6D.3 Automatic Constraint Transformation with Integrated Parameter SpaceExploration in Analog System SynthesisNagu R. Dhanwada, Adrian Nunez-Aldana and Ranga Vemuri .................................................... 153

6D.4 Node Sampling Technique to Speed Up Probability-Based Power EstimationMethodsHoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang and Chong-Min Kyung..................... 157

6D.5 Acceleration of Linear Block Code Evaluations Using New ReconfigurableComputing ApproachHidehisa Nagano, Takayuki Suyama and Akira Nagoya .............................................................. 161

6D.6 A New Numerical Method for Transient Noise Analysis of Nonlinear CircuitsM. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov and B. J. Mulvaney......................... 165

6D.7 Low Power CMOS Off-Chip Drivers with Slew-rate DifferenceRung-Bin Lin and Jinq-Chang Chen............................................................................................ 169

6D.8 Benchmark Circuits Improve the Quality of a Standard Cell LibraryRung-Bin Lin, Isaac Shuo-Hsiu Chou and Chi-Ming Tsai ............................................................ 173

6D.9 Formal Design Verification for Correctness of Pipelined Microprocessors withOut-of-order Instruction ExecutionTakashi Takenaka, Junji Kitamichi, Teruo Higashino and Kenichi Taniguchi .............................. 177

6D.10 Solving the Rectangular Packing Problem by an Adaptive GA Based onSequence-PairKoichi Hatta, Shin'ichi Wakabayashi and Tetsushi Koide ............................................................ 181

6D.11 Hazard-Free Synthesis and Decomposition of Asynchronous CircuitsRen-Der Chen, Jer Min Jou and Yeu-Horng Shiau ...................................................................... 185

6D.12 Hierarchical Floorplan Design on the InternetJiann-Horng Lin, Jing-Yang Jou and Hui-Ru Jiang ..................................................................... 189

6D.13 A Scheduling Method for Synchronous Communication in the Bach HardwareCompilerRyoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimotoand Takashi Kambe .................................................................................................................... 193

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Session 7ACircuit 2 - Multmedia chip designs

Chair: H. KuniedaCo-Chair: A. K. M. Wu

7A.1 Electronics Development of Silicon Mircodisplay for Virtual RealityApplicationsP. W. Cheng and H. C. Huang .................................................................................................... 197

7A.2 High-Speed and Low-Power Real-Time Programmable Video Multi-Processorfor MPEG-2 Multimedia Chip on 0.6 um TLM CMOS TechnologySeung-Min Lee, Jin-Hong Chung and M. M. –O. Lee................................................................... 201

7A.3 A Scalable Pipelined Architecture for Separable 2-D Discrete WaveletTransformJer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau and Ming-Shiang Liang......................................... 205

7A.4 A New Pipelined Architecture for Fuzzy Color CorrectionJer Min Jou, Shiann-Rong Kuang and Yeu-Horng Shiau.............................................................. 209

Session 7BPhysical Design 5 - Special Topics

Chair: D. Y. L. WuCo-Chair: X. Hong

7B.1 Watermarking Layout TopologiesEdoardo Charbon and Ilhami Torunoglu .................................................................................... 213

7B.2 Optimal Wire Space with Consideration of Coupling Capacitance under ElmoreDelay ModelYouxin Gao and D. F. Wong ....................................................................................................... 217

7B.3 New Multilevel and Hierarchical Algorithms for Layout Density ControlAndrew B. Kahng, Gabriel Robins, Anish Singh and Alexander Zelikovsky .................................. 221

7B.4 Function Smoothing with Applications to VLSI LayoutRoss Baldick, Andrew B. Kahng, Andrew Kennings and Igor L. Markov ...................................... 225

Session 7CPanel - System-on-a-chip

Chair: P. Ko

Session 8ATiming analysis

Chair: W. O. LawCo-Chair: C. Y. Tsui

8A.1 Layout-based Logic Decomposition for Timing OptimizationYun-Yin Lian and Youn-Long Lin ................................................................................................ 229

8A.2 Timing Optimization of Logic Network Using Gate DuplicationChun-hong Chen and Chi-ying Tsui ............................................................................................ 233

8A.3 Model Order Reduction of Large Circuits Using Balanced TruncationPayam Rabiei and Massoud Pedram ........................................................................................... 237

vii

Session 8BPhysical Design 6 - Placement & Route

Chair: D. F. WongCo-Chair: D. Y. L. Wu

8B.1 Optimization of Linear Placements for Wirelength Minimization with Free SitesAndrew B. Kahng, Paul Tucker and Alex Zelikovsky.................................................................... 241

8B.2 A New Global Routing Algorithm Independent of Net OrderingHaiyun Bao, Xianlong Hong and Yici Cai ................................................................................... 245

8B.3 A Timing-Driven Block Placer Based on Sequence Pair ModelGang Huang, Xianlong Hong, Changge Qiao and Yici Cai.......................................................... 249

8C Embedded Tutorial:Recent Advances in Asynchronous Design MethodologiesKenneth Y. Yun ........................................................................................................................... 253

Session 9Keynote Speech 3

Chair: R. M. M. Chen

Session 10ACircuit 3 - Analog & Mixed Circuit

Chair: H. LuongCo-Chair: P. Leong

10A.1 Universal Switched-Current Integrator Blocks for SI Filter DesignJack L. Chan and Steve S. Chung ................................................................................................ 261

10A.2 An On-Chip Automatic Tuning Circuit Using Integration Level ApproximationTechniqueSung-Dae Lee, Myung-Jun Jang and Won-Hyo Lee ..................................................................... 265

10A.3 A High-Speed and Low Power Phase-Frequency Detector and Charge PumpWon-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee ........................................................................ 269

10A.4 A Single-Chip CMOS CCD Camera Interface Circuit with Digitally ControlledAGCJin-Kug Lee, Dong-Young Chang, Geun-Soon Kang and Seung-Hoon Lee................................... 273

Session 10BTesting 1

Chair: P. CheungCo-Chair: A. K. M. Wu

10B.1 Data Path Synthesis for BIST with Low Area OverheadXiaowei Li and Paul Y. S. Cheung............................................................................................... 275

10B.2 Testing Interconnects of Dynamic Reconfigurable FPGAsChi-Feng Wu and Cheng-Wen Wu............................................................................................... 279

10B.3 Diagnosing Single Faults for Interconnects in SRAM Based FPGAsYinlei Yu, Jian Xu, Wei Kang Huang and Fabrizio Lombardi ...................................................... 283

10B.4 An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS CircuitsHafijur Rahaman, Debesh K. Das and Bhargab B. Bhattacharya................................................. 287

viii

Session 11APower Estimation/Low-power

Chair: M. PedramCo-Chair: C Y Tsui

11A.1 A Method for Evaluating Upper Bound of Simultaneous Switching Gates UsingCircuit PartitionKai Zhang, Tsuyoshi Shinogi, Haruhiko Takase and Terumine Hayashi....................................... 291

11A.2 Estimation of Peak Current through CMOS VLSI Circuit Supply LinesToshio Murayama, Kimihiro Ogawa and Haruhiko Yamaguchi ................................................... 295

11A.3 Power Consumption in XOR-Based CircuitsYibin Ye, Kaushik Roy and Rolf Drechsler................................................................................... 299

11A.4 Exploiting Don’t Cares During Data Sequencing using Genetic AlgorithmsNicole Drechsler and Rolf Drechsler........................................................................................... 303

Session 11BTesting 2 - Testing and formal Verification

Chair: M. WongCo-Chair: W. O. Law

11B.1 An Efficient Structural Approach to Board Interconnect DiagnosisChun-Keung Lo and Philip C. H. Chan ....................................................................................... 307

11B.2 On the Testing Quality of Random and Pseudo-random Sequences forPermanent and Intermittent FaultsJin Ding and Yu-Liang Wu.......................................................................................................... 311

11B.3 Combining GAs and Symbolic Methods for High Quality Tests of SequentialCircuitsMartin Keim, Nicole Drechsler and Bernd Becker ....................................................................... 315

11B.4 Formal Verification Method for Combinatorial Circuits at High Level DesignJunji Kitamichi, Hiroyuki Kageyama and Nobuo Funabiki .......................................................... 319

Session 11CPanel - VLSI Design Education

Chair: Prof. Asada

Session 12ABDD

Chair: R. DrechslerCo-Chair: A. Fong

12A.1 Minimization of Free BDDsWolfgang Günther and Rolf Drechsler ........................................................................................ 323

12A.2 Application Driven Variable Reordering and an Example Implementation inReachability AnalysisChristoph Meinel, Klaus Schwettmann and Anna Slobodova........................................................ 327

12A.3 Realization of Regular Ternary Logic Functions using Double-Rail LogicYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura and Atsumu Iseno ..................................... 331

ix

Session 12BSystems/HW SW co-design

Chair: T. OhtsukiCo-Chair: J. Poon

12B.1 A Hardware/Software Partitioning Algorithm for Processor Cores of DigitalSignal ProcessingNozomu Togawa, Takashi Sakurai, Masao Yanagisawa and Tatsuo Ohtsuki ................................ 335

12B.2 Generation of Interpretive and Compiled Instruction Set SimulatorsRainer Leupers, Johann Elste and Birger Landwehr .................................................................... 339

12B.3 Combining Speculative Execution and Conditional Resource Sharing toEfficiently Schedule Conditional BehaviorsApostolos A. Kountouris and Christophe Wolinski....................................................................... 343

12B.4 Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design EnvironmentMarcello Lajolo, Luciano lavagno and Alberto Sangiovanni-Vincentelli ...................................... 347

Session 12CBehavioral/FPGA

Chair: H. XueCo-Chair: P. Leong

12C.1 A Multi-Level FPGA Synthesis Method Supporting HDL Debugging forEmulation-Based DesignsWen-Jong Fang, Peng-Cheng Kao and Allen C.-H. Wu ............................................................... 351

12C.2 A Genetic Algorithm Based Approach for Multi-Objective Data-Flow GraphOptimizationBirger Landwehr ........................................................................................................................ 355

12C.3 Fast Boolean Matching under Permutation Using RepresentativeDebatosh Debnath and Tsutomu Sasao ....................................................................................... 359

12C.4 FSM Modeling of Synchronous VHDL Design for Symbolic Model CheckingJinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue and Xianlong Hong..................................... 363

Conference Author Index................................................................................................................... 367

x

Conference Author Index

B

Baldick, Ross 225 (7B.4)Bao, Haiyun 245 (8B.2)Becker, Bernd 315 (11B.3)Bei, Jinsong 363 (12C.4)Bhattacharya, Bhargab B. 287 (10B.4)Bian, Jinian 363 (12C.4)Bourai, Youcef 5 (2A.2)Byun, Sang Jin 49 (2C.7)

C

Cai, Yici 245 (8B.2)249 (8B.3)

Chan, Jack L. 261 (10A.1)Chan, Philip C. H. 141 (6B.4)

307 (11B.1)Chang, Chin-Chao 145 (6D.1)Chang, Dong-Young 45 (2C.6)

273 (10A.4)Chang, Jan-Yang 81 (3B.4)Charbon, Edoardo 213 (7B.1)Chen, Chun-hong 233 (8A.2)Chen, Jinq-Chang 169 (6D.7)Chen, Jong-Jang 133 (6B.2)Chen, Pei-Yin 205 (7A.3)Chen, Ren-Der 185 (6D.11)Chen, Sao-Jie 69 (3B.1)

133 (6B.2)Chen, Shuenn-Shi 133 (6B.2)Chen, Wen-Hsin 77 (3B.3)Cheng, Chung-Kuan 129 (6B.1)Cheng, P. W. 197 (7A.1)Cherng, Jong-Sheng 69 (3B.1)Cheung, Hon Nin 149 (6D.2)Cheung, Paul Y. S. 275 (10B.1)Cho, Jun-Dong 269 (10A.3)Choi, Byung-Soo 33 (2C.3)Choi, Hoon 157 (6D.4)Chong, J. W. 73 (3B.2)Chou, Isaac Shuo-Hsiu 173 (6D.8)Chung, Jin-Hong 201 (7A.2)Chung, Steve S. 261 (10A.1)Cong, Jason 13 (2B.1)

97 (4B.1)

D

Das, Debesh K. 287 (10B.4)Debnath, Debatosh 359 (12C.3)

Dhanwada, Nagu R. 153 (6D.3)Ding, Jin 311 (11B.2)Dooply, Ayoob E. 121 (6A.3)Drechsler, Nicole 303 (11A.4)

315 (11B.3)Drechsler, Rolf 299 (11A.3)

303 (11A.4)323 (12A.1)

E

Eem, C. K. 73 (3B.2)Elste, Johann 339 (12B.2)Eshraghian, Karmran 149 (6D.2)

F

Fang, Wen-Jong 351 (12C.1)Fujimoto, Tetsuya 193 (6D.13)Funabiki, Nobuo 319 (11B.4)

G

Gao, Youxin 217 (7B.2)Goto, Mutsuaki 37 (2C.4)Gotoh, Yoshinori 113 (6A.1)Gourary, M. M. 65 (3A.4)

165 (6D.6)Gullapalli, K. K. 65 (3A.4)Günther, Wolfgang 323 (12A.1)

H

Haba, Shintaro 41 (2C.5)Hatta, Koichi 37 (2C.4)

181 (6D.10)Hayashi, Terumine 291 (11A.1)Higashino, Teruo 177 (6D.9)Ho, Jan-Ming 69 (3B.1)Hong, Xianlong 21 (2B.3)

93 (4A.3)245 (8B.2)249 (8B.3)

363 (12C.4)Honsawek, Chawalit 41 (2C.5)Hou, Jinsong 93 (4A.3)Huang, Gang 249 (8B.3)Huang, H. C. 197 (7A.1)Huang, Wei Kang 283 (10B.3)Huang, Zhijun 101 (4B.2)Hwang, Seung Ho 157 (6D.4)

11

Hwang, Sung-Wook 25 (2C. 1)Hwang, Ting Ting 77 (3B.3)

I

Iguchi, Yukihiro 331 (12A.3)Iseno, Atsumu 331 (12A.3)

J

Jang, Myung-Jun 265 (10A.2)Jee, Yong 25 (2C. 1)Jeon, Byeong-Lyeol 29 (2C.2)Jiang, Hui-Ru 189 (6D.12)Jiang, Li 41 (2C.5)Jiang, Yao-Lin 61 (3A.3)Jou, Jer Min 185 (6D.11)

205 (7A.3)209 (7A.4)

Jou, Jing-Yang 189 (6D.12)

K

Kageyama, Hiroyuki 319 (11B.4)Kahng, Andrew B. 221 (7B.3)

225 (7B.4)241 (8B.1)

Kajitani, Yoji 125 (6A.4)Kambe, Takashi 193 (6D.13)Kang, Geun-Soon 45 (2C.6)

273 (10A.4)Kao, Peng-Cheng 351 (12C.1)Kay, Andrew 193 (6D.13)Keim, Martin 315 (11B.3)Kennings, Andrew 225 (7B.4)Kim, Beomsup 49 (2C.7)Kim, Hansoo 157 (6D.4)Kim, Jeong Pyo 49 (2C.7)Kim, Jin Wook 49 (2C.7)Kim, Ju-Hyung 25 (2C. 1)Kim, Tae Hun 49 (2C.7)Kim, Young Gon 49 (2C.7)Kitamichi, Junji 177 (6D.9)

319 (11B.4)Koide, Tetsushi 37 (2C.4)

181 (6D.10)Konaka, Shinsuke 113 (6A.1)Kong, Tianming 13 (2B.1)Kountouris, Apostolos A. 343 (12B.3)Kuang, Shiann-Rong 209 (7A.4)Kundert, Kenneth S. 85 (4A.1)Kunieda, Hiroaki 41 (2C.5)Kwon, Bae Sung 49 (2C.7)Kwon, Young-Su 117 (6A.2)

Kyung, Chong-Min 117 (6A.2)157 (6D.4)

L

Lajolo, Marcello 347 (12B.4)Landwehr, Birger 339 (12B.2)

355 (12C.2)lavagno, Luciano 347 (12B.4)Law, Wai-On 141 (6B.4)Lee, Dong-Ik 33 (2C.3)Lee, Dong-Wook 33 (2C.3)Lee, Jeong Eun 49 (2C.7)Lee, Jin-Kug 45 (2C.6)

273 (10A.4)Lee, Kang-Jin 29 (2C.2)Lee, M. M. –O. 201 (7A.2)Lee, Seung-Hoon 25 (2C. 1)

29 (2C.2)45 (2C.6)

273 (10A.4)Lee, Seung-Min 201 (7A.2)Lee, Sung-Dae 265 (10A.2)

269 (10A.3)Lee, Won-Hyo 265 (10A.2)

269 (10A.3)Leupers, Rainer 339 (12B.2)Li, Dongju 41 (2C.5)Li, Hongxing 363 (12C.4)Li, Xiaowei 275 (10B.1)Lian, Yun-Yin 229 (8A.1)Liang, Faming 13 (2B.1)Liang, Ming-Shiang 205 (7A.3)Lim, Kyoo Hyun 49 (2C.7)Lin, Jiann-Horng 189 (6D.12)Lin, Rung-Bin 169 (6D.7)

173 (6D.8)Lin, Shiuann-Shiuh 77 (3B.3)Lin, Wen-Wei 77 (3B.3)Lin, Youn-Long 229 (8A.1)Liu, Jun S. 13 (2B.1)Liu, Runsheng 9 (2A.3)Liu, Yu-Chen 81 (3B.4)Lo, Chun-Keung 307 (11B.1)Lombardi, Fabrizio 283 (10B.3)Luo, Rong 9 (2A.3)

M

Marek-Sadowska, Malgorzata 137 (6B.3)Markov, Igor L. 225 (7B.4)Matsuura, Munehiro 331 (12A.3)Meinel, Christoph 327 (12A.2)Mulvaney, B. J. 65 (3A.4)

165 (6D.6)Murayama, Toshio 295 (11A.2)

12

Mutoh, Shin'ichiro 113 (6A.1)

N

Nagano, Hidehisa 161 (6D.5)Nagoya, Akira 161 (6D.5)Nakayama, Yoshikatsu 37 (2C.4)Nam, Hyoung Sik 49 (2C.7)Narayan, Onuttom 57 (3A.2)Nunez-Aldana, Adrian 153 (6D.3)

O

Ogawa, Kimihiro 85 (4A.1)295 (11A.2)

Ohtsuki, Tatsuo 335 (12B.1)Ou, Shihliang 105 (4B.3)

P

Pan, David Zhigang 97 (4B.1)Park, Bong-il 117 (6A.2)Park, In-Cheol 117 (6A.2)

157 (6D.4)Pedram, Massoud 105 (4B.3)

109 (4C)237 (8A.3)

Q

Qiao, Changge 21 (2B.3)249 (8B.3)

R

Rabiei, Payam 237 (8A.3)Rahaman, Hafijur 287 (10B.4)Robins, Gabriel 221 (7B.3)Roy, Kaushik 299 (11A.3)Roychowdhury, Jaijeet 53 (3A.1)

57 (3A.2)Rusakov, S. G. 65 (3A.4)

165 (6D.6)

S

Sakurai, Ryoji 193 (6D.13)Sakurai, Takashi 335 (12B.1)Sangiovanni-Vincentelli, Alberto 347 (12B.4)Sasao, Tsutomu 331 (12A.3)

359 (12C.3)Schwettmann, Klaus 327 (12A.2)

Sen, Arunabha 129 (6B.1)Shi, C.-J. Richard 1 (2A.1)

5 (2A.2)Shiau, Yeu-Horng 185 (6D.11)

205 (7A.3)209 (7A.4)

Shigematsu, Satosh 113 (6A.1)Shinogi, Tsuyoshi 291 (11A.1)Singh, Anish 221 (7B.3)Slobodova, Anna 327 (12A.2)Suyama, Takayuki 161 (6D.5)

T

Takahashi, Atsushi 125 (6A.4)Takahashi, Masayuki 85 (4A.1)Takahashi, Mizuki 193 (6D.13)Takase, Haruhiko 291 (11A.1)Takenaka, Takashi 177 (6D.9)Tan, Maolin 149 (6D.2)Tan, Xiang-Dong 1 (2A.1)Tang, Pushan 101 (4B.2)Taniguchi, Kenichi 177 (6D.9)Tian, Lilin 89 (4A.2)Togawa, Nozomu 335 (12B.1)Tong, Jiarong 101 (4B.2)Torunoglu, Ilhami 213 (7B.1)Toshine, Naoyoshi 37 (2C.4)Tsai, Chia-Chun 69 (3B.1)

133 (6B.2)Tsai, Chi-Ming 173 (6D.8)Tsui, Chi-Ying 109 (4C)

233 (8A.2)Tucker, Paul 241 (8B.1)

U

Ulyanov, S. L. 65 (3A.4). 165 (6D.6)

V

Vemuri, Ranga 153 (6D.3)

W

Wakabayashi, Shin'ichi 37 (2C.4)181 (6D.10)

Wang, Dongsheng 129 (6B.1)Wang, Hui 9 (2A.3)Wang, Jinn-Shyan 145 (6D.1)Wang, Ting-Chi 81 (3B.4)Wang, Zeyi 93 (4A.3)

13

Wing, Omar 61 (3A.3)Wolinski, Christophe 343 (12B.3)Wong, D. F. 17 (2B.2)

217 (7B.2)Wong, Wai-chee 141 (6B.4)Wu, Allen C.-H. 351 (12C.1)Wu, Cheng-Wen 279 (10B.2)Wu, Chi-Feng 279 (10B.2)Wu, Qing 109 (4C)Wu, Xiaohai 21 (2B.3)Wu, Yu-Liang 311 (11B.2)

X

Xiao, Tong 137 (6B.3)Xu, Dongmin 13 (2B.1)Xu, Jian 283 (10B.3)Xue , Hongxi 363 (12C.4)

Y

Yamada, Akihisa 193 (6D.13)Yamaguchi, Haruhiko 295 (11A.2)Yanagisawa, Masao 335 (12B.1)Yang, Huazhong 9 (2A.3)Yang, Jeongsik 49 (2C.7)Yang, Zhilian 89 (4A.2)Ye, Yibin 299 (11A.3)Yeh, Chingwei 145 (6D.1)Yoda, Tomoyuki 125 (6A.4)Yoon, Sang-Won 29 (2C.2)Young, F. Y. 17 (2B.2)Yu, Yinlei 283 (10B.3)Yun, Kenneth Y. 121 (6A.3)

253 (8C)

Z

Zelikovsky, Alex 241 (8B.1)Zelikovsky, Alexander 221 (7B.3)Zhang, Kai 291 (11A.1)Zhang, Ping 129 (6B.1)Zhang, Wenjun 89 (4A.2)Zharov, M. M. 165 (6D.6)Zharov, M. M. 65 (3A.4)Zheng, Hui 89 (4A.2)Zhou, Feng 101 (4B.2)

Session Index

Session 1: Keynote Speech 1Session 2A: Analog CADSession 2B: Physical Design 1 – FloorplanningSession 2C: Design ContestSession 3A: Circuit Simulation 1Session 3B: Physical Design 2 – PartitioningSession 3C: EDA RoadmapSession 4A: Circuit Simulation 2Session 4B: Physical Design 3 – InterconnectionSession 5A: Keynote Speech 2Session 6A: Circuit 1 – Low-power/High-speedSession 6B: Physical Design 4 – Analog, NoiseSession 6C: DA for Electronic PackagesSession 6D: Poster SessionSession 7A: Circuit 2 – Multimedia chip designsSession 7B: Physical Design 5 – Special TopicsSession 7C: Panel – System-on-a-chipSession 8A: Timing analysisSession 8B: Physical Design 6 – Placement & RouteSession 9: Keynote Speech 3Session 10A: Circuit 3 – Analog & Mixed CircuitSession 10B: Testing 1Session 11A: Power Estimation/Low-powerSession 11B: Testing 2 – Testing and formal VerificationSession 11C: Panel - VLSI Design EducationSession 12A: BDDSession 12B: Systems/HW SW co-designSession 12C: Behavioral/FPGA