ASimpleProcessorArchitecture Register2 Register7

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Decoder

DestinationSelect

A Simple Processor Architecture

Register 1

Register 2

Register 7

B Select -*~ Multiplexer ,1

1 Multiplexer

[-*-A Select

B Bus --

4 A Bus

ALU

Shifter

Output

FunctionSelect

ShiftSelect

Martin B.H. WeissArithmetic-Logic Unit and Processor Design -1 University of' Pittsburgh

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ALU

Performs . Arithmentic FunctionsPerforms Logic FunctionsFunction is Selected by ControlStatus Bitso C - Carryo V - Overflowo Z = I If Resultant Contains All Zeroso S - Sign Bit of the Result

Decoder Selects Destination for the Resultant

Martin B.H. WeissArithmetic-Logic Unit and Processor Design - 2

University of Pittsburgh

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Inputso Operandso Input Carryo Operation Select

o Addo Subtracto ANDv ORo XOR

ALU

o Mode (Arithmetic or Logic) SelectOutputso Resultanto Output Carry

Martin B.H. WeissArithmetic-Logic Unit and Processor Design - 3 University of Pittsburgh

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Operation Select

ALU Function Table


1Iniversity of Pittsburgh

S2 S1 SO Cin Operation Function

0 0 0 0 F=A Transfer A0 0 0 1 F=A+1 Increment A0 0 1 0 F=A+B Add A and B0 0 1 1 F=A+B+1 Add A and B With Carry0 1 0 0 F=A+B' Add A and One's Compement of B0 1 0 1 F=A+B'+1 Subtract B From A0 1 1 0 F=A-1 Decrement A0 1 1 1 F=A Transfer A1 0 0 0 F=AB AND1 0 1 0 F=A+B OR1 1 0 0 F=A XOR B Exclusive OR1 1 1 0 F=A' Complement

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" Arithmetico Parallel Addo One Full Adder per Bito Selection Logic

" Logico Gateso Multiplexer

ALU Components

Martin B.H. Weiss

Arithmetic-Logic Unit and Processor Design - 5 University «f Pittsburgh

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Arithmetic-Logic Unit and Processor Design - 6


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Arithmetic-Logic Unit and Processor Design - 7 University of Pittsburgh

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Cn-1

SoS1S2

Internal Structure of ALU

0

Stage

Multiplexer


University o(' Pittsburgh

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Shifter

Generalo Extension of Shift Register Circuit is Possibleo This Requires Several Clock Pulseso This is Time Consuming

Alternate Approach (Figure 7-18, p. 246 of Mano)o Use Multiplexerso Wire to Cause Shift Effecto Control Determines Nature of Shifto Thus, a Single Clock Cycle is Used



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" MUXA Selector" MUX B Selector" ALU Operation Selector" Shift Selector" Destination Selector

Control Unit Requirements

Martin B.H. WeissArithmetic-Logic Unit and Processor Design -10 University Of Pittsburgh

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Control Word

" Number and Organization of Bits Required to Control ALU" Bit Requirements

o A : A Bus Select (Seven Registers Plus Input) : 3 bitso B : B Bus Select (Seven Registers Plus Input) : 3 bitso D : Destination Select (Seven Registers): 3 bitso F: ALU Control (Four bits)o H: Shift Control (Three bits)o TOTAL =16 bitso Thus, 16 Bits Can Be Used to Perform All Microoperations

Martin B.H. Weiss

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Arithmetic-Logic Unit and Processor Design -12

Control Word Encoding

Martin B.H. WeissUniversity of Pittsburgh

0Code

Operation (F)Cin = 0 Cin =1 A B D H

0 0 0 F=A F=A+1 Input Input None No Shift001 F=A+B F=A+B+1 R1 R1 R1 SHL010 F=A+B' F=A+B'+1 R2 R2 R2 SHR011 F=A-1 F=A R3 R3 R3 Bus=O100 F=AB R4 R4 R4101 F=A+B R5 R5 R5 ROL110 F=A XOR B R6 R6 R6 ROR111 F=A' R7 R7 R7

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Microoperations and Microprograms

Example Microoperationo RV- R2 - R3o Symbolically : R2,R3,R1,F=A-B,No Shifto Control Word = 010 0110010101000 = 4CA8 (H)

Clearly, Many Microoperations Are PossibleControl Memoryo Location of Available Microoperationso Width of Control Memory = Control Word

Microprograms Can be Written Using a Sequence ofMicrooperations

Martin B.H. Weiss

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Addressing Modes

Directo the address is contained in the address fieldo the size of the memory is limited by the size of the addressfield

Indirecto Content of the Memory Location Contained in the AddressField Points to The Actual Address

o Allows for a Larger Memory Because the Address Fields CanBe Larger

o Allows for Efficient Address ManipulationIndexedo Content of the Memory Field is Added to the Contents of theIndex Register

o Allows for Flexible Relative AddressingMartin B.H. Weiss

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Computer Organization - 10

Control System Design

" A Programmer Needs a Logical Structure and Instructions" A Hardware Designer has Microoperations" The Bridge Between These is a Microprogram


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Input

Structure of a Microprogrammed Control Unit

NextAddressGenerator

ControlAddressRegister

ControlMemory(ROM)

ControlData

Register

ControlWord10.

Martin B.H. Weiss

Computer Organization - 11 University of Pittsburgh

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Example

" Generalo 16 Bits for Processor Control (Bits 1-16; A,B,D,F,H AsBefore)

o One Bit for Address Source Selection (bit 17)o Three Bits For Status Bit Select (Bits 18-20)o Six Bits for the Next Address (Bits 21-26)

" 26=64 Microinstructions Are Possible" CAR Can be Loaded or Incremented, Depending on theCondition

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ExternalAddress

I I 1 1 21-26

Example

1-16

Control ,, Control 17Mux no Address

MemoryRegister 18-20

Incre-I Loadment

Input Control* Data

WordMultiplexer

01CC'ZZ'SVProcessorUnit

j' OutputData Martin B.H. Weiss


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Read/Write

A Simple Computer Design

Clock

CPU Memory

E:3~1iE3Interrupt

Martin B.H. WeissComputer Organization -14


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" I/O Interface" 16 Bit Data Bus" 16 Bit Address Bus

A Simple Computer Design

Martin B.11. WeissComputer Organization - 15 Universitv of 1'itttihnrgh

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Desti-nationDecoder

V S Z C

CPU Components

s_V Input

Fourteen Registers(16 Bits) sALSU(16 Bits)

OutputMartin B.H. Weiss

Computer Organization -16 University of Pittsburgh

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" ALSU" Registers" Internal Busses" Status Bits

CPU Components

Martin B.H. Weiss

Computer Organization -17 University of Pittsburgh

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Computer Organization -18

ALSU

" Two 16 Bit Input Busses" Four Units Multiplexed Together" Each Unit Always Operates on Both Operands" The Operation is Determined by the Selection Lines So and Sl" Operation is Selected by a 4:1 Multiplexer (S2 and S)" 16 Operations are Possible on the Output" Example 0110 => F=A B" Requires a Five Bit Control Word

Martin B.H. Weiss

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University of Pittshorgh

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Registers

Fourteen Total RegistersPCSix General Purpose RegistersSeven Special Purpose Registerso Index Registero Stack Pointero Source Registero Destination Registero Temporary Registero Two Constant Registers (Zero and N=16)

Martin B.H. WeissUniversity of Pittslwrph

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Three Internal Busses

" One for Each Operando Attached to One of the Registers via a Multiplexero One Mux for Each Operand Bus

" One For the Resulto Destination is One of the Registerso May Also Be External

Martin B.H. WeissUniversity of Pittslatiroh

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Control Word

" 17 Bits Long" Five Bits for ALSU (Four Control + Cin)

" Four Bits for Mux A" Four Bits for Mux B" Four Bits for Destination Decoder


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Computer Organization - 23 University of l'ittsliurgh

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Componentso Processor Unito Memoryo Control Unito Buffers/Registerso Busses

Busseso External to the Processoro Data Bus (16 bits)

CPU

u Direction Must be Mediatedo Read/Write Line (From/To Memory))

o Address Bus (16 bits)

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CPU Buffers and Registers

" Data Input Registero Input to IR or Processoro Data from Memory or From the Outside World

" Data Output Register - Output to Memory or Oustide World" Address Register - Current Memory Address" Instruction Register - OPcode of the Current Instruction


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SBR

IR (8-15)

ppcodeMap

Increment

Control Unit Organization

AddressMUX CAR Control

Memory

Martin B .H. WeissITniversity of Pittsburgh

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Componentso Subroutine Registero OPCode Mapo Incrementero Address Muxo Control Address Registero Control Memory

Subroutine Registero Used in Subroutine Callo Stores Return Address

Control Unit

Martin B.I-I. WeissUniversity or Pittsburgh

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Control Unit

Opcode Mapo Maps OPcode Into Control Memory Addresso May be a ROM

Incrementer - Increments AddressAddress Muxo Selects Source of Addresso Controlled by Control Memory (CS field)

Control Address Register - Holds the Memory AddressControl Memory - Contains the Microcode

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Type 0

Type 1

Type 2

Type 3

Instruction Types

Indirect BitsSI DI

10 1 o1

'oPCo4e

I

I SRI

I ~st I

11 1 11

,,O

ogle, -

0, 0, 0, 0, 0, 0, 001

Register to Register

Memory to Register

Branch

Implied

Martin B.II. WeissUniversity of Pittsburgh

~0 1 O

t~o4e

~S Dial): I I

I

e. .

A4em.r

.d

. .r o

.*or

. . .

1 0 O o e 0 0 0 0 0 0 0 0U,qm - r - d - r - o - Word

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Memory-RegisterTwo Word Instruction (Except for One Operand Instructionswith Operand in Register)Formato Bits 0-2 : Registero Bit 3: Indirect Bito Bits 4-5 : Addressing Mode

o Immediate : W is the Operando Directo Indirecto Index

Type 1

o Bit 6-7 : Source/Destination and Number of Operandso Memory or Registero One or Two Operands

Martin R.H. WeissUniversity of Pittsburgh

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Type 1

" Formato Bits 8-13 : OPCodeo Bits 14-15 : 01 (Indicates Memory-Register Operation)o Second Word for Memory Address or Intermediate Operand

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Type 2

" Branch" Two Word Instruction" Format

o Bits 0-7: 0o Bits 8-13 : OPCodeo Bits 14-15 : 10 (Indicates Branch Operation)

" Second Word Contains the Branch Address

Martin B .H. Weiss

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Type 3

Implied ModeOperand Either Does Not Exist or is Implicit in the InstructionExample: NOPOne WordFormato Bits 0-7 : 0o Bits 8-13 : OP codeo Bits 14-15 : 11

Martin B.H. Weiss



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An Assembly Language Instruction : ADD

Adds Two NumbersMay be Type 0 or Type 1o Type 0 if the Operands are in Registerso Type 1 if One of Them is in Memory

Example of Type 0: ADD R5,R2o Operation : R2<- R2+R5o Machine Code (0952H)

o Bits 0-2 : 010 (Register 2)o Bit 3 : Indirect Bit = 0 (Direct)o Bits 4-6 : 101 (Register 5)o Bit 7 : Indirect Bit = 0 (Direct)o Bits 8-13 : OPCode = 001001o Bits 14-15 : 00 (Indicates Register-Register Operation)

o Note That All Type 1 ADD Instructions Have 09H As FirstByte

Martin B.H . Weiss

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Alternate Form of ADD

" If We Used Indirect in R2 : ADD R5,(R2)o Operation : M[R2] M[R2]+R5o Machine Code:

o Bits 0-2 : 010 (Register 2)o Bit 3 : Indirect Bit =1 (Direct)o Bits 4-6 : 101 (Register 5)o Bit 7 : Indirect Bit = 0 (Direct)o Bits 8-13 : OPCode = 001001o Bits 14-15 : 00 (Indicates Register-Register Operation)

o Alternatively : 095AH

MartinB.11.'WeissUniversity of Pittsburgh

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Example of a Type 1 Addition : ADD TEMP,R2

" R2 I--R2+M[TEMP]" Machine Code

o Bits 0-2 : 010o Bit 3 : Indirect bit = 0o Bits 4-5 : Addressing Mode = 00o Bit 6-7 : Source/Destination and Number of Operandso Bits 8-13 : OPCode = 001001o Bits 14-15 : 01

" Machine Code : 4902H

00

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Notes

" Many Other Instructions Exist as Well" We Will Examine the Intel 8080 Later" The Software That Translates Assembly Code to Machine is anAssembler

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23 bits17 for ALSUo Operand A Select (4)o Operand B Select (4)o Destination Select (4)o ALSU Function Select (5)

Six for Other Functionso Two for Control Sequence

Microinstructions

o Distinguishes Microinstruction Formatso Controls the Address Mux in the Control Unit

o Four for Miscellaneous Microoperations

Martin B.H. WeissComputer Organization - 39 University of Pittsburgh

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Example : R2'--R2+R5

Refer to Mano, Figure 10-8(b) (p . 349)Control Sequence (CS) = 00Register Select "A" (AS) = 0010Register Select "B" (BS) = 0101Destination Select (DS) = 0010Function Control (FC) = 00010Miscellaneous (MS) = 0000Hex code: 04A620Microprograms Map OPcode Semantics into MicrooperationSequences

Martin B .H. Weiss

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Microprogram Flowchart for Type 0 ADD

Source

SourceIndirect A

Direct

ARE- R(S)

SRE- DIR

Destination

DestinationIndirect A

Direct

-- 4DOR<- SR + DIR

WRITE and Checkfor Interrupt

ADD (Type 0)

SRE- R(S)

R(D) E- SR + R(D)

FCheck for Interrupt

Martin 13 .H . WeissUniversity of Pittsburgh

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Generalo Contains Important CPU Status Indicationso Need Sufficient Information to Restore Processor Context(Status)

Typical Contentso Program Countero Stack Pointero Accumulator valueo Index Register(s)o Processor Status Registero Instruction Register

Program Status Word (PSW)

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Computer Organization - 43 University of Pitifimrgh

" Special Type of Memory" Operations

o PUSHo POP

Stack

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Input/Output for Communications

CPU

Memory

IsEEEceIMEE=11011011011Interface

Keyboard

Interface

Display

Interface

DiskStorage

Interface

Data Bus

Address Bus

Control

Martin B.li. WeissComputer Organization - 44 University of Pittsburgh

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Data Bus

Serial Communications Devices

Control

DayBuffer

Transmit Shift Register

Transmit Holding Regi

Receive Holding Register

ZZZZZZZIrm.kTM- ve ~nui negis~er

Control

Address Bus


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Computer Architecture - Intel 8080

Defines Only the CPUPhysical Featureso 40 Pin DIP Package (See Handout)o S Bit Data Buso 16 Bit Address Buso Control Pins


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"

8 Bit ALU" Registers

o ACCo PCo Stack Pointero IRo 6 Working Registers

o

Used in Pairso B-Co D-Eo H-L

0 2 Temporary RegistersOrganization (See Handout)

Logical Features

Alai-tin B.H. WeissComputer Organization - 47 University of Pittsburgh

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Instruction Format

"

8 Bit Opcode"

256 Instructions" 8080 Instructions (See Handout)" 8080 Microinstructions (See Handout)

Martin B.H. Weiss[University of Pittsburgh

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Summary of Digital and Computer Section

" Digital Computers Consist of Sequential and CombinationalCircuits

" General Purpose Devices That Can Be Programmed" Control is Often Implemented Via Microprograms

Martin B.fi . Weiss

High Level Assembly Machine Micro- ElectricalLanguage Code Code Program SignalsCode Code

Comb. &Seq. Circuits

IntendedResults

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ASimpleProcessorArchitecture Register2 Register7

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