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ASIC Back-End Design
By Bipeen Kiran Kulkarni
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Agenda
Introduction Design Flow
Overview Floorplan Timing Driven Placement
Clock Tree Synthesis Routing
Verification Design Example
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Introduction
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Introduction
Technological Advances 19 th Century - Steel 20 th Century Silicon
Growth in Microelectronic (Silicon) Technology Moores Law (# of transistors double/18 months)
One Transistor Small Scale Integration (SSI) Multiple Devices (Transistor / Resistor / Diodes) Possibility to create more than one logic gate (Inverter, etc)
Large Scale Integration (LSI) Systems with at least 1000 logic gates (Several thousand transistors)
Very Large Scale Integration Millions to hundreds of millions of transistors (Microprocessors)
Intel indicates that dual core processors will soon exist thatcontain 1 billion transistors
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Introduction
Manual (Human) design can occur with small number oftransistors
As number of transistors increase through SSI and VLSI,the amount of evaluation and decision making wouldbecome overwhelming (Trade-offs)
Maintaining performance requirements (Power / Speed / Area) Design and implementation times become impractical
How does one create a complex electronic design
consisting of millions of transistors?
Automate the Process using Computer-Aided Design (CAD) Tools
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Introduction
CAD tools provide several advantages Ability to evaluate complex conditions in which solving oneproblem creates other problems Use analytical methods to assess the cost of a decision Use synthesis methods to help provide a solution Allows the process of proposing and analyzing solutions to occur
at the same time
Electronic Design Automation Using CAD tools to create complex electronic designs (ECAD) Several companies who specialize in EDA
Cadence Design Systems
Magma Design Automation Inc. Synopsys
CAD Tools Allow Large Problems to be Solved
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Design Flow
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Design Flow - Overview
Generic VLSI Design Flow from SystemSpecification to Fabrication and Testing
Steps prior to Circuit/Physical design arepart of the FRONT-END flow
Physical Level Design is part of the BACK-END flow Physical Design is also known as Place and
Route
CAD tools are involved in all stages of VLSIdesign flow
Different tools can be used at differentstages due to EDA common data formats*
Synopsys CAD tool for Physical Design iscalled Astro
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What does Astro do?
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Where does the Gate Level Netlist come from?1 st Input to Astro
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Integrated circuits are built out of active and passive components, alsocalled devices :
Active devices Transistors Diodes
Passive devices
Resistors Capacitors
Devices are connected together with polysilicon or metal interconnect: Interconnect can add unwanted or parasitic capacitance, resistance
and inductance effects Device types and sizes are process or technology specific:
The focus here is on CMOS technology
Basic Devices and Interconnect
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Transistor or DeviceRepresentation
Gates are made up of active devices or transistors.
CMOS Inverter Example
OUT IN
Gate Schem atic
IN OUT
PMOS
NMOS
Transis to r o r Device View
VDD
GND
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What is Physical Layout?
Physical Layout Topography of devices and interconnects, made
up of polygons that represent different layers of material.
CMOS Inverter Example
NMOS
PMOS
OUT
VDD
GND Physical or Layout View
IN IN OUT
PMOS
NMOS
Transistor or Device View
VDD
GND
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Layout or Mask (aerial) view
Silicon Substrate
Process of Device Fabrication
Devices are fabricated vertically on a silicon substrate wafer by
layering different materials in specific locations and shapes on top ofeach other Each of many process masks defines the shapes and locations of a
specific layer of material (diffusion, polysilicon, metal, contact, etc) Mask shapes, derived from the layout view, are transformed to silicon
via photolithographic and chemical processes
Wafer (cross-sectional) view 40
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Wafer Representation of Layout Polygons
Example of complimentary devices in 0.25 um CMOS technology orprocess.
Input
VDD
GND
Output
PMOS
NMOS
0.25um
Aerial or Layout View Wafer Cross-sectional View
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Contacts: Connecting Metal 1 to Poly/Diffn
Diffusion, Poly and Metal layers are separated by insulatingoxide. Connecting from Poly or Diffusion to Metal 1 requiresa con tac t or cut .
Cut orContact
(a hole inthe oxide)
VDD
IN
GND
Diffusion DiffusionPoly
Oxide insulation Metal 1Metal 1
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What is meant by 0.xx um Technology?
- In CMOS Technology the um or n m dimension refers to thechannel length, a m i n i m u m dimension which is fixed for mostdevices in the same library.
- Current f low or drive s t rength of the device is proportional toW/L Device size or area is ro ortional to W x L.
Gate or Ch annel Dimensions (L and W)
Narrower
Width=
Lowercurrentthroug
hchanne
l
Length
Width
GATE
W
L
L
Width(W)
WiderWidth
=Highercurrentthroug
hchann
el
GATE
Length
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Comparing Technologies
The drive strength of both devices is the same: W/L = 6.The diffusion area (5xLxW) of A is 4x that of B.Which is preferred?
A: 0.5 um Technology
L = 0.5 um
2L 2L
W = 3 um
L = 0.25 um
W = 1.5 um
2L 2L
B: 0.25 um Technology Area Comparison
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Relative Device Drive Strengths
To double the drive strength of a device, double the channel width(W), or connect two 1X devices in parallel. The latter approachkeeps the height at a fixed or standard height.
1X NMOS (W/L = 6)
GND
OUT
L = 0.25 um
W = 1.5 um
IN
0.25 um
GND
3 um OUT
IN
2X NMOS (W/L = 12)
1.5 um
GND
0.25 um
OUT
IN
2X NMOS (W/L = 6 + 6)
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Input Output
Gate Drive Strength Example
PMOStransistor
1x
NMOS
transistor
Input Output
Parallel PMOS
transistors
2xinv1 inv2
Parallel NMOS
transistors
Each gate in the library is represented by multiple cells withdifferent drive strengths for effective speed vs. area optimization
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Drive/Buffering Rules: Max Transition/Cap
1x 2x 1x
1x
1x
Maximum TransitionRule Violation
Maximum Transition RuleMet
Upsized Driver or Added Buffers
A f t e r
O p
t i m i z a
t i o n
B e
f o r e
O p
t i m i z a
t i o n
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Timing Constraints3 rd Input to Astro
Derived from system specifications and implementation ofdesign
Identical to timing constraints used during logic synthesis
Common constraints in electronic designs Clock Speed/Frequency Input / Output Delays associated with I/O signals Multicycle Paths False Paths
Astro uses these constraints to consider timing duringeach stage of the place and route process
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Concept of Place and Route
Location of all standard cells is automatically chosen by thetool during placement (Based upon routing and timing)
Pins are physically connected during routing (Based upontiming)
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Concepts of Placement
Standard cells are placed in placement rows
Cells in a timing-critical path are placed close together to reduce routing relateddelays (Timing Driven)
Placement rows can be abutting or non-abutting
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Concepts of Routing
Connecting between metal layersrequires one or more vias
Metal Layers have preferred routingdirections Metal 1 (Blue) Horizontal Metal 2 (Yellow) Vertical Metal 3 (Red) Horizontal
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Floorplan
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Design Flow Floorplan
Layout design done at the chip level Defining layout hierarchy Estimation of required design area
A blueprint showing the placement of major components in thedesign (non-standard cell)
Inputs / Output (I/O) RAMs / ROMs/ Reusable Intellectual Property (IP) macros
Approaches to Floorplanning (Automatic or Manual) Constructive Iterative Knowledge-Based
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Design Must Be Floorplanned Before P&R
Floorplan of design: Core area defined with large macros placed Periphery area defined with I/O macros placed Power and Ground Grid (Rings and Straps) established
Utilization: The percentage of the core that is used by placed standard cells and
macros
Goal of 100%, typically 80-85%
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I/O Placement and Chip PackageRequirements
Some Bond Wirerequirements:
No Crossing
Minimum Spacing
Maximum Angle
Maximum Length
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Guidelines for a Good Floorplan
A few quick iterations of place and route with timing checksmay reveal the need for a different floorplan
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Defining the Power/Ground Grid andBlockages
Purpose of Grid is totake the VDD andVSS received fromthe I/O area anddistribute it over thecore area
Blockages can alsobe added in thefloorplan to prohibitstandards cells from
being placed in thoseareas
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Timing Driven Placement
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Design Flow Timing Driven Placement
Astro optimizes, places, androutes the logic gates to meetall timing constraints
Balancing design requirements Timing Area Power Signal Integrity
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Timing Constraints
Astro needs constraints tounderstand the timingintentions Arrival time of inputs Required arrival time at outputs Clock period
Constraints come from theLogic Synthesis tool SDC (Synopsys Design
Constraints) format
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Cell and Net Delays
Astro calculates delay for every cell and every net
To calculate delays, Astro needs to know theresistance and capacitance of each net Uses geometry of net and Look Up Tables to estimate the
resistances and capacitances
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Timing Driven Placement
Timing DrivenPlacement placescritical path cells closetogether to reduce netRC
Prior to routing, RCare based on VirtualRoutes
What if critical pathsdo not meet timingconstraints withplacement?
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Logic Optimizations
These optimizations can be done during pre-place, in-place,or post-place stages of placement
Each optimization can be done separately or all doneconcurrently during placement (none one all)
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Clock Tree Synthesis
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Design Flow Clock Tree Synthesis
All clock pins are driven by a single clock source
Large delay and transition time due to length of net
Clock signal reach some registers before others (Skew)
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Clock Tree Topologies
Clock source is connected to center of the network
Networks are distributed in a H or X shape until clockpin of register is driven by a local buffer
H-Tree and X-Tree Topologies Solve Single Clock Pin Problem
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After Clock Tree Synthesis
A clock (buffer) tree is built to balance the output loads andminimize the clock skew
A delay line can be added to the network to meet the minimuminsertion delay (clock balancing)
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Gated - CTS
Clocks may not be generated directly from I/O
Power saving techniques such as clock-gating are used toturn of the clock to sections of the design
Astro can interpret gated clocks and can build clock treesthrough the logic to the registers
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Effects of CTS
Several (Hundreds/Thousands)of clock buffers added to thedesign
Placement / Routing congestionmay increase
Non-clock cells may have beenmoved to less ideal locations
Timing violations can beintroduced
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Routing
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Process of Routing Can Be Timing Driven
Design Flow Routing
Routing is a fundamental step in the place and routeprocess
Create metal shapes that meet the requirements of afabrication process
The physical connection between cells in the design
Virtual routes used during placement and CTS need tobecome reality Timing of design needs to be preserved Timing data such as signal transitions and clock skew needs to
match the virtual route estimates
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Timing Driven Routing
Routing along the timing-critical path is given priority Creates shorter, faster connections
Non-critical paths are routed around critical areas Reduces routing congestion problems for critical paths Does not adversely impact timing of non-critical paths
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Concept of Routing Tracks
Metal routes must meet minimum width and spacingdesign rules to prevent open and short circuits duringfabrication
In grid based routing systems, these design rulesdetermine the minimum center-to-center distance for eachmetal layer (Track/Grid spacing)
Congestion occurs if there are more wires to be routedthan available tracks
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Grid-Based Routing System
Metal traces (routes) are builtalong and centered aroundrouting tracks
Each metal layer has its owntracks and preferred routingdirection Metal 1 Horizontal Metal 2 Vertical
Track and pitch information canbe located in the technology file Design Rules
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Verification
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What Happens After Place and Route?
Verification
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Formal Verification
New standard cells have been added to the designthrough timing optimizations and clock tree synthesis
The final netlist created by Astro needs to be comparedto the original gate-level netlist
Formal verification ensures the functional equivalency atthe logic level between the two implementations (originalvs. final) of the design The intended function was maintained throughout the physical
design process
Formality is the Sign-Off Tool for Formal Verification
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Timing Verification Star- RCXT performs the layout parasitic extraction of
the resistances and capacitances of all routes in thedesign
Results in a format such as SPEF (Standard ParasiticExtended Format) SPEF is an smaller, extended format of Standard Parasitic Format
(SPF), which enables the transfer of design specific resistancesand capacitances from physical design to timing analysis andsimulation tools
Primetime performs static timing analysis Detects timing violations by combining SPEF from Star- RCXT
and netlist from Astro and checks against the design timingconstraints (clock frequencies)
Star-RCXT and Primetimeare the Sign-Off Tools for Timing Verification
Physical Verification
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Physical Verification Checks the design for fabrication feasibility and physical
defects that could result in the design to not functionproperly 3 checks (DRC, ERC, and LVS)
Design Rule Checks (DRC) Verifies that design does not violate any fabrication rules
associated with the target process technology (metal width/space,antenna ratio, etc)
Electrical Rules Checks (ERC) Verifies that there are no short or open circuits with power and
ground as well as resistors/capacitors/transistors with floatingnodes (part of LVS)
Layout Versus Schematic (LVS) Final physical design matches the logical (schematic) version in
terms of correct connectivity and number of electrical devices
Hercules is the Sign -Off Tool for Physical Verification
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Fabrication
Physical Design process is completeupon successful completion of timing,functional, and physical verification
The design can be Taped -Out andGDSII created for the manufacturer GDSII (Graphic Design System II) is a
binary format containing the physicalgeometry information of the design.
The shapes are assigned numericattributes in the form of Layer Numberand Data Type (Metal 1 => 100:0)
Fabrication and Test determine whichchips can be implemented into thesystem (yield)
M k G ti GDSII /
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Physicaldesign
DataGDSII (Stream)
Masks
Wafer
Mask Generation GDSII /Stream
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Example Design Cory Ellinger Independent Study
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Example Design Cory Ellinger Independent Study
64x8 FIFO Block.
Inputs: Direct input Input through 64-bit addition Read, Write, Enable, and Sum Control
Able to be read and written simultaneously
Outputs: 64-bit FIFO out
Overflow flag Full, Empty flags
Block Diagram
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Block Diagram
register register
unsignedAdder
register bank
clkrst
add_fifo
sum_cnt
64 x 8FIFO
rdwren
fullempty
overfl
6464
64
64
data_in_x data_in_y_fifo_in
data_out
Block Diagram Critical Path
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Block Diagram Critical Path
register register
unsignedAdder
register bank
clkrst
add_fifo
sum_cnt
64 x 8FIFO
rdwren
fullempty
overfl
6464
64
64
data_in_x data_in_y_fifo_in
data_out
Critical Path
Major Physical Design Steps
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Major Physical Design Steps
Floorplan Placement
Clock Tree Synthesis Routing
Floorplanning
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Floorplanning
Aspect Ratio Power Planning Utilization
Pin Placement Macro Placement Define Core Rows and Routing Tracks
Read in Netlist, Libraries, and SDC. Groups and Regions
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Floorplan (Theoretical)
Aspect Ratio (2:1) W:H
FIFO
InputRegister
Data Flow
6 4
d a t a
_ i n
dataout
output
flags
6 4
d a
t a_
i n
sum_cnt clk reset
Floorplan
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Floorplan
Floorplan Showing Logic Modules
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Floorplan Showing Logic Modules
Placement
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Placement
Timing Driven Standard Cell Placement Ignore Scan Chains ( if any )
Timing First look at non-wire load model timing. Concentrate on any large setup violations. Ignore violations caused by design rule
failures.
AutoPlace of Logic Modules
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AutoPlace of Logic Modules
Design Placement
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Design Placement
Reset Net
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Reset Net
Pre-Clock Tree Synthesis
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e C oc ee Sy t es s
Clock Tree Synthesis
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y
Goals: Low Clock Skew Low Clock Insertion Delay Sharp Transitions
Timing Setup violations clean Design Rules fixed Initial evaluation of real hold violations
Post Clock Tree Synthesis
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y
Routed Design
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g
Route (zoom)
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( )
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QUESTIONS ?