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    Asic Verification

    -"Anything that can go wrong - Will"-Murphy

    What is my next step to be performed?

    Now Lets start with an assumption that anything may go wrong

    What are the various areas can things go wrong?

    - List down the areas in the flow that things can go wrong and derive a methodology to

    verify at each and every stage.

    - List down all your uncertainities that could potentially happen and how to model it and how

    to constrain and verify up-front.

    Lets Explore and re-visit each and every area in the Design flow to cover potential risk

    - Functional Verification (RTL level , Gate level)

    - Formal Verification

    - Static Timing Analysis

    - Physical Verification

    - Power Simulation

    - Thermal Simulation

    - Noise Simulation- Test Simulation

    - Emulation

    - Hardware proto-type

    - Hardware Software co-simulation

    - Transistor level Simulation

    Now lets Venture in to each area and insure it

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    Asic Verification

    Functional Verification:

    - TLM(Transaction Level Modelling)

    - Linting- RTL Simulation ( Enivronment involving : stimulus generators, monitors, response

    checkers, transactors)

    - Gate level Simulation

    - Mixed-signal simulations

    - Regression

    How Much Did I cover in the functional part - What is my Coverage Metric? and what are

    the methodologies used?

    - Is the verification tests covered pin-pointed tests or tests with random seeds to cover all

    the corner-cases.

    - Code-coverage

    - Line coverage

    - Functional coverage

    Formal Verification:

    - Equivalence checkers

    - RTL versus Gate

    - Pre-layout versus post-layout Netlist

    - Assertion based property checkers(Mathematical techniques to allow larger state space coverage)

    Timing Verification:

    - With whom the Chip is talking to (To know the Interface Timing's)

    - What is the Timing-budgets with in the chip, and how to constrain it within each I.P. and finally ana

    - How to address the timing targets with varying process parameters(on-chip variation) what is the o

    - Steps to minimize the clock -jitter.

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    Asic Verification

    Physical Verification:

    Is my design process friendly ?

    - DRC (Design Rule Check)

    - LVS

    - Antenna Checks

    - ERC

    - ESD checks

    - Speed monitor's

    Noise Simulation:

    How Noisy is my design so need to perform noise simulations addressing these areas

    - Simultaneous Switching Noise (SSN)

    - Package Noise- EMI Noise

    - Power-ground noise

    - Cross-talk noise

    - Analog Noise

    - Substrate noise

    Power Simulations:

    Is my design meeting power-targets

    - IR drop analysis

    - Dynamic power simulations

    Power related methodologies

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    Asic Verification

    - Optimum location for De-caps

    - Multiple Voltage domains

    - Multi Vt design

    - DVFS ( Dynamic Voltage and Frequency scaling)

    - Clock-gating Techniques- Power Management Unit (to shut-off when not required)

    - Level-Shifters across cross-voltage domains

    Thermal Simulations

    Study the thermal targets and mechanism to reduce

    Test Simulations

    Is my design testable once chip comes out, methodologies to identify the problematic areas

    - Boundary Scan

    - Memory BIST simulations- Tester specific vector generation and simulations

    - Tester vector compression techniques to reduce tester time

    - At-speed testing mechanism's

    - Scan-shift and scan-capture methodologies

    - IDDQ testing

    - Wafer Level Burn-in Tests to know Known Good Dies(KGD)

    - Wire pull tests

    - DC parameter tests

    - AC parameter tests

    - Path-delay tests- Delay tests

    - Transition fault testing

    Addressing DSM and Yield Issues

    - Redundant via's

    - Spacing non critical areas to be lithography friendly- Wire widening

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    Asic Verification

    - Metal Filling

    - Metal Slotting

    Emulation:

    Emulates the functional behaviour of the design. Synthesizable assertions are mapped to emulators to

    Hardware prototype:

    Proto-typing the system requirements in a programmble FPGA's

    Inspite of all the Verification Methodologies and Strategies if things goes wrong, how to addressin the design - Methodologies to reduce cost & time

    - Spare-gates- Redundant rows/columns in the memories

    - Redundant vias

    - Built-in self repair memories

    - Focussed Ion Beam Methodologies

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    Note: In case if you wish to add more to this topic, please do send me mail to :[email protected]

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Chip-Level Verification of an RF ASIC with CustomSim/VCStumbush.com/published_papers/Chip_Level_Verification_of...SNUG 2019 Page 5 Chip-Level verification of an RF ASIC with CustomSim/VCS

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Published by ASIC ASIC Gazette - ASIC Home | ASICdownload.asic.gov.au/media/1315003/ASIC46_08.pdf · ASIC GAZETTE Commonwealth of Australia Gazette ASIC 46/08, Tuesday, 10 June 2008

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Using Formal Verification to Exhaustively Verify SoC Assemblies by Mark Handover Kenny Ranerup Applications Engineer ASIC Consultant Mentor Graphics Corp.

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Design and Verification of FPGA and ASIC · PDF fileDesign and Verification of FPGA and ASIC Applications ... Model-Based Design for FPGA and ASIC ... Removes risk of manual error

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Formal Verification for ASIC & System-On-Chip Designs

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The Fujitsu ASIC · PDF fileClock Tree Synthesis RTL DesignRTL Design Physical Synthesis Logical Synthesis DFT Insertion Formal Verification Floorplanning ... The Fujitsu ASIC Platform

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Aviation Security Identification Card ASIC · ASIC Information for cardholders and applicants New identity verification requirements commence 1 August 2017 AUS AUG 19 John CITIZEN

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ASIC Design Services - nevatron.comnevatron.com › Nevatron.pdf2 Services ASIC design (Front-end & Back-end) ASIC verification (functional/formal) FPGA design/prototyping & FPGA to

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Published by ASIC ASIC Gazette - ASIC Home | ASIC · ASIC GAZETTE Commonwealth of Australia Gazette ASIC 38B/09, Tuesday, 12 May 2009 Banking Act Unclaimed Money Page 9 of 474 AMP

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