ASIC-System on Chip-VLSI Design_ Power Planning

7/25/2019 ASIC-System on Chip-VLSI Design_ Power Planning

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6/25/2016 ASIC-System on Chip-VLSI Design: Power Planning

http://asic-soc.blogspot.in/2007/10/power-planning.html

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ASIC-System on Chip-VLSI Design

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Power Planning

There are two types of power planning and management. They are core cell power

managementand I/O cellpower management. In former one VDD and VSS power rings

are formed around the core and macro. In addition to this straps and trunks are created

for macros as per the power requirement. In the later one, power rings are formed for I/O

cells and trunks are constructed between core power ring and power pads. Top to bottom

approach is used for the power analysis of flatten design while bottom up approach is

suitable for macros.

The power information can be obtained from the front end design. The synthesis tool

reports static power information. Dynamic power can be calculated using Value Change

Dump (VCD)or Switching Activity Interchange Format (SAIF)file in conjunction with

RTL description and test bench. Exhaustive test coverage is required for efficientcalculation of peak power. This methodology is depicted in Figure (1).

For the hierarchical design budgeting has to be carried out in front end. Power is

calculated from each block of the design. Astro works on flattened netlist. Hence here top

to bottom approach can be used. JupiterXT can work on hierarchical designs. Hence

bottom up approach for power analysis can be used with JupiterXT. IR drops are not

found in floor planning stage. In placement stage rails are get connected with power

rings, straps, trunks. Now IR drops comes into picture and improper design of power can

lead to large IR drops and core may not get sufficient power.

Figure (1) Power Planning methodology

Below are the calculations for flattened design of the SAMM. Only static power reported

by the Synthesis tool (Design Compiler) is used instead of dynamic power.

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2/5
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3/5
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4/5



Replies

Reply

Anonymous March 26, 2008 at 1:38 AM

I think that formulas for Current supply from each side of the block: should be

Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2

Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2

Could you please recheck?

Reply

Anonymous March 26, 2008 at 1:41 AMI think that formulas for Current supply from each side of the block: should be

Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2

Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2

Could you please recheck?

Reply

Anonymous December 24, 2008 at 10:02 PM

what is Roe here

Reply

AnonymousApril 11, 2009 at 3:54 PM

What is Roe & routing pitch and from where we get these values???

Reply

Anonymous October 30, 2012 at 8:51 PM

Hi, Roe is the sheet resistance of the metal layer used for the routing, that is,the

resistivity rho divided by the thickness of the routing layer

AnonymousJune 24, 2009 at 3:04 PM

how to draw PG mesh accurately?

Reply

ravikumarJuly 22, 2010 at 11:45 AM

where we get core voltage? its get from .lib library or not

Reply

Anonymous October 9, 2010 at 11:18 AM

Can any one tell.,

steps to calculate powerplanning with formulaes in Vlsi chip design.

Reply

pruthvi February 11, 2014 at 2:56 PM

fro where we get maximum current density of metal value?

Reply

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5/5



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Murali

M.Sc in ElectronicsM.S in VLSI System Designworked 3 years as

design engineer in embedded system domain experience of PICand 8051 based microcontroller applicationsworking as VLSI

physical design engineer photography,travel and literature are my

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ASIC-System on Chip-VLSI Design_ Power Planning

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