ASIC Development for the GLAST Trackerscipp.ucsc.edu/groups/fermi/publications/GTFE64_review.pdf ·...

November 24, 1997 Robert P. Johnson 1

ASIC Development for the GLAST TrackerRobert P. Johnson

Santa Cruz Institute for Particle Physics

University of California at Santa Cruz

• GLAST Instrument Concept• GLAST Tracker Electronics

Requirements• Analog Channel

• Preamplifier• Shaper• Comparator• Performance

• Readout Architecture

• Front-End Readout Chip• Architecture• Resistors• DACs• Command Decoder• Drivers and Receivers• Simulations• Layout and Verification

• Readout Controller Chip• Hybrids• Kapton Detector Interconnect• Flex Cables and Connectors


Santa CruzInstitute forParticle Physics

ASIC Development for the GLAST Tracker

The GLAST Instrument Concept

175

cm

24 cm

24 cm

6 cm

6 cm

Preamps

236

um p

itch

Scintillator Veto

Con

vert

er (

.5 r

l)

Si Strip Detector

Conceptual Design of GLASTGamma Large Area Space Telescope

Cal

orim

eter

(

10 r

l)

8 x 8 ArrayCsI(Tl) XtalsDiode Readout

Com

plet

e G

LA

ST

One

Tow

er M

odul

e of

GL

AS

T

60 c

m

60 cm

7 x 7 Array of Towers

10 Layers of .05 rad length convertereach with xy silicon strips

2 Layers of XY silicon strips only

Gamma Ray

Electron Positron

Trigger and Computer Tray

GLAST conceptual design. (The currentbaseline design is for a 5×5 array of 32-cm square towers, each with 16 x,ylayers.)

An assembly ofidentical modules,each with a vetoshield, a silicon-striptracker, and acalorimeter.

The current trackerbaseline design callsfor 32 cm squaredetector planes, eachwith a 5×5 array of6.4-cm detectors.




Electronics Requirements

• Power less than ≈250 µW/channel, including amplifiers and digital readout.

• Low noise occupancy (<0.05%) and good threshold uniformity.– Expected detector loading is about 1.2 pF/cm × 32 cm = 38 pF.

– Detector thickness is 400 µm, for about 5.3 fC/MIP.

– AC coupled detectors, with 194 µm pitch.

• Microsecond peaking time for the amplifiers.

• Sufficient redundancy to be immune to single-point failures.

• Self triggering.

• Radiation hard to 10 kRad with latch-up immunity.

• <1% dead-time at a 10 kHz trigger rate.

• Sparse readout and data formatting close to the front end.

Challenge: 1.3 million readout channels operating with high reliability ina space environment.




Analog Channel

• A first 16-channel prototype was fabricated and tested one year ago.• Later, a 32-channel version was produced for the recent beam test at SLAC.

– Slightly reduced peaking time (1.3 µs, down from 1.6 µs).– Slightly reduced gain (125 mV/fC, down from 150 mV/fC).– OR gates for trigger output, rather than open drains.

• Extensive bench-top noise measurements have been done on several 16-channel chips.

• 71 32-channel chipswere runsuccessfully in thebeam, but the dataanalysis has onlybegun.

HP CMOS26G process(0.8 µm, 3-metal, N-well)

One beam test module.




Preamplifier Design

• Standard folded cascodeamplifier with 2V bias for thefront end, to save power.

• ≈25 µA bias current set by anexternal resistor.

• Slow differential amplifierstabilizes the bias point andprovides a continuous reset.

• Input impedance ≈5 kΩ gives≈200 ns time constant withGLAST 38 pF detector load.

• Open loop gain: 64 dB at 0 Hz

• Power: ≈90 µW

Preamplifier schematic.




Shaping Amplifier Design

• AC coupling from the preamplifier.

• Conventional cascode amplifierwith capacitive feedback.

• Slow differential amplifier in thefeedback provides the“differentiation” function andstabilizes the output bias point.(Ref.: I. Kipnis, LBNL)

• Open loop gain: 62 dB at 0 Hz

• Voltage gain: ≈26

• Peaking time: ≈1.3 µs

• Pulse shape: reset current sourcemakes a tail that is more linear thanexponential, except at the lowestpulse heights.

• Power: ≈35 µW

Shaping Amplifier Schematic




Comparator Design

• 16-channel & 32-channelprototypes actually had NFETinputs. We need to go to PFETinputs (as shown here) toaccommodate better the biaslevel at the shaper output.

• Conventional two-stagecomparator, with DC couplingfrom the shaper output.

• No current in the second stagein the quiescent state (with noinput signals).

• Only 17µW of quiescent power.

“Old” Comparator Schematic

Old Design




Comparator Design

New Design• Pavel preferred the symmetric design

shown here, and this is what is in thelayout at this time.

• Advantage: no coupling of the largeoutput swing into the common biasnetwork.

• Disadvantage: turn-on transition is notas abrupt as in the old design:

• Old: ∆Q<0.04 fC at preamp inputproduces a change at the comparatoroutput from 0 to 5V.

• New: ∆Q≈0.28 fC is needed to swingthe output from 0 to 5V.

• I would like to change the comparatorsin at least 1/2 of the channels back tothe old, proven design.




Analog Channel Signal Shapes

• Top: preamp, shaper,and comparator outputsfor a 4 fC input charge.

• Bottom: 1 fC inputcharge.

• In both cases, the shaperbaseline and thethreshold (90 mV) areshown by solid blackhorizontal lines.

Spice Simulations




Analog Channel Performance

• Gain (shaper output): ≈150 mV/fC in 16-ch chip, ≈125 mV/fC in 32-ch chip.

• Peaking time:≈1.6 µs in 16-ch chip,≈1.3-µs in 32-ch chip.

• Power consumption, including biascircuitry: 150 µW/channel

• Noise: ENC=174 + 32×C electrons, withC in pF, measured by several methods, asshown here, for the 16-ch chip.

ENC=204 + 30.3 C

0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0

C (pF)

Channel 14 Noise

0

200

400

600

800

1000

1200

1400

EN

C (

elec

tron

s)

Noise measured fromthreshold curves on 10channels.

Noisemeasured byprobe andspectrumanalyzer.

Noise measured from threshold curveson 16 channels connected to detectorstrips with 7 pF capacitance.

External Capacitors

External Capacitors

With Si Strip Detector Attached

0 2 4 6 8 10 12 14 160

100

200

300

400

500

RM

S N

oise

(el

ectr

ons)

Channel Number

Average ENC=407 electrons

0 10 20 30 40

External Capacitance (pF)

100

300

500

700

900

1100

1300

1500

RM

S N

oise

(el

ectr

ons)

ENC=174 + 32 C




Threshold Matching

• Threshold matching from channelto channel across a given chipdepends primarily on the transistorpairs in the shaper feedback.

• Most chips meet the desired upperlimit of about 15 mV rmsthreshold variation (comparedwith the ≈32 mV rms noise level).

• Work is in progress to try toimprove this figure further in thenext prototypes.

• We plan always to have thecapability to set the thresholdindependently for each readoutchip, so chip-to-chip variationswon’t matter.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

RMS Offset (mV)

0

1

2

3

4

5

6

7

8

9

10

11

12

Num

ber

of C

hips

0 2 4 6 8 10 12 14 160

2000

4000

6000

8000

10000

12000

14000

Thr

esho

ld (

elec

tron

s)

Channel Number

RMS variation=325 electrons=6.5 mV

Results from threshold scans on asingle 16-channel prototypeconnected to a single detector.

Results fromthreshold scans on 5932-channel chips,with no detectorsattached.




Readout Architecture

• 25 64-channel readout chips handle asingle detector layer.

• Data can shift out left or right, or in bothdirections, with a readout-controller chipat each end of the chain. (20 MHz clockfrequency.)

• Trigger-output (Fast-OR) signals alsomove left or right, or in both directions.

• Either readout controller chip canreprogram the readout direction of anyof the front-end readout chips, so asingle dead chip can be bypassedwithout losing data from any other chips.

• The readout controller chips pass datadown the tower in a token-controlledprotocol.

data

trigger

trigger

data

data

trigger

trigger

data

data

trigger

trigger

data

cmd

cloc

k

trg

ack

cmd clk

trg

ack

toke

n

data

data

data

cmd

clk

trg

ack

trg

ack

cloc

k

cmd

Controller

Controller

FE FE FE

data

trigger

trigger

data

data

trigger

trigger

data

data

trigger

trigger

data

cmd

cloc

k

trg

ack

toke

nda

ta

data

toke

n

trg

ack

cloc

k

cmd

Controller

Controller

FE FE FE

toke

n

data

To the Tower Controller

To the next layer

Trigger

Trigger

Tr i

gger

Tri

gger

Simplified block diagram of the readout of aGLAST tower, showing only 2 of 16 layersand only 3 of 25 readout chips on eachlayer.




Front-End Readout Chip (GTFE64)

• The 64-channel chip currently beingdesigned has the followingadditional features:

– Calibration mask, to select anysubset of channels to be pulsed.

– Two 7 bit DACs, for settingcalibration and threshold levels.

– Separate masks for data and triggeroutput (Fast-OR).

– 8-deep FIFO event buffer.

– Dual redundant serial commanddecoders.

– Dual redundant output shiftregisters and trigger outputs.

– Bypasses to avoid clocking out datafrom empty chips.

– External communication via low-voltage-swing differential signals.

Cal

ibra

tion

Mas

k

64 in

put p

ads

Am

plif

iers

and

Dis

crim

inat

ors

FIFO

Buf

fer

(RA

M)

Shif

t Lef

t

Out

put R

egis

ter

Shif

t Rig

ht

Out

put R

egis

ter

ThresholdDAC

Cha

nnel

Mas

k

64inputOR

2inputOR

2inputOR

Fast-OR fromchip on left

Fast-OR fromchip on rightFast-OR to

chip on right

Fast-OR to chip on left

Command Receivers

Commands Clock Trigger

Dat

a In

Dat

a O

ut

Dat

a O

ut

Dat

a In

Controlregisteroutput

CalibrationDAC

Tri

gger

Mas

k




Resistors

Resistors are used in several places in thedesign:

• The DACs

• Drivers and receivers (to reducedependency of the power consumptionon the supply voltage)

However, the CMOS26G process has noreally good way for making evenmoderately large resistors. Therefore, wehave resorted to using N-well structuresfor that purpose.

We made a test chip that includes somestructures for testing the method that weemploy to make large resistors in thisprocess (N-wells).

1 2 3 4 5V

-100

0

100

200

300

400

500

Cu

rre

nt

(uA

)

I17.24 kohm

The resistance is nearly a factor of twohigher than what we anticipated.

This is being corrected accordingly inthe layout.

Predicted value was4.6 kΩ.




Threshold and Calibration DACs

• 6-bit linear DAC with 2 ranges.• Threshold DAC:

• 6 mV/step (≈0.05 fC).• or 24 mV/step (up to ≈12 fC).

• Calibration DAC (same voltage stepsinto a 42 fF calibration capacitor):

• 0.25 fC/step in low range.• 1 fC/step in high range (up to

about 12 MIPs).

• Functions by adding currents, the totalof which are converted to a voltage bya resistor (N-well structure).

• A reference current is derived fromthe 2V supply and a resistor (the tworesistor values cancel to 1st order).

• A test chip with this DAC wasreceived just last week from MOSIS.

0 10 20 30 40 50 60 70

Setting

0.0

0.1

0.2

0.3

0.4

0.5

Thr

esho

ld (

volts

)

MeasuredStep=5.77mVSimulatedStep=6.26mV

Measurement of the DAC performancein the low range, compared with aSpice simulation of the circuit. Theslope is close to expectations despitethe error in the resistor values.

The linearity is betterthan 0.5%.





Even though the DAC low range worksperfectly well, the high range does not.

-1 9 19 29 39 49 59 69Setting

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Thr

esho

ld (

volts

)

DataSpiceLine Fit

10 30 50 70

Setting

30

80

130

180

Cur

rent

(uA

)

Measured6.18+25.4n

10 30 50 70

Setting

-3

-1

1

3

Res

idua

l

However, the high range is OK if thevoltage is held constant and the current ismeasured, as on the right ⇒

There is someclear nonlinearityhere, but it isworking.

Measuring current atthe DAC output, withthe voltage = 1.5 V.





0.0 1.0 2.0 3.0 4.0Voltage Across Resistor

-100

0

100

200

300

400

500

600

Cur

rent

(uA

)

ITHR-IREF7.29 kohm

Vref held constant at 1.28 V

All bits set to 0.

It appears that current is flowing out ofthe threshold output node by somemeans other than through the resistorwhen the voltage gets above about 2.6 V.

This mystery is being investigated.

With V-ref held constant, V-threshold isscanned from V-ref up to 5 V. Above acertain point there is more current flowinginto the threshold node than is flowing outthe opposite end of the resistor.

7.3 kohm

Threshold

V-ref=1.28 V

0.66 uA

0.66 uA

ITHR

IREF




Command Decoder

The front-end chip is controlled by serial command strings delivered to either of 2 redundantcommand decoders. Either decoder can load the control register at any time, but all othercommands are accepted only if the decoder is selected by a bit in the control register.

• Command format:– Start bit.

– 3-bit command code.

– 5-bit chip address or 1F (for all chips).

– N-bits of data (load control register).

• Commands:– 000: no-op.

– 001: load control register.

– 010: read-event.

– 011: calibration strobe.

– 100: clear first event from FIFO.

– 101: reset chip (FIFO + cntrl. reg.).

– 110: reset FIFO.

– 111: end-read-event.

Control is by synchronous logic, with an11-bit state machine. The logic design wasdone by hand, using a schematic, but thelayout was made using DoD CMOSXstandard cells and Cadence automatic place-and-route.

The complete design was simulated inSpice, as well as in digital simulators(Viewsim and Verilog).




Drivers and Receivers

• Controller chip to Readout Chips(clock, commands, trigger):

– Differential current drive, with 1 kΩtermination on the hybrid between thetwo lines.

– Maximum load is estimated to be 50 pF.

– Voltage swing is 0.7 V. Peak current is12 mA.

– Rise time is 5.4 ns (compared with 50nsclock period).

– Receiver power consumption is about150 µW each, with 5 operating at anygiven time on each chip.

• Data (chip-to-adjacent-chip):– 3V differential CMOS.

– Simplifies implementation of the 1600-element shift register across 25 chips.

– Experience with the 32-channel chipssuggests that this should not be aproblem for these very short distances.

• Fast-OR output (chip-to-adjacent-chip):– Small-voltage-swing differential.

– Local charge storage provides currentfor the fast edge; the charge is slowlyreplenished from VDD and GND.

– Therefore, in normal operation, withintermittent triggers, no spikes areintroduced into the supplies.

– Only one set of the redundant driversand receivers is turned on at a giventime, so save power.

• Controller chip to and from adjacentlayers and to and from the towerreadout electronics:

– Some form of low-voltage-swingdifferential transmission will be used.

– Probably it will be similar to thecommunication from controller chips toreadout chips, but it has not yet beenstudied and designed.




GTFE64 Simulations

• All of the subcircuits designed by Pavelwere simulated thoroughly by him inSPICE (memory, shift registers, drivers,receivers, DACs, etc.).

• The complete analog channel has beenthoroughly simulated in SPICE (usingBSIM models).

• An 8-channel model of the completeoutput stage (FIFO plus shift registers)was simulated in SPICE (includingadditional load to account for themissing 56 channels).

• The command decoder was simulatedin SPICE as a single unit, as well as inVerilog, using the CMOSX standard-cell Verilog models.

• Logic simulations have been carried outon the complete chip and on a set ofthree chips connected together:

– each primitive cell was simulated inSPICE and analog timing diagramswere made.

– A VHDL model was written for eachcell and then executed to produce adigital timing diagram.

– Delays were introduced into the VHDLmodels to give a good match betweenthe digital and analog timing diagrams.

– Dummy VHDL models were made forthe analog components for which adigital simulation is meaningless (suchas the DACs).

– The entire schematic was thensimulated at 20 MHz and 40 MHz byViewsim, using Viewsim built-inmodels for the logic gates and inverters(with nominal 0.5 ns delays).




Layout and Verification

• All layout but that for the commanddecoder has been drawn manually usingthe Mentor Graphics IC-Station andMOSIS SCMOS design rules. Thisincludes all I/O pads, with ESDprotection. This has all passed LVSand DRC within Mentor Graphics.

• The command decoder layout was doneby automatic place-and-route inCadence using CMOSX design rules.

• The Mentor layout has been transferredinto Cadence by way of GDS2, and thetwo command decoders will be insertedand connected within Cadence. Thefinal LVS and DRC will be done inCadence before submission, aftertransferring the schematics fromPower-View to Cadence (using EDIF).

• Test-pads have been, or are being,added as follows:

– Reset pad, to force a reset of thecommand decoder, if necessary.

– External calibration pulse input, incase the internal system doesn’twork or is insufficient for testing.

– All analog channel bias points.

– All preamp and shaper outputs.

– All receiver CMOS outputs anddriver CMOS inputs.

– DAC outputs.

– All clock and control outputs fromthe command decoders.




Layout

11.5

20.1

DRIN

DRIP

TA

CK

LN

CT

RL

RE

G

A1

A3

A2

A4

A0

TA

CK

RN

AV

DD

DLOP

DLON

DROP

DRON

DLIP

DLINQV

DD

AV

DD

2

AG

ND

CL

KL

P

CL

KL

N

TA

CK

LP

CM

DL

N

CM

DL

P

DG

ND

R

DV

DD

R

CM

DR

P

CM

DR

N

CL

KR

P

CL

KR

N

TA

CK

RP

AG

ND

R

AV

DD

R

I1VIR

AV

DD

2R

0.2 0.25 0.30.2

0.70.95

1.05

TLON TLIN

DV

DD

DG

ND

TRIP

TRIN

TLOP

TRON

TROP

TLIP

• The chip is designed to match the 195 micron detector strip pitch.

• Analog power and ground pads are doubled, with one of each at each end ofthe chip.

• Analog power must pass over the chip-to-chip digital signals. One of themetal layers is used as a shield between them where they cross.

• Analog and digital circuitry are separated by a well structure, but both analogand digital grounds are tied solidly everywhere to the substrate, to avoid latch-up problems.




Readout Controller Chip (GTRC)

• Control initialization, calibration,and readout of the front-end readoutchips.

• Sparse readout—build list of hit-strip addresses.

• Calculate the time-over-threshold ofthe prompt trigger output.

• Build events and coordinate thereadout with neighboring layers viaa serial data line and a token.

• External communication via low-voltage-swing differential lines.

• Currently being designed for the HP0.8 µm process using the CMOSXstandard cells. The logic design issynthesized from Verilog code.

I/O ControlGlobal Control Comand Decoding

FIFO for TOT

TOT CounterHit Counter

Event buffer

1

Event buffer

2

Gate

tokendata tokendata

Previous Layer

Next Layer

Data from Front End Chips

Tri

gger

Ack

now

ledg

e

Clo

ck

Com

man

ds

To Front End Chips

Trigger Out Triggers from the Front-End Chips

Commands

Clock

Trigger Acknowledge

Simplified block diagram of thereadout controller chip.




Hybrids

To minimize dead area, the hybrid circuits holdingthe readout chips and controller chips must be mountedon the sides of the detector trays.

A Kapton flex circuit brings the signals around thecorner of the tray.

The hybrid is divided into 5 pieces, each the widthof one detector wafer and each holding 5 readout chips.They are connected by wire bonds. The two end pieceseach hold a controller chip and connector.




Hybrids

• The hybrid circuits include– bypass capacitors for each readout chip and the detector bias,

– resistors to set the front-end bias current, and termination resistors for the digitalsignal lines.

– Power supply filtering and fuses.

– Temperature monitors.

• Eight layers are used in the layout, including entire planes for power, ground,analog 2V, and detector bias. The central type has already been fabricated.

Left-Hand Hybrid: All analog signals pass alongplanes beneath the digital signal planes and areseparated from them by power and ground planes.Detectors and readout chips have wide low-inductance paths to the decoupling capacitors.




Flex-Circuit Detector Interconnect• Top layer of conductors for bias

(120 V), ground, and signals.

• Bottom layer is a shield plane toisolate detectors from the trays.

• 3 pads to supply bias to the backsof each of 25 detectors.

• 5 traces to bond to the bias-voltage strips to each of the 5hybrid circuits.

• 6 traces to bring the ground of thehybrids around the tray corner tothe detectors.

• 1600 traces to bring the signalsfrom the detectors around the traycorner to the readout chips.

• Alignment mark at the corner ofeach detector.

Status:• Manufacture of 5 prototype pieces is in progress.• 3-week turn-around.




Cabling and Connectors

• The connectors must lie flat on the hybrid tominimize dead space at the tower edge.

• Nanonics space-qualified 25-pin “Dualobe” 25-milpitch connectors appear to fit the requirements well.

• The cable must include connections from layer toadjacent layer, as well as from each layer to the towerbase. A Kapton circuit provides the best flexibility indesign and allows us to build in shielding.

• The design concept shown below will give goodaccess to the connectors and is manufacturable.

0.9

PC

Boa

rd

Chi

ps

Flex

Cir

cuit

Nanonics Connector

Analog power and ground, plus detector bias.

A connector forevery other tray.

Tower Base Digital Traces, surrounded by digital power and groun




Conclusion

• The near-term goal is to have allelectronics and detectors necessaryto begin assembly of anengineering prototype tower nextautumn.

– Submit GTFE64 chip for 1stprototype production by December10, 1997. Begin testing inFebruary, 1998.

– Submit GTRC chip for 1stprototype production in January orFebruary, 1998.

– Produce at least 10 wafers ofGTFE64 chips in July, 1998.

– Test 1st full readout section insummer 1998.

• Final loose ends of the GTFE64 layoutand verification must be tied up soon.

• Controller-chip simulations must becarried out together with the readout-chip digital model.

• I/O design of the controller chip mustbe finalized and layout done.

• Controller chip layout and verificationmust be done.

• End hybrid design needs to beprototyped, after some possiblemodifications (more terminationresistors?).

• Cables need to be prototyped.

• More interfacing to DAQ at Stanfordand mechanical work at SLAC.

• Lots of testing!

ASIC Development for the GLAST Trackerscipp.ucsc.edu/groups/fermi/publications/GTFE64_review.pdf ·...

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Transcript of ASIC Development for the GLAST Trackerscipp.ucsc.edu/groups/fermi/publications/GTFE64_review.pdf ·...