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09 September 2014

Asia Pacific

Equity Research

Semiconductor Devices (Technology - Foundries CN (Asia)/Technology -

Semiconductors CN (Asia)/Technology - IC Deisgn TW (Asia)/Small Cap HK

(Asia))

Asian Semiconductor Sector COMMENT

Semicon Taiwan targets IoT for the 10x growth

Figure 1: IoT the next driver after PC and mobile

Source: SEMI, Samsung

■ Semicon Taiwan looks to IoT as the next 10x driver for the industry. We

attended the annual Semicon Taiwan focusing on chip manufacturing

developments and drawing 40,000 participants. This year's event focused on

enabling the next 10x industry driver with the IoT with panels on 8"/specialty

foundry, 2.5D/3D, SiP and fan-out packaging, EUV lithography, advanced

flip chip bonders, memory, and a CFO panel on financial mgmt.

■ Fan-out/2.5D/3D packaging ready but costs keep it a high-end niche.

We published in 2012 that it was early and overblown to de-rate the back-

end from foundry competition on the advance to 2.5D/3D packaging and

continue to support that view. TSMC discussed its CoWoS/InFO

developments but higher costs vs. flip chip/wirebonding are still keeping it a

niche at 1-2% of the industry in 2015. ASE highlighted its rival aS3+ and SiP

process, where we believe USI has US$40 content in a flagship watch.

■ TCB bonding from ASM Pacific/K&S may add memory next. ASM

showcased its work with Intel commercializing TCB bonding for high-end

processors and K&S unveiled its tool with units shipped to two memory

customers. The companies believe memory would launch TCB next.

■ EUV making some progress, though TSMC also still developing E-

Beam. ASML and TSMC noted litho source power has reached 45W and

throughput 500 wafers "on a good day" and still hope for 125W by end 2015

to allow for a few layers on 10nm. TSMC is still spending R&D on e-Beam as

another option at 7nm, noting some cost and performance advantages. See

John Pitzer's separate report for more discussion on the litho updates.

■ CS ATC this week to provide the next read. We view ASE well positioned on SiP integration with opportunity more than offsetting some high-end push from TSMC into wafer level packaging. We also maintain ASM Pacific OUTPERFORM with TCB giving it a potential LT packaging driver. We look

ahead to CS ATC this week for updates from the 110 companies attending.

Research Analysts

Randy Abrams, CFA

886 2 2715 6366

randy.abrams@credit-suisse.com

Nickie Yue

886 2 2715 6364

nickie.yue@credit-suisse.com

09 September 2014

Asian Semiconductor Sector 2

Focus charts Figure 2: TSMC source power roadmap Figure 3: Multiple E-Beam cost may be lower than EUV

0

50

100

150

200

250

300

Q413 Q114 Q214 Q314 Q414 Q115 Q215 Q315 Q415

Source Power Watts

Cost of all layers of

7nm lithography 10nm 7nm

Lithography tool ArFi ArFi EUV EUV

Multiple E-

Beam

MEB cost

saving

Source Power 125W 250W

Case 1 1.00 2.10 2.40 2.00 1.70 -15%

Case 2 1.00 1.74 2.18 1.81 1.58 -13%

Case 3 1.00 1.49 1.56 1.45 1.40 -3%

Source: TSMC Source: TSMC data

Figure 4: Micron projects DRAM bit supply growth to slow

to 21% from '14-'18

Figure 5: Micron projects DRAM demand to still have 25%

YoY growth with growth from more applications

Source: Micron Source: Company data, Credit Suisse estimates

Figure 6: TSMC advanced packaging technologies Figure 7: TSMC advanced technology roadmap

Source: TSMC Source: TSMC

Figure 8: Chip attach assembly history Figure 9: Intel's next generation chip attach technology

Source: ASM, Intel Source: ASM, Intel

09 September 2014

Asian Semiconductor Sector 3

SEMICON Taiwan targets IoT for the next 10x growth SEMI, the chip equipment supplier’s member organisation hosted its annual Semicon

Taiwan starting yesterday featuring 40,000 industry representatives. The event provides a

view on technology trends from leading manufacturers and equipment suppliers though

not focused on financial updates. Key focus was on driving the industry to expand from the

2 bn unit smartphone market into the multi-billion unit Internet of Things market.

We attended sessions on 8"/specialty foundry technology, 2.5D/3D and system in

packaging, next generation lithography, advanced thermal compression flip chip bonders,

memory, and financial corporate management and present key themes and takeaways.

The Internet of Things as the next Semi growth driver

■ TSMC – Design ecosystem a key part of its grand alliance. TSMC’s Cliff Hou

provided several updates at his presentation on the design ecosystem and its ability to

enable the Internet of Things. The company featured several innovations including:

(1) Ultra low power 28nm (28nm ULP) – TSMC has developed an even lower process

suitable for the next wave of higher performance IoT devices, offering 30% lower

operating voltage, >40% lower active power and >75% lower standby power. The

company expects this process to move the sweet spot of IoT devices down from

40/55nm to 28nm and also will use this lower power process as the mainstream

alternative to challenge Samsung/GlobalFoundries licensing of FD-SOI for low power

28nm IoT ICs.

(2) Wafer level back-end packaging remains a key focus. TSMC will keep a joint track

for wafer level packaging including the very high-end CoWoS 2.5D stacking first

adopted by Xilinx but expensive for mass market applications and InFO for smaller

packages. We believe QCOM's RF 360 may use TSMC's InFO and Stats eWLB for its

initial fan-out application and have already seen Marvell produce with Marvell, though

revenue is still very small relative to flip chip and wirebonding.

(3) Virtual platform to integrate chip level and system level design. Cliff Hou also

discussed a new virtual platform to speed new chip and system level design. The

company noted its IP ecosystem is up to 7,500+ titles from 40 IP partners, giving it a

broad platform for customer engagement and expects to have this platform available

for customers by next year's show.

Figure 10: Silicon building blocks for the Internet of

Things

Figure 11: TSMC R&D pipeline for future opportunities

Source: TSMC Source: TSMC website

Semicon Taiwan technology

updates profiled

TSMC adds 28nm ULP to its

roadmap to offer a lower

power process to keep

competitive relative to

Samsung/GF with FD-SOI

09 September 2014

Asian Semiconductor Sector 4

■ ASE – Internet of Things has the building blocks – but needs to come together.

ASE’s COO Tien Wu highlighted the next major evolution of ICs is to grow the industry

with the next 10x move from the 2bn unit handset market to the 10+ bn IoT market

enabling machine to machine communication. ASE highlighted its ability to join

packaging and module design for SiPs for IC design and system companies as its

unique opportunity. The company is cautious however that more value is shifting to

software/services over ICs/hardware and doesn’t yet see a self-sustaining profitable

model to bring the pieces together for another big inflection for IoT volumes yet.

Figure 12: IoT the next 10x driver after PC and mobile

Source: SEMI, Samsung

■ UMC – IoT enables business for its 200mm (8") fabs. UMC noted that IoT

applications will drive the next wave after smartphones and PC. It believes it has a rich

portfolio of 8" technologies to support eNVM (65/55nm), CIS (65/55nm), HV

(65/55nm), PMIC (.18um), MEMS (.18um), and that it also has leadership on 12" for

55nm HV, CIS, eFlash.

■ SMIC – building technology platforms to meet the demand for 8" fabs. SMIC

sees three main types of demand supporting the growth of 8" fabs: 1) demand for

analog and mixed signal content for the mobile device market, 2) advanced up from

mature 6" IDM fabs (note Fairchild announced last week it would shut 6" capacity and

increase foundry outsourcing), and 3) injected by new wave applications (IoT,

wearable). The company also discussed its various technology offerings in its

specialty process generating one-third of sales: 1) CIS: SMIC has the top 5 unit

shipment, 1.75um and WLCSP ready and 3DIC CIS in development, 2) PMIC: .35um-

.18um in volume production, 3) eNVM (MCU, smart card): .18um – 55nm, 4) Flash

controller: 55/40nm with demonstrated yield, 5) MEMS: specialty process and total

TSV packaging solution.

Figure 13: UMC technology portfolio Figure 14: SMIC IoT applications and Technologies

Source: UMC Source: SMIC

ASE still sees some

developments needing to

come together to truly drive

the 10x growth from the IoT

market

09 September 2014

Asian Semiconductor Sector 5

2.5D & 3D to see more adoption next year, but cost is

still the hurdle to mass market adoption

We attended several forums at Semicon Taiwan's annual SiP forum focused mainly on

developments with next generation 2.5D & 3D packaging. Industry participants remain

more in agreement on some of the performance benefits, with integration of multiple chips

on a silicon interposer (commonly referred to as 2.5D or by TSMC as CoWoS) or directly

connected in a stack with Through Silicon Vias (referred to as 3D packaging). The

2.5D/3D stacks offer performance benefit in terms of higher memory density in a packaged

devices, higher bandwidth between logic and memory, lower power consumption, and

smaller form factor.

The industry is more confident in the 2.5D/3D technology readiness, but still sees conflicts

in ownership of the process between back-end and foundry and more importantly cost

continues to prohibit high volume application adoption relative to the mature flip chip and

wirebond processes. Key applications under development include homogeneous chips

(FPGA similar to Xilinx stacked interconnect), heterogeneous SiP (processor + memory) in

2016, cognitive computing SiP (multiple logic chips), wide I/O DRAM modules, CMOS

sensors and MEMS. Yole research expects to see start of production adoption of 3D IC in

2015 first by the memory companies (Micron, SK Hynix, and Samsung).

Figure 15: 2.5D/3D on the package roadmap from 2015 Figure 16: Industry readiness largely there now for 3D ICs

Source: ASE Source: ASE

■ ASE – maintains confidence in its SiP proposition and targets to support AMD

for 2.5D in 2015. ASE believes that it will lead the OSAT to capture opportunities in

the increasingly complex industry with its partnership combining Inotera's production

facility for the interposer production with ASE's packaging capability for the chip

connection and test. ASE noted that the 2.5D to 3D IC interconnection helps enrich

SiP solutions, which is driven by trends of hybrid sensors, connection, miniaturization,

minimum power consumption and effective cost. AMD is also going to 3D in FC-BGA

for its SoC effectiveness, wafer node efficiency, cost and yield concern, performance

and power efficiency. ASE also noted that AMD will have its first 2.5D shipping in

2015, supported by ASE.

2.5D/3D packaging more

ready now, but cost is still a

hurdle to lower cost

application adoption

ASE targets 3D work with

AMD in 2015

09 September 2014

Asian Semiconductor Sector 6

Figure 17: ASE 2D to 3D enriches its SiP solutions Figure 18: ASE working with AMD on 3D

Source: ASE Source: ASE

■ Inotera – forming a new business model for 2.5D with ASE, though capacity

looks limited. Inotera also believes that the industry is ready for 2.5D and 3D. 2.5D

with silicon interposer offers performance (yield & reliability), power and cost benefit

for advanced SiP. It also believes that its collaboration with ASE combines the

strength of an OSAT and a wafer foundry partner, and represents a competitive new

business model that offers a silicon interposer + assembly turnkey solution, which

simplifies supply chain management and offers large scale production efficiently.

We would caveat still that volumes may not be that material. Inotera has fully booked

out its 120k WPM capacity to Micron now and will lose 20% of its wafer capacity when

it shrinks from 30nm to 20nm over the next six quarters. Inotera may need to add new

capacity to materially grow its interposer production and make up for some of its

memory wafer capacity loss on 20nm.

Figure 19: ASE + Inotera partnering on 2.5D turnkey Figure 20: Inotera's new model as an Interposer foundry

Source: Inotera, ASE Source: Inotera, ASE

Thermal compression bonders from ASM Pacific and

KLIC battle out for advanced packaging business

A key enabler of advanced 2.5D and 3D packaging is the thermal compression flip chip

bonder. The product demand will be triggered by demand for finer pitch, thinner and more

complex packaging, high placement accuracy and die alignment as geometries shrink and

Moore's Law slows down. Both ASM Pacific and K&S held sessions to discuss the

opportunities they foresee in thermal compression bonding (TCB) and K&S was showing

its newly announced bonder in its customer meeting area on the Semicon Taiwan trade

ASE and Inotera partnership

for silicon interposers,

though Inotera is capacity

limited and will sacrifice

more to shrink to 20nm

ASM Pacific and Intel

demonstrate their TCB

bonders, K&S also

showcases its product

behind closed doors

09 September 2014

Asian Semiconductor Sector 7

show floor. The unique part of thermal compression bonding is it picks up the chip and

heats it up rapidly so it gets attached to the substrate locally without having to go through

a reflow oven. K&S launched its first TCB equipment called APAMA and noted that it is

able to heat it up and cool it down in 1 second.

Currently, Intel is using ASM's TCB tool as a high volume chip attach process. We expect

memory companies, including Micron, SK Hynix and Samsung, to be the next to adopt

thermal compression bonders as this technology is particularly suitable to meet the

technical requirements of 3D packaging.

However, larger scale roll out still hinges on the throughput (flip chip bonders process

3,000-5,000 units more per hour versus ~1,000 for thermal compression bonding) and

cost (a thermal compression bonder could cost 2-3x more than a flip chip bonder).

■ ASM Pacific – high-end thermal compression bonder in adoption by Intel. ASM

Pacific and Intel jointly presented the thermal compression bonding update, with use

now for high-end processors. The companies noted the benefits of thermal

compression bonding vs. traditional mass reflow are support for finer pitch, thinner and

better integrated system in packages, lower stress, and less warpage. However,

challenges include still relatively small installed base/maturity of process, throughput

and cost. Thermo compression bonding has been developed and implemented at Intel

towards high volume manufacturing starting in 2014. ASM believes its thermo

compression equipment provides unique features (high precision, large die handling

capability, portable, forward compatible) to enable high quality, fast and robust chip

attach process.

Figure 21: Chip attach assembly history Figure 22: Intel's next generation chip attach technology

Source: ASM, Intel Source: ASM, Intel

■ SPIL – technical session highlights its copper-silver alloy wirebonding

capability. On the other end of the spectrum, SPIL also discussed the benefits of

Silver-Copper alloy material as an alternative to gold or copper bonding. The

company cited silver’s lower hardness makes wire easier to bond with less force,

allowing higher throughput and still passing reliability, longevity and electrical tests.

The company has now converted 20-30% of its volume to silver alloy and 70% of

bonding to either silver alloy or copper, a key part of its margin improvement the past

few years transitioning from gold wirebonding.

Fan-out wafer-level packaging as a new solution to

advanced packaging, but still a niche market

TSMC also presented at Semicon on its roadmap on Wafer Level System Integration

(WLSI), with details on its advanced packaging technologies– CoWoS and INFO. TSMC

sees system integration as a new trend and opportunity, so it plans to do everything in

wafer form with its WLSI (wafer level system integration), which entails manufacturing,

design support, integrated services and also advanced packaging. TSMC believes this

SPIL highlights the merits of

its silver-copper alloy

09 September 2014

Asian Semiconductor Sector 8

total solution translates to competitiveness and its innovation and leadership technology

also help create values, scale, manufacturing efficiency, and capacity flexibility.

TSMC characterises WLSI as a "powerful and cool" technology, as it integrates chips and

packaging, reduces system size, shortens cycle times, increases customers' time to

money and also helps sustain Moore’s Law. It offers CoWoS for high performance, bigger

die size, suitable for 3D stacking, while InFO has a simpler architecture for smaller form

factor, and also supporting multi-chip integration but for more competitive cost.

TSMC noted strong interests from its big customers for its fan out technology, and that it

targets to maintain currently profitability levels even with the backend solutions. However,

we still expect challenges to wide adoption of CoWoS or even InFO in the near-term, as

both performance and cost must be optimised to be suitable for a wide range of

consumer/communication applications.

Figure 23: TSMC advanced packaging technologies Figure 24: TSMC advanced technology roadmap

Source: TSMC Source: TSMC

CoWoS designed for superior performance but also at high cost

TSMC's CoWoS (chip-on-wafer-on-substrate) enables high performance applications and

package sizes of 500mm2

and above with 1,000-4,000 I/O pin count. TSMC is moving its

CoWoS towards high function, bandwidth and data rate. It is also suitable for integrating

logic, DRAM and stacked DRAM chips that are on different nodes. It noted that CoWoS

has good yields and good thermal performance.

The benefit of having a substrate is that it helps achieve better performance, but the

substrate & bump also add to total thickness and cost. The only example of CoWoS has

been the project developed for Xilinx, which combined multiple 28nm die using an

interposer at very high cost but suitable for high-end applications.

TSMC targets to offer the next generation of InFO in 1H15

TSMC InFO (integrated fan out wafer level packaging) is designed for both single chip and

multi-chips, 2D & 3D, mobile application processor and baseband chips, linking logic to

memory and advanced & mature nodes. InFO also leverages on the wafer processing

technology and knowledge of CoWoS.

TSMC offering InFO for

mass market wafer level

packaging and CoWoS for

high-end packaging

09 September 2014

Asian Semiconductor Sector 9

Figure 25: TSMC InFO platforms – 2x2 mm2

upcoming

Source: TSMC, i-Micronews Source: TSMC, i-Micronews

TSMC claims that its InFO has a significantly thinner & lower profile package, tighter

bandwidth, better thermal performance for smaller form factor with much finer pitch (i.e.,

10um) and most importantly, at a lower cost. It noted that it targets to announce the next

generation InFO at 2x2 line spacing (L/S) in 1H15, a target that back-end companies only

aim for by end of 2015. Current InFO platforms include 8x8mm2

targeted at RF and WiFi

chips and the mid-sized platform (15x15mm2) for AP and baseband chips, the larger

25x25mm2 platform for multi-die could be for AP, GPU and networking applications. We

believe Qualcomm's RF 360 may be one of the first applications to adopt this package

type as it would allow for integration of multiple components in the package in a thin profile.

Figure 26: TSMC's InFO already qualified for production Figure 27: InFO architecture

Source: TSMC, i-Micronews Source: TSMC, i-Micronews

Besides TSMC, many backend/semis companies are also developing fan out wafer level

packaging, including STATS, Nanium, Amkor, ASE, STATS, Nepes, Freescale, Infineon,

J-Devices. According to Yole development estimates, the current Fan-out WLP technology

market size is roughly US$150 mn, or 1% of the US$25 bn OSAT total addressable

market, of which STATS has 58% market share and Nanium has 31%.

ASE highlighted aS3+ as ASE’s solution to provide a more cost effective coreless

substrate based flip chip or wirebond packaging that can use a lower density substrate as

an alternative to fan-out wafer level packaging (TSMC’s InFO or Stats eWLB). ASE noted

volumes have now passed 2 mn/month.

STATS also has its fan-out technology called Embedded Wafer Level Ball Grid Array

(eWLB) which has the design flexibility to accommodate an unlimited number of

interconnects, unconstrained by die size. STATS believe that its eWLB provides significant

performance, size and cost benefits. STATS' eWLB is offered for mass production – its

ASE's aS3+ an alternative

to wafer level packaging

09 September 2014

Asian Semiconductor Sector 10

key customers include Marvell now and we believe also may include Qualcomm for its RF

360 product alongside TSMC.

Figure 28: STATS' fan-out WLP technology - eWLB Figure 29: Stats 3D and eWLB packaging roadmap

Source: STATS Source: STATS

Memory demand drivers healthy and supply growth

still reasonable

Semicon Taiwan also featured several panels and sessions on the memory landscape.

Inotera's CEO Charles Kau and Micron Sr. Finance Director Kai Strohbecke reiterated

comments from Micron's recent Hong Kong analyst day focusing on structural

improvements in the memory sector. Charles Kau discussed improvements including (1)

supply constraints as technology migration now stretches cycle times and use more fab

space, thus lowering fab wafer capacity, (2) industry consolidation continues to improve

supply discipline and shift focus to returns over market share, (3) shipment growth is being

supplemented by new applications including mobile, Internet of Things, and in-memory

server computing, and (4) new memory types (LP DDR 4, 3D-ICs and ReRAM) have

potential in the coming couple of years to improve the value of memory by increasing

bandwidth and lowering latency.

The companies maintained their expectation for demand growth in DRAM sustaining

+25% YoY growth, outpacing a slowdown of bit growth from +30% YoY in 2014 to +21%

YoY average the next few years. Micron in the CFO session at the event also reiterated its

focus on efficient capital management and value creation. The company targets

investments over its 10% cost of capital, return driven investments with capex/sales

holding 20-25% and focusing investments on cost enablement and production efficiency

over market share.

Micron and Inotera reiterate

their expectation for slowing

bit growth in DRAM after

2014

09 September 2014

Asian Semiconductor Sector 11

Figure 30: Micron projects DRAM bit supply growth to

slow to 21% from '14-'18

Figure 31: Micron projects DRAM demand to still have

25% YoY growth with growth from more applications

Source: Micron Source: Micron

EUV making mild progress, although TSMC still

backing E-Beam as a 7nm and below alternative

TSMC and SEMI co-organised a Lithography and Mask technology symposium also

sponsored by ASML and featuring TSMC presentations on making lithography work for

7nm and beyond, multiple e-beam development toward 7nm and progress and challenges

of EUV for high volume manufacturing. We also attend sessions with updates on next

generation lithography from ASML, UMC, and Toshiba.

TSMC seeing some progress on EUV, but keeping a path toward E-Beam at 7nm as an

alternative

TSMC's Dr. Burn Lin, VP of R&D discussed limits and challenges on lithography on 7nm,

and noted the company would continue to work on EUV and e-Beam as options for 7nm

and below production. He acknowledged lithography has limits and many of these limits

are unexpected, making lithography work for 7nm "not a piece of cake".

The company outlined key limits on (1) overlay accuracy, (2) resolution, (3) defects and (4)

costs. He presented a case that e-Beam may provide some benefits over EUV in resolving

these issues, with e-Beam allowing (1) multiple additional high order turns to reduce

overlay error, (2) ability to avoid the problem of EUV mask flatness, (3) ability to resolve

some resolution limits, and (4) potentially better economics. The presentation showed

interesting data on cost comparison of ArF at 10nm vs 7nm cost for EUV of Multiple-E-

Beam. The data showed EUV is only lower cost than ArF at 250W but is still 3-15% more

expensive than e-Beam.

TSMC's Shy-Jay Lin presented on eBeam Direct Write Systems as a proponent to

continue industry development for possible production by 7nm. The company has

demonstrated a module and delivered a chip on 40nm using CMOS+MEMs and believes

e-Beam is still marching toward 7nm, with massive beams and multiple platforms possible

to enable the technology by 2017.

TSMC's Jack J.H. Chen, Department Manager of the company's next generation

lithography was more constructive on EUV's progress and challenges. He indicated the

company had achieved 45 watt performance in 2Q14 and was targeting 80 watts by 4Q14,

125 by 2Q15 and 250 watts by 4Q15, a level necessary to reach its 125 wafers per hour

for 300mm production. The company has improved tool availability of its first NXE 3100

systems from 50% in 2013 to 70-80% in 2014 and indicated it was one of the customers

ASML indicated was reaching 500 wafers processed "on a good day".

TSMC still doing R&D work

on e-Beam for 7nm next

generation lithography,

though also have the

mainstream EUV path still in

development

09 September 2014

Asian Semiconductor Sector 12

Figure 32: TSMC source power roadmap Figure 33: Multiple E-Beam cost may be lower than EUV

0

50

100

150

200

250

300

Q413 Q114 Q214 Q314 Q414 Q115 Q215 Q315 Q415

Source Power Watts

Cost of all layers of

7nm lithography 10nm 7nm

Lithography tool ArFi ArFi EUV EUV

Multiple E-

Beam

MEB cost

saving

Source Power 125W 250W

Case 1 1.00 2.10 2.40 2.00 1.70 -15%

Case 2 1.00 1.74 2.18 1.81 1.58 -13%

Case 3 1.00 1.49 1.56 1.45 1.40 -3%

Source: TSMC Source: TSMC data

ASML seeing customers progress toward EUV insertion at 10nm

ASML's Senior Product Manager Dr Kars Troost also provided an update on customer

status on EUV, with key message that multiple customers are now qualifying EUV for

insertion at the 10nm logic node. Dr Troost noted that a number of customers are now

getting to 500+ wafers per day with 40+ Watts source power and will allow the company to

reach that consistent target by year-end. The company remains confident in 2016 it will

provide customers with the production capability for volume production at 1,500

wafers/day. The company has six NXE 3300B systems fully qualified and shipped and five

more being integrated. The company's 4th generation NXE3350B has integration on-going.

TSMC financial session focused on managing return

on investment across the cycle

A newly added financial seminar featured TSMC CFO Lora Ho and Micron's Sr. Finance

Director Kai Strohbecke. Lora Ho highlighted three challenges foundries are facing in their

financial management:

(1) the economic challenges pursuing Moore's Law including rising technical challenges,

higher R&D/capex burden and fewer customers pushing down each node

(2) business challenge from slowing growth of mobile and uncertain timing and magnitude

of the next big thing (IoT), and

(3) intensifying need for risk management due to fast product cycles, and volatility of the

business and macro.

The company highlighted its ability to answer these challenges by growing 10%+ PBT the

past 5 years at 20%+ ROE with early engagement on new technology, accelerated tool

productivity, Grand Alliance ecosystem with IP, fabless, equipment and EDA, a

broadening spectrum of technology and financial discipline.

While the company acknowledged slowing growth in mobile, it still believes growth will

moderate to a still reasonable pace and be joined by continued growth in low-mid end

devices and Internet of Things. The company is increasing emphasis on its broader

technology platform including Ultra Low Power 28nm, sensors, embedded memory and

RF to capture the momentum on the Internet of Things. The company continues to

seriously consider increasing the dividend in 2015 and will target keeping low debt

leverage to maintain it’s A+ credit rating, targeting to take the debt ratio down from 33% to

30% this year and further next year.

ASML and TSMC have

achieved 40+ watt source

power and 500+ wafers per

day

TSMC seriously considers

increasing its dividend in

2015, investment emphasis

will expand to its broader

technology platform of

specialty and ultra-low

power technology

09 September 2014

Asian Semiconductor Sector 13

Companies Mentioned (Price as of 05-Sep-2014)

ASM Pacific Tech. (0522.HK, HK$81.0) ASML Holding N.V. (ASML.AS, €75.48) Advanced Micro Devices, Inc. (AMD.N, $4.15) Advanced Semicon. Engr. (2311.TW, NT$36.1) Freescale Semiconductor Inc. (FSL.N, $21.35) Infineon Technologies AG (IFXGn.DE, €9.047) Inotera Memories Inc. (3474.TW, NT$48.0) Intel Corp. (INTC.OQ, $35.0) Kulicke & Soffa (KLIC.OQ, $14.95) Marvell Technology Group Ltd. (MRVL.OQ, $14.13) Micron Technology Inc. (MU.OQ, $32.94) QUALCOMM Inc. (QCOM.OQ, $75.81) SK Hynix Inc. (000660.KS, W43,200) STATS (STTS.SI, S$0.595) Samsung Electronics (005930.KS, W1,201,000) Semiconductor Manufacturing International Corp. (0981.HK, HK$0.73) Siliconware Precision (2325.TW, NT$43.8) Taiwan Semiconductor Manufacturing (2330.TW, NT$127.0) Toshiba (6502.T, ¥465) United Microelectronics (2303.TW, NT$13.3) Xilinx (XLNX.OQ, $43.06)

Disclosure Appendix

Important Global Disclosures

Randy Abrams, CFA and Nickie Yue, each certify, with respect to the companies or securities that the individual analyzes, that (1) the views expressed in this report accurately reflect his or her personal views about all of the subject companies and securities and (2) no part of his or her compensation was, is or will be directly or indirectly related to the specific recommendations or views expressed in this report.

3-Year Price and Rating History for ASM Pacific Tech. (0522.HK)

0522.HK Closing Price Target Price

Date (HK$) (HK$) Rating

30-Oct-11 95.40 68.00 U

08-Mar-12 98.95 79.50

25-Apr-12 103.10 89.50 N

27-Jul-12 101.10 77.50 U

22-Aug-12 85.05 73.50

26-Oct-12 86.70 67.50

07-Mar-13 101.60 93.00 N

24-Apr-13 78.80 72.50

26-Jul-13 86.20 75.50

04-Nov-13 68.05 55.20 U

27-Feb-14 70.25 78.00 O

13-Mar-14 67.50 *

24-Apr-14 82.80 97.00 O

* Asterisk signifies initiation or assumption of coverage.

U N D ERPERFO RM

N EU T RA L

O U T PERFO RM

09 September 2014

Asian Semiconductor Sector 14

3-Year Price and Rating History for Advanced Semicon. Engr. (2311.TW)

2311.TW Closing Price Target Price

Date (NT$) (NT$) Rating

31-Oct-11 23.64 29.83 O

23-Apr-12 25.40 31.58

26-Jul-12 19.48 27.20

26-Apr-13 25.85 31.00

16-Jul-13 25.35 R

29-Aug-13 25.45 31.00 O

09-Oct-13 29.00 34.00

20-Dec-13 27.25 31.50

10-Feb-14 29.15 32.50

08-Apr-14 33.45 40.00

28-Apr-14 34.75 42.00

08-Jul-14 39.90 47.00

* Asterisk signifies initiation or assumption of coverage.

O U T PERFO RM

REST RICT ED

3-Year Price and Rating History for Taiwan Semiconductor Manufacturing (2330.TW)

2330.TW Closing Price Target Price

Date (NT$) (NT$) Rating

03-Oct-11 68.60 77.00 O

27-Oct-11 71.90 79.00

19-Mar-12 83.70 90.00

27-Apr-12 86.00 95.00

19-Jul-12 77.50 87.00

08-Oct-12 89.10 95.00 N

06-Dec-12 96.60 109.00 O

19-Apr-13 106.50 116.00

19-Feb-14 108.00 122.00

12-Mar-14 113.00 130.00

18-Apr-14 123.00 137.00

10-Jul-14 134.50 150.00

17-Jul-14 124.50 145.00

* Asterisk signifies initiation or assumption of coverage.

O U T PERFO RM

N EU T RA L

The analyst(s) responsible for preparing this research report received Compensation that is based upon various factors including Credit Suisse's total revenues, a portion of which are generated by Credit Suisse's investment banking activities

As of December 10, 2012 Analysts’ stock rating are defined as follows:

Outperform (O) : The stock’s total return is expected to outperform the relevant benchmark*over the next 12 months.

Neutral (N) : The stock’s total return is expected to be in line with the relevant benchmark* over the next 12 months.

Underperform (U) : The stock’s total return is expected to underperform the relevant benchmark* over the next 12 months.

*Relevant benchmark by region: As of 10th December 2012, Japanese ratings are based on a stock’s total return relative to the analyst's coverage universe which consists of all companies covered by the analyst within the relevant sector, with Outperforms representing the most attractiv e, Neutrals the less attractive, and Underperforms the least attractive investment opportunities. As of 2nd October 2012, U.S. and Canadian as well as European ra tings are based on a stock’s total return relative to the analyst's coverage universe which consists of all companies cove red by the analyst within the relevant sector, with Outperforms representing the most attractive, Neutrals the less attractive, and Underperforms the least attractive investment opportunities. For Latin Ame rican and non-Japan Asia stocks, ratings are based on a stock’s total return relative to the average total return of the relevant country or regional benchmark; prior to 2nd Oc tober 2012 U.S. and Canadian ratings were based on (1) a stock’s absolute total return potential to its current share price and (2 ) the relative attractiveness of a stock’s total return potential within an analyst’s coverage universe. For Australian and New Zealand stocks, 12 -month rolling yield is incorporated in the absolute total return calculation and a 15% and a 7.5% threshold replace the 10-15% level in the Outperform and Underperform stock rating definitions, respectively. The 15% and 7.5% thresholds replace the +10-15% and -10-15% levels in the Neutral stock rating definition, respectively. Prior to 10th December 2012, Japanese ratings were based on a stock’s total return relative to the average total return of the relevant country or regional benchmark.

Restricted (R) : In certain circumstances, Credit Suisse policy and/or applicable law and regulations preclude certain types of communications, including an investment recommendation, during the course of Credit Suisse's engagement in an investment banking transaction and in certain other circumstances.

09 September 2014

Asian Semiconductor Sector 15

Volatility Indicator [V] : A stock is defined as volatile if the stock price has moved up or down by 20% or more in a month in at least 8 of the past 24 months or the analyst expects significant volatility going forward.

Analysts’ sector weightings are distinct from analysts’ stock ratings and are based on the analyst’s expectations for the fundamentals and/or valuation of the sector* relative to the group’s historic fundamentals and/or valuation:

Overweight : The analyst’s expectation for the sector’s fundamentals and/or valuation is favorable over the next 12 months.

Market Weight : The analyst’s expectation for the sector’s fundamentals and/or valuation is neutral over the next 12 months.

Underweight : The analyst’s expectation for the sector’s fundamentals and/or valuation is cautious over the next 12 months.

*An analyst’s coverage sector consists of all companies covered by the analyst within the relevant sector. An analyst may cover multiple sector s.

Credit Suisse's distribution of stock ratings (and banking clients) is:

Global Ratings Distribution

Rating Versus universe (%) Of which banking clients (%)

Outperform/Buy* 44% (54% banking clients)

Neutral/Hold* 40% (51% banking clients)

Underperform/Sell* 13% (44% banking clients)

Restricted 3%

*For purposes of the NYSE and NASD ratings distribution disclosure requirements, our stock ratings of Outperform, Neutral, and Underperform most closely correspond to Buy, Hold, and Sell, respectively; however, the meanings are not the same, as our stock ratings are determined on a relative basis. (Please refer to definitions above.) An investor's decision to buy or sell a security should be based on investment objectives, current holdings, and other indivi dual factors.

Credit Suisse’s policy is to update research reports as it deems appropriate, based on developments with the subject company, the sector or the market that may have a material impact on the research views or opinions stated herein.

Credit Suisse's policy is only to publish investment research that is impartial, independent, clear, fair and not misleading. For more detail please refer to Credit Suisse's Policies for Managing Conflicts of Interest in connection with Investment Research: http://www.csfb.com/research and analytics/disclaimer/managing_conflicts_disclaimer.html

Credit Suisse does not provide any tax advice. Any statement herein regarding any US federal tax is not intended or written to be used, and cannot be used, by any taxpayer for the purposes of avoiding any penalties.

See the Companies Mentioned section for full company names

The subject company (2330.TW) currently is, or was during the 12-month period preceding the date of distribution of this report, a client of Credit Suisse.

Credit Suisse expects to receive or intends to seek investment banking related compensation from the subject company (0522.HK) within the next 3 months.

As of the end of the preceding month, Credit Suisse beneficially own 1% or more of a class of common equity securities of (2311.TW, 2330.TW).

Credit Suisse has a material conflict of interest with the subject company (2330.TW) . Credit Suisse is acting as the financial advisor to Motech Industries Inc in relation to the share subscription by Taiwan Semiconductor Manufacturing Co., Ltd.

Important Regional Disclosures

Singapore recipients should contact Credit Suisse AG, Singapore Branch for any matters arising from this research report.

The analyst(s) involved in the preparation of this report have not visited the material operations of the subject company (0522.HK, 2311.TW, 2330.TW) within the past 12 months

Restrictions on certain Canadian securities are indicated by the following abbreviations: NVS--Non-Voting shares; RVS--Restricted Voting Shares; SVS--Subordinate Voting Shares.

Individuals receiving this report from a Canadian investment dealer that is not affiliated with Credit Suisse should be advised that this report may not contain regulatory disclosures the non-affiliated Canadian investment dealer would be required to make if this were its own report.

For Credit Suisse Securities (Canada), Inc.'s policies and procedures regarding the dissemination of equity research, please visit http://www.csfb.com/legal_terms/canada_research_policy.shtml.

Credit Suisse has acted as lead manager or syndicate member in a public offering of securities for the subject company (2311.TW) within the past 3 years.

As of the date of this report, Credit Suisse acts as a market maker or liquidity provider in the equities securities that are the subject of this report.

Principal is not guaranteed in the case of equities because equity prices are variable.

Commission is the commission rate or the amount agreed with a customer when setting up an account or at any time after that.

09 September 2014

Asian Semiconductor Sector 16

Taiwanese Disclosures: This research report is for reference only. Investors should carefully consider their own investment risk. Investment results are the responsibility of the individual investor. Reports may not be reprinted without permission of CS. Reports written by Taiwan based analysts on non-Taiwan listed companies are not considered recommendations to buy or sell securities under Taiwan Stock Exchange Operational Regulations Governing Securities Firms Recommending Trades in Securities to Customers.

To the extent this is a report authored in whole or in part by a non-U.S. analyst and is made available in the U.S., the following are important disclosures regarding any non-U.S. analyst contributors: The non-U.S. research analysts listed below (if any) are not registered/qualified as research analysts with FINRA. The non-U.S. research analysts listed below may not be associated persons of CSSU and therefore may not be subject to the NASD Rule 2711 and NYSE Rule 472 restrictions on communications with a subject company, public appearances and trading securities held by a research analyst account.

Credit Suisse AG, Taipei Securities Branch ........................................................................................................ Randy Abrams, CFA ; Nickie Yue

For Credit Suisse disclosure information on other companies mentioned in this report, please visit the website at https://rave.credit-suisse.com/disclosures or call +1 (877) 291-2683.

09 September 2014

Asian Semiconductor Sector 17

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TC2033