ASEN4519 lecture3 - CH2
-
Upload
masaud-jan-khan -
Category
Documents
-
view
230 -
download
0
Transcript of ASEN4519 lecture3 - CH2
-
8/12/2019 ASEN4519 lecture3 - CH2
1/23
ASEN 4519/5519Lecture #3
1Copyright University of Colorado, 2005
Architecture of the PIC18F452 Architecture of the PIC18F452
-
8/12/2019 ASEN4519 lecture3 - CH2
2/23
ASEN 4519/5519Lecture #3
2Copyright University of Colorado, 2005
Comments
Questions? New students
Must attend ITLL orientation to receive computer accountand after hours access
Sign-up for orientation at the ITLL front desk
-
8/12/2019 ASEN4519 lecture3 - CH2
3/23
ASEN 4519/5519Lecture #3
3Copyright University of Colorado, 2005
Overview PIC18F452 block diagram PIC18F452 Pin out
Ports and resources QwikFlash board schematic PIC18F451 memory management Numbering systems
Decimal, binary, octal and hexadecimal
RAM layout Special function registers
Addressing modes
-
8/12/2019 ASEN4519 lecture3 - CH2
4/23
ASEN 4519/5519Lecture #3
4Copyright University of Colorado, 2005
PIC18Fx52PIC18Fx52
block
diagramRAM1536
EEPROM
256 FLASH32K
-
8/12/2019 ASEN4519 lecture3 - CH2
5/23
ASEN 4519/5519Lecture #3
5Copyright University of Colorado, 2005
PIC 18F452 Pin diagram
-
8/12/2019 ASEN4519 lecture3 - CH2
6/23
ASEN 4519/5519Lecture #3
6Copyright University of Colorado, 2005
The PIC18F452
The PIC18F452 has 5 ports (A-E) Each port has 3 associated 8-bit registers
TRISx.bit defines the direction of bit in port x TRISx.bit = 0 sets port x bit to be output TRISx.bit =1 sets port x bit to be input
PORTx.bit is used to read the value of bit on port x
LATx.bit is used to set the value of bit on port x A register is a reserved memory location in RAM For example TRISA is at memory location 0xF92 If the value of TRISA = 00101101 then
TRISA.0 =1 so port A pin 0 (RA0) is an input (pin #2) TRISA.1 = 0 so port A pin 1 (RA1) is an output (pin #3)
-
8/12/2019 ASEN4519 lecture3 - CH2
7/23
ASEN 4519/5519Lecture #3
7Copyright University of Colorado, 2005
The PORTS Port A 7 bit wide bidirectional port
Resources: Timer0, Low voltage detect, ADC
Port B 8 bit wide bidirectional port with weak pull-up resistors Resources: Interrupts, alt CCP2
Port C 8 bit wide bidirectional port Resources: Timers 1-3, capture compare, SPI, I2C, UART
Port D 8 bit wide bidirectional port Resources: Parallel slave port data
Port E 3 bit wide bidirectional port Resources: Parallel slave port control
-
8/12/2019 ASEN4519 lecture3 - CH2
8/23
ASEN 4519/5519Lecture #3
8Copyright University of Colorado, 2005
PORT A
Digital I/O, OSC2, clock outputRA6, OCS2, CLK0146
Digital I/O, analog input 4, slave selectinput (synchronous serial port), lowvoltage detect
RA5, AN4, SS,LVDIN
75
Digital I/O (open drain), timer0 clock inRA4, TOCKI64
Digital I/O, analog input 3, analog Vref +RA3, AN3, VREF+53
Digital I/O, analog input 2, analog Vref -RA2, AN2, VREF-42
Digital I/O, analog input 1RA1, AN131Digital I/O, analog input 0RA0, AN020
FunctionNamePin #Bit #
-
8/12/2019 ASEN4519 lecture3 - CH2
9/23
ASEN 4519/5519Lecture #3
9Copyright University of Colorado, 2005
PORT B
Digital I/O, IOC, serial programming dataRB7, PGD407Digital I/O, IOC, serial programming clockRB6, PGC396
Digital I/O, IOC, low voltage ICSP programmingRB5 1, PGM385
Digital I/O, IOCRB4374
Digital I/O, capture 2 input, compare 2 output,pulse width modulation with CCP2MX bitdisabled
RB3, CCP2363
Digital I/O, external interrupt 2RB2, INT2352
Digital I/O, external interrupt 1RB1, INT1341
Digital I/O, external interrupt 0RB0, INT0330
FunctionNamePin #Bit #
-
8/12/2019 ASEN4519 lecture3 - CH2
10/23
ASEN 4519/5519Lecture #3
10Copyright University of Colorado, 2005
PORT C
Digital I/O, USART asynchronous RX,USART synchronous data
RC7, TX, DT267
Digital I/O, USART asynchronous TX,USART synchronous clock
RC6, TX, CK256
Digital I/O, SPI data outputRC5, SDO245
Digital I/O, SPI data input or I 2C data I/ORC4, SDI, SDA234
Digital I/O, synchronous serial clock forI2C and SPI
RC3, SCK, SCL183
Digital I/O, capture 1 in, compare 2 out,pulse width modulator out
RC2, CCP1172
Digital I/O, timer1 oscillator in, capture 2in, compare 2 out, pulse width modulatorout with CCP2MX bit enabled
RC1, T1OSI, CCP2161
Digital I/O, timer1 oscillator out, timer1clock in
RC0, T1OSO,T1CKI
150
FunctionNamePin #Bit #
-
8/12/2019 ASEN4519 lecture3 - CH2
11/23
ASEN 4519/5519Lecture #3
11
Copyright University of Colorado, 2005
PORT D
Digital I/O, parallel slave port bit 7RC6, PSP7307
Digital I/O, parallel slave port bit 6RC6, PSP6296
Digital I/O, parallel slave port bit 5RD5, PSP5285
Digital I/O, parallel slave port bit 4RD4, PSP4274
Digital I/O, parallel slave port bit 3RD3, PSP3223
Digital I/O, parallel slave port bit 2RD2, PSP2212
Digital I/O, parallel slave port bit 1RD1, PSP1201
Digital I/O, parallel slave port bit 0RD0, PSP0190
FunctionNamePin #Bit #
-
8/12/2019 ASEN4519 lecture3 - CH2
12/23
ASEN 4519/5519Lecture #3
12
Copyright University of Colorado, 2005
PORT E
Digital I/O, analog input 7,parallel slave port chip selectRE2, AN7, CS102
Digital I/O, analog input 6,parallel slave port write
RE1, AN6, WR91
Digital I/O, analog input 5,parallel slave port read
RE0, AN5, RD80
FunctionNamePin #Bit #
-
8/12/2019 ASEN4519 lecture3 - CH2
13/23
ASEN 4519/5519Lecture #3
13
Copyright University of Colorado, 2005
Resources Timer0
8 or 16 bit timer 8 bit prescaler Internal or external clock Interrupt on overflow
Timer1 16 bit time or counter
Internal or external clock Interrupt on overflow
Timer2 8 bit timer 8 bit period register (PR2) Prescaler Postscaler Intrrupt on TMR2=PR2
Timer3 16 bit timer or counter
CCP1 & CCP2 16 bit capture/compare
Pulse width modulation (PWM) 10 bit resolution
Analog to digital converter (ADC) 10 bit resolution 8 channels multiplex to a single
ADC
Serial interfacing
I2C, SPI, UART Interrupts
Timer, UART, SPI, I2C, ADC,
-
8/12/2019 ASEN4519 lecture3 - CH2
14/23
-
8/12/2019 ASEN4519 lecture3 - CH2
15/23
-
8/12/2019 ASEN4519 lecture3 - CH2
16/23
ASEN 4519/5519Lecture #3
16
Copyright University of Colorado, 2005
Number systems I Basic numbering systems
Base X (X digits) number ABC = A*X^2 + B*X^1 + C*X^0 N th place represents X^n
Decimal system Base 10 (10 digits, 0-9) Number 467 = 4*100 + 6*10 + 7*1
Binary system Base 2 (2 digits, 0 &1, ON & OFF, TRUE & FALSE) Number 1101 = 1*2^3 + 1*2^2 + 0*2^1 + 1*2^0 = 8 + 4 + 0 + 1 = 13 10
Octal system Base 8 (8 digits, 0-7) Number 467 = 4*8^2 + 6*8^1 + 7*8^0 = 4*64 + 6*8 + 7 = 311 10
-
8/12/2019 ASEN4519 lecture3 - CH2
17/23
ASEN 4519/5519Lecture #3
17
Copyright University of Colorado, 2005
Number systems II Hexadecimal system
Base 16 (17 digits, 0-9 & A-F) Number 467 = 4*16^2 + 6*16^1 + 7*16^0 = 4*256 + 6*16 + 7 = 1127 10
Relationship between number systems 1 octal digit = 3 binary digits
111= 7
1 hexadecimal digit = 4 binary digits 1111 = F
Notation Number are assumed to be in decimal unless otherwise specified 0x76 or H76 refers to a hexadecimal number O76 refers to an octal number
B01001100 refers to a binary number
-
8/12/2019 ASEN4519 lecture3 - CH2
18/23
ASEN 4519/5519Lecture #3
18
Copyright University of Colorado, 2005
Relationship between numbers
F17111115
E16111014
D15110113
C14110012
B13101111
A 12101010
91110019
81010008
7701117
6601106
5501015
4401004
3300113
2200102
1100011
0000000
HexadecimalOctalBinaryDecimal
-
8/12/2019 ASEN4519 lecture3 - CH2
19/23
ASEN 4519/5519Lecture #3
19
Copyright University of Colorado, 2005
Binary numbering language
Bit a binary digit (0 or 1) Nibble or nybble a group of 4 bits. Corresponds to a single
hexadecimal digit Byte a group of 8 bits. It can be represented by two hexadecimal
digits. Word - a group of 16 bits
-
8/12/2019 ASEN4519 lecture3 - CH2
20/23
ASEN 4519/5519Lecture #3
20
Copyright University of Colorado, 2005
RAM layout 12 bit address space
2^12 = 4096 bytes Only 1536 +128 are used
RAM divided into 16 bankseach 256 bytes large
PIC18F452 uses 6 banks forgeneral purpose registers(GPR) and 128 bits for specialfunctions registers (SFR).
The SFR are located at the topof ram
Addresses 0xF80 to 0xFFF
The lowest 128 bits of RAMare called access RAM Addresses 0x000 to 0x080
GPR
GPR
GPR
GPR
GPR
UNUSED
Access RAM
SFR
0x000
0x100
0x200
0x300
0x400
0x500
0x600
0xF00
0xF80
0xFFF
0x080Bank 0
Bank 3
Bank 4
Bank 5
Bank 1
Bank 2
Bank 15
GPR
Banks 6-14 and the lowerhalf of bank 15 are unused
-
8/12/2019 ASEN4519 lecture3 - CH2
21/23
-
8/12/2019 ASEN4519 lecture3 - CH2
22/23
-
8/12/2019 ASEN4519 lecture3 - CH2
23/23
ASEN 4519/5519Lecture #3 23
Copyright University of Colorado, 2005
Homework LAB WEDNESDAY 31-AUG-05
ITLL Electronics shop (2-3pm)
Build your board Read
Lab handout Peatman Chapter 4
Peartman Appendix A1
LAB FRIDAY 02-SEP-05 ITLL Electronics shop (2-4pm)