Array Synthesis in SystemC Array Synthesis in SystemC Hardware CompilationHardware Compilation

Authors: J. Ditmar and S. McKeeverAuthors: J. Ditmar and S. McKeeverOxford University Oxford University

Computing Laboratory, UKComputing Laboratory, UK

Conference: Field Programmable Logic and Applications Conference: Field Programmable Logic and Applications (FPL), 2007(FPL), 2007

Presenter: Presenter: Tareq Hasan KhanTareq Hasan Khan ID: 11083577ID: 11083577

ECE, U of SECE, U of S

Literature review-1 (EE 800)Literature review-1 (EE 800)

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OutlineOutline

Introduction to SystemC and Agility Introduction to SystemC and Agility compilercompiler

Mapping SystemC ArrayMapping SystemC Array In RegisterIn Register In FPGA’s RAM In FPGA’s RAM

ResultsResults

Conclusion Conclusion

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SystemCSystemC

High level programming language to High level programming language to describe hardwaredescribe hardware

C++ syntaxC++ syntax

Synthesizable subset defined by Open Synthesizable subset defined by Open SystemC Initiative (OSCI)SystemC Initiative (OSCI)

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AgilityAgility SystemC Compiler SystemC Compiler

Translate SystemC program to HDL Translate SystemC program to HDL language (VHDL, Verilog, RTL SystemC)language (VHDL, Verilog, RTL SystemC)

AgilityAgility accepts most C++ constructs, such accepts most C++ constructs, such as:as: conditional statements — conditional statements — if, switchif, switch loop statements — loop statements — while, do...while, forwhile, do...while, for control flow — control flow — break, continue, returnbreak, continue, return

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AgilityAgility Design Flow Design Flow

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OutlineOutline

Introduction to SystemC and Agility Introduction to SystemC and Agility compilercompiler

Mapping SystemC ArrayMapping SystemC Array In RegisterIn Register In FPGA’s RAM In FPGA’s RAM

ResultsResults

Conclusion Conclusion

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Mapping SystemC ArrayMapping SystemC Array

SystemC Array SynthesisSystemC Array Synthesis Registers using general purpose logicRegisters using general purpose logic RAM blocks of modern FPGARAM blocks of modern FPGA

ConstrainConstrain SystemC arrays offer parallel access to elements SystemC arrays are accessed in one cycle SystemC arrays have write-before-read semantics

““Semantics of SystemC array must be Semantics of SystemC array must be

preserved after synthesis “preserved after synthesis “

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OutlineOutline

Introduction to SystemC and Agility Introduction to SystemC and Agility compilercompiler

Mapping SystemC ArrayMapping SystemC Array In RegisterIn Register In FPGA’s RAM In FPGA’s RAM

ResultsResults

Conclusion Conclusion

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Array Synthesis in Registers for Array Synthesis in Registers for Read AccessRead Access

Each array element produces a register in hardwareThe address decoder translates address x into a bit vector which controls the output multiplexerThe multiplexer selects the output of the particular element that is indexed by xIf an array is read several times, several address decoders and multiplexers are required

Mux

y = Array [ x ] x

y

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Array Synthesis in Registers for Array Synthesis in Registers for Write AccessWrite Access

The output lines of the address decoder are connected to the write enables of the registers to select in which register to writeIf an array is written to multiple times in a same clock cycle, multiplexers are required on the inputs of the registers to select which data to write

Array [ x ] = y

x

y

1111

OutlineOutline

Introduction to SystemC and Agility Introduction to SystemC and Agility compilercompiler

Mapping SystemC ArrayMapping SystemC Array In RegisterIn Register In FPGA’s RAM In FPGA’s RAM

ResultsResults

Conclusion Conclusion

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Array Synthesis in FPGA’s RAMArray Synthesis in FPGA’s RAM

Modern FPGA contains large amount of Modern FPGA contains large amount of RAMRAM Altera Cyclone II has 512KB of SRAMAltera Cyclone II has 512KB of SRAM

A SystemC Array can be accessed by A SystemC Array can be accessed by several processesseveral processes in a single clock cycle in a single clock cycle Multi-port RAM is neededMulti-port RAM is needed An algorithm is developed to automatically An algorithm is developed to automatically

assign memory access to RAM ports assign memory access to RAM ports

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Algorithm Constraints and StepsAlgorithm Constraints and Steps

The algorithm must assign memory access to The algorithm must assign memory access to ports such a way that:ports such a way that:

A memory port is never accessed more than once in A memory port is never accessed more than once in a clock cyclea clock cycle

The total number of memory ports must be The total number of memory ports must be minimizedminimized

StepsSteps1.1. Control Flow Graph (CFG) Control Flow Graph (CFG) 2.2. Access AnalysisAccess Analysis3.3. Port AssignmentPort Assignment

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Control Flow Graph (CFG)Control Flow Graph (CFG)

Codes between Codes between two consecutive two consecutive waitwait statements statements executes executes concurrently in a concurrently in a clock cycleclock cycle

All possible pathsAll possible paths that might be that might be traversed during traversed during program program executionexecution

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Access Analysis and Access Analysis and Port Assignments Port Assignments

PathPath RR WW

11 11 11

22 11 11

33 00 22

One Read only port and Two Write only port required

One Write only port and One Read-Write port required

PathPath WW RWRW

11 11 11

22 11 11

33 11 11

R=Read only port W=Write only port RW = Read-Write port

Each path executes in a single clock cycle

OR

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Access Analysis Algorithm Access Analysis Algorithm

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OutlineOutline

Introduction to SystemC and Agility Introduction to SystemC and Agility compilercompiler

Mapping SystemC ArrayMapping SystemC Array In RegisterIn Register In FPGA’s RAM In FPGA’s RAM

ResultsResults

Conclusion Conclusion

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ResultsResults

Inverse Desecrate Cosine Transform Inverse Desecrate Cosine Transform (IDCT) algorithm written in C contains (IDCT) algorithm written in C contains array of 1KBarray of 1KBThe design ported from C to SystemCThe design ported from C to SystemCUsed Used AgilityAgility compiler to produce EDIF compiler to produce EDIF (Xilinx Virtex-4 FPGA)(Xilinx Virtex-4 FPGA)

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ConclusionConclusion

Mapping of SystemC Array to hardwareMapping of SystemC Array to hardware In Resister FileIn Resister File

Take more logic areaTake more logic area

Less performanceLess performance In FPGA RAMIn FPGA RAM

A new algorithm to map arrays to memory has A new algorithm to map arrays to memory has been presentedbeen presented

More efficient in terms of logic areaMore efficient in terms of logic area

2020

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