ARM Core AP/Memory/PMIC WiFi/BT/BLE/ZigBee HW Security … · The information in this publication...

ARM Core AP/Memory/PMIC WiFi/BT/BLE/ZigBee

HW Security Module

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Important Notice

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ARTIK-5 Data Sheet

Copyright © 2015 Samsung Electronics Co., Ltd.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

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Contact Us: [email protected]

Home Page: http://www.samsung.com/us/ssic/

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Revision History

Revision Date Description Author(s)

FS 0.1 January 5, 2015 Initial Release Daehwan Kim

FS 0.2 April 16, 2015 Updated Connectivity Information Daehwan Kim

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Table of Contents

1 PRODUCT OVERVIEW 2 DIMENSION AND PIN ASSIGNMENTS

2.1 MECHANICAL DIMENSION 2.2 PIN ASSIGNMENTS 2.3 MODULE UBM SIZE

3 PIN DESCRIPTIONS 4 ELECTRICAL CHARACTERISTICS

4.1 DC CHARACTERISTICS 4.2 ENVIRONMENTAL CHARACTERISTICS 4.3 POWER CONSUMPTION

5 COMPONENT FEATURES

5.1 MAIN CPU SUBSYSTEM 5.2 HW SECURITY FEATURES (EMBEDDED SECURITY ELEMENT) 5.3 CONNECTIVITY FEATURES

5.3.1 WIFI IEEE 802.11b/g/n FEATURES 5.3.2 BLUETOOTH FEATURES 5.3.3 WIFI/BT COMBO SECURITY 5.3.4 ZIGBEE (THREAD PLANED) FEATURES

5.4 POWER MANAGEMENT IC (PMIC) 6 AP BOOTING SEQUENCING

6.1 BOOTING LOADERS 6.2 RESET STATUS 6.3 OM PIN CONFIGURATION

7. INTERFACES

7.1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART) FEATURES 7.2 I2C FEATURES 7.3 SERIAL PERIPHERAL INTERFACE (SPI) FEATURES 7.4 USB 2.0 FEATURES 7.5 AUDIO INTERFACE

7.5.1 I2S-BUS INTERFACE FEATURES 7.5.2 PCM AUDIO INTERFACE FEATURES

7.6 FIMC_LITE (CAMERA INTERFACE) 7.7 MIPI CSI FEATURES 7.8 MIPI DSIM FEATURES 7.9 WIFI/BT COMBO INTERFACES

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7.9.1 WLAN SDIO INTERFACES 7.9.2 BT INTERFACES

7.9.2.1 BT UART INTERFACE 7.9.2.2 BT I2S INTERFACE 7.9.2.3 BT PCM INTERFACE

7.10 ZIGBEE INTERFACES (THREAD PLANNED) 7.10.1 ZIGBEE SERIAL CONTROLLERS 7.10.2 ZIGBEE USB 7.10.3 ZIGBEE SERIAL WIRE AND JTAG (SWJ) INTERFACE

7.11 HW SECURITY ELEMENT (eSE) INTERFACES 7.11.1 eSE SPI INTERFACE 7.11.2 eSE I2C INTERFACE 7.11.3 eSE SERIAL I/O INTERFACE

8 WIRELESS SPECIFICATIONS

8.1 WIFI/BT COMBO 8.1.1 WLAN 2.4GHZ RECEIVER RF SPECIFICATIONS 8.1.2 WLAN 2.4GHZ TRANSMITTER RF SPECIFICATIONS 8.1.3 BLUETOOTH RF SPECIFICATIONS 8.1.4 ZIGBEE RF SPECIFICATIONS

9 APPLICATION REFERENCE DESIGN

9.1 APPLICATION REFERENCE SCHEMATIC 9.2 KEEP-OUT AREA

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1 PRODUCT OVERVIEW

ARTIK-5 is a combination module for the Internet of Things (IoT) applications like mid/low end IoT hub, IP camera (720p), and personal cloud with a powerful application processor, memories, PMIC, sensors, and HW embedded Security Element (eSE) as well as a variety of the wireless connectivity technologies including WiFi, BT/BLE, and ZigBee (Thread planned).

Key ARTIK-Pro Module Components Application Processor ARM A7 Dual @ 1GHz Memory 512MB LPDDR3 + 4GB eMMC

HW + SW Security HW Embedded Security Element (eSE) + TLS (DTLS), Data Encryption, Device Authentication, FW Security & Update, and Secure OS

Display T.B.D PMIC 5 Buck converters + 25 LDOs WiFi 802.11 b/g/n Bluetooth BT/BLE ZigBee Thread planned External Interface GPIO 47 (2 PWM output including) Analog Capture 2 (0 – 1.8V range) UART 2 I2C 4 SPI 1 I2S 1 USB 1 MMC 1 (T Flash) MIPI 1 DSI (2 LANE) + 1 CSI (2 LANE) Clock Out 1 - 24MHz + 1 - 32.768KHz Power Input Power 3.4V – 5.0V Output Power 1.8V/100mA + 2.4V/100mA Power Consumption T.B.D Software OS Yocto 1.6 OS (Fedora)

Development Environments Arduino® IDE + Samsung SDK C/C++/Java/Groovy

Physical Dimensions 29 x 25 x 3.5 mm

Connectors 60pins, 2 Panasonic AXT460124 40pin, 1 Panasonic AXT440124 (Debugging) (0.4 mm pin pitch, mating height 1.5 or 2.5mm)

Operating Temperature T.B.D Multimedia / Network

HW Video Codec HW Encoder & Decoder H.263/H264/MPEG-4/VP8 (720p)@30fps and decoding of MPEG-2/VC1/Xvid

GPU Mali 400 MP2 GPU, Open GL ES1.1/2.0, OpenVG1.1

Network LW M2M, CoAP, MQTT, 6LoWPAN, IPv6, Audio/Video Codec, and mDNS for WiFi

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2 DIMENSION AND PIN ASSIGNMENTS

2.1 MECHANICAL DIMENSION

2.2 PIN ASSIGNMENTS

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2.3 MODULE UBM SIZE

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3 PIN DESCRIPTIONS

Pin# Signal Name Type Connection to IC Pin Power Domain Description

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4 ELECTRICAL CHARACTERISTICS

4.1 DC CHARACTERISTICS

Symbol Parameter Min Typ. Max Unit

VBAT Main input supply from battery V

VIO DC supply for IO V

Table 4.1 Absolute Maximum Ratings

Symbol Parameter Min Typ. Max Unit

VBAT Main input supply from battery V

VIO DC supply for IO V

Table 4.2 Recommended Operating Conditions

4.2 ENVIRONMENTAL CHARACTERISTICS

Symbol Parameter Conditions Min. Max. Unit

ESD Electro-static discharge voltage

To Operating temperature °C

Ts Storage temperature °C

4.3 POWER CONSUMPTION

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5 COMPONENT FEATURES

5.1 MAIN CPU SUBSYSTEM

• ARM Cortex-A7 dual CPU as a power-efficient performance processor with 32/32 KB I/D Cache • 128-bit multi-layer AXI bus architecture • Memory subsystem

− 1-ports 32-bit 400MHz LPDDR2/LPDDR3 interfaces • Multi-format Video Hardware Codec

− 720p 30 fps (capable of decoding and encoding MPEG-4/H.263/H.264/VP8) − 720p 30fps (capable of decoding MPEG-2/VC1/Xvid)

• Image Signal Processor (ISP) − Supports BayerRGB with 3MP 30fps through MIPI CSI2 and some special functionalities such as

dynamic range compression and face detection • JPEG hardware codec • Supports 3D and 2D graphics hardware OpenGL ES 1.1/2.0 and OpenVG 1.1 • LCD single qHD display supports MIPI (T.B.D) • Real time clock, PLLs, timer with PWM, and watchdog timer

5.2 HW SECURITY FEATURES (EMBEDDED SECURITY ELEMENT)

• eSE CPU − SC300 32-bit core (MPU extension to 4 GB) − Thumb2 mode − Harvard architecture

• Memory protection unit • Memory allocation • NOR flash memory • Data security • Crypto accelerator • SWP interface • SPI interface • I2C interface • Serial I/O interface • Interrupt controller • Timers • Random number generator • Reset • Intelligent power and performance management • Supported standards

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− ETSI TS 102 221 (Class C) − ETSI TS 102 613 v9.2.0 − EMV 2000 − ISO 7816

5.3 CONNECTIVITY FEATURES

5.3.1 WiFi IEEE 802.11b/g/n FEATURES

• TX and RX low-density parity check (LDPC) support for improved range and power efficiency • Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while

maintaining excellent sensitivity for both Bluetooth and WLAN • Supports IEEE 802.15.2 external co-existence interface to optimize bandwidth utilization with other co-

located wireless technologies such as LTE or GPS • Supports standard SDIO v3.0 (up to SDR 104 mode at 208 MHz, 4-bit and 1-bit) host interfaces • Backward compatible with SDIO v2.0 host interfaces • Alternative host interface supports HSIC v1.0 • PCI mode complies with PCI Express base specification revision 3.0 for x1 lane and power management

running at Gen1 speeds

5.3.2 BLUETOOTH FEATURES

• Complies with Bluetooth Core Specification Version 4.1 with provisions to support future specifications • Bluetooth Class 1 or Class 2 transmitter operation • Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for re-

transmission of dropped packets • Adaptive frequency hopping (AFH) for reducing radio frequency interference • Interface support, host controller interface (HCI) using a USB or high-speed UART interface and PCM for

audio data • USB 2.0 full-speed (12 Mbps) supported for Bluetooth • Low power consumption improves battery life of handheld devices • Support multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound • Automatic frequency detection for standard crystal and TCXO values • Support serial flash interfaces

5.3.3 WiFi/BT COMBO SECURITY

• WPATM and WPA2TM (Personal) support for powerful encryption and authentication • AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility

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• Reference WLAN subsystem provides Cisco® Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0)

• Reference WLAN subsystem provides Wi-Fi Protected Setup (WPS)

5.3.4 ZIGBEE (THREAD PLANNED) FEATURES

• 2.4 GHz IEEE 802.15.4-2003 transceiver & lower MAC • 256 or 512 kB flash, with optional read protection • 32 or 64 kB RAM memory • AES128 encryption accelerator • Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers • Optional USB serial communications

5.4 POWER MANAGEMENT (PMIC)

5 High-efficiency and programmable Buck Converters

Number of

Buck Pin Current [A] Range [V] Step [mV] Default [V]

Buck1 VDD_MIF 1.0 0.6 to 1.4 6.25 1.0

Buck2 VDD_ARM 1.0 0.6 to 1.4 6.25 1.0

Buck3 VDD_INT/G3D 1.2 0.6 to 1.4 6.25 1.0

Buck4 VDD_MLDO 1.5 1.8 to 2.1 12.5 2.0

Buck5 VDD_LLDO 1.0 1.2 to 1.5 6.25 1.35

Table 5.1 Buck Converters

25 LDO Regulators (18 PMOS LDOs, 7 NMOS LDOs, N:NMOS type LDO, P:PMOS type LDO)

Number of

Buck Pin Current [A] Range [V] Step [mV] Default [V]

LDO1(N) N 150 0.9 to 1.1 12.5 1

LDO2(N) N 150 1.075 to 1.4 12.5 1.2

LDO3(P) P 300 1.6 to 2.0 25 1.8

LDO4(P) P 150 1.6 to 2.0 25 1.8

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LDO5(N) N 150 0.9 to 1.212 12.5 1.0

LDO6(N) N 150 0.9 to 1.212 12.5 1.0

LDO7(P) P 150 1.6 to 2.0 25 1.8

LDO8(P) P 150 2.25 to 3.3 25 3.0

LDO9(N) N 300 1.075 to 1.5 12.5 1.2

LDO10(N) N 150 0.9 to 1.1 12.5 1.0

LDO11(P) P 150 0.8 to 2.375 25 1.8

LDO12(P) P 150 1.8 to 3.375 25 2.85

LDO13(P) P 150 1.8 to 3.375 25 2.8

LDO14(P) P 150 1.8 to 3.375 25 2.7

LDO15(P) P 150 1.8 to 3.375 25 3.3

LDO16(P) P 150 1.8 to 3.375 25 3.3

LDO17(P) P 300 1.8 to 3.375 25 3.0

LDO18(P) P 300 1.8 to 3.375 25 2.8

LDO19(P) P 300 0.8 to 2.375 25 1.8

LDO20(P) P 150 0.8 to 2.375 25 1.8

LDO21(P) P 150 0.8 to 2.375 25 1.8

LDO22(N) N 150 0.8 to 1.5 12.5 1.2

LDO23(P) P 150 0.8 to 2.375 25 1.8

LDO24(P) P 150 1.8 to 3.375 25 3.0

LDO25(P) P 150 1.8 to 3.375 25 3.0

Table 5.2 LDO Regulators

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6 AP BOOTING SEQUENCING

6.1 BOOTING LOADERS

For initial booting, the internal memory that the AP provides are:

• 64 KB ROM (iROM) • 256 KB SRAM (iRAM)

You can select the booting device from:

• eMMC • SD/MMC

When you reset the system, the program executes at iROM. iROM can be executed on the system reset and on

the wakeup event by using low-power modes. Therefore, the boot loader code executes appropriate processes

according to the reset status.

The boot loader consists of two loaders: First and second boot loaders.

The features of these boot loaders are:

• iROM: It is a code to initiate SOC. iROM is implemented on an internal ROM of SOC • First boot loader (BL1): It is chip-specific and stored in an external memory device • Second boot loader (BL2): It is platform-specific and stored in external memory device. You should

assemble BL2 and store it in the external memory device • iROM is placed in an internal 64 KB ROM. It initializes basic functions such as Clock and Stack • iROM loads BL1 image from a specific booting device to the internal SRAM. Operating Mode (OM) pins

select the booting device. iROM verifies BL1 image according to the values of secure book key • In BL1 or BL2, the system clocks are initialized. You can configure DRAM controller. After initializing the

DRAM controller, you can transfer the OS image from the booting device to DRAM. iROM verifies OS image according to the values of secure boot key

• After booting, the program counter on the internal SRAM progresses to the operating system

iROM reads the OM pins to locate the booting device. The OM register provides the OM pin and other

information required for booting. The OM pin decides the booting devices such as eMMC, SD/MMC. USB

booting is used to debug system and reprogram flash. It is not used for normal booting.

6.2 RESET STATUS

There are several scenarios for system reset, such as:

• Hardware reset • Watchdog reset • Software reset

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• Wakeup from power-down modes

Initialization

in iROM PLL Setting

in iROM BL1 Loading

PLL and DRAM

Setting in BL1

OS Loading Restore Previous

State

XnRESET O O O O O X Watchdog

reset O O O O O X

Wakeup from SLEEP

O O O O X O

SW reset O O O O O Wake up

from AFTRmode

X X X X X O

Table 6.1 Functions Required for Various Reset Status

During the hardware and watchdog reset, the system should fully boot with BL1 and loaded with OS image. The

new reset status is classified as reset group0. You need not load the OS image to DRAM because the contents of

DRAM memory are preserved in the Sleep mode. However, during Sleep mode, SoC internal power is not

supplied to internal logic and not all contents in internal SRAM are preserved. Therefore, BL1 should be loaded

again. This reset status is classified as reset group1.

During software reset, the contents of internal SRAM and external DRAM are preserved. Therefore, it is not

required to load the boot loader. If system enters into all power down mode, you save the current system status

to a safe memory region such as DRAM. It facilitates the system processing seamlessly after waking up from

power-down modes. Finally, you must restore the previous state function on wake up from Sleep, and

AFTRmodes.

6.3 OM PIN CONFIGURATION

Table 6.3 lists the booting options. OM pins set the booting options.

OM[5:1] 1st Device 2nd Device

5’b00010 SD/MMC (MSH CH2) USB

5’b00011 eMMC (MSH CH0) USB

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5b’00101 to 5b’01001 Reserved

5b’10010 eMMC (MSH CH0) SD/MMC(MSH CH2)

5’b10011 to 5’b11001 Reserved

5b’11100 to 5b’11111 Reserved

Table 6.3 OM Pin Setting

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7. INTERFACES

7.1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART) FEATURES

The ports operate in an interrupt-based or a DMA-based mode. The UART generates an interrupt or a DMA

request to transfer data to and from the CPU and the UART. The UART supports bit rates up to 3 Mbps.

• RxD0, TxD0, RxD1, TxD1, RxD2, TxD2, RxD3 and TxD3 with DMA-based or interrupt-based operation • UART Ch 0, 1, 2, and 3 with irDA 1.0 • UART Ch 0 with 256-byte FIFO, Ch 1 with 64-byte FIFO, Ch 2 with 256-byte FIFO, Ch 3 with 16-byte FIFO • UART Ch 0, 1, 2 with nRTS0, nCTS0, nCTS1, nCTS2 and nRTS2 for auto flow control • Supports handshake transmit/receive

7.2 I2C FEATURES

To transmit information between bus masters and peripheral devices that connected to the I2C bus, it uses a

dedicated bi-directional Serial Data Line (SDA) and a Serial Clock Line (SCL).

• Includes eight channels multi-Master, Slave I2C BUS interfaces • Includes 7-bit addressing mode • Includes serial, 8-bit oriented, and bidirectional data transfer • Supports up to 100 Kbit/s in the standard mode • Supports up to 400 Kbit/s in the fast mode • Supports Master transmit, Master receive, Slave transmit, and Slave receive operation • Supports interrupt or polling events

7.3 SERIAL PERIPHERAL INTERFACE (SPI) FEATURES

Serial Peripheral Interface transfers serial data by using various peripherals. SPI includes two 8, 16, 32-bit shift

registers to transmit and receive data. During an SPI transfer, data is simultaneously transmitted (shifted out

serially) and received (shifted in serially). Includes a full duplex

• Includes 8/16/32-bit shift register for Tx/Rx • Two independent 32-bit wide transmit and receive FIFOs: Depth 64 in port 0 and depth 16 in port 1 • Supports receive-without-transmit operation • Supports National Semiconductor Microwire and Motorola SPI protocol

• Tx/Rx maximum frequency up to 50 MHz

7.4 USB 2.0 FEATURES

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Samsung USB 2.0 device controller aids the rapid implementation of USB 2.0 peripheral device. It supports both

high-speed (HS, 480Mbps) and full-speed (FS, 12Mbps) transfers. The USB 2.0 Controller can support up to

16endpoints (including Endpoint0) by using the standard UTMI interface and AHB interface.

• Complies with USB 2.0 specification (revision 1.0a) • Supports UTMI+ level 3 interface (revision 1.0) • Supports only 32-bit data on the AHB • Includes a control endpoint 0 for control transfer • Includes 15 device mode programmable endpoints

− Programmable endpoint type: Bulk, Isochronous, or Interrupt − Programmable IN/OUT direction

• Supports packet-based, dynamic FIFO memory allocation of 7936 depths (35-bit width)

7.5 AUDIO INTERFACE

7.5.1 I2S-BUS INTERFACE FEATURES

Inter-IC Sound (I2S or IIS) is one of the popular digital audio interfaces. The I2S bus handles audio data and other

signals, namely, sub-coding and control, are transferred separately. You can transmit data between two I2S bus.

To minimize the number of pins required and to keep wiring simple, a 3-line serial bus is used.

• Supports 1-port stereo (1 channels) I2S-bus for audio interface with DMA-based operation • Supports serial, 8/16/24-bit per channel data transfers • Supports Master/Slave mode • Supports I2S, MSB-justified and LSB-justified data format

7.5.2 PCM AUDIO INTERFACE FEATURES

The PCM audio interface module provides PCM bi-directional serial interface to an external Codec.

• Supports 16-bit PCM, one ports audio interface • Supports only Master mode • All PCM serial timings and strobes including the main shift clock, are on the basis of an PCM_EXTCLK • OSC, EPLL_FOUT or AUDIO_SCLK can be used as PCM_EXTCLK source clock • Optional timing on the basis of the internal APB PCLK • Supports input (16-bit x 32 depth) and output (16-bit x 32 depth) FIFOs to buffer data • Optional DMA interface for Tx and/or Rx

7.6 FIMC_LITE (CAMERA INTERFACE)

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The camera interface (CAMIF) in FImC_LITE is a fully interactive mobile camera interface. CAMIF supports

parallel I/F like ITU R BT-601 standard and MIPI (CSI) Slave I/F. The maximum input image size is 8192 x 8192

pixels.

CAMIF in FIMC_LITE is designed to perform some functions.

• T_PatternMux generates test pattern to calibrate input sync signals as HREF and VSYNC • Capture specifies the capturing signal • Window cut • Use the register settings to invert video sync signals and pixel clock polarity

7.7 MIPI CSI FEATURES

• Compliant to Samsung L3LP D-phy (D-phy standard specification V1.0) • Compliant to MIPI CSI2 Standard Specification V1.01r06 • Interfaces

− Compatible to PPI (Protocol-to-PHY Interface) in MIPI D-PHY Specification − AMBA3.0 APB Slave for Register configuration − Image output data bus width: 32 bits (optional)

• Memory − Non-image memory

o 8KB SRAM for async clock domain o This memory can store maximum 4 KB of non-image data per frame

• All of Flip-Flop of MIPI CSIS V3.0 are async reset FF type

Figure 7.7 Block Diagram of Camera System with MIPI CSIS V3.0

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7.8 MIPI DSIM FEATURES

• Complies with MIPI DSI standard specification V1.01r11 − Includes a maximum resolution that ranges up to qHD (960 x 540) (T.B.D) − Supports 1 or 2 data lanes − Supports pixel format: 24 bpp

• Includes interfaces − Complies with protocol-to-PHY interface (PPI) in MIPI D-PHY specification V0.90 − Supports RGB interface for video image input from display controller − Supports I80 interface for command mode image input from display controller − Supports PMS control interface for PLL to configure byte clock frequency − Supports prescaler to generate escape clock from byte clock − Complies with MIPI DSI standard specification V1.01r11

• MIPI DSIM supports only command mode not video mode

7.9 WIFI/BT COMBO INTERFACES

7.9.1 WLAN SDIO Interfaces

All three package options of the WIFI/BT COMBO WLAN section provide support for SDIO version 3.0, including

the new UHS-I modes:

• SDR12 : SDR up to 25MHz (1.8V signaling) • SDR25 : SDR up to 50MHz (1.8V signaling) • SDR50 : SDR up to 100MHz (1.8V signaling) • SDR104 : SDR up to 208MHz (1.8V signaling) • DDR50 : DDR up to 50MHz (1.8V signaling)

The SDIO interface also has the ability to map the interrupt signal onto a GPIO pin for applications requiring an

interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks

from within the device is also provided. SDIO mode is enabled by strapping options.

Three functions are supported :

• Function 0 Standard SDIO function (Max BlockSize / ByteCount = 32B) • Function 1 Backplane Function to access the internal System On Chip (SOC) address space (Max

BlockSize / ByteCount = 64B) • Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize / ByteCount

= 512B)

SD 4-Bit Mode SD 1-Bit Mode

DATA0 Data Line 0 DATA Data Line

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DATA1 Data Line 1 or Interrupt IRQ Interrupt

DATA2 Data Line 2 or Read Wait RW Read Wait

DATA3 Data Line 3 N/C Not Used

CLK Clock CLK Clock

CMD Command Line CMD Command Line

Table 7.9.1 SDIO PIN Description

7.9.2 BT INTERFACES

7.9.2.1 BT UART INTERFACE

The WiFi/BT combo shares a signal UART for Bluetooth and FM. The UART is a standard 4-wire interface (RX, TX,

RTS, CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate

detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a

vendor-specific UART HCI command. The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to

support EDR. The UART supports the Bluetooth 4.0 UART HCI specification : H4, a custom Extended H4, and H5.

The defaults baud rate is 115200 baud.

7.9.2.2 BT I2S INTERFACE

The WiFi/BT combo supports two independent I2S digital audio ports. The I2S signal are :

• I2S Clock : BT_ I2S_CLK • I2S Word Select : BT_ I2S_WS • I2S Data Out : BT_ I2S_DO • I2S Data In : BT_ I2S_DI

The clock rate in master mode is either of the following :

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

The master clock is generated from the input reference clock using a N/M clock divider.

In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.

7.9.2.3 BT PCM INTERFACE

The PCM interface on the WiFi/BT combo can connect to linear PCM Codec devices in master or slave. In master

mode, the WIFI/BT COMBO generates the PCM_CLK and PCM_SYNC signals and in slave mode, these signals are

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provided by another master on the PCM interface and are inputs to the WIFI/BT COMBO. The configuration of

the PCM interface may be adjusted by the host through the use of vendor-specific HCI Commands.

The WIFI/BT COMBO supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM

interfaces. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting

scheme where the 8KHz or 16KHz audio sample interval is divided into as many as 16 slots. The number of slots

is dependent on the selected interface rate of 128KHz, 512KHz, or 1024KHz. The corresponding number of slots

for these interface rate is 1,2,4,8, and 16, respectively. The WIFI/BT COMBO supports both short- and long-

frame synchronization in both master and slave mode.

7.10 ZIGBEE INTERFACES (THREAD PLANNED)

7.10.1 ZIGBEE SERIAL CONTROLLERS

The ZigBee/Thread SoC has two serial controllers, SC1 and SC2, which provide several options for full-duplex

synchronous and asynchronous serial communications.

• SPI (Serial Peripheral Interface), master or slave • TWI (Two Wire serial Interface), master only • UART (Universal Asynchronous Receiver/Transmitter), SC1 only • Receive and transmit FIFOs and DMA channels, SPI and UART modes • The SPI master controller has the following features:

− Full duplex operation − Programmable clock frequency (12 MHz max.) − Programmable clock polarity and phase − Selectable data shift direction (either LSB or MSB first) − Receive and transmit FIFOs − Receive and transmit DMA channels

• Both SC1 and SC2 SPI controllers include a SPI slave controller with these features: − Full duplex operation − Up to 5 Mbps data transfer rate − Programmable clock polarity and clock phase − Selectable data shift direction (either LSB or MSB first) − Slave select input

Receive and transmit FIFOs allow faster data speeds using byte-at-a-time interrupts. For the highest SPI and

UART speeds, dedicated receive and transmit DMA channels reduce CPU loading and extend the allowable time

to service a serial controller interrupt.

24

7.10.2 ZIGBEE USB

The ZIGBEE/THREAD SoC has a USB 2.0-compliant full-speed (12 Mbps) device peripheral, with on-chip

transceiver. It supports up to six endpoints (in addition to the control endpoint 0). There are five endpoints that

can be used as either interrupt or bulk and one isochronous endpoint. The USB peripheral is interfaced to the

CPU through memory mapped registers for control, and DMA for data. The USB device generates its own 48

MHz internal clock from the main 24 MHz crystal clock. The ZigBee/Thread SoC, where applicable, fully supports

USB suspend and resume modes, and meets the USB specification suspend current of <2.5mA. It achieves this by

switching the chip to run from a divided down version of the system clock.

7.10.3 ZIGBEE SERIAL WIRE AND JTAG (SWJ) INTERFACE

The ZigBee/Thread SoC includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug

and programming interface of the ZigBee/Thread SoC. The SWJ gives debug tools access to the internal buses of

the ZigBee/Thread SoC, and allows for non-intrusive memory and register access as well as CPU halt-step style

debugging. Therefore, any design implementing the ZigBee/Thread SoC should make the SWJ signals readily

available.

7.11 HW SECURITY ELEMENT (eSE) INTERFACES

7.11.1 eSE SPI INTERFACE

The eSE supports one SPI (Single Peripheral Interface) salve interface. The SPI supports serial data

communication. The key feature of SPI include :

• Support 10 MHz speed mode • Support operation based on interrupt • Transmits and receives data separately using FIFO • Contains two independent transmit and receive FIFO, each 64 samples deep by 8-bit wide • Operates in one mode, namely, slave modes

7.11.2 eSE I2C INTERFACE

The eSE supports two I2C (Inter Integrated Circuit) interfaces. The key feature of I2C include :

• Supports 400KHz Fast-mode and 3.4 MHz High-speed mode • Support operation based on interrupt

25

• Transmits and receives data separately using FIFO • Contains two independent transmit and receive FIFO, each 64 samples deep by 8-bit wide • Operates in two modes, namely, master and slave modes

7.11.3 eSE SERIAL I/O INTERFACE

The eSE supports asynchronous half-duplex serial I/O in conformance with the ISO 7816-3 standard. There are 2

interrupt sources for serial I/O1 interface: I/O1 falling edge interrupt, I/O1 Buffer available interrupt. You can

choose one among two SIO implementation methods as follows.

The first, you can implement serial I/O by software.

• Set IOCON1 control register for S/W SIO (Disable H/W UART)

The second, you can use the H/W UART.

• Set IOCON1 control register for H/W UART • UART operation conforms to ISO 7816-3 specification • Selectable attributes: Baud rate, Convention, Parity, Guard time, etc.

26

8 WIRELESS SPECIFICATIONS

8.1 WiFi/BT COMBO

8.1.1 WLAN 2.4GHZ RECEIVER RF SPECIFICATIONS

Parameter Conditions Min Typ. Max Unit

Minimum receiver sensitivity in 802.11b mode

1Mbps PER<8%,

Packet size = 1024 bytes

- - -80 dBm

2Mbps - - -80 dBm

5.5Mbps - - -76 dBm

11Mbps - - -76 dBm

Minimum receiver sensitivity in 802.11g mode

6Mbps PER<10%,

Packet size= 1024 bytes

- - -82 dBm

9Mbps - - -81 dBm

12Mbps - - -79 dBm

18Mbps - - -77 dBm

24Mbps - - -74 dBm

36Mbps - - -70 dBm

48Mbps - - -66 dBm

54Mbps - - -65 dBm

Minimum receiver sensitivity in 802.11n mode

MCS 0 PER<10%,

Packet size= 4096 bytes,

GF, 800ns GI, Non-STBC

- - -82 dBm

MCS 1 - - -79 dBm

MCS 2 - - -77 dBm

MCS 3 - - -74 dBm

MCS 4 - - -70 dBm

MCS 5 - - -68 dBm

MCS 6 - - -65 dBm

MCS 7 - - -64 dBm

Minimum receiver sensitivity in 802.11ac mode (VHT20)

27

MCS 0 PER<10%,

Packet size= 4096 bytes,

GF, 800ns GI, Non-STBC

- - -82 dBm

MCS 1 - - -79 dBm

MCS 2 - - -77 dBm

MCS 3 - - -74 dBm

MCS 4 - - -70 dBm

MCS 5 - - -66 dBm

MCS 6 - - -65 dBm

MCS 7 - - -64 dBm

MCS 8 - - -59 dBm

Maximum input level

Maximum input signal level

in 802.11b mode

PER<8% -10 - - dBm


in 802.11g mode

PER<10% -20 - - dBm


in 802.11n mode

PER<10% -20 - - dBm


in 802.11ac mode

PER<10% -30 - - dBm

Table 8.1.1 WLAN 2.4GHz Receiver RF Specifications

8.1.2 WLAN 2.4GHZ TRANSMITTER RF SPECIFICATIONS


Linear output power

Maximum output power in 802.11b mode As specified in

IEEE802.11

- 19 - dBm

Maximum output power in 802.11g mode - 16 - dBm

Maximum output power in 802.11n mode HT20 - 15 - dBm

Maximum output power in 802.11ac mode VHT20 - 15 - dBm

Transmit spectrum mask

Margin to 802.11b spectrum mask Maximum

output power

0 - - dBr

Margin to 802.11g spectrum mask 0 - - dBr

28

Margin to 802.11n spectrum mask 0 - - dBr

Transmit modulation accuracy in 802.11b mode

1Mbps As specified in

IEEE 802.11b

- - 35 %

2Mbps - - 35 %

5.5Mbps - - 35 %

11Mbps - - 35 %

Transmit modulation accuracy in 802.11g mode

6Mbps Mandatory - - -5 dB

9Mbps Optional - - -8 dB







Transmit modulation accuracy in 802.11n mode

MCS7 As specified in

IEEE 802.11n

- - -27 dB

Transmit modulation accuracy in 802.11ac mode

MCS8 VHT20 - - -30 dB

MCS9 VHT20 - - -32 dB

Transmit power-on and power-down ramp time in 802.11b mode

Transmit power-on ramp time from 10% to

90% output power

- - 2 μs

Transmit power-down ramp time from

90% to 10% output power

- - 2 μs

Other spectral parameters

Spurious emissions at the antenna port 30MHz ~ 1GHz

BW=100kHz

- - -62 dBm

1GHz~12.75GHz - - -47 dBm

29

BW=1MHz

Table 8.1.2 WLAN 2.4GHz Transmitter RF Specifications

8.1.3 BLUETOOTH RF SPECIFICATIONS


GFSK

Output Power Average Power - 11 - dBm

Frequency Range 2402 - 2480 MHz

Carrier Frequency Drift DH1 -25 - 25 kHz

DH3 -40 - 40 kHz

DH5 -40 - 40 kHz

Maximum Drift Rate -20 -- 20 kHz

Modulation dF1 Avg 140 - 175 kHz

dF2 Max 115 - - kHz

dF1 Avg / dF2 Avg 80 - - %

Sensitivity (BER) BER ≤0.1% - - -70 dBm

Maximum Input Level BER ≤0.1% -20 - - dBm

EDR (DPSK)

Relative Power п/4-DQPSK -4.0 - 1.0 dB

8DPSK -4.0 - 1.0 dB

RMS DEVM п/4-DQPSK - - 20.0 %

8DPSK - - 13.0 %

Peak DEVM п/4-DQPSK - - 35.0 %

8DPSK - - 25.0 %

99% DEVM п/4-DQPSK

DEVM ≤ 0.30

99 - - %

DEVM ≤ 0.20

8DPSK

99 - - %

EDR Sensitivity (BER) п/4-DQPSK

BER ≤ 0.01%

- - -70 dBm

30

BER ≤ 0.01%

8DPSK

- - -70 dBm

EDR Maximum Input Level п/4-DQPSK

BER ≤ 0.1%

-20 - - dBm

BER ≤ 0.1%

8DPSK

-20 - - dBm

Low Energy

Output Power Output Power -20 - 10 dBm

Operating Frequency 2402+K*2MHz

(K=0~39)

2400 - 2483.5 MHz

Table 8.1.3 Bluetooth RF Specifications

8.1.4 ZIGBEE RF SPECIFICATIONS

Receive measurements were collected with the ZigBee/Thread SoC Ceramic Balun Reference Design (Version A0)

at 2440 MHz. The typical number indicates one standard deviation above the mean, measured at room

temperature (25 °C). The Min and Max numbers were measured over process corners at room temperature.

Parameter Test Condition Min Typ Max Unit

Frequency range 2400 — 2500 MHz

Sensitivity (boost mode) 1% PER, 20 byte packet defined by

IEEE 802.15.4-2003;

— –102 –96 dBm

Sensitivity 1% PER, 20 byte packet defined by

IEEE 802.15.4-2003;

— –100 –94 dBm

High-side adjacent channel rejection IEEE 802.15.4-2003 interferer

signal, wanted IEEE 802.15.4-2003

signal at –82 dBm

— 35 — dB

Low-side adjacent channel rejection IEEE 802.15.4-2003 interferer


signal at –82 dBm

— 35 — dB

2nd high-side adjacent channel rejec-

tion

IEEE 802.15.4-2003 interferer


— 46 — dB

31

signal at –82 dBm

2nd low-side adjacent channel

rejection



signal at –82 dBm

— 46 — dB

High-side adjacent channel rejection Filtered IEEE 802.15.4-2003 inter-

ferer signal, wanted IEEE 802.15.4-

2003 signal at –82 dBm

— 39 — dB

Low-side adjacent channel rejection Filtered IEEE 802.15.4-2003 inter-



— 47 — dB

2nd high-side adjacent channel

rejection

Filtered IEEE 802.15.4-2003 inter-



— 49 — dB


rejection

Filtered IEEE 802.15.4-2003 inter-



— 49 — dB

High-side adjacent channel rejection CW interferer signal, wanted IEEE

802.15.4-2003 signal at –82 dBm

— 44 — dB

Low-side adjacent channel rejection CW interferer signal, wanted IEEE

802.15.4-2003 signal at –82 dBm

— 47 — dB

2nd high-side adjacent channel

rejection

CW interferer signal, wanted IEEE

802.15.4-2003 signal at –82 dBm

— 59 — dB


rejection

CW interferer signal, wanted IEEE

802.15.4-2003 signal at –82 dBm

— 59 — dB

Channel rejection for all other

channels



signal at –82 dBm

— 40 — dB

802.11g rejection centered at +12

MHz or –13 MHz



signal at –82 dBm

— 36 — dB

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Maximum input signal level for

correct operation

0 — — dBm

Co-channel rejection IEEE 802.15. 4-2003 interferer


signal at –82 dBm

— –6 — dBc

Relative frequency error

(50% greater than the 2x40 ppm

required by IEEE 802.15.4-2003)

–120 — +120 ppm

Relative timing error

(50% greater than the 2x40 ppm

required by IEEE 802.15.4-2003)

–120 — +120 ppm

Linear RSSI range As defined by IEEE 802.15.4-2003 40 — — dB

RSSI Range –90

— –40 dB

Table 8.1.4 ZigBee Receive Characteristics

Transmit measurements were collected with the Silicon Labs ZigBee/Thread SoC Ceramic Balun Reference

Design (Version A0) at 2440 MHz. The Typical number indicates one standard deviation below the mean,

measured at room temperature (25 °C). The Min and Max numbers were measured over process corners at

room temperature. In terms of impedance, this reference design presents a 3n3 inductor in parallel with a

100:50 Ω balun to the RF pins.

Parameter Test Condition Min Typ Max Unit

Maximum output

power(boost mode)

At highest boost mode power setting (+8) — 8 — dBm

Maximum output power At highest normal mode power setting

(+3)

1 5 — dBm

Minimum output power At lowest power setting — –55 — dBm

Error vector magnitude

(Offset-EVM)

As defined by IEEE 802.15.4-2003, which

sets a 35% maximum

— 5 15 %

Carrier frequency error –40 — +40 ppm

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PSD mask relative 3.5 MHz away –20 — — dB

PSD mask absolute 3.5 MHz away –30 — — dBm

Table 8.1.5 ZigBee Transmit Characteristics

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9 APPLICATION REFERENCE DESIGN

9.1 APPLICATION REFERENCE SCHEMATIC

9.2 KEEP-OUT AREA

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