Arithmetic-Logic Units. Logic Gates AND gate OR gate NOT gate.
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Transcript of Arithmetic-Logic Units. Logic Gates AND gate OR gate NOT gate.
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Arithmetic-Logic Units
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Logic GatesAND gate
OR gate
NOT gate
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Logic GatesNOR gate
NAND gate
XOR gate
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Half Adders
c
ab
a b c s 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
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Full Addercin a b cout s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
s=cin xor a xor b
cout=ab+cin(a xor b)
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Full Addercinab
cout
s
s=cin xor a xor b cout = ab+cin(a xor b)
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Ripple Carry Adder
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Ripple Carry Adders Each gates causes a delay
our example: 3 gates for carry generation book has example with 2 gates
Carry might ripple through all n adders O(n) gates causing delay intolerable delay if n is large
Carry lookahead adders
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Faster Adderscin a b cout s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
cout=ab+cin(a xor b) =ab+acin+bcin
=ab+(a+b)cin
= g + p cin
Generate g = abPropagate p = a+b
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Fast AddersIterate the idea, generate and propagateci+1 = gi + pici
= gi + pi(gi-1 + pi-1 ci-1) = gi + pigi-1+ pipi-1ci-1
= gi + pigi-1+ pipi-1gi-2 +…+ pipi-1 …p1g0
+pipi-1 …p1p0c0
Two level AND-OR circuit Carry is known early!
Assignment: Draw the schematic of Carry-lookahead adder and compare its delay to Ripple carry adder in terms of n
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Carry Lookahead Adders Based on the previous identity
Fast because critical path is shorter O(log n) gate delays [assuming 2-input gates] More complex to implement Design is less regular Layout of one bit adder cells depend on i
Compromise couple blocks of carry lookahead adders
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Building an ALU
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
AdditionSubtractionANDOR
What is missing? Zero flag & Overflow flags? From 32-bit ALU
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Determine a<b Calculate b-a If MSB equals
1, then a<b 0, then a>=b
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
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0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection Overflow
a.
b.
subtraction output available
Connect MSB set output
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Seta31
0
ALU0 Result0
CarryIn
a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Binvert
CarryIn
Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
LSB indicates whether a<b
0 if false 1 if true
How to detect zero?
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Conclusions We can build an ALU to support the MIPS
instruction set key idea: use multiplexor to select the output we want we can efficiently perform subtraction using two’s complement we can replicate a 1-bit ALU to produce a 32-bit ALU
Important points about hardware all of the gates are always working the speed of a gate is affected by the number of inputs to the
gate the speed of a circuit is affected by the number of gates in
series(on the “critical path” or the “deepest level of logic”)
We focused on basic principles. We noted that clever changes to organization can improve performance
(similar to using better algorithms in software) faster addition, next time: faster multiplication