Architecture of Sha.sa-1 Microprocessor
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Transcript of Architecture of Sha.sa-1 Microprocessor
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ArchitArchitecture of our Microprocessor
Sha.SaSha.Sa--11
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MAIN UNITSThe microprocessor consists of:
Timing & Control unit : control microprocessoroperations.
ALU : performs data processing function. Re gist e rs : provide storage internal to CPU. I nt e rrupts : to handle another service temporarily I nt e rnal data bus : main data path Acc umulator : to store intermediate results F lag : indicates the result of previous operation IO c ontroll e r : controls input/output
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BUS STRUCTURE
uP
MEMORY INPUT
OUTPUT
Address Bus
Data Bus
Control Bus
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CP U Architecture
CIS C (Complex I nstruction S et Computer)
- traditional architecture of a computer- uses microcode to execute very comprehensive instruction set- variable in length and use all addressing modes (complex decoding circuit )
R IS C (R educed I nstruction S et Computer)- constant size- ban indir e c t addressing- very fast execution due to simple instruction- fewer transistors ; cheaper to design
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Instruction SetI nstru c tion
- b inary pattern designed inside a microprocessor to
perform a specific function.I nstru c tion s e t
- group of instructions
Instructions can be divided into 5 functional categoriesi. arithmeticii. logical iii. Data transferiv. Conditional b ranch
v. Unconditional b
ranch
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Instruction Seti. A rithm e ti c
- addition, su b traction, increment or decrement
ii. L ogi c al- AN D, OR, Exclusive OR, Rotate, Shift, Compare, and Complement
iii. Data transf e r- Load, store word
iv. Conditional Bran c h- branch on equal, branch on not equal
v. U n c onditional Bran c h- jump, jump register
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Instruction Format
Each instruction has two parts:
i. opcode - task to be performedii. operand - data to be operated on
Instruction execution cycleInstruction Fetch Instruction Decode Operand Fetch
ExecuteStoreNext instruction
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Instruction Format
Eg:
opcode
source operandsdest. operands
a = b + c
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Addressing modes
Addressing modes define the ways- to ge t the data for the op e rands- put the data into the d e stination
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Addressing modes A ddr e ssingMod e
Sy ntax M e aning
Immediate #K K Direct K M[K]
I ndir e c t (K) M[ M[K] ]
Register (Rn) M[Rn]
Register Indexed (Rm + Rn) M[Rm + Rn]
Register Based (Rm + X) M[Rm + X]
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EndiannessMulti-byte words are stored in memory locationas a sequence of bytes2 - waysi. big - end ian
- MSB at lower byte
ii. l itt le - end ian- LSB at lower byte
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Endiannessbig end ian a
MSB LSB a + 4
L itt le end ian a
MSB LSBa + 4
AA BB CC DD EE
BB
CCDD
AA
EE
AA BB CC DD EE DDCCBB
EE
AA