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Homework 3

CAP 208

INTRODUCTION TO COMPUTER ORGANISATION AND

ARCHITECTURE

SUBMITTED TO-

Anjlee Mam

SUBMITTED BY-

SACHIN RAJ

B34

D3901

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Part-A

Q1. Explain the basic computer instruction format. Also tell how is

I bit useful in determining the type of instruction?

Ans-

There are three types of Instruction Format

A type of instruction usually requiring two machine cycles, one to fetch

the instruction, the other to fetch the data at an address (part of the

instruction itself) and to execute the instruction.

Memory reference instruction :Uses 12bits to specify an address & 1

bit to specify addressing mode (direct or indirect).

Basically ,we have to refer the instruction in particular location of

memeory.

Symbol op decoder symbolic description

AND D0 AC AC M[AR]

ADD D1 AC AC + M[AR], E Cout

LDA D2 AC M[AR]

STA D3 M[AR] AC

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BUN D4 PC AR

BSA D5 M[AR] PC, PC AR + 1

ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1

Register refrence instruction.

Here It for Register and we have to refer the instruction to register

that is register refrence instruction.

Register reference ins. Is recognized by opcode 111 with a 0 in the

leftmost bit.

r: SC 0

CLA rB11: AC 0

CLE rB10: E 0

CMA rB9: AC AC

CME rB8: E E

CIR rB7: AC shr AC, AC(15) E, E AC(0)

CIL rB6: AC shl AC, AC(0) E, E AC(15)

INC rB5: AC AC + 1

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I/o Instructions

if we are taking instruction from input device and sending instruction

to output device that is I/o Instructions.

p: SC 0 Clear SC

INP pB11: AC(0-7) INPR, FGI 0 Input char. to AC

OUT pB10: OUTR AC(0-7), FGO 0 Output char. from AC

SKI pB9: if(FGI = 1) then (PC PC + 1) Skip on input flag

SKO pB8: if(FGO = 1) then (PC PC + 1) Skip on output flag

ION pB7: IEN 1 Interrupt enable on

IOF pB6: IEN 0 Interrupt enable off

If I will be 0 then this is register-reference instruction and if

I=1(InDirect Mode) then this is I/o instructions.

Register Reference Instructions are identified when-D7 = 1,

I = 0

I/o Instructions are identified when-D7 = 1, I = 1

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Q2.Show with the help of flow chart, different types of memory

reference instructions.

Ans-

AND TO AC

This instruction performs the AND logic operation on pairs of bits in

AC and the memory word specified by the effective address. The

result of the operation is transferred to Accumulator. The

microoperations that execute this instruction are:

D0T4: DRM[AR]

D0T5: AC

AC DR, SC

0.

ADD TO AC

The content of the memory word specified by the effective address is

added to the value of AC with the help of this instruction. The sum is

transferred into accumulator and the output carry Cout is transferred

to the E (extended accumlator) flip-flop. The microoperations needs to

execute this instruction are:

D1T4: DRM[AR]D1T5: ACAC + DR, E Cout, SC0

LOAD TO AC

This instruction is used to transfers the memory word specified by the

effective address to accumulator.

Following microoperations are needed to execute this instruction:

D2T4: DR

M[AR]D2T5: ACDR, SC0.

STORE AC

This Instruction is used to store the content of accumulator into the

memory word specified by the effective

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address. Since the output of AC is applied to the bus and the data

input of memory is connected to the bus,

we can execute this instruction with one microoperation:

D3T4: M[AR]AC, SC 0

INCREMENT AND SKIP IF ZERO

D6T4: DRMR[AR]

D6T5: DR DR + 1

D6T6: M[AR]DR, if (DR = 0) then (PC PC +1), SC 0

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Q3. Show diagrammatically, how data would be transferred from DR

to OUTR and from Memory to IR through common bus?

Ans-

DR TO OUTR-

First of all I have to select 011 (DR) from select line then data will be

travel in common bus then we have to enable the load pin of OUTR

,the data will be automatically transfer to OUTR.

Memory To IR-

Take data from memory unit (enable read pin of memory ) and send

data to common bus now we have to select (101) from select line and

enable load pin of IR, the data will be automatically transfer to IR.

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Part-B

Q4.Explain stack organisation. And the complete design of basic

computer

Ans-Two types of stack organization:

1.Register STACK ORGANIZATION

Stack-

It is storage media and we can store value in it. It perform LIFO

operation.

In stack We Perform Two operations-

Push-

SP

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always 0.now I have to insert data in first location then it will be like

that : 000000

+1

____________________

000001(First Location)

If we want to apply push operation then it will be increment again

: 000001

+1

____________________

000010(2nd Location)

After Continuing this process Sp will go to 63 location.

Pop Operation-

DR

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Push-

SP SP 1

M[SP] DR

If we want to insert data then we have to Decrement the stack

pointer.

It will be location from(40001)

Pop-

DR M[SP]

SP SP + 1

If we want to perfor pop operation then we have to increment the

data from(3997).

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Q5.Show how the zero insertion works in the bit-oriented protocol

when a zero followed by the 10 bits that represent the binary

equivalent of 1023 are transmitted.

Ans-

Information to be sent (1023):

1023-01111111111(Binary Form)

After zero insertion, information transmitted: 0111110111110

Information received after Os deletion: 01111111111

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Q6. What are the microinstructions needed for fetch routine?

Write a symbolic micro program for the fetch routine.

Ans-

The control memory has 128 words, and each word contains 20 bits.

To micro-program the control memory, it is necessary to determine the

bit values of each of the 128 words. The first 64 words (addresses 0-

63) are to be occupied by the routines for the 16 instructions. The last

64 words may be used for any other purpose. A convenient starting

location for the fetch routine is address 64. The microinstructions

needed for the fetch routine are as follows:--

1)

ARPCDRM[AR], PCPC+1ARDR(0-10),CAR(2-5)DR(11-14),CAR(0,1,6)0The address of the instruction is transferred from PC to AR and the

instruction is then read from memory into DR. Since no instruction

register is available, the instruction codes remains in the DR. The

address part is transferred to AR and then control is transferred to

one of 16 routines by mapping the operation code part of the

instruction from DR into CAR.

2)

The fetch routine needs three microinstructions, which are placed in

control memory in addresses 64,65 and 66.Using the assembly language

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conventions defined previously, we can write the symbolic micro-

program for the fetch routine as follows:--

ORG 64

FETCH: PCTAR U JMP NEXT

READ,INCPC U JMP NEXT

DRTAR U MAP

3)

Binary Address F1 F2 F3 CD BR AD

1000000 110 000 000 00 00 1000001

1000001 000 100 101 00 00 1000010

1000010 101 000 000 00 11 0000000

The microinstructions that constitute the fetch routine have been

listed in three different representations as illustrated above.