Application Study of EAPR based Partial Dynamic Reconfiguration
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Application Study of EAPR based Partial Dynamic Reconfiguration
RCG Presentation (12/07/2007)
Ramachandra Kallam
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OUTLINE
Introduction Background Partial Dynamic Reconfiguration Iterative Repair Processor Results and Observations Conclusions Publications References
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Introduction: Partial Reconfiguration
Partial Reconfiguration: Static Partial Reconfiguration: Reconfiguring a
portion of the device (changing the functionality) when the device is inactive without affecting other areas of the device
Dynamic Partial Reconfiguration (PDR): Reconfiguring a portion of the device while the remaining design is still active and operating without affecting the remaining portion of the device.
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Intuitive Benefits of using PDR
Saves space on the FPGA Less time to change only a part of design Reduction of power dissipation by storing
functionality to external memory Smaller FPGAs can be used to run an
application
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Applicability of PDR
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NASA’s missions
Space missions cannot rely on constant and reliable communication between earth and spacecraft
On-board Processing FPGAs
Low Cost compared to ASICs Reconfigurable
Spacecraft event scheduling Iterative Repair and Simulated Annealing Iterative Repair Processor
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Iterative Repair and Simulated Annealing
Initial solution modified over several iterations
Greedy Algorithm – may not yield optimal schedule (solution) Altering the solution randomly Evaluating the solution in a particular way
Perfect solution? Different Solutions
The way the initial solution is altered The way the solution is evaluated
Different alter and evaluate stages
Simulated Annealing
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Spacecraft Event Scheduling A set of 100 events Need to find the best
solution.
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Different ‘Alter’ functions
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Impact of ‘alter’ functions
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Alternate ‘Evaluate’ functions
Suppose a problem has three different tasks We can assign different weights to different
tasks depending on the degree of importance of each task
Can we store different ‘alter’ and ‘evaluate’ functions on the FPGA?
Area constraints on the FPGA
Solution?
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PDR based on-board event scheduling
IRP 1Short-termscheduling
IRP 2Mid-term
scheduling
IRP 3Long-termscheduling
MicroBlaze - 1
MicroBlaze - 2
MicroBlaze - 3
FPGA
Bit Streams
External memory
evaluate - 1
alter - 1
evaluate - 1 evaluate - 1
alter - 1
evaluate - 1
alter - 1
evaluate - 2
alter - 2
alter - 1
alter - 2
evaluate - 2
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Lets review the definitions again:
Partial Reconfiguration: Static Partial Reconfiguration: Reconfiguring a
portion of the device (changing the functionality) when the device is inactive without affecting other areas of the device
Dynamic Partial Reconfiguration (PDR): Reconfiguring a portion of the device while the remaining design is still active and operating without affecting the remaining portion of the device.
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BACKGROUNDMethod of Partial Reconfiguration
Internal Configuration Access Port (ICAP)
Bus Macros
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Partial Reconfiguration
Partial Reconfiguration is useful for systems with multiple functions that can time-share the same FPGA resources.
TERMINOLOGY Reconfigurable Region (PRR) Reconfigurable Module (PRM) Static Logic Bus Macro Partial Bitstream Merged Bitstream
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Literature "Run-time dynamic reconfiguration: a reality check based on
FPGA architectures from Xilinx", Wu, K.; Madsen, J., NORCHIP Conference, 2005. 23rd, Vol., Iss., 21-22 Nov. 2005 Pages: 192- 195
"Study on column wise design compaction for reconfigurable systems", Kalte, H.; Lee, G.; Porrmann, M.; Ruckert, U., Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, Vol., Iss., 6-8 Dec. 2004 Pages: 413- 416
"Modular partial reconfigurable in Virtex FPGAs", Sedcole, P.; Blodget, B.; Anderson, J.; Lysaghi, P.; Becker, T., Field Programmable Logic and Applications, 2005. International Conference on, Vol., Iss., 24-26 Aug. 2005 Pages: 211- 216
"A Decade of Reconfigurable Computing: a Visionary Retrospective", Hartenstein, R., Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
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Literature "Application-driven Research in Partial
Reconfiguration", Juanjo Noguera, Robert Esser, Xilinx Research Labs
“Two Flows for Partial Reconfiguration: Module Based or Difference Based”, Xilinx Research Labs
"A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration", Claus, C.; Muller, F.H.; Zeppenfeld, J.; Stechele, W., Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
"A lightweight approach for embedded reconfiguration of FPGAs", Blodget, B.; McMillan, S.; Lysaght, P., Design, Automation and Test in Europe Conference and Exhibition, 2003
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Partial Reconfiguration Methods
Module-based Partial Reconfiguration Systematic design of larger systems Modular Design Methodology Communication between modules is done
through tri-state buffers Care should be taken that tri-state buffers are
not being reconfigured High storage cost Long reconfiguration Latency Area-constrained placement and routing
process. No hardware support to guarantee successful P&R
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Partial Reconfiguration Methods
Difference-based Partial Reconfiguration Suitable for very small designs Compares the circuit description of two designs,
note the different frames between the two designs and creates a partial bitstream that only modifies the frames that are different
The reconfiguration time and storage cost are proportional to number of frames that are different
Very inefficient for large designs Both the designs have to be same at the layout
level
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Partial Reconfiguration Methods
Early Access Partial Reconfiguration (EAPR) Similar to Modular-design methodology Allows Partial Reconfigurable regions of any
rectangular size Allows signals in the base design to pass through
PR regionPlacer will not locate any logic elements in PRR
Router can route static nets through PRR Communication between static and partially
reconfigurable region is done using slice-based (or LUT-based) bus macros
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Medium for Partial Reconfiguration
External – JTAG, UART (RS232) Internal – ICAP
ICAP (Internal Configuration Access Port) Self-Reconfiguration controlled by soft-processor
o Internal read and write access to configuration logic
Faster hwicap (provided by Xilinx)
o Wraps the ICAP with additional logic to read and write frames to BRAM
o Slave to OPB (On-chip Peripheral Bus)
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ICAP - Flow
Bitstream Flow Factors effecting Reconfiguration Time
Bitstream length Bitstream transfer
Ways to Improve Reduce the bitstream
size (combitgen) Optimize the way the
bitstreams are transferred
SystemACE
BRAM (Microblaze)
ICAP Memory
ConfigurationMemory
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Bus Macros Bus Macros: Means of communication between PRMs
and static design All connections between PRMs and static design must
pass through a bus macro with the exception of a clock signal
Type of Bus Macros Tri-state buffer (TBUF) based bus macros Slice-based (or LUT-based) bus macros
Advantage of slice-based bus macros No signals lines should cross the border in partial
reconfiguration TBUFs – will ignore the boundaries Slice-based – signals not crossing boundaries
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Bus Macros All Bus Macros provide eight bits of data bandwidth
and enable/disable control Provided with EAPR software tools as pre-placed and
pre-routed with .nmc extension Expanded during NGDBuild Placement of Bus Macros
Placed such that the bus macrosare placed half on the static side and half in the PR Region Placed such that they do not straddle a DSP or BRAM column
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Literature "An FPGA-Based Dynamically Reconfigurable Platform:
From Concept to Realization", Mateusz Majer, Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, Vol., Iss., Aug. 2006 Pages:1-2
Communicating with other modules is difficult as there may be routing through partial reconfigurable regions
Proposed a new architecture for partial reconfiguration
With the introduction of EAPR, it is possible to send static nets through partial reconfigurable regions
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Literature "Modular partial reconfigurable in Virtex FPGAs",
Sedcole, P.; Blodget, B.; Anderson, J.; Lysaghi, P.; Becker, T., Field Programmable Logic and Applications, 2005. International Conference on, Vol., Iss., 24-26 Aug. 2005 Pages: 211- 216
Apart from partial reconfiguration methods, this paper gives a analytical method to calculate reconfiguration time
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Literature "Dynamic and Partial FPGA Exploitation", Jrgen
Becker; Michael Hubner; Gerhard Hettich; Rainer Constapel; Joachim Eisenmann; Jrgen Luka, Proceedings of the IEEE, Vol.95, Iss.2, Feb. 2007 Pages:438-452
Motivation: electronics in automobiles are increasing with time.
A Reconfigurable system for automotive industry to reduce the high number of control systems necessary for all the functions is presented
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Literature "Dynamic loading of peripherals on reconfigurable
system-on-chip", Yi Lu; Bergmann, N., Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on, Vol., Iss., 11-14 Dec. 2005 Pages: 279- 280
Auto peripheral detection using partial dynamic self reconfiguration
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Invoking Partial Dynamic Reconfiguration throughXilinx Early Access Partial Reconfiguration methodology
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Early Access Partial Reconfiguration (EAPR) – Design Flow
New Design flow by Xilinx in which slice based bus macros are used
EAPR Design Flow HDL (Design Description) EDK (System level design) PlanAhead (Floor plan)
o Constraints (area, timing etc)o Design Rule Check (DRC)o Implement Static Designo Implement PR Moduleso Create Bitstreams
Programming the FPGA
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Design Description
HDL (Design Description) Have to decide which part of the design is to be
implemented in static design Decide on number of PR regions Which functionality to implement (PRMs) in each
PRR VHDL or Verilog Synthesis
o Keep Hierarchyo Disable ‘Add I/O Buffers’o Set Global Clocks to ‘0’(Figure of drc error)
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Design Description
Partial Reconfiguration Modules (PRMs)o Pin Compatibleo Same port names
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EDK (System Level Design)
EDK (System Level Design) Create Peripherals
Entity names should match System Architecture
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EDK (System Level Design)
Create software to run in Microblaze Create Netlist for the entire design Compile the software
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PlanAhead (Floor Planning)
PlanAhead (Floor Planning) Import system netlist
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PlanAhead (Floor Planning)
Set Constraints (area, location, timing)
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PlanAhead (Floor Planning)
Virtex-4 SX35 device with static and partial reconfigurable region
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PlanAhead (Floor Planning)
Set the Partial Reconfigurable Region (PRR) Add PRMs to the PRR
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PlanAhead (Floor Planning)
Design Rule Check (DRC)
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PlanAhead (Floor Planning)
ExploreAhead Static Runs PR Runs
PRAssemble To create full and partial bitstreams
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PAR of Full Design and PR Region
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PlanAhead
Some Disadvantages of PlanAhead Module has to be top level to set it as a
reconfigurable region Cannot have gaps when specifying boundaries
for a partial region
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Programming the FPGA
Programming the FPGA Export full bitstream to EDK Create SystemACE file Program the FPGA
(file names should be small)
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Test Application:ITERATIVE REPAIR PROCESSOR
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Iterative Repair Processor Simulated Annealing
consists of calling the same 5 functions repeatedly
This structure has been exploited through use of a pipelined processor
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System Architecture
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Socket Bridge
Communication between OPB and PRR using slice-based Bus Macros
Capable of isolating PRR while Reconfiguration
Courtesy: Xilinx
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PR of Iterative Repair Processor
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Event Scheduling
Short-term Mid-term Lon-term
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Basic idea of setting up the system
IRP 1Short-termscheduling
IRP 2Mid-term
scheduling
IRP 3Long-termscheduling
MicroBlaze - 1
MicroBlaze - 2
MicroBlaze - 3
FPGA
Bit Streams
External memory
evaluate - 1
alter - 1
evaluate - 1 evaluate - 1
alter - 1
evaluate - 1
alter - 1
evaluate - 2
alter - 2
alter - 1
alter - 2
evaluate - 2
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RESULTS & OBSERVATIONS
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Results and Observations
Partial Reconfiguration Observations Time for partial reconfiguration
IR Processor Setup for Partial Reconfiguration Tested PR by reconfiguring with itself Ready for thermal capturing
Partial Reconfiguration Tutorial
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Partial Reconfiguration Latecny
Design slicesBRAM,
DSP file size (in kb)no. of.
Bitsclk
cyclestime(in
sec) frames
Bessel_1 2289 1,16 260 2129632 68105716 0.68 2387
Bessel_2 2241 1,16 261 2137408 68528740 0.68 2387
Periotti 2930 1,24 332 2716960 82175782 0.82 3095
Reiss 2949 1,20 332 2717256 82176825 0.82 3095
ellintr_d 2072 1,16 406 3323336 99130369 0.99 3869
ellintr_g 3869 1,28 406 3323336 99130369 0.99 3869
multiplier 0 0,1 245 2001379 64080682 0.634 2258
affine 55 0,6 138 1128272 38889520 0.38 1247
perspective 725 0,9 139 1137432 38034143 0.38 1247
bessel_1_new 2289 1,16 260 2121760 67922458 0.67 2387
bessel_2_new 2241 1,16 259 2115744 67742436 0.67 2387
overhead = 51 clock cycles
approx 2.5ms to reconfigure 1kb of bits
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Designs – ellintr_g and ellintr_d
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Designs – ellintr_g and multiplier
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Experimental vs. Analytical
Design frames time (in sec) time (in sec) using formula
Bessel_1 2387 0.68 0.65
Bessel_2 2387 0.68 0.65
Periotti 3095 0.82 0.84
Reiss 3095 0.82 0.84
ellintr_d 2321 0.99 1.06
ellintr_g 3869 0.99 1.06
mult 3869 0.63 1.06
affine 1247 0.38 0.34
perspective 1247 0.38 0.34
bessel_1_new 2387 0.67 0.65
bessel_2_new 2387 0.67 0.65
ellintr_d(with ellin_g) 3869 1 1.06
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IR Processor
Time to Reconfigure the whole IR Processor: It takes 0.55 sec to reconfigure the whole
processor If we reconfigure only two of the five stages
in the Iterative Repair processor, the reconfiguration time will reduce significantly
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CONCLUSIONS
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Conclusions Current Status
Ready to partial reconfigure the entire IR Processor
Ready to test the IR Processor with thermal camera
Need to set up IR Processor to reconfigure just two stages instead of the whole IR Processor
Proposing a method to improve event scheduling in deep space missions using PDR
Thesis defense in August?
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PUBLICATIONS
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Publications
Journal Articles under review IET Transactions on Computers and Digital
Techniques Phillips, J., Sudarsanam, A., Kallam, R., Carver, J., and
Dasu, A., “Methodology to Derive Polymorphic Soft-IP Cores for FPGAs”
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REFERENCES
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References "An FPGA-Based Dynamically Reconfigurable Platform: From Concept
to Realization", Mateusz Majer, Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, Vol., Iss., Aug. 2006 Pages:1-2
"Run-time dynamic reconfiguration: a reality check based on FPGA architectures from Xilinx", Wu, K.; Madsen, J., NORCHIP Conference, 2005. 23rd, Vol., Iss., 21-22 Nov. 2005 Pages: 192- 195.
"Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation", Berthelot, F.; Nouvel, F., Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, Vol.00, Iss., 2-3 March 2006 Pages: 2 pp.
"Dynamic loading of peripherals on reconfigurable system-on-chip", Yi Lu; Bergmann, N., Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on, Vol., Iss., 11-14 Dec. 2005 Pages: 279- 280
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References "Dynamic and Partial FPGA Exploitation", Jrgen Becker; Michael
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References "Fast IP-Core Generation in a Partial Dynamic Reconfiguration
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