APPle imac 27 #039 A1312 K23 051-7863-A cpu test & misc. 11 09/02/2009 k22 11 cpu power, gnd, decaps...

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DRAWING

DRAWING


3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

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NOTICE OF PROPRIETARY PROPERTY:

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12APPDCK

DESCRIPTION OF REVISION





















































































K23

1 OF 110

0000774489A

051-7863

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1 OF 110

PRODUCTION RELEASED 2009-08-20

LAST_MODIFIED=Wed Sep 2 16:45:56 2009

LAST_MODIFIED=Wed Sep 2 16:45:56 2009

4655

K22

09/02/2009

Thermal Sensors

SyncDate

Page(.csa)

Contents(.csa) Date

Contents SyncPage

ABBREV=DRAWING

TITLE=K22

Table of Contents11 N/A

MASTER

SCH,K23,MLB

4756

K22

09/02/2009

HD AND OD FAN

4857

K22

09/02/2009

CPU FAN

4961

K22

09/02/2009

SPI ROM

5062

K22

09/02/2009

AUDIO: CODEC/REGULATOR

5163

SKIPAUDIO

04/20/2009

AUDIO: FILTER/BUFFER

5264

SKIPAUDIO

04/20/2009

AUDIO: Tweeter Amp 1

5365

SKIPAUDIO

04/20/2009

AUDIO: Woofer Amp

5466

K22

09/02/2009

Audio: MLB to I/O Conn.

5567

SKIPAUDIO

04/20/2009

AUDIO: Detects/Grounding

5668

K22

09/02/2009

AUDIO: Mikey

5769

K22

09/02/2009

POWER SEQUENCING BLOCK DIAGRAM

5870

K22

09/02/2009

PGOOD and Power Sequencing

5971

K22

09/02/2009

VREG: PPVCORE_S0_CPU

6072

K22

09/02/2009

VREG: PPVCORE_S0_CPU

6173

K22

09/02/2009

5V_S3 REGULATOR

6274

K22

09/02/2009

MCP CORE REGULATOR

6375

K22

09/02/2009

1.5V DDR SUPPLY

6476

K22

09/02/2009

FSB VTT/3.3V S5 SUPPLIES

6578

K22

09/02/2009

S3 & S0 FETs

6679

K22

09/02/2009

1V1 S5 POWER SUPPLY

6784

K22

09/02/2009

MXM PCIe, DP & Power

6885

K22

09/02/2009

MXM I/O

6986

K22

09/02/2009

MXM PCIE CAPS

7087

MARKVIDEO

03/12/2009

Display: Aliases

7190

MARKVIDEO

03/12/2009

Display: Int DP Connector

7291

MARKVIDEO

03/12/2009

Display: BiDiVi Mux1

7392

MASTER

N/A

BIDIVI DP MUX2

7494

MARKVIDEO

03/12/2009

Display: Ext DP Connector

7595

MARKVIDEO

03/12/2009

Display: BiDiVi Support

76100

K22

09/02/2009

CPU/FSB Constraints

77101

K22

09/02/2009

Memory Constraints

78102

K22

09/02/2009

MCP Constraints 1

79103

K22

09/02/2009

MCP Constraints 2

80104

K22

09/02/2009

Ethernet Constraints

81105

K22

09/02/2009

FireWire Constraints

82106

K22

09/02/2009

SMC Constraints

83107

MASTER

N/A

Graphics Constraints

84108

K22

09/02/2009

K22/K23 SPECIFIC CONSTRAINTS

85109

K22

09/02/2009

K22/K23 RULE DEFINITIONS

86110

K22

09/02/2009

K22/K23 ICT/FCT

System Block Diagram22 09/02/2009

K22

Power Block Diagram33 09/02/2009

K22

BOM Configuration44 N/A

MASTER

Power Conn / Alias56 N/A

MASTER

Holes67 N/A

MASTER

UNUSED SIGNAL ALIAS78 09/02/2009

K22

Signal Aliases89 N/A

MASTER

CPU FSB910 09/02/2009

K22

CPU TEST & MISC.1011 09/02/2009

K22

CPU POWER, GND, DECAPS1112 09/02/2009

K22

eXtended Debug Port (XDP)1213 09/02/2009

K22

MCP CPU Interface1314 09/02/2009

K22

MCP Memory Interface1415 09/02/2009

K22

MCP MEMORY CNTRL & MISC1516 09/02/2009

K22

MCP PCIe Interfaces1617 09/02/2009

K22

MCP Ethernet & Graphics1718 09/02/2009

K22

MCP PCI & LPC1819 09/02/2009

K22

MCP SATA & USB1920 09/02/2009

K22

MCP HDA & MISC2021 09/02/2009

K22

MCP Power & Ground2122 09/02/2009

K22

MCP Standard Decoupling2225 09/02/2009

K22

MCP Graphics Support2326 09/02/2009

K22

SB Misc2428 09/02/2009

K22

FSB/DDR3 Vref Margining2529 09/02/2009

K22

MEMORY CAPS2630 N/A

MASTER

DDR3 SO-DIMMs 0 & 22731 07/06/2009

K22

DDR3 SO-DIMM CONNECTOR B2832 09/02/2009

K22

DDR3 SUPPORT AND BITSWAPS2933 N/A

MASTER

PCI-E Wireless Connector3034 05/28/2009

K22

Ethernet PHY (RTL8211CL)3137 09/02/2009

K22

Ethernet Support3238 09/02/2009

K22

ETHERNET CONNECTOR3339 N/A

MASTER

FireWire LLC/PHY (XIO2213B)3441 09/02/2009

K22

FW: 1394B MISC3542 09/02/2009

K22

FIREWIRE CONNECTOR3643 09/02/2009

K22

SATA Connectors3745 09/02/2009

K22

EXTERNAL USB CONNECTORS3846 09/02/2009

K22

Internal USB Connections3947 09/02/2009

K22

SMC4049 03/12/2009

MARKVIDEO

SMC Support4150 03/12/2009

MARKVIDEO

LPC+SPI Debug Connector4251 09/02/2009

K22

SMBus Connections4352 N/A

MASTER

CPU/MXM CURRENT AND VOLTAGE SENSE4453 09/02/2009

K22

MCP CURRENT AND VOLTAGE SENSE4554 09/02/2009

K22

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INTERNAL

J9410

PORT

CONN

FW643

MXM CONNECTOR

64-Bit

XDP CONNPG 10

MEMORY

PG 15

LPC+SPI CONN

PG 56,57

PG 51

PG 53

PG 55

U4900

J3100, J3200

PG 31,32

PG 61

PG 49

J4780

PG 47

PG 20

27

11

J4720

PG 21

SATA-A0

LVDS OUT

U3900

PG 39

PG 37

PG 17

Mini PCI-E

ConnAirPort

J3400

U4100

PG 43

PG 41

GPIOs

PG 34

PG 18

DP OUT

DVI OUT

RGB OUT

TMDS OUT

J8400

HDMI OUT

65

84

13

CLK

PG 13

SYNTH

J5100Ser

Prt

ADC

SMCBSBB,0

SPI

U1000

U1300

PG 13

PG 20

SATA-A1

E-NET

MAGNETICS

ConnFireWire

J4300

CPU DIE

CPU HEATSINKMXM - GPU DIE

TEMP SENSORS

J5600, J5601, J5700

PG 19

Boot ROM

PG 21

Port80,serial

PG 21

Bluetooth

PWR

U1400

CTRL

PG 84

PG 45

J4510

HD

SATA1.05V/3GHZ.

1.05V/3GHZ.

Conn

SATA

ODD

ConnPG 45

J4520

PG 94DISPLAY

J9002

PG 90

DISP

INTEL CPU

LCD TEMP

LPC

DDR3-1067MHZ

MAIN

3.X GHZ

LGA775 - WOLFDALEPG 10-12

4 SO-DIMMs

MCP7A

PG 47

IR

J4700

PG 47

CAMERA

PG 47

J47xx

WHICH PORT?

EXTERNALJ4610,4620,4630,4640

ConnectorsUSB

PG 47

SD CARD

SPIU6100

Misc

PG 24

USB

(UP TO 12 DEVICES)

910

Fan

MCP DIE

AMBIENT INTAKE

HARD DRIVEOPTICAL DRIVE

MCP HEATSINK

FAN CONN AND CONTROL

POWER SENSE

FSB INTERFACE

GPU HEATSINK

TEMP, CURRENT SENSE

POWER SUPPLY

1333 MHZ

FSB

DIMM

NVIDIA

SATA

UP TO 20 LANES3

X16 PCI-E

T3900

PG 39

Conns

Audio

U3700Audio

U6201

Mikey

U6806

Codec

PG 19

PCI

0

RGMII

PCI-E

SMBMIKEY

HDA(UP TO FOUR PORTS)

DIMM’s

PG 18

E-NET

Speaker

Amps

U6400, U6500

GB

RTL8211CLGR

Line InInt/Ext MicsHeadphones

J6600,J6601,J6602,J6603

051-7863

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

System Block DiagramSYNC_MASTER=K22 SYNC_DATE=09/02/2009

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PAGE 6

MXM20" INVERTER

CPU_CORE

PAGE 76

PPVTT_S0_FSB

PM_SLP_S3

CPU_AVDD

DDR3 MAIN MEMORYPPVCORE_CPU

PAGE 71-72

PAGE 74

MCP, CPU FSB (VTT)

MCP_PLLCPU_VCCP

PP1V8_S0_REG

MCP

PP1V1_S5

SMBUS

PAGE 78

PPDDR_S3_REGPP5V_S3_REG CAMERA

MEM_VTT

AP PCIE

AUDIO

20" PANEL24" PANEL

FANS

MCP_ENET

FW

AP

ETHERNET

PAGE 78

USB

PP12V_S0

MCP

PAGE 76

BT

HDD

20" PANEL

PP12V_S5

CLOCK

PAGE 38

PP1V2_S3

PAGE 75

PP1V5_S0

PP0V75_S0

ENET

PAGE 75

PM_SLP_S3_OD

12V_S5

MAIN MEMORY

MCP79 MEM

TEMP SENSOR

CONTROL

PP12V_S0_INV

PP12V_S0_HDD

HARD DRIVE

PAGE 79

PP5V_S0

IR

BOOT ROM

AC/DC POWER SUPPLY

PAGE 76

MCP_CORE

DCM/FCM

PAGE 80OPTICAL

MCP_VDD_AUXC

MXM

PAGE 74

P5VS0_EN

FIREWIRE PORTS

AUDIO

PPMCPCORE_S0_REG

MXM

FW

PP3V3_S3

P3V3S3_EN

P3V3S0_EN

PP3V3_S0

PAGE 78

AUDIO

PAGE 42

PP1V_S5

SMCPP3V3_S5_REG

3 OF 110

051-7863

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Power Block DiagramSYNC_MASTER=K22 SYNC_DATE=09/02/2009

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM




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TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM


PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants

CPUS

BOM GROUPS

COMMON

MCP -J SKU HAS INTEGRATED GPU

GROUND7654

BOTTOM

SIGNAL

POWER

GROUND23

TOP SIGNAL

POWER

SIGNAL

SIGNAL

MCP -D SKU DOES NOT

ALTERNATES

K23 PARTS

BOARD STACK-UP

(338S0489 - BLNK)

4 OF 110

051-7863

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K23,3P06GHZ_CPU,BASIC,MXM,K23_MXMPCBA,MLB,3.06 GHZ,K23639-0509

PCBA,MLB,DEV,K23607-4427 DEVELOPMENT,DEV_GROUP

630-9880 PCBA,MLB,ULTIMATE,K23 K23,3P33GHZ_CPU,BASIC,MXM,K23_MXM

PCBA,MLB,3.16 GHZ,K23(INVESTIGATION) K23,3P16GHZ_CPU,BASIC,MXM,K23_MXM639-0109

PCBA,MLB,2.93 GHZ,K23 K23,2P93GHZ_CPU,BASIC,MXM,K23_MXM639-0185

630-9983 PCBA,MLB,BEST,K23 K23,3P0GHZ_CPU,BASIC,MXM,K23_MXM

639-0394 K23,2P80GHZ_2M_CPU,BASIC,MXM,K23_MXMPCBA,MLB,2.80 GHZ-2M,K23

PCBA,MLB,BETTER,K23

COMMON,ALTERNATE,MCP7A,XDP,BETTER,MCP_ISL9563A,PRODUCTION

BOOT_MODE_USER,MEMRESET_HW,MEMRESET_MCP

1 IC,EFI BOOTROM,K22/K23

IC,MCP,MCP7A-DA,B03,35X35MM,BGA1437,DT

IC,GMCP,MCP7A-JA,B03,35X35MM,BGA1437,DT CRITICAL

MLB LABEL,48.0X4.8

IC,RTL8251CA,GIGE TRANSCEIVER, 48P TQFP U3700

2P83GHZ_CPU

BOM ConfigurationSYNC_MASTER=MASTER SYNC_DATE=N/A

820-2507 K231 MLB1PCBF,K23,MLB

341T0169 K23U49001 IC,SMC,K23 CRITICAL

630-9879 K23,2P80GHZ_CPU,BASIC,MXM,K23_MXM

CPU1337S3766 3P06GHZ_CPU

CRITICAL1 U4100338S0765 IC,XIO2211ZAY,1394B,167BGA

U1400338S0732 MXMCRITICAL1

051-7863 K231 SCH,K23,MLB SCH1

CPU CRITICAL

WLF,SLB9J,PRQ,3.0G,65W,1333,E0,6M,LGA 3P0GHZ_CPU1 CRITICALCPU

1 CRITICALCPUWLF,SLB9K,PRQ,3.16G,65W,1333,E0,6M,LGA

CPU CRITICAL1 WLF,SLB9J,PRQ,2.83G,65W,1333,E0,6M,LGA

338S0694 1 CRITICAL

U6100 CRITICAL341T0170

U1400 IG338S0731 1

1 CRITICALX14825-7122

CPU CRITICAL

DEV_GROUP XDP_CONN,LPCPLUS,VREFMRGN,MCP_PWR_SENSE,MCP_CPU_TDIODE,PECI_SMB,MOJOMUX

BASIC

MCP7A

3P16GHZ_CPU

3P33GHZ_CPU

2P93GHZ_CPU

CRITICAL

1

337S3727

337S3807

WLF,SLB9L,PRQ,3.33G,65W,1333,E0,6M,LGA1

337S3715

337S3726

337S3742

WLF,SLB9L,PRQ,3.06G,65W,1333,E0,6M,LGA

WLF,SLB9L,PRQ,2.93G,65W,1333,E0,6M,LGA

CRITICALCPU1337S3745 WLF,QXXX,QS,2.80G,65W,1066,R0,3M,LGA 2P80GHZ_CPU

1 CPU CRITICAL337S3804 WLF,SLGU9,PRQ,2.80G,65W,1066,R0,2M,LGA 2P80GHZ_2M_CPU

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SYNC_DATE=12/05/2008SYNC_MASTER=K22

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IN G S

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IN

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ON IN RUN AND SLEEP

SILKSCREEN:4

"S0" RAILS518-0352

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

PLACE AT J600."S5" RAILS

GND RAILS

ONLY ON IN RUN

"S3" RAILSEMC: C600,C626,C627,C628,C629,C630,C631

SILKSCREEN:2

SILKSCREEN:3

SILKSCREEN:1

sourced from buffer on csa 90

6 OF 110

051-7863

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4

5

3

Q602

2

1R603

1

2

6

Q602

9

8

7

6

5

4

3

2

14

13

12

11

10

1

J600

2

1 C631

2

1 C630

2

1 C623

2

1 C600

2

1

3

Q610

2

1 C626

2

1 C624

2

1 C627

2

1

LED602

2

1R602

2

1

LED604

2

1R604

2

1

LED603

2

1

LED605

2

1R600

2

1

LED601

2

1R601

MXM_GOOD

PP3V3_S0

=PP3V3_S0_MCP_PLL_UF

PP3V3_S3

=PPSPD_S0_MEM_B

=PP3V3_S0_VRD

=PP3V3_S0_SMC_LS

=PP3V3_S0_SMBUS_SMC_0_S0

=PP5V_S3_1V8

GPU_PRESENT_DRAIN

VIDEO_ON_L

=PPSPD_S0_MEM_A

GPU_PRESENT_R

ALL_SYS_PWRGD_R=PP3V3_S0_SMBUS_SMC_B_S0

CORE_VOLTAGES_ON

CORE_VOLTAGES_ON_R

=PP3V3_S0_TSENS

=PP3V3_S0_DPCONN

=PP3V3_S0_SMBUS_SMC_MGMT

PP5V_S3_REG

MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

VOLTAGE=5VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

LCD_SHOULD_ON

PP3V3_S0

PP3V3_S0MAKE_BASE=TRUE


NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MAX_NECK_LENGTH=3 MM

=PP3V3_FWRS0_FWXIO

PP1V5_S0

MIN_LINE_WIDTH=0.15MM

MAKE_BASE=TRUE

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.1MM

VOLTAGE=1.5V

=PP3V3_FW_FWPHY

=PP1V5_FWRS0_FWXIO

=PP3V3_S0_DP

=PP5V_S0_LPCPLUS

=PP1V5_S0_AUD_DIG

LCD_PWM

PPVTT_S0_FSB_REG


MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

NET_SPACING_TYPE=PWR

MAKE_BASE=TRUEVOLTAGE=1.2V


=PP0V75_S0_MEM_VTT_A

=PP1V05_S0_MCP_HDMI_VDD_R

=PPVTT_S0_FSB_CPU

=PP3V3_S0_VIDEO

=PP3V3_S0_SMC

=PPVTT_S0_XDP

=PP1V8_S0_PGCMP

=PP0V75_S0_MEM_VTT_B

=PP1V05_S0_MCP_PEX_DVDD

=SMB_ACDC_SCL

=PP5V_S0_SATA

PP12V_S5


NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUEVOLTAGE=12V

=PP12V_S5_REG

=PPVIN_S5_P5VS3

=PPVIN_S5_P3V3S5

=PPVIN_S5_DDRREG

=PP12V_S5_FW

PP5V_S5_LDO


VOLTAGE=5V


MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_VREFMRGN

PP3V3_S3MAKE_BASE=TRUE


VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 mm


LCD_BKL_ON

PP12V_S0

PM_ACDC_PS_ON

PPMCPCORE_S0_REG

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=1.05VMAKE_BASE=TRUE


=PP5V_S3_CAMERA

=PPDDR_S3_PGCMP

PM_SLPS3_BUF2_L

=PP3V3_S5_SMBUS_SMC_BSA

PPVCORE_S0_CPU

VOLTAGE=1.1VMAKE_BASE=TRUE


NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.3MM


=PP3V3_S5_P1V1S5

=PPVIN_S0_MCPCORE

PP12V_S0

NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUEVOLTAGE=12V


=PP12V_S5_PWRCTL

PP3V3_S3

ITS_PLUGGED_IN

=PP3V3_S5_SMCUSBMUX

=PP5V_S5_AVREF

PP3V3_S5_REG

ITS_ALIVE

=PP3V3_S0_MCPTHMSNS

=PP3V3_S5_MEMRESET

=PP3V3_S5_LPCPLUS

=PP3V3_S5_SMC

=PP3V3_S5_RTC_D

=PP3V3_S5_ROM

=PP1V05_S5_MCP_VDD_AUXC

=PP1V1_S5_ENET_FET

PP1V1_S5_REG

MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.1V

=PP5V_S3_S0FET

PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm



PP12V_S5

=SMB_ACDC_SDA

=PPVCORE_S0_MCP

=PP3V3_S5_MCP_GPIO

=PP3V3_S5_MCP

=PPDDR_S3_S0FETNET_SPACING_TYPE=PWR

MAKE_BASE=TRUEPPVTT_S0_DDR_LDO

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm


VOLTAGE=0.75V

=PPVCORE_S0_CPU

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_SATA_DVDD0

=PP3V3_S0_MCP

=PP3V3_S3_MCPREG

=PP3V3_S3_MINI

=PPVTT_S3_DDR_BUF

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_B

=PP3V3_S3_BT

=PP3V3_S3_SMC

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S5_ENET_FET

=PP3V3_S5_S0FET

=PP3V3R1V8_S0_MCP_IFP_VDD_R

=PP3V3_S5_S3FET

=PP3V3_S5_PWRCTL

=PP3V3_S0_MXM

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_AUDIO

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_SMBUS

=PP3V3_S0_XDP

=PP3V3_S0_SATALED

=PPVTT_S0_VTTCLAMP

=PP3V3_S0_FAN

=PP3V3_S0_MCP_GPIO

=PP5V_S0_AUDIO

=PP12V_S0_FAN

=PP12V_S0_AUDIO_SPKRAMP

=PP12V_S0_VRD

=PPV_S0_MXM_PWR

=PPVIN_S0_PPVTT_FSB

=PP12V_S0_LCD

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_VRD

=PP5V_S0_MXM

=PP5V_S0_SATA

=PP5V_S0_PWRCTL

PP5V_S0MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

VOLTAGE=5V

PP3V3_S5_REG

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=3.3VMAKE_BASE=TRUE

=PP5V_S3_USB

=PP5V_S3_VTTCLAMP

=PP5V_S3_PWRCTL

=PP5V_S3_MCPREG

=PP1V5_S0_CPU_VCCPLL

=PP5V_S3_IR

=PP5V_S3_DDRREG

=PP3V3_S3_SDCARD

=PPVTT_S0_CPU

=PP1V05_S0_MCP_FSB

=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S3_MEM_APPDDR_S3_REGMAKE_BASE=TRUE



NET_SPACING_TYPE=PPDDR_MEM

VOLTAGE=1.5V


=PP3V3_S0_PWRCTL

=PP3V3_S0_ODD

PP1V8_S0_REG


MIN_NECK_WIDTH=0.1 MMNET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.4 mmVOLTAGE=1.8VMAKE_BASE=TRUE

=PP5V_S0_ISENSE

NET_SPACING_TYPE=AUDIO

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.1MM

MAX_NECK_LENGTH=4.1 MMMAKE_BASE=TRUE

GND

VOLTAGE=0V

Power Conn / AliasSYNC_DATE=N/ASYNC_MASTER=MASTER

70

GREEN-3.6MCD2.0X1.25MM-SM

402MF-LF

5%1K1/16W

9


402MF-LF

1K1/16W5%

2.0X1.25MM-SMGREEN-3.6MCD

GREEN-3.6MCD

DEVELOPMENT

2.0X1.25MM-SM

DEVELOPMENT

1K5%1/16WMF-LF402

MF-LF1/16W

402

1K5%

2.0X1.25MM-SMGREEN-3.6MCD

SOT-3632N7002DW-X-G

90

402

1K1/16W5%

MF-LF

2N7002DW-X-GSOT-363

CRITICAL

76833-0100M-RT-TH

0.001UF

402

10%

X7R50V

X7R

0.001UF10%50V

402

10UF20%10VX5R805

50VX7R402

10%0.001UF

2N7002SOT23-HF1

0.001UF

402

10%

X7R50V

10UF10%16V

1210X5R-CERM

70 50 49 9

0.001UF

402

50V10%

X7R

6 78

25

110 6 78

32

71

55 50

52

31

52

55

94

52

110 73

6 78

6 78

41

54

43 42 41

41

92 91 90 87 95

51

62

90

76

25

31

26

12 11

90

54 53 50

13

70

32

28 25

52

45 6

6

76

73

76

75

43

76

21

29

110 6 78

90

6 70

54 74

47

70

52

72 71

79

74

6 70

78 70 38

110 6 78

46

50

6 76

55

33

51

50 49

28

61 51

25 22

38

79

78

75

6

52

25 22

20 18

25 22

78

75

12

25

20 28

25 22 21

74

34

29

33

32 30 108

47

50

52

38

78

26

78

70

84 85

26

68 67 66 65 64 62

25 21

52

13

45

78

57 56

21 19 18

68 62

57 56

67

71 70

53

76

90

71

84

45 6

110 78

6 76

46

78

70

74

12

47

75

47

71 55 50 10

25 22 14

30 25 16

31 30 108 75

70

45

53

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36

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REVISION

DRAWING NUMBER SIZE

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Rear Cover

Standoffs (860-1255)

CPU Heatsink

4mm Plated Holes (998-0850)

EMC Springs (870-1125)

DIMM CONNECTOR NUTS

Nuts (805-9582)

Backer Plate

MCP Heatsink

Nuts (835-0269)

7 OF 110

051-7863

A.0.0


1

SDF0719

1

SDF0718

1

SDF0717

1

SDF0715

1

SDF0714

1

NUT0750

1

NUT0751

1

NUT0752

1

NUT0753

1

NUT0703

1

NUT0702

1

NUT0701

1

NUT0700

1SC0700

1SC0701

1

SDF0713

1

ZH07031

ZH07021

ZH07011

ZH0700

SYNC_MASTER=MASTER SYNC_DATE=N/A

Holes

STDOFF-6.8OD15.0H-1.56-TH

CRITICALCRITICAL


CRITICAL


CRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICAL

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICALCRITICAL

NUT-6.5OD1.4H-1.56-3.8-THNUT-6.5OD1.4H-1.56-3.8-TH

CRITICALCRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CLIP-SM1EMI-SPRING

CRITICAL CRITICAL

EMI-SPRINGCLIP-SM1


CRITICAL

4P75R4

OMIT

4P75R4

OMITOMIT

4P75R44P75R4

OMIT

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NC ON UNUSED ALIASES

MCP HAS INTERNAL 15K PULL-DOWNS

UNUSED MEMORY SIGNALS

UNUSED GMUX JTAG FROM MCP

8 OF 110

051-7863

A.0.0


TP_PE4_CLKREQ_LMAKE_BASE=TRUE NO_TEST=TRUENC_PE4_CLKREQ_L

TP_ENET_PWRDWN_L

USB_MINI_NMAKE_BASE=TRUE NO_TEST=TRUENC_USB_MINI_N

TP_USB_10P

TP_USB_10N

MAKE_BASE=TRUE NO_TEST=TRUENC_USB_MINI_PUSB_MINI_P

MAKE_BASE=TRUENC_USB_EXCARD_P

NO_TEST=TRUE

MAKE_BASE=TRUENC_USB_EXCARD_N

NO_TEST=TRUE

USB_EXCARD_P

USB_EXCARD_N

NO_TEST=TRUENC_ENET_INTR_LMAKE_BASE=TRUE

NC_MCP_KBDRSTIN_LNO_TEST=TRUEMAKE_BASE=TRUE

TP_PCIE_PE4_D2RN

NO_TEST=TRUENC_PCIE_EXCARD_D2R_PMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_MCP_PCI_GNT0_L

TP_PCI_AD<8>MAKE_BASE=TRUENC_PCI_AD<8>

NO_TEST=TRUE

TP_PCI_AD<12..10>MAKE_BASE=TRUENC_PCI_AD<12..10>

NO_TEST=TRUE

EXCARD_CLKREQ_L NC_EXCARD_CLKREQ_LMAKE_BASE=TRUE NO_TEST=TRUE

PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_NMAKE_BASE=TRUE NO_TEST=TRUE

PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_PMAKE_BASE=TRUE NO_TEST=TRUE

ODD_PWR_EN_L NC_ODD_PWR_EN_LNO_TEST=TRUEMAKE_BASE=TRUE

NC_USB_10PMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_USB_10N

NO_TEST=TRUE

TP_SB_A20GATE NC_SB_A20GATEMAKE_BASE=TRUE NO_TEST=TRUE

TP_PE4_PRSNT_LMAKE_BASE=TRUENC_PE4_PRSNT_L

NO_TEST=TRUE

PCIE_EXCARD_PRSNT_LNO_TEST=TRUE

NC_PCIE_EXCARD_PRSNT_LMAKE_BASE=TRUE

TP_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6NNO_TEST=TRUEMAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_PE6PTP_PCIE_CLK100M_PE6P



TP_PCI_PAR

TP_PCI_INTZ_L

TP_PCI_INTW_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_FRAME_L

TP_PCI_CLK1

TP_PCI_CLK0

TP_PCI_C_BE_L<3>

PCIE_EXCARD_D2R_N

TP_PCIE_PE4_R2D_CN

NC_PCIE_PE4_R2D_CPNO_TEST=TRUEMAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUENC_USB_TPAD_P

NO_TEST=TRUE

TP_PCIE_PE4_D2RP

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_PE4_D2RN

NC_PCIE_PE4_D2RPNO_TEST=TRUEMAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

NO_TEST=TRUENC_MEM_A_CLK2PMAKE_BASE=TRUE

GMUX_JTAG_TMS

MAKE_BASE=TRUE NO_TEST=TRUENC_MCP_BUF_SIO_CLK

NC_PCI_IRDY_LNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_MCP_TV_DAC_RSET

CRT_IG_G_Y_Y

TP_PCI_AD<31..15>

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_FRAME_L

NO_TEST=TRUENC_ENET_PWDWN_LMAKE_BASE=TRUE

MAKE_BASE=TRUENC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

NC_PCI_CLK0NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_CLK1

USB_TPAD_N

NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_HSYNC

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

NC_PCI_AD<31..15>NO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_PERR_L

NO_TEST=TRUENC_MCP_CLK27M_XTALOUTMAKE_BASE=TRUE

NC_MCP_GPIO_18MAKE_BASE=TRUE NO_TEST=TRUE

NC_PCI_INTW_LMAKE_BASE=TRUE NO_TEST=TRUE

NC_PCI_INTY_LMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_PCI_INTZ_L

NO_TEST=TRUE

MCP_TV_DAC_RSET

MCP_CLK27M_XTALOUT

TP_PCI_IRDY_L

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_PCI_C_BE_L<1..0>

TP_ENET_INTR_L

TP_MCP_KBDRSTIN_L

NO_TEST=TRUEMAKE_BASE=TRUENC_MCP_TV_DAC_VREF

MAKE_BASE=TRUENC_MCP_RGB_VSYNC

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_MCP_RGB_HSYNC

TP_MCP_BUF_SIO_CLK

NO_TEST=TRUENC_LPC_DRQ0_LMAKE_BASE=TRUE

TP_LPC_DRQ0_L

TP_PCI_PERR_LNO_TEST=TRUE

NC_MEM_A_CLK2NMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_MEM_A_CLK5PTP_MEM_A_CLK5P

NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_A_CLK5N

MAKE_BASE=TRUE NO_TEST=TRUENC_GMUX_JTAG_TCK_LGMUX_JTAG_TCK_L

NC_GMUX_JTAG_TDONO_TEST=TRUEMAKE_BASE=TRUE

NC_GMUX_JTAG_TDINO_TEST=TRUEMAKE_BASE=TRUE

GMUX_JTAG_TDI

NO_TEST=TRUENC_GMUX_JTAG_TMSMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_C_BE_L<1..0>

CRT_IG_VSYNC

MAKE_BASE=TRUENC_MEM_B_CLK2P NO_TEST=TRUETP_MEM_B_CLK2P

MAKE_BASE=TRUENC_MEM_B_CLK2N NO_TEST=TRUETP_MEM_B_CLK2N

MAKE_BASE=TRUENC_MEM_B_CLK5P NO_TEST=TRUE

TP_PCI_INTY_L

NO_TEST=TRUEMAKE_BASE=TRUENC_MLB_RAM_SIZE

NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_R_C_PR

TP_MEM_B_CLK5P

NC_CRT_IG_VSYNCNO_TEST=TRUEMAKE_BASE=TRUE

TP_PCI_DEVSEL_L

TP_PCI_SERR_LNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCI_SERR_L

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_DEVSEL_L

TP_MEM_A_CLK5N

NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_G_Y_Y

NO_TEST=TRUENC_CRT_IG_B_COMP_PBMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4PMAKE_BASE=TRUE NO_TEST=TRUE

PCIE_EXCARD_R2D_C_N

TP_PCI_RESET1_L

TP_PCI_STOP_L

MAKE_BASE=TRUENC_PCIE_CLK100M_PE5P

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5NMAKE_BASE=TRUE NO_TEST=TRUE

TP_PCI_TRDY_L

NC_PCIE_CLK100M_PE4NNO_TEST=TRUEMAKE_BASE=TRUE

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_TRDY_L

MAKE_BASE=TRUENC_PCI_GNT1_L

NO_TEST=TRUE

NC_PCI_STOP_LMAKE_BASE=TRUE NO_TEST=TRUE

TP_MEM_B_CLK5N

MAKE_BASE=TRUENC_PCI_INTX_L

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_C_BE_L<3>

TP_MLB_RAM_SIZE

TP_MCP_GPIO_18

NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_B_CLK5N

TP_PCIE_PE4_R2D_CP

GMUX_JTAG_TDO

USB_TPAD_P

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_PE4_R2D_CN

NC_PCIE_EXCARD_D2R_NMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_PCIE_EXCARD_R2D_C_PMAKE_BASE=TRUE

NO_TEST=TRUENC_PCIE_EXCARD_R2D_C_NMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_USB_TPAD_N

TP_PCI_INTX_L

MAKE_BASE=TRUENC_PCI_PAR

NO_TEST=TRUE

MAKE_BASE=TRUENC_PCI_RESET1_L

NO_TEST=TRUE

UNUSED SIGNAL ALIASSYNC_DATE=09/02/2009SYNC_MASTER=K22

17

18

20

20

20

20

20

20

17

19

19

17

17

17

21

21

17

17

17

17

17

17

17

17

19

19

19

19

19

19

19

19

19

17

17

17

17

17

19

18

19

20

18

18

18

18

18

18

18

19

18

18

19

18

21

21

19

19

16

17

19

18

15

15

19

16

19

19

16

17

19

19

19

15

15

16

21

17

17

20

19

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OUT

OUTIN

IN

IN

IN

OUT

OUT

IN

IN OUT

OUT

OUT

OUT

OUTIN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUTIN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MCP_CPUVDD_EN WILL ASSERT AFTER MCP_PS_PWRGD IS UP

LPC Reset (Unbuffered)

PCIE Reset (Unbuffered)

(P50 HAS A 100K TO GROUND)

Platform Reset ConnectionsSIGNAL ALIAS

PEG Slot Support

K22/K23 Use one GPIO for both ports 2&3 OCUSB PORT 2 AND 3 (C AND D) SHARE OVER-CURRENT WITH PORT 2PREVIOUSLY, PORT 3 HAD IT’S OWN BUT EFI MAPS THAT TO EXPRESSCARDSEE RDAR://6250424

9 OF 110

051-7863

A.0.0


21

R993

2

1R912

21

R911

21

R910

21

R930

2

1R955

21

R983

21

R981

21

R992

21

R990

21

R991

21

R971

2

1 C973

21

R925

21

R972

21

R926

21

R929

21

R900

PEG_R2D_C_P<0..15>MAKE_BASE=TRUE

PEG_D2R_N<0..15>MAKE_BASE=TRUE

MAKE_BASE=TRUEHPLUG_DET2

MAKE_BASE=TRUEUSB_EXTC_OC_L

MCP_CPUVDD_EN

CARDREADER_PLT_RST_L

PCA9557D_RESET_L

MEM_VTT_EN_R

PM_SLPS3_BUF1_LMAKE_BASE=TRUE

DEBUG_RESET_L

=PEG_D2R_N<0..15>

MAKE_BASE=TRUEPEG_R2D_C_N<0..15>=PEG_R2D_C_N<0..15>

=MCP_MII_RXER

=MCP_MII_COL

FW_RESET_L

SMC_LRESET_L

LPC_CLK33M_LPCPLUS

=MCP_MII_CRS

MCP_MII_NUMAKE_BASE=TRUE

PEG_CLK100M_N

=DVI_HPD_GMUX_INT

=PEG_R2D_C_P<0..15>

=PEG_D2R_P<0..15>

PEG_PRSNT_L

MINI_RESET_L

MAKE_BASE=TRUEPEG_D2R_P<0..15>

GPU_CLK100M_PCIE_NMAKE_BASE=TRUE

TP_MLB_RAM_VENDOR

MAKE_BASE=TRUEPM_SLPS3_BUF2_LPM_SLP_S3_L

MAKE_BASE=TRUEMXM_DETECT_L

MCP_CPU_VLD

PCIE_FW_PRSNT_L

LPC_RESET_L

MXM_GOODMAKE_BASE=TRUE

PCIE_MINI_PRSNT_L

DDRVTT_EN

PEG_RESET_L

PCIE_RESET_L

LPC_CLK33M_SMC

PM_CLK32K_SUSCLKPM_CLK32K_SUSCLK_R

LPC_CLK33M_SMC_R

USB_EXTD_OC_L

GPU_CLK100M_PCIE_PMAKE_BASE=TRUE

PEG_CLK100M_P

SYNC_DATE=N/ASYNC_MASTER=MASTER

Signal Aliases

1/16W

0

MF-LF

5%

402

47

402

100K5%1/16WMF-LF

402MF-LF1/16W5%

15

5%1/16W

402MF-LF

15

21

PLACEMENT_NOTE=Place close to U1400

402

22

MF-LF

5%1/16W

21

5%

MF-LF402

47K1/16W

51

49

41

34

87

29

78 75

49 103

51 103

49 103


33

MF-LF

5%1/16W

402


402

33

5%1/16WMF-LF

103 19

MF-LF

5%

0

402

1/16W

1/16WMF-LF402

5%

0

5%

MF-LF

0

1/16W

402

402

5%

MF-LF

0

1/16W

NO STUFF

402

10%

CERM-X5R6.3V

0.47UF

MF-LF1/16W5%

PLACEMENT_NOTE=Place close to U1400 33

402

5%1/16W

33

MF-LF402


33

MF-LF1/16W5%

402


402

22

MF-LF

5%1/16W

17

19

103 19

103 21

402MF-LF

20K

5%1/16W

17 85

17

17

102 87

102 87 17

17

17

17

102 86

102 86

17

17 86 102

86 102

20 46

94 73

18

18

18

18

21

70 50 49 6 102 21

6

46

www.bblianmeng.com

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BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

A_34*

A_35*

REQ_4*

A_7*

DBSY*

INIT*

A_20*

A20M*

ADS*

ADSTB_0*

ADSTB_1*

A_3*

A_4*

A_6*

A_8*

A_10*

A_14*

A_15*

A_16*

A_17*

A_18*

A_19*

A_21*

A_22*

A_23*

A_24*

A_25*

A_26*

A_27*

A_28*

A_29*

A_30*

A_31*

A_32*

A_33*

BCLK_0

BCLK_1

BNR*

BPRI*

BR_0*

DEFER*

DRDY*

FERR_PBE*

IERR*

IGNNE*

LINT0

LINT1

REQ_0*

REQ_1*

REQ_3*

RS_0*

RS_1*

RS_2*

SMI*

STPCLK*

REQ_2*

A_13*

A_12*

A_11*

A_9*

A_5*

LOCK*

RESET*

TRDY*

HIT*

HITM*

CONTROL

ADDR GROUP0

(1 OF 7)

CLK

SB

ADDR GROUP1

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

D_11*

D_10*

D_9*

D_1*

D_2*

D_8*

D_7*

D_6*

DBI_0*

DBI_1*

DBI_2*

DBI_3*

DSTBN_0*

DSTBN_1*

DSTBN_2*

DSTBN_3*

DSTBP_0

DSTBP_1

DSTBP_2

DSTBP_3

D_0*

D_3*

D_4*

D_5*

D_12*

D_13*

D_14*

D_15*

D_16*

D_17*

D_18*

D_19*

D_20*

D_21*

D_22*

D_23*

D_24*

D_25*

D_26*

D_27*

D_28*

D_29*

D_30*

D_31*

D_32*

D_33*

D_34*

D_35*

D_36*

D_37*

D_38*

D_39*

D_40*

D_41*

D_42*

D_43*

D_44*

D_45*

D_46*

D_47*

D_48*

D_49*

D_50*

D_51*

D_52*

D_53*

D_54*

D_55*

D_56*

D_57*

D_58*

D_59*

D_60*

D_61*

D_62*

D_63*

(2 OF 7)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE W/ A TESTPOINT W/ A GND NEARBY

CPU GTLREF

(63.5% OF 1.2V) = 0.762V

GTLREF VOLTAGE SHOULD BE 0.635 * VTT

10 OF 110

051-7863

A.0.0


2

1R1044

2

1R1043

2

1R1001

2

1 C1042

21

R1045

2

1 C1043

2

1R1041

2

1 C1040

2

1R1040

2

1 C1041

21

R1042

C17

G19

E12

B9

A16

G20

G12

C8

C20

D19

G11

A8

A11

A10

A7

B22

A22

A19

B19

B7

B21

C21

B18

A17

B16

C18

B15

C14

C15

A14

B6

D17

D20

G22

D22

E22

G21

F21

E21

F20

E19

A5

E18

F18

F17

G17

G18

E16

E15

G16

G15

F15

C6

G14

F14

G13

E13

D13

F12

F11

D10

E10

D7

A4

E9

F9

F8

G9

D11

C12

B12

D8

C11

B10

C5

B4

J1000

E3

M3

P2

A3

F5

B3

G23

J6

K6

M6

J5

K4

C3

L1

K1

P3

N2

AB2

E4

D4

R3

C1

G7

B2

F3

G8

C2

G28

F28

AD5

R6

D2

T5

R4

M4

L4

M5

P6

AJ6

AJ5

AH5

AH4

AG5

AG4

L5

AG6

AF4

AF5

AB4

AC5

AB5

AA5

AD6

AA4

Y4

Y6

W6

AB6

W5

V4

V5

U4

U5

T4

U6

K3

J1000

2

1R1004

2

1R1003

2

1R1000

CPU_GTLREF_DIV1

PPCPU_VTT_OUT_LEFT

FSB_A_L<8>

CPU_INTR

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<32>

FSB_A_L<33>

FSB_A_L<31>

FSB_A_L<5>

FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<12>

FSB_A_L<13>

FSB_REQ_L<2>

CPU_SMI_L

FSB_REQ_L<3>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_DRDY_L

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<10>

FSB_A_L<6>

FSB_A_L<4>

FSB_ADSTB_L<0>

CPU_A20M_L

FSB_A_L<7>

FSB_REQ_L<4>

CPU_GTLREF_DIV0 CPU_GTLREF0

PPCPU_VTT_OUT_LEFT

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<0>

FSB_DSTB_L_P<3>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_N<2>

FSB_DINV_L<3>

FSB_DINV_L<2>

FSB_D_L<6>

FSB_D_L<7>

FSB_D_L<8>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<10>

FSB_A_L<3>

FSB_LOCK_L

FSB_D_L<9>

FSB_D_L<12>

FSB_DSTB_L_N<0>

CPU_IGNNE_L

=PPVTT_S0_CPU

FSB_ADS_L

FSB_D_L<11>

FSB_D_L<13>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<25>

FSB_D_L<28>

FSB_D_L<29>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_BNR_L

CPU_GTLREF1

FSB_D_L<27>

FSB_A_L<17>

FSB_A_L<18>

FSB_A_L<19>

FSB_A_L<20>

FSB_TRDY_L

FSB_RS_L<2>

PPCPU_VTT_OUT_RIGHT

FSB_RS_L<1>

FSB_RS_L<0>

CPU_INIT_L

CPU_IERR_L

FSB_CPURST_L

FSB_HITM_L

FSB_HIT_L

CPU_NMI

CPU_STPCLK_L

PPCPU_VTT_OUT_RIGHT

CPU_FERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DEFER_L

FSB_BPRI_L

PPCPU_VTT_OUT_LEFT

SYNC_DATE=09/02/2009

CPU FSBSYNC_MASTER=K22

402MF-LF1/16W1%100

1/16W1%

402

57.6

MF-LF

1/16W

62

402

5%

MF-LF

10%

402CERM6.3V

1UF

1/16W

10

1%

402MF-LF

50V

402

10%220PF

NOSTUFF

X7R-CERM

402

100

MF-LF1/16W1%

402

1UF6.3V10%

CERM

1%

MF-LF402

57.61/16W

NOSTUFF

220PF50VX7R-CERM402

10%

402MF-LF

1%

10

1/16W

BGA-NOHSKWOLFDALE-SKT-1

CRITICAL

CPU

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

BGA-NOHSKWOLFDALE-SKT-1

CRITICAL

CPU

MF-LF

5%

402

1/16W

2001/16W5%

MF-LF

62

402

1/16W

62

402

5%

MF-LF

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

13 14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

14 100

10 11 12

11 29 100

10 11 12

6 50 55 71

11 29 100

10 11 12

100

10 11 12

10 11 12

www.bblianmeng.com

www.vinafix.vn

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

IN

BI

TESTHI_0

BPM_0*

BPM_1*

BPM_2*

BPM_3*

BPM_4*

BPM_5*

DBR*

FC3

FC8

FC10

FC15

FC18

FC23

FC26

FC27/BPMB0*

FC28/TDO_M

FC29

FC30

FC31

FC32

FC33

FC34

FC35

FC36

FC37

FC39

FC40

FC41/BPMB1*

ITPCLK_0

ITPCLK_1

RSVD_A20

RSVD_AC4

RSVD_AE4

RSVD_AE6

RSVD_AH2

RSVD_D1

RSVD_D14

RSVD_D16

RSVD_E5

RSVD_E6

RSVD_E7

RSVD_E23

RSVD_F23

RSVD_F29

RSVD_G6

RSVD_J3

RSVD_N4

RSVD_N5

RSVD_P5

RSVD_V2

TCK

TDI

TDO

TESTHI_1

TESTHI_2

TESTHI_3

TESTHI_4

TESTHI_5

TESTHI_6

TESTHI_7

TESTHI_8/BPMB3*

TESTHI_9/BPMB2*

TESTHI_10

TESTHI_12/TDI_M

TMS

TRST*

(4 OF 7)

RESERVED

TEST

JTAG

XDP/ITP

PROCHOT*

THERMTRIP*

GTLREF1

GTLREF0

THERMDC

FC5/GTLREF2

BOOTSELECT

BSEL_0

BSEL_1

BSEL_2

COMP_0

COMP_1

COMP_2

COMP_3

COMP_8

DPRSTP*

DPSLP*

IMPSEL

MSID_0

MSID_1

PECI

PSI*

PWRGOOD

SKTOCC*

SLP*

THERMDA

VRDSEL

FC38/GTLREF3

(3 OF 7)

THERMAL

PWR MGMT

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

OUT

OUT OUT

IN

OUT

OUT

OUTOUT

OUT

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(TDI)

WITHIN 38MM (1.5IN) OF THE CPU

FROM 975X PDG: IMPSEL

0 - 51 PD TO GND

IPU

NC

NC

NC

NC

PLACE TMS/TMI/TCK TERMINATION

(TMS)

(TCK)

NC

(ALSO WRITTEN AS BPM2)

CPU BPMB TERM

KENTSFIELD CPU SUPPORT

CPU BPM TERM

(SELECTS 50 OHM SYSTEM IMPEDANCE)

11 OF 110

051-7863

A.0.0


2

1R1150

2

1R1120

2

1R1121

2

1R1122

2

1R1123

2

1R1128

2

1R1151 2

1R1109

2

1R1129

2

1R1180

2

1R1181

2

1R1182

2

1R1183

2

1R1130

2

1R1133

2

1R1132

2

1R1135

AL3M2

AK1

AL1

L2

AE8

N1

Y3AL2

G5

V1

W1

F6

H2

H1

F2

G10

P1

T2

B13

R1

G2

T1

A13

G30

H30

G29

Y1

J1000

AG1

AC1

G4

G3

F24

G24

G26

G27

G25

F25

W2

H5

W3

F26

AF1

AD1

AE1

V2

P5

N5

N4

J3

G6

F29

F23

E7

E6

E5

E23

D16

D14

D1

AH2

AE6

AE4

AC4

A20

AJ3

AK3

AK6

C9

AM6

AA2

AB3

AD3

H4

J17

H16

H15

J16

U3

J2

U2

U1

G1

E29

A24

AE3

H29

E24

AC2

AG3

AF2

AG2

AD2

AJ1

AJ2

J1000

2

1R1191

2

1R1195

2

1R1190

2

1R1192

2

1R1193

2

1R1194

21

R1102

21

R1101

21

R1100

CPU_PD_IMPSEL

CPU_COMP<8>

CPU_COMP<1>

PM_THRMTRIP_L

XDP_DBRESET_L

CPU_XDP_BPMB<3>

CPU_XDP_BPMB<2>

CPU_XDP_BPM_L<5>

CPU_XDP_BPM_L<4>

CPU_XDP_BPM_L<3>

CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<1>

CPU_XDP_BPM_L<0>

CPU_XDP_TRST_L

CPU_XDP_TDO

CPU_XDP_BPMB<1>

CPU_XDP_BPMB<0>

CPU_XDP_BPMB<2>

CPU_XDP_BPMB<3>

CPU_XDP_BPMB<1>

CPU_XDP_BPMB<0>

PM_PGOOD_PVCORE_CPUCPU_TESTHI_10

CPU_TESTHI_1

CPU_TESTHI_0

PPCPU_VTT_OUT_LEFT

PPCPU_VTT_OUT_RIGHT

CPU_TESTHI_2_7

CPU_TESTHI_M

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TCK

PPCPU_VTT_OUT_RIGHT

PPCPU_VTT_OUT_RIGHT

CPU_XDP_BPM_L<0>

CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<1>

CPU_XDP_BPM_L<5>

CPU_XDP_BPM_L<4>

CPU_XDP_BPM_L<3>

PPCPU_VTT_OUT_LEFT

=PPVTT_S0_FSB_CPU

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<8>

CPU_COMP<1>

CPU_COMP<0>

CPU_GTLREF0

CPU_COMP<0>

CPU_COMP<2>

CPU_COMP<3>

CPU_PECI_L

CPU_THERMD_P

CPU_THERMD_N

CPU_BSEL<2>

FSB_CPUSLP_L

CPU_PSI_L

CPU_BSEL<1>

CPU_BSEL<0>

CPU_BOOT

CPU_GTLREF1

PPCPU_VTT_OUT_RIGHT

CPU_PROCHOT_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU TEST & MISC.SYNC_MASTER=K22 SYNC_DATE=09/02/2009

70 71

14 50 100

14 50 100 71

14 100

14 100

13 14 100

14 100

NOSTUFF

1%130

MF-LF1/16W

402

49.91%

402

1/16WMF-LF

1/16W1%49.9

MF-LF402

49.9

MF-LF402

1%1/16W

402MF-LF1/16W1%49.9 24.9

1/16WMF-LF402

1%

51

MF-LF1/16W5%

402

55 108

55 108

55 108

MF-LF

5%1/16W

402

51

14 100

14 100

14 100

402

5%1/16W

51

MF-LF

11 13 100

11 13 100

11 13 100

11 13 100

51

MF-LF402

1/16W5%

MF-LF

51

402

1/16W5%

511/16WMF-LF402

5%51

402MF-LF1/16W5%

11 13 100

11 13 100

11 13 100

5%1/16W

51

402MF-LF

515%

1/16W

402MF-LF MF-LF

402

5%1/16W

511/16W

402

5%51

MF-LF

CRITICAL

CPU

WOLFDALE-SKT-1BGA-NOHSK

CPU

CRITICAL


51

402MF-LF

5%1/16W

402

5%1/16W

51

MF-LF

5%

MF-LF

511/16W

402

5%1/16WMF-LF402

515%1/16WMF-LF402

51

402MF-LF

5%1/16W

51

11 13 100

MF-LF1/16W

402

5%

51

1/16WMF-LF402

51

5%

MF-LF1/16W

402

51

5%

13 28

11 13 100

11 13 100

11 13 100

11 13 100

11 13 100

11 13 100

13 100

13 100

13 100

13 100

13 100

11 100

11 100

10 11 12

10 11 12

10 11 12

10 11 12

11 13 100

11 13 100

11 13 100

11 13 100

11 13 100

11 13 100

10 11 12

6 12

11 100

11 100

11 100

11 100

11 100

10 29 100

11 100

11 100

11 100

10 29 100

10 11 12

www.bblianmeng.com

www.vinafix.vn

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCCP

VCCP

VTT_C29

VTT_C30

VTT_D25

VTT_D26

VTT_D27

VTT_D28

VTT_D29

VTT_D30

VTT_OUT_RIGHT

VTT_OUT_LEFT

VTT_SEL

VTT_C28

VTT_C27

VTT_C26

VTT_C25

VTT_B29

VTT_B28

VTT_B27

VTT_B26

VTT_B25

VTT_A30

VTT_A29

VTT_A28

VTT_A27

VTT_A26

VTT_A25

VTT_B30

VCCA

VCCIOPLL

VCCP

VCCPLL

VCC_MB_REGULATION

VCC_SENSE

VID_0

VID_1

VID_2

VID_3

VID_4

VID_5

VID_6

VID_7

VID_SELECT

VSSA

VSS_MB_REGULATION

VSS_SENSE

VCCP

(7 OF 7)

OUT

GND GND

(5 OF 7)

GNDGND

(6 OF 7)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

POWER

GND

VCC PLL DECOUPLING

(SEE VREG PAGE)

VCCP CORE DECOUPLING

~125MA CURRENT

THIS IS FOR OLDER CPU SUPPORT

GND

WILL PLACE FILTER BUT NOT CONNECT FOR WOLFDALE

VID PULLUPS WITH VREG

FSB VTT DECOUPLING

12 OF 110

051-7863

A.0.0


2

1R1200

V25

E20

R7

V27

R5

V28

V29

R2

V30

V26

E26

P7

P4

N7

N6

N3

M7

M1

L7

L6

C13

V7

B8

B5

B1

D3

D5

R30

D6

C4

D9

E2

H6

T7

Y2

H3

AN24

AN27

AN28

E27

H12

B11

K7B14

C22

K2

C24

D12

C10

C19

AN2

D18

F7

D21

E11

Y5

L28

E14

H7

H8

H28

H9

AN23

AN20

J4

K5

J7

L25

D24

E28

F10

F13

F16

F22

F4

E17

F19

C16

H13

H14

H17

H18

H19

H20

H21

H22

H10

H23

H24

H25

B17

H26

B20

E8

H27

L3

B24

L23

L24

H11

L26

L27

Y7

D15

L29

L30

C7

P23

W7

P25

W4

P26

P27

V6

P28

P29

V3

P30

R23

R24

U7

R25

R26

R27

R28

R29

E25

T6

V23

V24

T3

P24

J1000

AN10

AA24

AA25

AA26

AA27

AN13

AA28

AM4

AA29

AA30

AB23

AB24

AB25

AN16

AB26

AB1

AB27

AN17

AB28

AB29

AB30

AK24

AJ27

AH1

AE26

AJ4

A9

A6

A2

A18

AF13

AE10

AF16

AF17

AG24

AF23

AF24

AF25

AF26

AF27

AL7 AJ7

AH7

AK7

AF7

AK23

AL10

AF28

AE16

AN1

AF29

AL17

AL13

AM1

AM27

AK20

AK16

AL20

AK13

AL24

AL16

AM24

AE24

AF10

AE30

AE29

AF30

AE28

A12

AL23

AK30

AG7

AE13

AJ23

AM10

AK10

AH3

AJ17

AK29

AF6

AG10

AE17

AJ16

AK5

AF3

AJ10

AJ30

AH24

AM13

AE7

AH23

AE5

AH20

AH17

AK17

AH16

AD7

AH13

AJ28

AE27

AG13

AE25

AM16

AH6

AC7

AC6

AC3

AM17

AG16

AJ24

AB7

AA6

AG17

AA7

AA3

AM20

AK28

AK27

AJ29

AE2

A21

AH10

A15

AM23

AG20

AD4

AL27

AG23

AJ20

AJ13

AM28

AF20

AK2

AL28

AA23

AE20

J1000

F27

AA1

J1

D30

D29

D28

D27

D26

D25

C30

C29

C28

C27

C26

C25

B30

B29

B28

B27

B26

B25

A30

A29

A28

A27

A26

A25

B23

AN4

AN6

AN7

AM7

AM5

AL4

AK4

AL6

AM3

AL5

AM2

D23

AM15

AD23

AF11

AK15

AG27

J21

J18

J26

AL15

AF18

AD29

AH15

AN9

AG26

AJ15

J10

AK26

AG11

AN29

AK22

AF22

AL29

AF9

N26

AG9

AN12

AK8

T27

AJ19

U26

AJ8

AN15

AG8

AL22

AH12

N28

T26

AM8

AL19

K23

P8

K25

J11

AA8

J29

AH9

AJ25

AL30

N29

AG14

AK11

AJ9

AL12

AH25

AG18

AN30

AL14

K30

AJ11

AL11

AM11

AJ21

AG30

AK21

AK14

J30

Y24

AF21

AD30

AL9

AG19

J27

J12

W28

T28

J13

AF14

J24

AM12

AL26

AG28

AH27

AH29

AH19

J15

AL8

AE11

AE12

AM26

K29AG22

AJ14

AB8

AM19

AM18

AC27

J23

U24

M29

AC29

Y26

AD28

AH11

AN14

Y30

W30

AC25

AL18

Y28

T25

W25

W24

W23

AK9

M27

Y25

Y27

AN18

AN11

AN25

AN26

Y23

AC23

AC24

U29

M28

W29

N23

AE14

AC8

AF15

AM9

T30

J28

J8AC26

AF12

W26

AE18

N25

AC28

T8

AN21

M24

K27

M30

AE15

N8

AC30

AE19

AM30

AE21

K8

V8

AN19

AE22

AE23

AD24

AF19

K28

U28

AM22

N27

AG29

M23

U23

AD27

AJ12

Y8

K26

U25

L8

M26

M25

AM29

AJ26

AD26

N30

M8

AD25

J14

AM21

AG21

T24

J22

AG15

AK19

AK25

Y29AE9

AM25

AN22

AM14

T29

AH22

AK12

AH21

AH28

K24

AD8

AK18

U8

N24

R8

T23

AH14

AN8

AL25

W27

AH26

AH18

J20

AJ22

AH8

AG12

AH30

J19

AJ18

AG25

AL21

U30

J25

AF8

W8

J9

U27

C23

A23

AN3

AN5

J1000

2

1 C1200

2

1 C1201

2

1 C1281

2

1 C1280

2

1 C1210

2

1 C12132

1C1211

2

1 C1212

21

R1211

21

R121021

L1210

2

1 C1238

2

1 C1237

2

1 C1236

2

1 C1235

2

1 C1234

2

1 C1226

VOLTAGE=0VCPU_VSSA

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

=PPVTT_S0_FSB_CPU

CPU_VID<7>

CPU_VCC_PKG_SENSE_N

CPU_VID<1>

TP_VTT_SEL

PPCPU_VTT_OUT_RIGHT

CPU_VCCA

CPU_VCCIOPLL

CPU_VID<2>

CPU_VID<5>

CPU_VID<6>

CPU_VSSA

CPU_VID<0> CPU_VCCA_FLT


PPCPU_VTT_OUT_LEFT

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWR

PPCPU_VTT_OUT_LEFTVOLTAGE=1.2V


CPU_VID<3>

CPU_VCCAVOLTAGE=1.2VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

CPU_VCCIOPLLVOLTAGE=1.2VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

CPU_VID<4>

=PPVTT_S0_FSB_CPU

TP_CPU_VSS_SENSE

=PPVTT_S0_FSB_CPU

CPU_VID_SELECT

VOLTAGE=1.2VMIN_LINE_WIDTH=0.6 mm


PPCPU_VTT_OUT_RIGHT

=PPVCORE_S0_CPU

PPCPU_VTT_OUT_RIGHT

CPU_VID_SELECT

CPU_VCC_SENSE

CPU_VCC_PKG_SENSE_P

CPU POWER, GND, DECAPSSYNC_DATE=09/02/2009SYNC_MASTER=K22

10V0.1UF20%

402CERM

0.1UF

CERM10V

402

20%0.1UF20%

402

10VCERM

0.1UF

CERM20%10V

402CERM20%10V0.1UF

402402CERM

0.1UF20%10V

402

6805%1/16WMF-LF

CRITICAL

CPU


CRITICAL

CPU


71 100 CRITICAL

CPU


402CERM10V

0.1UF20%

10V20%

402CERM

0.1UF

402

16V10%CERM

0.01UF

603

6.3VX5R

10UF20%

805-3CERM-X5R6.3V20%22UF

6.3VX5R

10uF

603

20%

NOSTUFF

1UF10%

402CERM6.3V

NOSTUFF

6.3V

1UF10%

CERM402

603MF-LF1/10W5%

0

MF-LF

5%

603

0

1/10W

FERR-120-OHM-0.2A

0603

CONROE

71 100

71 100

53 108

71 100

71 100

71 100

71 100

71 100

71 100

71 100

12

6 11 12

10 11 12

12

12

12

6 12

10 11 12

10 11 12

6 12

12

12

6 11 12

6 11 12

12

10 11 12

6

10 11 12

12

www.bblianmeng.com

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IN

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

NC

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PWRGD/HOOK0

OBSDATA_A3

OBSDATA_A2

TRSTn

DBR#/HOOK7

RESET#/HOOK6

OBSFN_D1

OBSFN_D0

OBSDATA_C1

OBSDATA_C0

OBSFN_C1

OBSFN_C0

OBSDATA_C2

OBSDATA_C3

OBSDATA_B3

OBSDATA_D1

OBSDATA_A1

MCP79-specific pinout

OBSFN_A1

HOOK3

OBSFN_B1

OBSDATA_B2

TDO

TDI

XDP_PRESENT#

TMSTCK0

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_B0

OBSFN_A0

HOOK1

OBSDATA_D0

VCC_OBS_CD

OBSDATA_A0

OBSFN_B0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_D2

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

HOOK2

VCC_OBS_AB

13 OF 110

051-7863

A.0.0


2

1R1301

2

1R1316

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1300

21

R1303

2

1 C1301

2

1C1300

2

1R1315

21

R1399

CPU_XDP_BPMB<2>

CPU_XDP_BPMB<0>

XDP_OBS20

SMBUS_MCP_0_DATA

CPU_XDP_TCK

CPU_XDP_TRST_LSMBUS_MCP_0_CLK

PM_LATRIGGER_L

JTAG_MCP_TCK

XDP_PWRGD

XDP_DBRESET_L

TP_XDP_OBSFN_B1

=PPVTT_S0_XDP

CPU_XDP_BPM_L<3>

CPU_PWRGD

CPU_XDP_BPM_L<5>

MCP_DEBUG<7>

FSB_CPURST_L

MCP_DEBUG<6>

CPU_XDP_TDI

CPU_XDP_TMS

CPU_XDP_BPM_L<4>

CPU_XDP_BPM_L<1>

CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<0>

MCP_DEBUG<5>

MCP_DEBUG<4>CPU_XDP_BPMB<3>

CPU_XDP_BPMB<1>

=PP3V3_S0_XDP

JTAG_MCP_TDO

JTAG_MCP_TRST_L

MCP_DEBUG<0>

MCP_DEBUG<1>

MCP_DEBUG<2>

MCP_DEBUG<3>

JTAG_MCP_TMS

JTAG_MCP_TDI

FSB_CLK_ITP_N

XDP_CPURST_L

CPU_XDP_TDO

FSB_CLK_ITP_P

TP_XDP_OBSFN_B0

eXtended Debug Port (XDP)SYNC_MASTER=K22 SYNC_DATE=09/02/2009

MF-LF1/16W

XDP

5%

402

51

11 100

11 100

11 100

11 100

402

5%62

XDP

1/16WMF-LF

19

11 28

11 100

11 100

11 100

11 100

14 100

14 100

21

21

19

19

19

19

19

19

19

19

21

21

21

11 100

11 100

11 100

11 100

F-ST-SM

CRITICAL

XDP_CONN

LTH-030-01-G-D-A-TR

MF-LF

PLACEMENT_NOTE=Place close to CPU to minimize stub.

402

1K

XDP

1/16W5%

10 14 100

11 100

11 100

11 100

XDP

0.1uF10%

402

16VX5R

XDP

0.1uF10%

X5R402

16V

402

54.91%

1/16WMF-LF

XDP

21 52 106

21 52 106

402

1K

MF-LF

5%1/16W

XDP

11 14 100

6

6

100

www.bblianmeng.com

www.vinafix.vn

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

CPU_ADSTB0*

CPU_BPRI*

CPU_A25*

CPU_A24*

CPU_D4*

BCLK_OUT_CPU_N

BCLK_VML_COMP_GND

BCLK_VML_COMP_VDD

CPU_A14*

CPU_A15*

CPU_A10*

CPU_A11*

CPU_A13*

CPU_A12*

CPU_A16*

CPU_A31*

CPU_A18*

CPU_A30*

CPU_A26*

CPU_A33*

CPU_A21*

CPU_A20*

CPU_A23*

CPU_A19*

CPU_A22*

CPU_A28*

CPU_A29*

CPU_A7*

CPU_A17*

CPU_A27*

CPU_A35*

CPU_A34*

CPU_A32*

CPU_REQ2*

CPU_A9*

CPU_REQ3*

CPU_A4*

CPU_A8*

CPU_A3*

CPU_ADSTB1*

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

CPU_COMP_GND

CPU_COMP_VCC

CPU_D1*

CPU_D3*

CPU_D15*

CPU_D11*

CPU_D10*

CPU_D8*

CPU_D13*

CPU_D9*

CPU_D23*

CPU_D19*

CPU_D21*

CPU_D22*

CPU_D2*

CPU_D18*

CPU_D20*

CPU_D17*

CPU_D31*

CPU_D28*

CPU_D27*

CPU_D25*

CPU_D26*

CPU_D24*

CPU_D7*

CPU_D30*

CPU_D29*

CPU_D38*

CPU_D33*

CPU_D32*

CPU_D39*

CPU_D37*

CPU_D36*

CPU_D5*

CPU_D42*

CPU_D44*

CPU_D43*

CPU_D40*

CPU_D41*

CPU_D45*

CPU_D49*

CPU_D55*

CPU_D6*

CPU_D50*

CPU_D53*

CPU_D52*

CPU_D51*

CPU_D48*

CPU_D54*

CPU_D59*

CPU_D57*

CPU_D62*

CPU_D58*

CPU_D0*

CPU_D61*

CPU_D60*

CPU_D63*

CPU_D56*

CPU_D14*

CPU_D12*

CPU_DBI1*

CPU_DBI2*

CPU_DPRSTP*

CPU_DPSLP*

CPU_DPWR*

CPU_DSTBN0*

CPU_DSTBN2*

CPU_DSTBN3*

CPU_DSTBP0*

CPU_DSTBP1*

CPU_DSTBP2*

CPU_DSTBP3*

CPU_FERR*

CPU_HIT*

CPU_LOCK*

CPU_NMI

CPU_PECI

CPU_PROCHOT*

CPU_REQ0*

CPU_REQ1*

CPU_A6*

CPU_RESET*

CPU_RS0*

CPU_RS1*

CPU_RS2*

CPU_SLP*

CPU_SMI*

CPU_THERMTRIP*

CPU_TRDY*

V1P1_DLLDLCELL_AVDD

V1P1_PLL_CPU

V1P1_PLL_FSB

V1P1_PLL_MCLK

CPU_D16*

CPU_D47*

CPU_D46*

CPU_A5*

CPU_DBI3*

CPU_D35*

CPU_D34*

BCLK_OUT_ITP_N

CPU_DEFER*

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P

BCLK_IN_N

BCLK_OUT_NB_N

BCLK_OUT_NB_P

CPU_INIT*

BCLK_IN_P

CPU_A20M*

CPU_IGNNE*

CPU_INTR

CPU_PWRGD

CPU_STPCLK*

CPU_BR0*

CPU_BR1*

CPU_DBSY*

CPU_DRDY*

CPU_HITM*

CPU_BNR*

CPU_ADS*

CPU_REQ4*

CPU_DBI0*

CPU_DSTBN1*

FSB

(1 OF 11)




36

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DRAWING NUMBER SIZE

DR


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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

20 mA

29 mA

15 mA

206 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Loop-back clock for delay matching.

270 mA (A01)

NC

14 OF 110

051-7863

A.0.0


2

1R1420

2

1R1421

2

1R1422

AH27

AG28

AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC39

AC37

AE38

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

T43

T41

W41

H39

H43

K41

J40

V42

H41

H42

L41

M43

M42

K42

N41

N40

M40

P41

Y39

L42

H40

J39

J38

J37

L39

L38

L37

N38

N36

Y42

R39

N33

R37

R38

N34

P35

R34

R35

U38

R33

W42

U37

U36

U35

U34

U33

W38

W35

W34

W33

AA34

Y40

AA37

AA36

AA35

AA38

R42

P42

R41

U41

T39

T42

Y43

Y41

AM43

AM42

F42

D42

F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AE34

AE35

AC34

AC35

AC33

AE37

AN34

AR39

AN36

AN35

AN38

AL33

AB35

AN37

AL34

AL35

AJ33

AL38

AL39

AJ36

AL37

AJ35

AF41

AJ37

AJ38

AG33

AJ34

AG34

AG35

AF35

AG37

AG38

AE33

AG39

AM39

AM40

AL41

AK42

AL43

AL42

G42

G41

AJ40

AK41

U1400

2

1R1416

2

1R1440

2

1R1410

2

1R1435

2

1R1430

2

1R1431

2

1R1436

CPU_INIT_L

FSB_BREQ1_L

FSB_TRDY_L

CPU_PROCHOT_L

PM_THRMTRIP_L

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<22>

FSB_A_L<21>

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

FSB_HIT_L

FSB_RS_L<1>

FSB_RS_L<2>

PP1V05_S0_MCP_PLL_FSB

MCP_CPU_COMP_VCC

CPU_DPSLP_L

FSB_CPUSLP_L

MCP_BCLK_VML_COMP_VDD

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_GND

FSB_A_L<24>

FSB_D_L<42>

FSB_D_L<45>

CPU_IGNNE_L

CPU_INTR

CPU_NMI

CPU_SMI_L

CPU_PWRGD

FSB_A_L<23>

FSB_A_L<17>

FSB_A_L<15>

FSB_A_L<10>

FSB_DINV_L<3>

FSB_A_L<5>

FSB_D_L<46>

FSB_D_L<47>

FSB_D_L<16>

CPU_STPCLK_L

FSB_RS_L<0>

FSB_CPURST_L

FSB_A_L<6>

FSB_REQ_L<4>

FSB_REQ_L<1>

FSB_REQ_L<0>

CPU_PECI_MCP

FSB_LOCK_L

FSB_HITM_L

FSB_DSTB_L_P<3>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<1>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<3>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<0>

FSB_DRDY_L

CPU_DPRSTP_L

FSB_DBSY_L

FSB_DINV_L<2>

FSB_DINV_L<1>

FSB_DINV_L<0>

FSB_D_L<12>

FSB_D_L<14>

FSB_D_L<56>

FSB_D_L<63>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<0>

FSB_D_L<58>

FSB_D_L<62>

FSB_D_L<57>

FSB_D_L<59>

FSB_D_L<54>

FSB_D_L<48>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<50>

FSB_D_L<6>

FSB_D_L<55>

FSB_D_L<49>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<5>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<39>

FSB_D_L<34>

FSB_D_L<32>

FSB_D_L<33>

FSB_D_L<38>

FSB_D_L<35>

FSB_D_L<29>

FSB_D_L<30>

FSB_D_L<7>

FSB_D_L<24>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<27>

FSB_D_L<28>

FSB_D_L<31>

FSB_D_L<17>

FSB_D_L<20>

FSB_D_L<18>

FSB_D_L<2>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<19>

FSB_D_L<23>

FSB_D_L<9>

FSB_D_L<13>

FSB_D_L<8>

FSB_D_L<10>

FSB_D_L<11>

FSB_D_L<15>

FSB_D_L<3>

FSB_D_L<1>

FSB_BREQ0_L

FSB_BNR_L

FSB_ADSTB_L<1>

FSB_ADS_L

FSB_A_L<3>

FSB_A_L<8>

FSB_A_L<4>

FSB_REQ_L<3>

FSB_A_L<9>

FSB_REQ_L<2>

FSB_A_L<32>

FSB_A_L<34>

FSB_A_L<35>

FSB_A_L<27>

FSB_A_L<7>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<20>

FSB_A_L<33>

FSB_A_L<26>

CPU_A20M_L

FSB_A_L<18>

FSB_A_L<31>

FSB_A_L<16>

FSB_A_L<12>

FSB_A_L<13>

FSB_A_L<11>

FSB_A_L<14>

FSB_CLK_MCP_P

FSB_CLK_MCP_N

FSB_CLK_ITP_P

FSB_CLK_ITP_N

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_D_L<4>

FSB_A_L<25>

FSB_BPRI_L

FSB_DEFER_L

FSB_ADSTB_L<0>

=PP1V05_S0_MCP_FSB

CPU_FERR_L

=PP1V05_S0_MCP_FSB


MCP CPU Interface

5%1/16WMF-LF

470

402 402

4705%

MF-LF1/16W

402

4705%

MF-LF1/16W

MCP7ABGA

OMIT

1/16W

402MF-LF

625%

NO STUFF

150

1/16W

402MF-LF

5%

5%62

402MF-LF1/16W

49.9

1/16W1%

402MF-LF

49.9

MF-LF402

1%1/16W

1/16W1%

402MF-LF

49.9 49.9

1/16W1%

402MF-LF

10 100

10 100

11 50 100

11 50 100

55 108

11 100

10 100

11 100

11 100

11 13 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

13 100

13 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 100

10 13 100

10 100

11 100

11 100

11 100

100

25

100

100

100

100

100

100

6 14 22 25

6 14 22 25

www.bblianmeng.com

www.vinafix.vn

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MDQ0_1

MDQ0_2

MCLK0A_1_N

MCLK0A_0_P

MCS0A_0*

MDQ0_63

MDQ0_62

MDQ0_61

MDQS0_1_P

MDQS0_0_P

MDQ0_57

MDQ0_41

MDQ0_40

MDQ0_28

MDQ0_42

MDQ0_43

MDQ0_44

MDQ0_45

MDQ0_46

MDQ0_47

MDQ0_48

MDQ0_49

MDQ0_38

MA0_0

MA0_1

MA0_10

MA0_11

MA0_12

MA0_13

MA0_14

MA0_2

MA0_4

MA0_5

MA0_6

MA0_7

MA0_8

MA0_9

MBA0_0

MBA0_1

MBA0_2

MCAS0*

MCKE0A_0

MCKE0A_1

MCLK0A_0_N

MCLK0A_1_P

MCLK0A_2_N

MCLK0A_2_P

MCS0A_1*

MDQ0_0

MDQ0_10

MDQ0_11

MDQ0_12

MDQ0_13

MDQ0_14

MDQ0_15

MDQ0_16

MDQ0_17

MDQ0_18

MDQ0_20

MDQ0_21

MDQ0_22

MDQ0_23

MDQ0_24

MDQ0_25

MDQ0_26

MDQ0_27

MDQ0_29

MDQ0_3

MDQ0_30

MDQ0_31

MDQ0_32

MDQ0_33

MDQ0_34

MDQ0_35

MDQ0_36

MDQ0_37

MDQ0_39

MDQ0_4

MDQ0_5

MDQ0_55

MDQ0_56

MDQ0_58

MDQ0_59

MDQ0_6

MDQ0_60

MDQ0_7

MDQ0_9

MDQM0_0

MDQM0_1

MDQM0_2

MDQM0_3

MDQM0_4

MDQM0_5

MDQM0_6

MDQM0_7

MDQS0_0_N

MDQS0_1_N

MDQS0_2_N

MDQS0_2_P

MDQS0_3_N

MDQS0_3_P

MDQS0_4_N

MDQS0_4_P

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MODT0A_0

MODT0A_1

MRAS0*

MWE0*

MDQ0_54

MDQ0_53

MDQ0_52

MDQ0_51

MDQ0_50

MA0_3

MDQ0_19

MDQ0_8 0A

MEMORYCONTROL

MEMORY PARTITION 0

(2 OF 11)

MDQ1_43

MA1_0

MA1_1

MA1_10

MA1_11

MA1_12

MA1_13

MA1_14

MA1_2

MA1_3

MA1_4

MA1_5

MA1_6

MA1_7

MA1_8

MA1_9

MBA1_0

MBA1_1

MBA1_2

MCAS1*

MCKE1A_0

MCS1A_0*

MDQ1_0

MDQ1_1

MDQ1_10

MDQ1_11

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_16

MDQ1_17

MDQ1_18

MDQ1_19

MDQ1_2

MDQ1_20

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_25

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_3

MDQ1_30

MDQ1_31

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_4

MDQ1_40

MDQ1_41

MDQ1_42

MDQ1_44

MDQ1_45

MDQ1_46

MDQ1_47

MDQ1_48

MDQ1_49

MDQ1_5

MDQ1_50

MDQ1_51

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_55

MDQ1_56

MDQ1_57

MDQ1_58

MDQ1_59

MDQ1_6

MDQ1_61

MDQ1_62

MDQ1_63

MDQ1_7

MDQ1_8

MDQ1_9

MDQM1_0

MDQM1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQS1_0_N

MDQS1_0_P

MDQS1_1_N

MDQS1_1_P

MDQS1_2_P

MDQS1_3_N

MDQS1_3_P

MDQS1_4_N

MDQS1_4_P

MDQS1_5_N

MDQS1_5_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_7_P

MODT1A_1

MRAS1*

MWE1*

MDQ1_60

MDQS1_2_N

MCLK1A_2_P

MCLK1A_2_N

MCLK1A_1_P

MCLK1A_1_N

MCLK1A_0_P

MCLK1A_0_N

MCS1A_1*

MODT1A_0

MCKE1A_1

MEMORYCONTROL

1A

MEMORY PARTITION 1

(3 OF 11)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

15 OF 110

051-7863

A.0.0


BA16

AW16

BB13

AY15

AT2

AT1

AY2

AY1

BB6

BA6

BA10

AY11

BB33

BA33

BB37

BA37

BA43

AY42

AT42

AT43

AT5

BA2

AY7

BA11

BB34

BB38

AY43

AR42

AW42

AW41

AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9

BB10

BB12

AW12

BB8

BB9

AY12

BA12

BC32

AW32

AU40

BA35

AY36

BA32

BB32

BA34

AY35

BC36

AW36

BA39

AY40

AU41

BA36

BB36

BA38

AY39

BB40

AW40

AV42

AV41

BA40

BC40

AR41

AP42

BB14

BB16

BA42

BB42

BB22

BA22

BA19

AY19

AY31

BB30

BA15

BB29

BB18

BB17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BA29

BA14

AW28

BC28

BA17

BB25

BA18

U1400

AR17

AV17

AP15

AV15

AL10

AL11

AR8

AR9

AW7

AW8

AP13

AR13

AV25

AW25

AU30

AU29

AT35

AU35

AU39

AT39

AN5

AU5

AR10

AN13

AN27

AW29

AV35

AR34

AT37

AU37

AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5

AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9

AP11

AW6

AY5

AU9

AV9

AR38

AU11

AV11

AV13

AW13

AR11

AT11

AR14

AU13

AR26

AU25

AV38

AT27

AU27

AP25

AR25

AP27

AR27

AP29

AR29

AP31

AR31

AW38

AV27

AN29

AV29

AN31

AU31

AR33

AV37

AW37

AT31

AV31

AR35

AP35

AT15

AR18

AW33

AV33

BA24

AY24

BB20

BC20

AU23

AT23

AP17

AP23

AP19

AW17

AV21

AR22

AU21

AP21

AR21

AN21

AV19

AU19

AR23

AU15

AN23

AW21

AN19

AT19

AR19

U1400

MEM_B_CKE<0>

MEM_B_ODT<0>

MEM_B_DQ<0>

MEM_A_DQ<19>

MEM_A_A<3>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_ODT<0>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_DQ<7>

MEM_A_DQ<60>

MEM_A_DQ<6>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<56>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<39>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<3>

MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<0>

MEM_A_CS_L<1>

TP_MEM_A_CLK2P

TP_MEM_A_CLK2N

MEM_A_CLK_P<1>

MEM_A_CLK_N<0>

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CAS_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQ<38>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<28>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<57>

MEM_A_DQS_P<0>

MEM_A_DQS_P<1>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_CS_L<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<55>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

TP_MEM_B_CLK2P

MEM_B_DQS_N<2>

MEM_B_DQ<60>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_ODT<1>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<3>

MEM_B_DM<2>

MEM_B_DM<1>

MEM_B_DM<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<6>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<5>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<4>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<3>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<2>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<1>

MEM_B_CS_L<0>

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<43>

MEM_A_ODT<1>

MEM_A_DQ<8>

MEM_A_DQ<9>


MCP Memory Interface

BGA

OMIT

MCP7AMCP7ABGA

OMIT

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

32 101

32 101

32 101

32 101

32 101

32 101

33 101

33 101

33 101

33 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

32 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

31 101

31 101

31 101

31 101

31 101

31 101

33 101

33 101

33 101

33 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

31 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

33 101

8

8 8

8

www.bblianmeng.com

www.vinafix.vn

MRESET0*

MCLK0B_0_P

MCLK0B_1_P MCLK1B_1_P

MCLK1B_2_P

GND

MCKE1B_0

MCKE1B_1

MCLK0B_2_N

MCLK0B_2_P

MCLK1B_0_N

MCLK1B_0_P

MCLK1B_1_N

MCS0B_0* MCS1B_0*

MCS1B_1*

MODT0B_1 MODT1B_1

V1P1_PLL_DP

V1P8_MEM_VDDPGND

MEM_COMP_1P8V

MEM_COMP_GND

V1P1_PLL_XREF_XS

V1P1_PLL_CORE

V1P1_PLL_V

MCKE0B_1

MODT0B_0

MCLK0B_0_N

MCLK0B_1_N

MODT1B_0

MCLK1B_2_N

MCS0B_1*

MCKE0B_0

MEMORY CONTROL 1B

MEMORY CONTROL 0B

(4 OF 11)

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA

12 mA


19 mA

39 mATP or NC for DDR2.

87 mA (A01)

16 OF 110

051-7863

A.0.0


AR16

AV16

AP24

AP20

AN22

BC29

AN16

AM29

AM27

AM25

AP16

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AT17

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AN24

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AN20

AM17

T27

T28

U28

U27AY32

BC13

AY16

AN15

AN17

AM41

AN41

BA13

BC16

AR15

AU17

BA41

BB41

AY23

BA23

BA20

AY20

AU33

AU34

BB24

BC24

BA21

BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

2

1R1611

2

1R1610

MCP_MEM_COMP_GND

MCP_MEM_COMP_VDD

MEM_B_CS_L<2>

MEM_B_CLK_N<3>

MEM_B_CLK_P<3>


PP1V05_S0_MCP_PLL_CORE

TP_MEM_A_CLK5N

MEM_A_CLK_N<4>

MEM_A_ODT<2>

MEM_A_CS_L<2>


MEM_A_CKE<2>

MEM_A_CS_L<3>

TP_MEM_B_CLK5N

MEM_B_ODT<2>

MEM_A_CLK_N<3>

MEM_A_CKE<3>

MEM_B_ODT<3>MEM_A_ODT<3>

MEM_B_CS_L<3>

MEM_B_CLK_N<4>

TP_MEM_A_CLK5P

MEM_B_CKE<2>

TP_MEM_B_CLK5P

MEM_B_CLK_P<4>MEM_A_CLK_P<4>

MEM_A_CLK_P<3>

MEM_B_CKE<3>

MCP_MEM_RESET_L

MCP MEMORY CNTRL & MISCSYNC_MASTER=K22 SYNC_DATE=09/02/2009

33

402

1/16W1%

MF-LF

40.2

MF-LF402

1/16W

40.21%

OMIT

BGAMCP7A

101

101

32 101

33 101

33 101

6 16 25 30

25

8

33 101

31 101

31 101

6 16 25 30

31 101

31 101

8

32 101

33 101

31 101

32 101 31 101

32 101

33 101

8

32 101

8

33 101 33 101

33 101

32 101

www.bblianmeng.com

www.vinafix.vn

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

PEB_CLKREQ*/GPIO_49

PEB_PRSNT*

PE0_RX13_N

PE0_RX14_P

PEE_CLKREQ*/GPIO_16

V1P1_PEX_AVDD0

V1P1_PEX_AVDD1

V1P1_PEX_DVDD0

V1P1_PEX_DVDD1

V1P1_PLL_PEX

PE_WAKE*

PE0_PRSNT_16* PE0_REFCLK_N

PE0_REFCLK_P

PE0_RX0_N

PE0_RX0_P

PE0_RX1_N

PE0_RX1_P

PE0_RX10_N

PE0_RX10_P

PE0_RX11_N

PE0_RX11_P

PE0_RX12_N

PE0_RX12_P

PE0_RX13_P

PE0_RX14_N

PE0_RX15_N

PE0_RX15_P

PE0_RX2_N

PE0_RX2_P

PE0_RX3_N

PE0_RX3_P

PE0_RX4_P

PE0_RX6_N

PE0_RX6_P

PE0_RX7_N

PE0_RX7_P

PE0_RX8_N

PE0_RX8_P

PE0_RX9_N

PE0_RX9_P

PE0_TX0_N

PE0_TX0_P

PE0_TX1_N

PE0_TX1_P

PE0_TX10_P

PE0_TX11_N

PE0_TX11_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_N

PE0_TX13_P

PE0_TX14_N

PE0_TX14_P

PE0_TX15_N

PE0_TX15_P

PE0_TX2_N

PE0_TX2_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_N

PE0_TX4_P

PE0_TX5_N

PE0_TX5_P

PE0_TX6_N

PE0_TX6_P

PE0_TX7_N

PE0_TX7_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_N

PE0_TX9_P

PE1_REFCLK_N

PE1_REFCLK_P

PE1_RX0_N

PE1_RX0_P

PE1_RX1_N

PE1_RX1_P

PE1_RX2_N

PE1_RX2_P

PE1_RX3_N

PE1_RX3_P

PE1_TX0_N

PE1_TX0_P

PE1_TX1_N

PE1_TX1_P

PE1_TX2_N

PE1_TX2_P

PE1_TX3_N

PE1_TX3_P

PE3_REFCLK_N

PE3_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_N

PE6_REFCLK_P

PEC_CLKREQ*/GPIO_50

PEC_PRSNT*

PED_CLKREQ*/GPIO_51

PED_PRSNT*

PEE_PRSNT*/GPIO_46

PEF_CLKREQ*/GPIO_17

PEF_PRSNT*/GPIO_47

PEX_CLK_COMP

PEX_RST0*

PE0_RX5_P

PE0_RX5_N

PE0_RX4_N

PE0_TX10_N

PE2_REFCLK_N

PE2_REFCLK_P

PEG_PRSNT*/GPIO_48

PEG_CLKREQ*/GPIO_18

PCI EXPRESS

(5 OF 11)

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU


84 mA (A01)

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Minimum 1.025V for Gen2 support

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Int PU

Int PU

Int PU

57 mA (A01, DVDD0 & 1)


Int PU

17 OF 110

051-7863

A.0.0


T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

R12

P12

M12

AB12

AA12

W12

V12

AD12

U12

T12

N12

AC12

Y12

K11

A11

M19

M17

M18

M16

L18

L16

B10

M15

C10

E8

D9

D5

F17

N14

M14

L14

K14

J13

H13

G13

F13

J11

J10

B6

C6

A7

B7

B8

A8

D8

C8

H7

G7

F9

E9

H9

G9

K9

J9

G11

F11

H3

H2

G3

H4

F3

F4

E2

F2

D2

E1

C1

D1

B3

B2

A4

A3

C4

B4

M2

M1

M4

M3

L4

L3

K2

K3

J2

J3

H1

J1

C5

D4

L11

L10

J5

J4

J7

J6

G5

H5

C3

D3

E4

E3

E5

F5

E6

F6

D7

C7

N5

N4

N7

N6

N9

P9

N11

N10

L7

L6

L9

L8

F7

E7

E11

D11C9

U1400

2

1R1710

CARDREADER_RESET

GMUX_JTAG_TCK_L

AUD_IP_PERIPHERAL_DET

TP_PE4_PRSNT_L

=PP1V05_S0_MCP_PEX_DVDD0

PCIE_MINI_D2R_P

PCIE_WAKE_L

PCIE_EXCARD_PRSNT_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

MINI_CLKREQ_L

PEG_PRSNT_L

=PEG_D2R_N<15>

=PEG_D2R_P<15>

PCIE_FW_PRSNT_L

TP_PE4_CLKREQ_L

GMUX_JTAG_TDO

PCIE_MINI_D2R_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

TP_PCIE_PE4_D2RN

PCIE_EXCARD_R2D_C_NPCIE_EXCARD_D2R_N


PP1V05_S0_MCP_PLL_PEX

MCP_PEX_CLK_COMP

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_D2R_P<0>

=PP1V05_S0_MCP_PEX_AVDD0

PCIE_MINI_PRSNT_L

=PEG_D2R_N<13>

=PEG_D2R_P<14>


PEG_CLK100M_N

PEG_CLK100M_P

=PEG_D2R_N<0>

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<10>

=PEG_D2R_P<10>

=PEG_D2R_N<11>

=PEG_D2R_P<11>

=PEG_D2R_N<12>

=PEG_D2R_P<12>

=PEG_D2R_P<13>

=PEG_D2R_N<14>

=PEG_D2R_N<2>

=PEG_D2R_P<2>

=PEG_D2R_N<3>

=PEG_D2R_P<3>

=PEG_D2R_P<4>

=PEG_D2R_N<6>

=PEG_D2R_P<6>

=PEG_D2R_N<7>

=PEG_D2R_P<7>

=PEG_D2R_N<8>

=PEG_D2R_P<8>

=PEG_D2R_N<9>

=PEG_D2R_P<9>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<13>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<5>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<6>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<9>

=PEG_R2D_C_P<9>

PCIE_CLK100M_MINI_N

PCIE_CLK100M_MINI_P

PCIE_EXCARD_D2R_P

TP_PCIE_PE4_D2RP

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_EXCARD_R2D_C_P

TP_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_P







PCIE_RESET_L

=PEG_D2R_P<5>

=PEG_D2R_N<5>

=PEG_D2R_N<4>

=PEG_R2D_C_N<10>

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P


MCP PCIe Interfaces

47

OMIT

BGAMCP7A

67

8

8

9

PLACEMENT_NOTE=Place within 12.7mm of U1400

NO STUFF

1/16W1%

MF-LF402

2.37K

9

8

8

34 102

34 102

8

8

41 102

41 102

41 102

41 102

34 102

34 102

8

8

9

34

8

8

41 102

41 102

34

42

9

34 102

34 102

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

8

25 28

8

8

28

25

102

25 28

28

8

8

8

8

8

8

8

8

8

www.bblianmeng.com

www.vinafix.vn

IN

BI

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

BI

XTALIN_TV

RGB_DAC_RSET

MII_COMP_GND

MII_COMP_VDD

V1P1_DUAL_MACPLL

MII_COL/GPIO_20/MSMB_DATA

BUF_25MHZ

DDC_CLK0

DDC_CLK2/GPIO_23

DDC_CLK3

DDC_DATA0

DDC_DATA2/GPIO_24

DDC_DATA3

DP_AUX_CH0_N

DP_AUX_CH0_P

GPIO_6/FERR*/IGPU_GPIO6

GPIO_7/NFERR*/IGPU_GPIO7

HDMI_RSET

HDMI_TXC_N/ML0_LANE3_N

HDMI_TXC_P/ML0_LANE3_P

HDMI_TXD0_N/ML0_LANE2_N

HDMI_TXD0_P/ML0_LANE2_P





HDMI_VPROBE

HPLUG_DET2/GPIO_22

HPLUG_DET3

IFPA_TXC_N

IFPA_TXC_P

IFPA_TXD0_N

IFPA_TXD0_P

IFPA_TXD1_N

IFPA_TXD2_N

IFPA_TXD2_P

IFPA_TXD3_N

IFPA_TXD3_P

IFPAB_RSET

IFPAB_VPROBE

IFPB_TXC_N

IFPB_TXC_P

IFPB_TXD4_N

IFPB_TXD4_P

IFPB_TXD5_N

IFPB_TXD5_P

IFPB_TXD6_N

IFPB_TXD6_P

IFPB_TXD7_N

IFPB_TXD7_P

LCD_BKL_CTL/GPIO_57

LCD_BKL_ON/GPIO_59

LCD_PANEL_PWR/GPIO_58

MII_RESET*

MII_RXER/GPIO_36

MII_VREF

V3P3_DUAL_RMGT0

V3P3_DUAL_RMGT1

V1P0_DUAL_RMGT_0

V1P0_DUAL_RMGT_1

V3P3_PLL_HDMI

V3P3_PLL_IFPAB

V3P3_RGBDAC_VDD

V3P3_TVDAC_VDD

V1P1_HDMI_VDD

V1P8_IFPA_VDD

V1P8_IFPB_VDD

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB_DAC_RED

RGB_DAC_VREF

RGB_DAC_VSYNC

MII_MDC

MII_MDIO

MII_PWRDWN/GPIO_37

MII_RXCLK

MII_RXDV

MII_RXD0

MII_RXD1

MII_RXD2

MII_RXD3MII_TXD0

MII_TXD1

MII_TXD2

TV_DAC_BLUE

TV_DAC_GREEN

TV_DAC_HSYNC/GPIO_44

TV_DAC_RED

TV_DAC_RSET

TV_DAC_VREF

TV_DAC_VSYNC/GPIO_45

XTALOUT_TV

MII_TXEN

MII_TXCLK

MII_TXD3

RGB_DAC_GREEN

IFPA_TXD1_P

MII_CRS/GPIO_21/MSMB_CLK

MII_INTR/GPIO_35

DACS

LAN

FLAT PANEL

(6 OF 11)

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

LVDS: Power +VDD_IFPx at 1.8V

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: HDMI port requires level-shifting. IFP interface can

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

TP_DP_IG_AUX_CHP/N

TMDS_IG_HPD

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N

=MCP_HDMI_TXD_P/N<0>



be used to provide HDMI or dual-channel TMDS without

DP_IG_DDC_DATA

DP_IG_DDC_CLK

Interface Mode

level-shifters.

DP_IG_AUX_CH_P/N

NOTE: 20K pull-down required on DP_HPD_DET.

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This

avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

TMDS_IG_DDC_DATA

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

8 mA

8 mA

16 mA (A01)

95 mA (A01)


TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_ML_P/N<0>

(See below)

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low

by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

18 OF 110

051-7863

A.0.0


D38

C38

K32

J32

M28

M29

K24

J24

M26

M27

T25

T23

V23

U23

C37

A35

E36

A36

D36

B36

C36

A41

B38

C39

B39

A40

A39

B40

E28

C26

D25

C25

C24

B24

D24F23

C22

A24

E24

B23

C23

A23

J23

G23

C21

D21

J22

B22

C27

B27

B26

F40

E37

G39

N30

M30

L30

K30

L29

K29

J29

H29

L31

K31

G31

E32

B34

C34

D33

C33

D32

C32

B32

A32

B35

C35

F31

C31

J30

J33

H33

F33

G33

G35

F35

D35

E35

J31

B15

E16

D43

C43

E31

B30

A31

D31

C30

B31

E23

U1400

2

1R1820

2

1R1860

2

1R1861

2

1R1850

2

1R1811

2

1R1810

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_N<1>

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

TP_ENET_INTR_L

=MCP_MII_CRS

LVDS_IG_A_DATA_P<1>

TP_MCP_RGB_GREEN

ENET_TXD<3>

ENET_CLK125M_TXCLK

ENET_TX_CTRL

MCP_CLK27M_XTALOUT

CRT_IG_VSYNC

MCP_TV_DAC_RSET

CRT_IG_R_C_PR

CRT_IG_HSYNC

CRT_IG_G_Y_Y

CRT_IG_B_COMP_PB

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_RX_CTRL

ENET_CLK125M_RXCLK

TP_ENET_PWRDWN_L

ENET_MDIO

ENET_MDC

TP_MCP_RGB_VSYNC

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_RED

TP_MCP_RGB_HSYNC

TP_MCP_RGB_BLUE

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD

PP3V3_S0_MCP_DAC

PP3V3_S0_MCP_VPLL



MCP_MII_VREF

=MCP_MII_RXER

ENET_RESET_L

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

LVDS_IG_BKL_PWM

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK_N

=MCP_HDMI_HPD

=DVI_HPD_GMUX_INT

MCP_HDMI_VPROBE

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

MCP_HDMI_RSET

DP_IG_CA_DET

LPCPLUS_GPIO

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

=MCP_HDMI_DDC_DATA

LVDS_IG_DDC_DATA

MCP_DDC_DATA0

=MCP_HDMI_DDC_CLK

LVDS_IG_DDC_CLK

MCP_DDC_CLK0

MCP_CLK25M_BUF0_R

=MCP_MII_COL

PP1V05_ENET_MCP_PLL_MAC

MCP_MII_COMP_VDD

MCP_MII_COMP_GND

TP_MCP_RGB_DAC_RSET

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

MCP Ethernet & GraphicsSYNC_DATE=09/02/2009SYNC_MASTER=K22

37 104

37 104

37 104

26 102

37 104

26 102

9

9

89

89

89 107

89 107

89 107

89 107

89 107

37 104

89 107

89 107

89 107

89 107

89 107

89 107

89 107

89 107

89 107

89 107

37 104

89 107

89 107

89 107

89 107

89 107

37 104

OMIT

BGAMCP7A

1/16WMF-LF402

47K5%

51

100K

1/16W5%

MF-LF402

MF-LF1/16W

100K5%

402

MF-LF

5%1/16W

402

10K

9

9

9

8

8

93

1/16W1%

402

49.9

MF-LF

49.9

402MF-LF1/16W

1%

8

8

8

8

8

26 107

26 107

9

9

93 107

93 107

9

9

9

9

9

9

9

9

89

89

89

8

8

37

37 104

37 104

37 104

37 104

37 104

37 104

38 104

37 104

25

6 19 21

18 25 38

6 20

8

8

8

8

26

26

26

26

25 38

18 25 38

25

104

104

www.bblianmeng.com

www.vinafix.vn

OUT

OUT

BI

BI

BI

BI

IN

BI OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

(7 OF 11)

PCI

GND

LPC

PCI_AD28

PCI_REQ4*/GPIO_52/RS232_SIN*

PCI_REQ2*/GPIO_40/RS232_DSR*

PCI_AD31

LPC_PWRDWN*/GPIO_54/EXT_NMI*

LPC_RESET0*

LPC_AD1

LPC_AD2

LPC_AD3

LPC_CLK0

LPC_FRAME*

PCI_TRDY*

PCI_STOP*

PCI_SERR*

PCI_RESET1*

PCI_RESET0*

PCI_REQ3*/GPIO_38/RS232_CTS*

PCI_REQ1*/FANRPM2

PCI_REQ0*

PCI_PME*/GPIO_30

PCI_PERR*/GPIO_43/RS232_DCD*

PCI_PAR

PCI_IRDY*

PCI_INTZ*

PCI_INTY*

PCI_INTX*

PCI_INTW*

PCI_GNT4*/GPIO_53/RS232_SOUT*

PCI_GNT3*/GPIO_39/RS232_RTS*

PCI_GNT2*/GPIO_41/RS232_DTR*

PCI_GNT1*/FANCTL2

PCI_GNT0*

PCI_FRAME*

PCI_DEVSEL*

PCI_CLKRUN*/GPIO_42

PCI_CLKIN

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CBE3*

PCI_CBE2*

PCI_CBE1*

PCI_CBE0*

PCI_AD30

PCI_AD29

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

PCI_AD22

PCI_AD21

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD0

LPC_SERIRQ

LPC_DRQ0*

LPC_AD0

GND GND

LPC_DRQ1*/GPIO_19




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU

Int PU

Int PU

Int PU (S5)

19 OF 110

051-7863

A.0.0


Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2

AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

21R195321R195221R195121R1950

21R1960

2

1R1961

21R199221R1994

21R199021R1991

21R1989

2

1R1910

CRTMUX_SEL_TV_L

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

MCP_RS232_SIN_L

=PP3V3_S0_MCP_GPIO

FW_PME_L

LPC_AD_R<0>

TP_LPC_DRQ0_L

LPC_SERIRQ

MCP_DEBUG<0>

MCP_DEBUG<1>

MCP_DEBUG<2>

MCP_DEBUG<3>

MCP_DEBUG<4>

MCP_DEBUG<5>

MCP_DEBUG<6>

MCP_DEBUG<7>

TP_PCI_AD<8>

TP_PCI_AD<9>

TP_PCI_AD<10>

TP_PCI_AD<11>

TP_PCI_AD<12>

TP_PCI_AD<13>

TP_PCI_AD<14>

TP_PCI_AD<15>

TP_PCI_AD<16>

TP_PCI_AD<17>

TP_PCI_AD<18>

TP_PCI_AD<19>

TP_PCI_AD<20>

TP_PCI_AD<21>

TP_PCI_AD<22>

TP_PCI_AD<23>

TP_PCI_AD<24>

TP_PCI_AD<25>

TP_PCI_AD<27>

TP_PCI_AD<29>

TP_PCI_AD<30>

TP_PCI_C_BE_L<0>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<3>

TP_PCI_CLK0

TP_PCI_CLK1

PCI_CLK33M_MCP_R

PM_CLKRUN_L

TP_PCI_DEVSEL_L

TP_PCI_FRAME_L

TP_PCI_GNT1_L

GMUX_JTAG_TMS

GMUX_JTAG_TDI

MCP_RS232_SOUT_L

TP_PCI_INTW_L

TP_PCI_INTX_L

TP_PCI_INTY_L

TP_PCI_INTZ_L

TP_PCI_IRDY_L

TP_PCI_PAR

TP_PCI_PERR_L

PM_LATRIGGER_L

PCI_REQ0_L

PCI_REQ1_L

AUD_IPHS_SWITCH_EN

MEM_VTT_EN_R

TP_PCI_RESET1_L

TP_PCI_SERR_L

TP_PCI_STOP_L

TP_PCI_TRDY_L

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_RESET_L

LPC_PWRDWN_L

TP_PCI_AD<31>

CRTMUX_SEL_TV_L

MCP_RS232_SIN_L

TP_PCI_AD<28>

TP_PCI_GNT0_L

PCI_CLK33M_MCP

TP_PCI_AD<26>


MCP PCI & LPC

OMIT

BGAMCP7A

8

8

68

13

13

13

13

13

13

13

13

13

19

19

42

9

225% 1/16W MF-LF 402

402MF-LF1/16W5%22 40222

MF-LF1/16W5%

40222

MF-LF1/16W5%

5%22

402MF-LF1/16W

10K5%1/16W

402MF-LF

19

402MF-LF1/16W5%8.2K

5%8.2K

1/16W MF-LF 402

8.2K5% 1/16W MF-LF 4028.2K5% 1/16W MF-LF 402

8.2K5% 1/16W MF-LF 402

225%1/16W

402MF-LF

PLACEMENT_NOTE=Place close to pin R8

49 51

9 103 49 51

49 51

49 51 103

49 51 103

49 51 103

49 51 103

9 103

49 51 103

19

19 103

19 103

19

19

6 18 21

103

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

103

8

8

8

8

8

8

8

8

8

8

19 103

19 103

8

8

8

8

103

103

103

103

8

8

8

103

8

www.bblianmeng.com

www.vinafix.vn

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

USB9_P

USB9_N

USB8_P

USB8_N

USB7_P

USB7_N

USB6_P

USB6_N

USB5_P

USB5_N

USB4_P

USB4_N

USB3_P

USB3_N

USB2_P

USB2_N

USB11_P

USB11_N

USB10_P

USB10_N

USB1_P

USB1_N

USB0_P

USB_RBIAS_GND

USB_OC3*/GPIO_28/MGPIO

USB_OC2*/GPIO_27/MGPIO

USB_OC1*/GPIO_26

USB_OC0*/GPIO_25

SATA_TERMP

SATA_C1_RX_P

SATA_C1_RX_N

SATA_C0_TX_P

SATA_C0_TX_N

SATA_C0_RX_P

SATA_C0_RX_N

SATA_B1_TX_P

SATA_B1_TX_N

SATA_B1_RX_P

SATA_B1_RX_N

SATA_B0_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_RX_N

SATA_A1_TX_P

SATA_A1_TX_N

SATA_A1_RX_P

SATA_A1_RX_N

SATA_A0_TX_N

SATA_A0_RX_N

V3P3_PLL_USB

V1P1_SATA_DVDD1

V1P1_SATA_DVDD0

V1P1_SATA_AVDD1

V1P1_SATA_AVDD0

GND

SATA_A0_TX_P

SATA_C1_TX_N

SATA_C1_TX_P

SATA_LED*

V1P1_PLL_SATA

USB0_N

SATA_A0_RX_P

USB

SATA

(8 OF 11)

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

19 mA (A01)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)


Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

External D

External A

Camera

Bluetooth

IR

External B

External C


43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.


ExpressCard

20 OF 110

051-7863

A.0.0


L28

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AE16

A27

H21

J21

K21

L21

H25

J25

K25

L25

D27

E27

F27

G27

J26

J27

K27

L27

F29

G29

A28

B28

C28

D28

K23

L23

F25

G25

C29

D29

AE3

E12

AP3

AP2

AN2

AN3

AN1

AM1

AM3

AM2

AM4

AL3

AK3

AL4

AK2

AJ3

AJ1

AJ2

AJ11

AJ10

AK9

AJ9

AJ7

AJ6

AJ4

AJ5

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

U1400

2

1R2050

2

1R2051

2

1R2052

2

1R2053

2

1R2060

2

1R2010

TP_USB_10N

USB_SDCARD_P

USB_SDCARD_N

USB_EXTB_N

TP_SATA_D_D2RN

SATA_ODD_D2R_N

USB_EXTC_P

USB_EXTC_N

USB_EXCARD_P

USB_EXCARD_N

USB_EXTB_P

USB_BT_N

USB_TPAD_P

USB_IR_P

USB_IR_N

USB_CAMERA_P

USB_CAMERA_N

USB_EXTD_P

USB_EXTD_N

TP_USB_10P

USB_MINI_P

USB_MINI_N

USB_EXTA_P

MCP_USB_RBIAS_GND

MCP_SATA_TERMP

TP_SATA_F_D2RP

TP_SATA_F_D2RN

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RP

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_C_D2RP

TP_SATA_C_D2RN

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_N



=PP1V05_S0_MCP_SATA_AVDD1


SATA_HDD_R2D_C_P

TP_SATA_F_R2D_CN

TP_SATA_F_R2D_CP

TP_MCP_SATALED_L

PP1V05_S0_MCP_PLL_SATA

USB_EXTA_N

SATA_HDD_D2R_P

USB_BT_P

USB_TPAD_N

=PP3V3_S5_MCP_GPIO

PP3V3_S0_MCP_PLL_USB

EXCARD_OC_L

USB_EXTC_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L


MCP SATA & USB

47 103

47 103

OMIT

BGAMCP7A

45 102

45 102

45 102

45 102

45 102

45 102

45 102

45 102

8.2K5%

MF-LF1/16W

402

MF-LF402

1/16W

8.2K5%

8.2K5%

MF-LF1/16W

402

402

1/16WMF-LF

8.2K5%

402

1/16W1%

MF-LF

806

2.49K

402

1/16W1%

MF-LF

9 46

46

46

46 103

46 103

8

8

46 103

46 103

47 103

47 103

8

8

47 103

47 103

47 103

47 103

46 103

46 103

8

8

46 103

46 103

8

8

103

102

28

6 28

28

28

45

25

6 18

25

www.bblianmeng.com

www.vinafix.vn

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN OUT

IN

IN

OUT

IN

EXT_SMI*/GPIO_32

V1P1_PLL_NV_H

A20GATE

BUF_SIO_CLK

CPU_DPRSLPVR

CPU_VLD CPUVDD_EN

FANCTL0/GPIO_61

FANCTL1/GPIO_62

FANRPM0/GPIO_60

FANRPM1/GPIO_63

GPIO_1/PWRDN_OK/SPI_CS1

GPIO_12/SUS_STAT*/ACCLMTR_EXT_TRIG

HDA_BITCLK

HDA_RESET*

HDA_SDATA_IN0

GPIO_2/HDA_SDATA_IN1/PS2_KB_CLK

GPIO_3/HDA_SDATA_IN2/PS2_KB_DATA

HDA_SDATA_OUT

HDA_SYNC

INTRUDER*

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST*

KBRDRSTIN*

LID*

LLB*

GPIO_13/MCP_VID0

GPIO_14/MCP_VID1

GPIO_15/MCP_VID2

V3P3_DUAL_HDA_0

V3P3_DUAL_HDA_1

V1P1_PLL_SP_SPREF

PKG_TEST

PS_PWRGD

PWRBTN*

PWRGD_SB

RSTBTN*

RTC_RST*

SIO_PME*

SLP_RMGT*

SLP_S3*

SMB_ALERT*/GPIO_64

SMB_CLK0

SMB_CLK1/MSMB_CLK

SMB_DATA0

SMB_DATA1/MSMB_DATA

GPIO_11/SPI_CLK

GPIO_10/SPI_CS0

GPIO_8/SPI_DI

GPIO_9/SPI_DO

SPKR

SUS_CLK/GPIO_34

TEST_MODE_EN

THERM_DIODE_N

THERM_DIODE_P

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

SLP_S5*

GPIO_5/HDA_DOCK_RST*/PS2_MS_DATA

GPIO_4/HDA_DOCK_EN*/PS2_MS_CLKHDA_PULLDN_COMP

HDA

MISC

(9 OF 11)

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)

Int PU (S5)

17 mA

20 mA37 mA (A01)

7 mA (A01)


HDA Output CapsFor EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

Int PU

25 MHz

42 MHz 0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

1

0

SPI_CLKSPI_DO

0

1

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls

1

1

0

0

LPC_FRAME#

0

1

0

1

Int PD

Int PD

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support

SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

SAFE mode: For ROMSIP

recovery

USER mode: Normal

Connects to SMC for

(MXM_OK for MXM systems)

automatic recovery.Int PU

NC

21 OF 110

051-7863

A.0.0


B19

B16

A19

A16

K16

J16

AE17

AE18

B11

C11

K22

B18

C13

F21

K19

G21

L19

M23

H17

G17

J17

C19

C20

D16

D20

C16

E20

L22

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15G15

K15

A15

E15

B14

C15

L17

K17

J15

J14

L24

M21

M20

L20

L26

D13

C14

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

2

1R2140

2

1R2143

2

1R2154

2

1R2151

2

1R2155

2

1R2156

2

1R2157

2

1R2141

2

1R2142

2

1R21472

1C2172

2

1C2170

2

1 C2173

2

1 C2171

2

1R2150

2

1R2110

21

R2172

2

1R2181

2

1R2180

2

1R2160

2

1R2163

21

R2173

21

R2171

21

R2170

2

1R2190

2

1R2120

2

1R2121

RTC_RST_L

MCP_VID<2>

SMBUS_MCP_0_DATA

SMBUS_MCP_1_DATA

AP_PWR_EN

ARB_DETECT

JTAG_MCP_TCK

JTAG_MCP_TRST_L

=PP3V3_S0_MCP_GPIO

MCP_VID<0>

MCP_VID<1>

MCP_VID<2>

PM_PWRBTN_L

MCP_CPU_VLD

=PP3V3_S3_MCP_GPIO

TP_MCP_BUF_SIO_CLK

=PP3V3_S0_MCP

SMC_IG_THROTTLE_L

MEM_EVENT_L

HDA_SYNC

ARB_DETECT

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R


PP3V3_G3_RTC

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

MCP_GPIO_4

AUD_I2C_INT_L

AP_PWR_EN

MCP_HDA_PULLDN_COMP MCP_GPIO_4

AUD_I2C_INT_L

PM_SLP_S4_L

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALIN

MCP_THMDIODE_P

MCP_THMDIODE_N

MCP_TEST_MODE_EN

PM_CLK32K_SUSCLK_R

MCP_SPKR

SPI_MOSI_R

SPI_MISO

SPI_CS0_R_L

SPI_CLK_R

SMBUS_MCP_1_CLK

SMBUS_MCP_0_CLK

PM_SLP_S3_L

PM_SLP_RMGT_L

SMC_WAKE_SCI_L

PM_SYSRST_DEBOUNCE_L

PM_RSMRST_L


MCP_VID<1>

MCP_VID<0>

PM_BATLOW_L

TP_MCP_LID_L

TP_MCP_KBDRSTIN_L

JTAG_MCP_TMS

JTAG_MCP_TDO

JTAG_MCP_TDI

SM_INTRUDER_L

HDA_SYNC_R

HDA_SDOUT_R

TP_MLB_RAM_VENDOR

TP_MLB_RAM_SIZE

HDA_SDIN0

HDA_RST_R_L

HDA_BIT_CLK_R

SMC_ADAPTER_EN

=SPI_CS1_R_L_USE_MLB

SMC_IG_THROTTLE_L

MEM_EVENT_L

ODD_PWR_EN_L

MCP_CPUVDD_EN

TP_SB_A20GATE

PP1V05_S0_MCP_PLL_NV

SMC_RUNTIME_SCI_L

MCP_PS_PWRGD


MCP HDA & MISC

51 103

51 61 103

51 61 103

28

49

49

70

28 103

28 103

28 103

28 103

OMIT

BGAMCP7A

21 50

50

402

1/16WMF-LF

5%10K 10K

5%1/16W

402MF-LF

402

100K5%

MF-LF1/16W

100K

1/16W5%

MF-LF402

MF-LF

5%22K

1/16W

402 402

1/16WMF-LF

5%22K

402

1/16WMF-LF

5%22K

10K5%

MF-LF1/16W

402MF-LF402

1/16W5%10K

100K5%

MF-LF1/16W

402

21 31 32 49 55

49 50

99

21 68

8

CERM402

5%10PF

50VCERM402

5%10PF

50V

CERM402

5%10PF

50VCERM402

5%50V

10PF

13

13

13

13

13

10K5%

MF-LF1/16W

402

402

1%1/16WMF-LF

49.9

51

MF-LF1/16W

22

5%

402

1/16W

BOOT_MODE_USER

MF-LF402

10K5%

1/16W

402

BOOT_MODE_SAFE

MF-LF

10K5%

402

1/16W5%8.2K

MF-LF

1/16W

10K5%

402MF-LF

402

1/16WMF-LF

22

5%

22

402

1/16W5%

MF-LF

1/16W

22

5%

402MF-LF

49

49

9 103

1/16W1%1K

MF-LF402

1/16W

402MF-LF

49.9K1%

49.9K

402

1%1/16WMF-LF

62 103

62 103

62 103

62 103

62 103

49

70

55 108

21

21 74

21 74

55 108

21 74

52

13 52 106

52

13 52 106

70 102

9 102

51 61 103

21

6 18 19

21 74

21 74

21 74

6

8

6 22 25

21 50

21 31 32 49 55

21

21 103

21 103

21 103

21 103

6 21 25

22 28

21

21 68

21

103 21

6 21 25

8

21 103

21 103

9

8

21 103

21 103

8

25

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V1P0_CORE_VDD

V3P3

V3P3_DUAL_USB

V3P3_DUAL

V3P3_VBATV1P0_VDD_AUXC

V1P2_CPU_VTT

V1P2_CPUCLK_VTT

(10 OF 11)(11 OF 11)

GNDGND




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

23065 mA (A01, 1.2V)

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

80 uA (S0)


10 uA (G3)

16 mA 266 mA (A01)

1182 mA (A01)

450 mA (A01)

22 OF 110

051-7863

A.0.0


T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

AG32

AL31

AD32

AK32

AK31

W32

V32

AJ32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

AH32

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

AE32

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

AF32

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

P31

R32

V21

U21

T21

AC21

AA16

AC20

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AC19

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AC18

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AC17

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AC16

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AA28

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

AA27

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AA26

AA25

U1400

=PP1V05_S0_MCP_FSB=PPVCORE_S0_MCP

=PP3V3_S0_MCP

=PP3V3_S5_MCP

PP3V3_G3_RTC



MCP Power & Ground

BGA

OMIT

MCP7A MCP7ABGA

OMIT

6 14 25 6 25

6 21 25

6 25

21 28

6 25

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36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

23 OF 110

051-7863

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BLANK PAGE

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36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

24 OF 110

051-7863

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SYNC_MASTER=K22 SYNC_DATE=09/02/2009

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OUT




36

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PAGE


A

B

C

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8 7 5 4 2 1

REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD

QTY DESCRIPTIONPART#TABLE_5_ITEM

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP SATA (DVDD) PowerNV: 1X 4.7UF 0402, 2X 1UF 0402, 2X 0.1UF 0402 (6.9UF)

84 mA (A01)

270 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

19 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

5 mA (A01)

87 mA (A01)

562 mA (A01)

84 mA (A01)

BALLS FOR AVDD0 SO 80% OFCAPACITANCE ON AVDD0

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)


450 mA (A01)

57 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

83 mA (A01)

131 mA (A01)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

MCP 3.3V Ethernet Power

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

4771 mA (A01, DDR3)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 1.05V AUX Power

105 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

MCP PCIE (DVDD) Power

APPLE: 4X 4.7UF 0402, 4X 1UF 0402, 6X 0.1UF 0402 (23.4 UF)

MCP Core Power

DIFFERENT THAN ON T18

PEX_AVDD RAIL SPLIT BASEDON IG VS. EG. 12 OUT OF 15

PEX_DVDD RAIL SPLIT BASEDON IG VS. EG. 8 OUT OF 10

CAPACITANCE ON DVDD0BALLS FOR DVDD0 SO 80% OF

Apple: 7x 2.2uF 0402 (15.4 uF)

43 mA (A01) 333 mA (A01)

MCP 1.05V RMGT Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

K50: 2X 2.2UF 0402, 2X 1UF 0402, (6.4 UF)

25 OF 110

051-7863

A.0.0


2

1C2597

2

1C2528

2

1 C2529

2

1 C2596

2

1 C2587

2

1 C2585

2

1 C2583

2

1 C2581

2

1 C2518

2

1 C2521

2

1R2591

2

1 C2591

2

1R2590

21

L2595

2

1C2595

2

1 C2590

2

1 C2589

2

1 C2560

2

1 C2525

2

1 C2526

21

L2580

2

1C2501

2

1C2500

21

L2555

21

L2586

21

L2588

21

L2584

21

L2582

21

L2575

21

L2570

2

1C2580

2

1 C2564

2

1 C2562

2

1C2540

2

1 C2541

2

1 C2542

2

1 C2543

2

1 C2544

2

1 C2545

2

1 C2546

2

1 C2547

2

1 C2548

2

1 C2549

2

1 C2550

2

1 C2551

2

1 C2552

2

1 C2553

2

1 C2575

2

1 C2576

2

1 C2573

2

1 C2574

2

1 C2570

2

1C2520

2

1 C2571

2

1 C25722

1C2515

2

1 C2516

2

1 C2517

2

1 C2530

2

1 C2531

2

1 C2532

2

1 C2533

2

1 C2534

2

1 C2535

2

1 C2536

2

1 C2512

2

1 C2513

2

1 C2508

2

1 C2509

2

1 C2510

2

1 C2511

2

1 C2504

2

1 C2505

2

1 C2506

2

1 C2507

2

1C2502

2

1 C2555

2

1C2586

2

1C2584

2

1C2588

2

1C2582

2

1C2503

=PP1V05_S0_MCP_PEX_DVDD0=PP1V05_S0_MCP_PEX_DVDD


=PPVCORE_S0_MCP

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MMPP1V05_S0_MCP_PEX_AVDD

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_MCP_SATA_DVDD


=PP1V05_S0_MCP_FSB



VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_USB


MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

PP1V05_S0_MCP_PLL_PEX

PP1V05_ENET_MCP_PLL_MACMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM

=PP1V05_ENET_MCP_PLL_MAC


MCP_MII_VREF


=PP3V3_S5_MCP =PP3V3_ENET_MCP_RMGT


MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_SATA


PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V


PP1V05_S0_MCP_SATA_AVDDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

=PP1V05_S0_MCP_AVDD_UF

=PP3V3_S0_MCP =PP3V3_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

PP1V05_S0_MCP_PLL_FSB

116S0004 RES,0,5%,0402 IG2 C2574,C2518

MCP Standard DecouplingSYNC_DATE=09/02/2009SYNC_MASTER=K22

4V20%

402X5R

4.7UF

X5R402

20%4.7UF

4V

4.7uF4V

X5R402

20%

CERM

0.1uF

402

20%10V

402

20%4VX5R

4.7UF

402

20%

X5R4V

4.7UF

402

20%4VX5R

4.7UF

402X5R4V20%4.7UF

X5R402

4.7UF4V20%

2.2UF20%

CERM6.3V

402-LF

MXM

CERM402

10V20%0.1uF

18

MF-LF

1%1/16W

1.47K

402

0.1UF

CERM

20%10V

402

1.47K

1/16W1%

MF-LF402

30-OHM-1.7A

0402

20%4.7UF

4VX5R402

4VX5R

2.2UF20%

402X5R4V20%

402

4.7UF

6.3V

2.2UF20%

402-LFCERM

CERM

20%0.1uF10V

402CERM

20%0.1uF10V

402

0402

30-OHM-1.7A

4V

4.7UF20%

X5R402

4V20%

X5R402

4.7UF

30-OHM-1.7A

0402

0402

30-OHM-1.7A

30-OHM-1.7A

0402

30-OHM-1.7A

0402

0402

30-OHM-1.7A

0603

30-OHM-5A

0603

30-OHM-5A

4V

402X5R

20%4.7UF

CERM402-LF

20%2.2UF6.3V

402-LF

6.3V

2.2UF20%

CERM

20%4.7UF

X5R402

4V

0.1UF

CERM

20%10V

402

20%0.1UF10VCERM402

20%10V

402CERM

0.1UF 0.1UF20%

CERM10V

402

0.1UF20%10VCERM402

10V20%

402CERM

0.1UF 0.1UF20%

CERM10V

402

0.1UF20%

CERM10V

402

0.1UF20%

CERM10V

402

6.3V

2.2UF20%

402-LFCERM

2.2UF6.3V20%

402-LFCERM CERM

6.3V

2.2UF20%

402-LF

2.2UF6.3V20%

402-LFCERM

6.3V20%

CERM

2.2UF

402-LFCERM402-LF

20%6.3V

2.2UF

6.3VCERM402-LF

20%2.2UF

MXM MXM

6.3VCERM402-LF

20%2.2UF

402-LFCERM6.3V

2.2UF20%

402

20%4V

4.7UF

X5RCERM402-LF

20%2.2UF6.3V

MXM

2.2UF

CERM402-LF

20%6.3V

MXM2.2UF

402-LF

MXM

6.3VCERM

20%10%1UF

402-1X5R10V

402-1

1UF10%10V

MXM

X5R

CERM402-LF

20%2.2UF6.3V

402-LF

20%6.3VCERM

2.2UF6.3V

2.2UF20%

402-LFCERM

6.3V

2.2UF20%

CERM402-LF

2.2UF6.3V20%

402-LFCERM

6.3V

2.2UF20%

402-LFCERM

402-LFCERM6.3V20%2.2UF

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R402-1

1UF10%

10VX5R

10%

402-1

1UF10%1UF

402-1X5R10V4V

20%

X5R402

4.7UF

402-LF

2.2UF6.3V20%

CERM

4V

4.7UF20%

X5R402

4.7UF20%4V

X5R402

20%4.7UF

4VX5R402

4V

4.7UF20%

X5R402

17 28 6 28

6 16 30

6 22

2828

18 38

6 14 22

6 22

20

17

1838

18 25 38

6 21

6 22 18 25 38

17 28

21

20

6

16

28

6

6 21 22 6

14

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TABLE_5_ITEM








36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

190 mA (A01, 1.8V)

95 mA (A01)


Apple: ???

16 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 110

051-7863

A.0.0


21

R2680

21

R2690

21

R2650

2

1 C2616

2

1 C2641

21

L2640

2

1C2640

2

1C2615

2

1C2630

2

1R2630

2

1C2620

2

1 C2610

2

1R2620

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

MCP_IFPAB_RSET

=PP3V3_S0_MCP_VPLL_UF

POWER_MCP_DACMAKE_BASE=TRUE

PP3V3_S0_MCP_DAC

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_VPLL

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

=PP1V05_S0_MCP_HDMI_VDD_R

PP3V3R1V8_S0_MCP_IFP_VDDMAKE_BASE=TRUE


MAKE_BASE=TRUEPP1V05_S0_MCP_HDMI_VDD


=PP3V3R1V8_S0_MCP_IFP_VDD_R

MCP_HDMI_RSET

MCP_HDMI_VPROBE

MCP Graphics SupportSYNC_MASTER=K22 SYNC_DATE=09/02/2009

MXMC2616RES,0,5%,4021116S0004

C2610 MXMRES,0,5%,402116S0004 1

116S0004 RES,0,5%,4021 C2641 MXM

IG

2.2UF

402-LF

6.3V20%

CERM

1K

402

1/16W1%

MF-LF

402

0

5%

MF-LF1/16W

IG

1/16W5%

402

0

IG

MF-LF

0

402

5%

MF-LF1/16W

10V

402

20%

IG

CERM

0.1UF

0.1uF

402

10V20%

CERM

IG

30-OHM-1.7A

0402

IG

402X5R-CERM

IG

6.3V20%

4.7UF

4V20%

4.7UF

IG

402X5R

NO STUFF

0.1UF20%10VCERM402

MF-LF1/16W

402

1K1%

NO STUFF

NO STUFF

20%10VCERM402

0.1UF

18

18

18 102

6

18

18 102

18

6

6

18 107

18 107

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

27 OF 110

051-7863

A.0.0


BLANK PAGESYNC_MASTER=K22 SYNC_DATE=09/02/2009

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IN OUT

NCNC

IN

OUT

IN

OUT

NCNC

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

10K pull-up to 3.3V S0 inside MCP

RTC Power Sources

Reset Button

Coin-Cell HolderIMAC

PEG POWER ALIAS/OPTION TO GND UNUSED POWER PIN

UNPOWER PEG INTERFACE WHEN IG IS USED

DVDD DOES NOT NEED FILTER

AVDD IS FILTERED ON P25

UNPOWER PEG INTERFACE WHEN IG IS USED

SATA ALIAS/GROUNDING UNUSED DVDD1 AND AVDD1

PLACE AT LEAST 1 CAP NEAR MCP PIN A20

511S0054 fault protection for RTC battery.

NOTE: R2800 and D2800 form the double-

RTC Crystal

MCP 25MHz Crystal

28 OF 110

051-7863

A.0.0


2

1Y2815

41

Y2810

21

R2882

21

R2880

2

1R2898 2

1 C2899

21

R2899

2

1R2816

21

R2815

21

C2816

21

C2815

2

1 C2801

2

1 C2802

1

2

J2800

25

3

6

4

1

D2800

21

R2896

2

1R2811

21

R2810

21

C2811

21

C2810

12

R2800

2

1C2800



RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALOUT

=PP1V05_S0_MCP_PEX_DVDD

MAKE_BASE=TRUEPP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V


MAKE_BASE=TRUE


PP1V05_S0_MCP_PEX_AVDD0



MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PEX_DVDD0

MAKE_BASE=TRUEPP1V05_S0_MCP_SATA_AVDD

=PP1V05_S0_MCP_SATA_DVDD





XDP_DBRESET_L

=PP3V3_S5_RTC_D

PM_SYSRST_L


VOLTAGE=3.3V

PP3V3_G3_RTC


PM_SYSRST_DEBOUNCE_L

VOLTAGE=3.3V

PPVBATT_G3_RTC_RMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

PPVBATT_G3_RTCMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM

SB MiscSYNC_MASTER=K22 SYNC_DATE=09/02/2009

402CERM

10%1UF6.3V

CRITICAL

SM-3-LF25.0000M

CRITICAL

SM-HF

32.768K-12.5PF

MXM

0

402MF-LF1/16W5%

MXM

MF-LF1/16W

402

5%

0

05%

MF-LF

NO STUFF

1/10W

603

SILK_PART=RESET_BTN

49

402

10V

1UF10%

X5R

NO STUFF5%

402

1/16WMF-LF

33

21 103

21 103

5%

MF-LF402

1/16W

10M

NO STUFF1/16W5%

MF-LF

0

402

50VCERM402

5%

20PF

5%50VCERM402

20PF

10VCERM402

20%0.1UF

CERM

20%0.1UF10V

402

21 103

21 103

BB10201-C1403-7H

CRITICAL

SM

SOT-363BAT54DW-X-G

MF-LF402

0

1/16W5%

XDP

5%

402MF-LF1/16W

10M

1/16W5%

0

402MF-LF

50V

12pF

CERM402

5%

CERM50V5%

402

12pF

5%

402

1K

MF-LF1/16W

2111 13

20

20

6 25

25

17

25

25

20

17 25

17

17 25

6 21 22

6 20

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V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

OUT

V-

V+

RESET*

A0A1

A2

SCL

SDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPADIN

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI

OUT

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Place close to J3200.1

PRODUCTION

- =I2C_VREFDACS_SCL

Signal aliases required by this page:

- =PPVTT_S3_DDR_BUF

Required zero ohm resistors when no VREF margining circuit stuffed

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

DAC channel A B A B C

ADDR=0x30(WR)/0x31(RD)

MEM B VREF DQ

Min DAC code 0x00 0x00 0x00 0x00 0x00Max DAC code 0x87 0x87 0x87 0x87 0x55Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 VMax Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

CPU FSB VREFMEM B VREF CAPower aliases required by this page:

Page NotesMEM A VREF DQ MEM A VREF CA

(per DAC LSB)

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

BOM options provided by this page:

VREFMRGN10mA max load

PLACE CLOSE TO U1000



(i.e. not simultaneously) due to current limitation of TPS51116 regulator. SO-DIMM A and SO-DIMM B Vref settings should be margined separately


Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

PLACE CLOSE TO U1000

ADDR=0x98(WR)/0x99(RD)

29 OF 110

051-7863

A.0.0


B4

B1

A4

A1

A2

A3

U2904

21

R2913

21

R2914

21

R2903

21

R2905

21

R2909

21

R2911

B4

B1

A4

A1

A2

A3

U2902

B4

B1

C4

C1

C2

C3

U2902

B4

B1

A4

A1

A2

A3

U2903

B4

B1

C4

C1

C2

C3

U2904

21

R2912

21

R2916

21

R2910

21

R2906

21

R2904

B4

B1

C4

C1

C2

C3

U2903

21

R2915

2

1 C2905

2

1 C2900

2

1 C2901

5

4

2

1

8

7

6

3

10

9

U2900

21

R2908

2

1 C2904

21

R2907

21

R2901

21

R2902

2

1 C2902

2

1 C2903

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2901

VREFMRGN_CPUFSB_BUF0

VREFMRGN_CPUFSB_BUF1 CPU_GTLREF1

VREFMRGN_CPUFSB0

=PP3V3_S3_VREFMRGN

VREFMRGN_CA_SODIMM

VREFMRGN_CA_SODIMMA_EN


PP0V75_S3_MEM_VREFDQ_A

VOLTAGE=0.75V

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN1

CPU_GTLREF0

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL


PP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

=PPVTT_S3_DDR_BUF

VREFMRGN_CPUFSB1

PCA9557D_RESET_L

VREFMRGN_CPUFSB_EN0

VREFMRGN_CPUFSB_EN1

VREFMRGN_DQ_SODIMMA_ENVREFMRGN_CA_SODIMMB_EN

=I2C_PCA9557D_SDA=I2C_PCA9557D_SCL TP_PCA9557_P6

TP_PCA9557_P7

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_BUF


PP0V75_S3_MEM_VREFDQ_B

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFCA_BMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

VREFMRGN_CPUFSB_EN0

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMM


FSB/DDR3 Vref Margining

VREFMRGNRES,MTL FILM,200,1%,0402,SM,LF114S0149 1 R2903 CRITICAL

RES,MTL FILM,200,1%,0402,SM,LF R2905 VREFMRGN114S0149 1 CRITICAL

PRODUCTIONCRITICAL1116S0004 R2911RES,MTL FILM,0,5%,0402,SM,LF

CRITICALR2909 VREFMRGNRES,MTL FILM,200,1%,0402,SM,LF114S0149 1

R2911 CRITICAL1114S0149 RES,MTL FILM,200,1%,0402,SM,LF VREFMRGN

PRODUCTION1 CRITICAL116S0004 R2909RES,MTL FILM,0,5%,0402,SM,LF

PRODUCTIONR2905 CRITICAL1116S0004 RES,MTL FILM,0,5%,0402,SM,LF

PRODUCTIONRES,MTL FILM,0,5%,0402,SM,LF116S0004 1 R2903 CRITICAL

10 11 100

VREFMRGN

CERM10V

402

20%0.1UF

1/16W5%

402MF-LF

VREFMRGN100K

0.1UF

VREFMRGN

10V

402CERM

20%

402-LF

VREFMRGN

20%

CERM

2.2UF6.3V

0.1UF

402CERM

20%

VREFMRGN

10V

52

52

DAC5574

VREFMRGN

MSOP

52

52

9

VREFMRGN

1/16W5%

MF-LF

100K

402

CERM10V

0.1UF20%

VREFMRGN

402

VREFMRGN

PCA9557QFN

VREFMRGN100K5%

402MF-LF1/16W

1/16W

100K

402MF-LF

VREFMRGN5%

VREFMRGN5%

402

100K1/16WMF-LF

UCSP

VREFMRGN

MAX4253

MF-LF402

5%100K1/16W

VREFMRGN

100

402MF-LF1/16W1%

FSB_VREFMRGN

10 11 100

1%

200

1/16WMF-LF402

OMIT

MF-LF

1%1/16W

402

200OMIT

MF-LF

1%

200

1/16W

402

OMIT

1%1/16WMF-LF402

OMIT

200

UCSP

VREFMRGN

MAX4253

MAX4253

VREFMRGN

UCSP

MAX4253UCSP

VREFMRGN

CERM402

10V20%0.1UF

VREFMRGN

UCSP

VREFMRGN

MAX4253

100

MF-LF

1%

VREFMRGN

1/16W

402

100

402MF-LF

1%1/16W

FSB_VREFMRGN

402MF-LF1/16W1%

100VREFMRGN

MF-LF402

1%

100

1/16W

VREFMRGN

402MF-LF

100

1/16W1%

VREFMRGN

VREFMRGN

MAX4253UCSP

6

29

31

29

29

31

6

29

29

29

29

29

32

32

29

29

29

29

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR

4771 mA (A01, DDR3)

4771 mA (A01, DDR3)

EXTRA DECOUPLING CAPS FOR MCP MEM RAIL

DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

4771 mA (A01, DDR3)

DIMM A (FURTHER FROM MCP) CAPS TO COUPLE MCP 1V5_S0_MEM DIMM B (CLOSER TO MCP)

30 OF 110

051-7863

A.0.0


2

1 C30BD

2

1 C30B8

2

1 C30B9

2

1 C30BA

2

1 C30BB

2

1 C30BC

2

1 C30A5

2

1 C30A6

2

1 C30A7

2

1 C30A8

2

1 C30B5

2

1 C30B6

2

1 C30A9

2

1 C30AA

2

1 C30AB

2

1 C30AC

2

1 C30AD

2

1 C30AE

2

1 C30AF

2

1 C30B0

2

1 C30B1

2

1 C30B2

2

1 C30B3

2

1 C30B4

2

1 C30B7

2

1 C30A0

2

1 C30A1

2

1 C30A2

2

1 C30A3

2

1 C30A4

2

1 C3002

2

1 C3001

2

1 C3000

2

1 C3099

2

1 C3098

2

1 C3040

2

1 C3043

2

1 C3045

2

1 C3047

2

1 C3048

2

1 C3049

2

1 C3090

2

1 C3091

2

1 C3092

2

1 C3093

2

1 C3094

2

1 C3095

2

1 C3096

2

1 C3097

2

1 C3070

2

1 C3071

2

1 C3072

2

1 C3073

2

1 C3074

2

1 C3075

2

1 C3076

2

1 C3077

2

1 C3078

2

1 C3079

2

1 C3080

2

1 C3081

2

1 C3082

2

1 C3083

2

1 C3084

2

1 C3085

2

1 C3050

2

1 C3051

2

1 C3052

2

1 C3053

2

1 C3054

2

1 C3055

2

1 C3056

2

1 C3057

2

1 C3058

2

1 C3059

2

1 C3060

2

1 C3061

2

1 C3062

2

1 C3063

2

1 C3064

2

1 C3065

2

1 C3010

2

1 C3019

2

1 C3018

2

1 C3017

2

1 C3016

2

1 C3035

2

1 C3034

2

1 C3033

2

1 C3032

2

1 C3031

2

1 C3030

2

1 C3014

2

1 C3023

2

1 C3022

2

1 C3021

2

1 C3020

2

1 C3029

2

1 C3028

2

1 C3027

2

1 C3026

2

1 C3025

2

1 C3041

2

1 C3042

2

1 C3044

2

1 C3046

=PP1V8R1V5_S0_MCP_MEM=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B




MEMORY CAPSSYNC_MASTER=MASTER SYNC_DATE=N/A

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

20%0.1UF

CERM10V

402402

10VCERM

0.1UF20%20%

402CERM10V

0.1UF

402

10VCERM

0.1UF20%

0.1UF

402

10V20%

CERM

10VCERM

0.1UF20%

402

20%0.1UF

CERM10V

402

20%0.1UF

CERM10V

402

20%0.1UF

CERM10V

402

20%0.1UF

CERM10V

402

20%0.1UF

CERM10V

402

20%0.1UF

CERM10V

402

20%0.1UF

CERM10V

402

0.1UF20%

402CERM10V

20%0.1UF

CERM10V

402402

20%0.1UF

CERM10V10V

20%0.1UF

CERM402

0.1UF20%

CERM10V

402

0.1UF20%

CERM10V

402CERM10V20%

402

0.1UF

402

10V

0.1UF20%

CERM

CERM

20%10V

402

0.1UF 0.1UF

CERM

20%

402

10V20%

CERM10V

402

0.1UF 0.1UF20%

CERM10V

402

6.3V

1UF10%

CERM402402

10%

CERM6.3V

1UF10%1UF

402CERM6.3V 6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402 402

CERM

10%1UF6.3V

1UF6.3VCERM402

10%

402CERM

1UF6.3V10%

402CERM

10%1UF6.3V

CERM

10%1UF

402

6.3V6.3V

1UF

CERM402

10%1UF

CERM402

10%6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402

10%1UF6.3VCERM

402

10%1UF

CERM6.3V

402CERM

10%1UF6.3V

402CERM

1UF6.3V10%

402CERM

1UF6.3V10%

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

402CERM

10%1UF6.3V

1UF

402

10%

CERM6.3V 6.3V

1UF

CERM402

10%1UF

CERM402

6.3V10%

1UF

CERM402

6.3V10%

1UF

CERM402

6.3V10%

6.3V

1UF10%

CERM402402

CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402

10%

CERM6.3V

1UF10%6.3V

1UF

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402 402

CERM

10%1UF6.3V

10UF

603X5R6.3V20% 20%

X5R6.3V

10UF

603

6.3V

1UF

CERM

10%

402 402CERM

1UF6.3V10%

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

10UF

X5R6.3V20%

603

20%

X5R6.3V

10UF

603

6.3V

1UF

CERM

10%

402 402CERM

1UF6.3V10%

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

30 25 16 6 30 25 16 6

31 108 6

32 108 6

30 25 16 6

30 25 16 6

3025 16 6

www.bblianmeng.com

www.vinafix.vn

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54

DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6

DQ7

VREFDQ

VSS_1

VSS_3

DQ0

DQ1

DM0

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

DQ31

VSS_25

VDD_1

CKE1

A15

A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2

A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2

DQ3

VSS_6

DQ8

DQ9

VSS_8

DQS1*

DQS1

VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2

VSS_17

DQS2*

VSS_14

VSS_21

DQ24

DQ25

DQ19

VSS_19

VSS_24

DQ27

DQ26

DM3

VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16

TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6*

DQS6

VSS_40

DQ49

DQ50

VSS_45

DQ56

DQ57

VSS_47

DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9

VSS_8

DQS1*

DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP

BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47

DM7

DQ58

DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6

VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26

DQ32

DQ33

TEST

VDD_16

S1*

A13

CAS*

VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0

NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0

VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46

DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38

DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6

A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15

A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30

DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18

DQ19

DQ25

DQ24

DM3

VSS_22

DQ27

VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

DIMM 0

DIMM 2

DIMM2 SPD ADDR=0XA4(WR)/0XA5(RD)DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)


Power aliases required by this page:

(NONE)

- =I2C_SODIMMA_SDA

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S3_MEM_A

- =PP1V5_S0_MEM_A

- =PP0V75_S0_MEM_VTT_A

Page Notes

- =I2C_SODIMMA_SCLTO FACILITATE BITSWAPS WITH ALIASES

- ALL DQ, DQS, DM SIGNALS;


31 OF 110

051-7863

A.0.0


113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B

202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B

188B

169B

171B

152B

154B

135B

137B

62B

64B

45B

47B

27B

29B

10B

12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B

97B

78B

80B

119B

83B 84B

107B

98B

J3100

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A

202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A

188A

169A

171A

152A

154A

135A

137A

62A

64A

45A

47A

27A

29A

10A

12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A

97A

78A

80A

119A

83A 84A

107A

98A

J3100

2

1R3143

2

1R3142

2

1 C3140

2

1R3140

2

1R3141

2

1 C3150

2

1 C3151

2

1 C3135

2

1 C3136

2

1 C3130

2

1 C3131

402

10V

0.1UF20%

CERMCERM

2.2UF20%6.3V

402-LF

10V20%0.1UF

402CERM

402-LF

20%

CERM6.3V

2.2UF

CERM402-LF

6.3V

2.2UF20%

6.3V

2.2UF20%

402-LFCERM

MF-LF

5%

402

10K

1/16W5%10K

1/16W

402MF-LF

402-LF

6.3VCERM

20%2.2UF

10K5%

402

1/16WMF-LF

10K

402

5%1/16WMF-LF

F-RT-TH

DDR3-SODIMM-DUAL

CRITICAL

F-RT-TH

DDR3-SODIMM-DUALCRITICAL

DDR3 SO-DIMMs 0 & 2SYNC_DATE=07/06/2009SYNC_MASTER=K22

=MEM_A_DQ<58>

=MEM_A_DQ<59>

MEM_DIMM0_SA<0>

=PPSPD_S0_MEM_A

=MEM_A_DM<7>


=MEM_A_DQ<57>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<43>

=MEM_A_DQ<34>

MEM_A_A<10>

=PP1V5_S3_MEM_A

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<0>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

=MEM_A_DQ<51>

=MEM_A_DQ<56>

=I2C_SODIMMA_SCL

=MEM_A_DQ<50>

MEM_A_A<13>

MEM_A_CS_L<1>

=MEM_A_DQ<32>

=MEM_A_DQ<33>

=MEM_A_DQS_N<4>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3>

MEM_A_A<1> MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<7>

MEM_A_A<11>

=MEM_A_DQ<3>

=MEM_A_DQ<9>

=MEM_A_DQS_N<1>

=MEM_A_DQS_P<1>

=MEM_A_DQ<26>

MEM_A_CKE<2>

MEM_A_BA<2>

MEM_A_A<9>

MEM_A_A<8>

=PP1V5_S3_MEM_A

=MEM_A_CLK_N<2>

MEM_A_A<10>

MEM_A_BA<0>

MEM_DIMM2_SA<0>


MEM_DIMM2_SA<1>

=PPSPD_S0_MEM_A

=MEM_A_DM<7>

=MEM_A_DQ<58>

=MEM_A_DQ<59>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<42>

=MEM_A_DM<5>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<32>

=MEM_A_DQ<33>

MEM_A_CS_L<3>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

=MEM_A_CLK_P<2>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<12>

=MEM_A_DQ<11>

=MEM_A_DQ<16>

=MEM_A_DQ<10>

=MEM_A_DQ<8>

=MEM_A_DM<0>

=MEM_A_DQ<2>


=MEM_A_DQ<0>

=MEM_A_DQ<1>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA


=MEM_A_DQ<63>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

MEM_EVENT_L

=MEM_A_DQ<62>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

=MEM_A_DQ<61>

=MEM_A_DQ<52>

=MEM_A_DQ<44>

=MEM_A_DQS_N<5>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<45>

=MEM_A_DQS_P<5>

=MEM_A_DM<4>


=PP1V5_S3_MEM_A

=MEM_A_DQ<37>

MEM_A_BA<1>

MEM_A_ODT<2>

=MEM_A_CLK_P<3>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_CKE<3>

=MEM_A_DM<1>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

MEM_RESET_L

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQS_N<0>

=MEM_A_DQS_P<0>

=MEM_A_DQ<21>

=MEM_A_DM<2>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQS_N<3>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2>

=MEM_A_DQS_P<2>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DM<3>

=MEM_A_DQ<27>

=MEM_A_CLK_N<3>

MEM_A_RAS_L

MEM_A_CS_L<2>

MEM_A_ODT<3>

MEM_A_CAS_L

MEM_A_WE_L

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQS_P<0>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

MEM_RESET_L

=MEM_A_DQ<13>

=MEM_A_DM<1>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3>

=MEM_A_DQ<29>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_CLK_P<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_RAS_L

=MEM_A_CLK_N<1>

MEM_A_BA<1>

MEM_A_CS_L<0>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>


=MEM_A_DM<4>

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DM<6>

MEM_EVENT_L

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=MEM_A_DQ<8>

=MEM_A_DQS_N<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<24>

=MEM_A_DQ<26>

=MEM_A_DM<3>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DM<5>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

MEM_A_A<12>

MEM_A_BA<2>


MEM_DIMM0_SA<1>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

=PPSPD_S0_MEM_AMEM_DIMM0_SA<1>




=PPSPD_S0_MEM_A

MEM_DIMM0_SA<0>

=MEM_A_DQS_P<1>

=MEM_A_DQ<16>

=MEM_A_DQ<25>

=MEM_A_DQ<27>

MEM_A_CKE<0>

=MEM_A_CLK_N<0>

MEM_A_BA<0>

=MEM_A_CLK_P<0>


=MEM_A_DQ<4>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQS_P<2>

MEM_A_A<5>

=MEM_A_DQS_P<3>

MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<6>

=MEM_A_DQ<5>

=MEM_A_DQ<12>

=MEM_A_DM<2>

=MEM_A_DQ<9>

=MEM_A_DQ<3>

=MEM_A_DQ<2>

=MEM_A_DM<0>

MEM_A_A<15>

=PP1V5_S3_MEM_A

MEM_A_CKE<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<17>

=MEM_A_DQ<38>

=MEM_A_DQ<43>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQS_N<6>

=I2C_SODIMMA_SDA

=MEM_A_DQ<36>

=MEM_A_DM<6>

=MEM_A_DQ<39>

33 31

33 31

31

31 6

33 31

31 6

33 31

33 31

33 31

33 31

33 31

101 31 15

108 31 30 6

33 31

33 31

33 31

33 31

33 31

33 31

33 31

52 31

33 31

101 31 15

101 15

33 31

33 31

33 31

101 31 15

101 31 15

101 31 15

101 31 15 101 31 15

101 31 15

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

101 16

101 31 15

101 31 15

101 31 15

108 31 30 6

33

101 31 15

101 31 15

31

31 6

31

31 6

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

101 16

101 31 15

101 31 15

101 31 15

33

101 31 15

101 31 15

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

33 31

31 29

33 31

33 31

52 31

52 31

31 6

33 31

33 31

33 31

55 49 32 31 21

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

31 29

108 31 30 6

31

101 31 15

101 16

33

101 31 15

101 31 15

101 31 15

101 31 15

101 31 15

101 31 15

33 31

101 31 15

101 16

33 31

33 31

33 31

33 31

33 32 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33

101 31 15

101 16

101 16

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 32 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33

101 15

101 15

101 31 15

33

101 31 15

101 15

33 31

33 31

33 31

33 31

31 29

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

55 49 32 31 21

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

101 31 15

101 31 15

31 6

31

31

31

31 6 31

31 29

31 29

31 6

31 6

31

33 31

33 31

33 31

33 31

101 15

33

101 31 15

33

31 29

33 31

33 31

33 31

33 31

101 31 15

33 31

101 31 15

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

108 31 30 6

101 15

33 31

33 31

33 31

33 31

33 31

33 31

33 31

52 31

33

33 31

33 31

33

33

31

www.bblianmeng.com

www.vinafix.vn

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54

DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6

DQ7

VREFDQ

VSS_1

VSS_3

DQ0

DQ1

DM0

VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

DQ31

VSS_25

VDD_1

CKE1

A15

A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2

A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA

SCL

DQ2

DQ3

VSS_6

DQ8

DQ9

VSS_8

DQS1*

DQS1

VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2

VSS_17

DQS2*

VSS_14

VSS_21

DQ24

DQ25

DQ19

VSS_19

VSS_24

DQ27

DQ26

DM3

VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16

TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6*

DQS6

VSS_40

DQ49

DQ50

VSS_45

DQ56

DQ57

VSS_47

DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9

VSS_8

DQS1*

DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP

BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47

DM7

DQ58

DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6

VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26

DQ32

DQ33

TEST

VDD_16

S1*

A13

CAS*

VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0

NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0

VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46

DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38

DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6

A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15

A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30

DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18

DQ19

DQ25

DQ24

DM3

VSS_22

DQ27

VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

- =I2C_SODIMMB_SCL


TO FACILITATE BITSWAPS WITH ALIASES- ALL DQ, DQS, DM SIGNALS;

(NONE)


Page Notes

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMB_SDA


DIMM1 SPD ADDR=0XA2(WR)/0XA3(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

DIMM 1

DIMM 3

32 OF 110

051-7863

A.0.0


113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B

202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B

188B

169B

171B

152B

154B

135B

137B

62B

64B

45B

47B

27B

29B

10B

12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B

97B

78B

80B

119B

83B 84B

107B

98B

J3200

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A

202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A

188A

169A

171A

152A

154A

135A

137A

62A

64A

45A

47A

27A

29A

10A

12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A

97A

78A

80A

119A

83A 84A

107A

98A

J3200

2

1R3241

2

1R3240

2

1 C3240

2

1R3242

2

1R3243

2

1 C3250

2

1 C3251

2

1 C3235

2

1 C3236

2

1 C3230

2

1 C3231

MEM_B_WE_L

=MEM_B_DQ<32>

=MEM_B_DQ<27>

MEM_B_CKE<0>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_BA<2>

=MEM_B_DQ<25>

=PPSPD_S0_MEM_B



PP0V75_S3_MEM_VREFCA_B

=PPSPD_S0_MEM_B

MEM_DIMM1_SA<1>

MEM_DIMM1_SA<0>

=PPSPD_S0_MEM_B

MEM_DIMM3_SA<1>

MEM_DIMM3_SA<0>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DM<5>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<33>

=MEM_B_CLK_P<0>

=MEM_B_DM<3>

=MEM_B_DQ<26>

=MEM_B_DQ<19>

=MEM_B_DQ<24>

=MEM_B_DQS_N<2>

=MEM_B_DQS_P<2>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62>

=MEM_B_DQ<63>

MEM_EVENT_L

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>


=MEM_B_DM<6>

=MEM_B_DQ<53>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_N<5>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

=MEM_B_DM<4>


=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

MEM_B_CS_L<0>

MEM_B_BA<1>

=MEM_B_CLK_N<1>

MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_ODT<1>

=MEM_B_CLK_P<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<11>

MEM_B_CKE<1>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DM<2>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<21>

=MEM_B_DM<1>

MEM_RESET_L

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DM<0>

=MEM_B_DQ<1>

=MEM_B_DQ<0>


=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQS_N<0>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_CS_L<1>

=MEM_B_DQ<27>

=MEM_B_DM<3>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<17>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DM<2>

=MEM_B_DQ<21>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<12>

=MEM_B_DQ<20>

MEM_RESET_L

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DM<1>

MEM_B_CKE<3>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_A<11>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<2>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>


=MEM_B_DQ<36>

=MEM_B_DM<4>

=MEM_B_DQS_P<5>

=MEM_B_DQ<45>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQS_N<5>

=MEM_B_DQ<44>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<53>

=MEM_B_DQ<60>

=MEM_B_DM<6>

=MEM_B_DQ<62>

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<7>

=MEM_B_DQ<63>


=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

=MEM_B_DQ<1>

=MEM_B_DQ<0>


=MEM_B_DQ<2>

=MEM_B_DM<0>

=MEM_B_DQ<8>

=MEM_B_DQ<10>

=MEM_B_DQ<16>

=MEM_B_DQ<11>

MEM_B_A<12>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<1>

=MEM_B_CLK_P<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_CS_L<3>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DM<5>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DM<7>

=PPSPD_S0_MEM_B

MEM_DIMM3_SA<1>


MEM_DIMM3_SA<0>

MEM_B_BA<0>

MEM_B_A<10>

=MEM_B_CLK_N<2>

=PP1V5_S3_MEM_B

MEM_B_A<8>

MEM_B_A<9>

MEM_B_BA<2>

MEM_B_CKE<2>

=MEM_B_DQ<26>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<9>

=MEM_B_DQ<3>

MEM_B_A<0>

=PP1V5_S3_MEM_B

MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_CS_L<2>

MEM_B_RAS_L

MEM_B_BA<1>

=MEM_B_CLK_N<3>

=MEM_B_CLK_P<3>

=MEM_B_DQ<13>

=MEM_B_DQ<12>

=MEM_B_DQ<22>

=MEM_B_DQS_N<3>

=PP1V5_S3_MEM_B

MEM_B_BA<0>

MEM_B_A<10>

=PP1V5_S3_MEM_B

=MEM_B_CLK_N<0>

MEM_B_A<1>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_A<5>


=MEM_B_DM<7>

=MEM_B_DQ<51>

MEM_DIMM1_SA<1>

=PPSPD_S0_MEM_B

MEM_DIMM1_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>


DDR3 SO-DIMM CONNECTOR B

DDR3-SODIMM-DUAL

CRITICAL

F-RT-TH

CRITICAL

F-RT-TH

DDR3-SODIMM-DUAL

10K

402

5%1/16WMF-LF

10K5%

402

1/16WMF-LF

20%2.2UF

6.3V

402-LFCERM

10K

MF-LF1/16W

402

5%10K

402

5%1/16WMF-LF

6.3V

2.2UF20%

402-LFCERM CERM

402-LF

6.3V20%2.2UF

402-LF

20%

CERM6.3V

2.2UF

10V

402CERM

0.1UF20%

CERM

2.2UF20%6.3V

402-LF

0.1UF20%10VCERM402

15 32 101

32 33

32 33

15 101

15 32 101

15 32 101

15 32 101

32 33

6 32

6 32

29 32

29 32

6 32

32

32

6 32

32

32

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 52

32 52

32 33

32 33

21 31 32 49 55

32 33

32 33

6 32

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

29 32

32 33

32 33

32 33

32 33

15 101

15 32 101

33

15 32 101

15 101

15 101

33

15 32 101

15 32 101

15 32 101

15 101

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

31 32 33

32 33

32 33

32 33

32 33

32 33

32 33

29 32

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

15 32 101

15 32 101

15 32 101

15 101

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

31 32 33

32 33

32 33

32 33

32 33

16 101

15 32 101

32 33

15 32 101

15 32 101

15 32 101

15 32 101

15 32 101

32 33

32 33

32 33

29 32

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

21 31 32 49 55

32 33

32 33

32 33

6 32

32 52

32 52

32 33

32 33

29 32

32 33

32 33

32 33

32 33

32 33

32 33

15 32 101

15 32 101

15 32 101

15 32 101

33

15 32 101

15 32 101

15 32 101

16 101

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

32 33

6 32

32

6 32

32

15 32 101

15 32 101

33

6 30 32 108

15 32 101

15 32 101

15 32 101

16 101

32 33

32 33

32 33

32 33

32 33

15 32 101

6 30 32 108

16 101

16 101

16 101

15 32 101

15 32 101

33

33

32 33

32 33

32 33

32 33

6 30 32 108

15 32 101

15 32 101

6 30 32 108

33

15 32 101

15 32 101

15 32 101

15 32 101

15 32 101

15 32 101

32 33

15 32 101

6 32

32 33

32 33

32

6 32

32

32 33

32 33

www.bblianmeng.com

www.vinafix.vn

IN

G S

D

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MCP CHANNEL A DQS 7 -> DIMM A DQS 7


MCP CHANNEL B DQS 6 -> DIMM B DQS 6









MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

DDR3 RESET Support

avoid glitch on MEM_RESET_L.






MCP MEMORY CLOCK ALIASING

MCP MEMORY TEST POINT ALIASING

before 1.5V starts to rise to

3.3V input must be stable before

33 OF 110

051-7863

A.0.0


2

1

3

Q3306

2

3

1Q3305

2

1R3309

2

1R3300

2

1 C3300

2

1R3301

2

1R3305

2

1R3310

=PP1V5_S3_MEMRESET

=PP3V3_S5_MEMRESET

MEM_RESET_L

MEM_RESET

MCP_MEM_RESET_L

MAKE_BASE=TRUETP_MEM_B_A<15> MEM_B_A<15>

MAKE_BASE=TRUETP_MEM_A_A<15> MEM_A_A<15>

MAKE_BASE=TRUEMEM_B_CLK_N<4> =MEM_B_CLK_N<3>

MEM_A_CLK_P<0>MAKE_BASE=TRUE

=MEM_A_CLK_P<1>

=MEM_B_CLK_P<1>

=MEM_B_DQS_P<3>

=MEM_A_CLK_P<0>

MEM_B_CLK_P<4>MAKE_BASE=TRUE

=MEM_B_CLK_P<3>

MEM_B_CLK_N<3>MAKE_BASE=TRUE

=MEM_B_CLK_N<2>


=MEM_B_CLK_P<2>MAKE_BASE=TRUE

MEM_B_CLK_N<1> =MEM_B_CLK_N<1>

MEM_B_CLK_N<0>MAKE_BASE=TRUE

=MEM_B_CLK_N<0>


MAKE_BASE=TRUEMEM_B_CLK_P<0> =MEM_B_CLK_P<0>

MAKE_BASE=TRUEMEM_A_CLK_N<4> =MEM_A_CLK_N<3>


MAKE_BASE=TRUEMEM_A_CLK_P<4> =MEM_A_CLK_P<3>

MAKE_BASE=TRUEMEM_A_CLK_P<3> =MEM_A_CLK_P<2>

MAKE_BASE=TRUEMEM_A_CLK_P<1>



MAKE_BASE=TRUEMEM_A_DM<6>

=MEM_A_DQ<55>MAKE_BASE=TRUE

MEM_B_DQ<55> =MEM_B_DQ<55>

=MEM_B_DQ<9>

MEM_B_DQS_N<7>MAKE_BASE=TRUE

MEM_B_DQS_P<7>MAKE_BASE=TRUE

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<7>

=MEM_B_DM<7>

=MEM_B_DQ<56>MEM_B_DQ<56>MAKE_BASE=TRUE

=MEM_A_DQS_N<7>

MEM_B_DQ<49>MAKE_BASE=TRUE


=MEM_A_DQ<51>

MEM_A_DQS_P<2>MAKE_BASE=TRUE


=MEM_A_DQ<4>

MAKE_BASE=TRUEMEM_A_DQS_N<0>

MAKE_BASE=TRUEMEM_A_DQS_P<0>

MEM_A_DQ<7>MAKE_BASE=TRUE


=MEM_A_DM<0>


=MEM_A_DQ<2>

=MEM_A_DQ<1> MEM_B_DQ<1>MAKE_BASE=TRUE


=MEM_A_DQ<45>

=MEM_A_DQ<44>

=MEM_A_DQ<43>

MAKE_BASE=TRUEMEM_B_DQ<53>

=MEM_B_DQ<50>

=MEM_A_DQ<52>

MAKE_BASE=TRUEMEM_B_DQ<51> =MEM_B_DQ<51>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<44>



=MEM_B_DQ<43>

=MEM_B_DQ<46>MEM_B_DQ<46>MAKE_BASE=TRUEMEM_B_DQ<45>MAKE_BASE=TRUE


=MEM_B_DQ<47>MEM_B_DQ<47>MAKE_BASE=TRUE

=MEM_B_DQ<40>

=MEM_B_DQS_N<6>

=MEM_A_DQ<46>

=MEM_B_DQ<45>


=MEM_B_DM<5>

=MEM_B_DQ<49>

=MEM_B_DQ<52>

MAKE_BASE=TRUEMEM_B_DQS_N<5>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<34>

=MEM_A_DQ<33>

=MEM_A_DQ<47>

=MEM_A_DM<5>




=MEM_A_DQ<25>

=MEM_A_DQ<26>


MAKE_BASE=TRUEMEM_B_DQ<24> =MEM_B_DQ<24>

=MEM_B_DQ<18>

=MEM_B_DQ<19>


=MEM_A_DQ<12>


MEM_B_DM<2>MAKE_BASE=TRUE



=MEM_B_DQ<20>

=MEM_A_DQ<22>

=MEM_A_DQ<20>


=MEM_B_DM<1>

=MEM_B_DQ<15>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<10>

=MEM_B_DQ<12>

=MEM_B_DQ<11>=MEM_A_DQ<11>





MAKE_BASE=TRUEMEM_B_DM<1>




=MEM_A_DQ<41>



=MEM_B_DQ<32>

=MEM_B_DQ<33>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DM<4>

=MEM_B_DQ<26>

=MEM_B_DQ<31>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQ<8>

=MEM_A_DQ<3>

MEM_A_DQS_N<5>MAKE_BASE=TRUEMEM_A_DQS_P<5>MAKE_BASE=TRUE

MEM_A_DM<5>MAKE_BASE=TRUE


MEM_A_DQ<46>MAKE_BASE=TRUEMEM_A_DQ<45>MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_DQ<44>




=MEM_A_DQS_P<7>







=MEM_A_DQ<40>

MAKE_BASE=TRUEMEM_A_DQS_P<3>






=MEM_B_DQ<21>


=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<0>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<0>

=MEM_A_DQ<10>MAKE_BASE=TRUE

MEM_A_DQ<11>



=MEM_A_DQ<9>

=MEM_A_DQ<8>

=MEM_B_DM<2>

=MEM_B_DQS_P<2>














=MEM_A_DQ<59>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<62>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DM<6>

=MEM_A_DQS_P<6>

=MEM_A_DQ<42>

=MEM_A_DQS_N<2>

=MEM_B_DQS_P<1>

=MEM_B_DQ<22>

=MEM_B_DQS_N<4>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQS_N<5>

=MEM_B_DQS_P<5>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<48>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<60>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_A_DQS_N<6>





MAKE_BASE=TRUEMEM_B_DQS_P<4>








MAKE_BASE=TRUEMEM_B_DQS_P<3>


=MEM_B_DM<0>









=MEM_A_DQS_P<2>






=MEM_A_DQ<63>

=MEM_A_DM<7>

=MEM_A_DQ<50>










MEM_A_DQS_N<1>MAKE_BASE=TRUE









=MEM_B_DQS_P<0>



=MEM_B_DQ<61>








MEM_A_DQ<21>MAKE_BASE=TRUEMEM_A_DQ<20>MAKE_BASE=TRUE

=MEM_A_DQ<19>

=MEM_A_DQ<17>

=MEM_A_DQ<32>

=MEM_A_DQS_N<5>

=MEM_B_DM<6>

=MEM_A_DQS_P<4>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQ<31>

=MEM_A_DM<3>

=MEM_A_DQS_P<3>

=MEM_A_DQ<16>

=MEM_A_DM<2>

=MEM_B_DQ<25>

=MEM_B_DQ<27>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DM<3>

=MEM_B_DQS_N<3>




=MEM_A_DQ<18>

=MEM_A_DQ<21>

=MEM_A_DQ<23>

=MEM_B_DQS_N<1>









=MEM_A_DQS_N<3>

=MEM_A_DQ<30>

=MEM_A_DQ<27>

=MEM_A_DQ<24>

MEM_A_DQS_N<4>MAKE_BASE=TRUE


=MEM_B_DQ<23>

=MEM_B_DQ<5>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<1>MAKE_BASE=TRUEMEM_B_DQ<6>

=MEM_B_DQ<4>





=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQS_N<4>


=MEM_A_DM<4>

=MEM_A_DQS_P<5>

=MEM_B_DQS_P<6>




=MEM_A_DQ<6>



=MEM_A_DQS_N<1>

=MEM_A_DM<1>

=MEM_A_DQS_P<1>

=MEM_A_DQ<0>

=MEM_A_DQ<5>

=MEM_A_DQ<7>

=MEM_A_DQS_N<0>

=MEM_A_DQS_P<0>






=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<15>

=MEM_A_DQ<49>

=MEM_A_DQ<48>


=MEM_A_DQ<58>

=MEM_A_DQ<60>

=MEM_A_DQ<61>





MEM_RESET_RC_L

SYNC_MASTER=MASTER

DDR3 SUPPORT AND BITSWAPSSYNC_DATE=N/A

402MF-LF

MEMRESET_HW

5%1/16W

20K

32 31

MF-LF

5%

402

1/16W

20K

MEMRESET_HW

SOT23-HF12N7002

MEMRESET_HW

SOT23MMBT3904G

MEMRESET_HW402

0

1/16W5%

MF-LF

MEMRESET_MCP

16

MF-LF402

1/16W5%

10K

MEMRESET_HW

10V

MEMRESET_HW

0.1UF20%

CERM402

402

1K

MF-LF1/16W5%

6

6

32

31

101 16 32

101 15

31

32

32

31

101 16 32

101 16 32

101 16 32

101 15 32

101 15 32

101 15

101 15 32

101 16 31

101 16 31

101 16 31

101 16 31

101 15

101 15 31

101 15 31

101 15

31 101 15 32

32

101 15

101 15

32

32

32

32101 15

31

101 15

101 15

31

101 15

101 15

31

101 15

101 15

101 15

101 15

31

101 15

31

31 101 15

101 15

31

31

31

101 15

32

31

101 15 32

32

32

32

101 15

101 15

32

32101 15

101 15

101 15

32101 15

32

32

31

32

101 15

32

32

32

101 15

31

31

31

31

31

31

101 15

101 15

101 15

31

31

101 15

101 15 32

32

32

101 15

31

101 15

101 15

101 15

101 15

32

31

31

101 15

32

32

32

32

32

32

3231

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

101 15

101 15

32

32

32

32

32

32

32

32

32

32

32

32

32

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

101 15

101 15

101 15

101 15

101 15

101 15

31

101 15

101 15

101 15

101 15

101 15

101 15

32

101 15

32

32

32

32

32

31

101 15

101 15

101 15

31

31

32

32

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

31

31

31

31

31

31

31

31

31

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

101 15

101 15

101 15

101 15

101 15

31

31

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

101 15

101 15

32

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

31

31

31

32

31

31

31

31

31

31

31

31

32

32

32

32

32

32

32

101 15

101 15

101 15

31

31

31

32

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

31

31

31

101 15

101 15

32

32

32

32

32

101 15

32

101 15

101 15

101 15

101 15

31

31

31

31

101 15

31

31

32

101 15

101 15

101 15

31

101 15

101 15

31

31

31

31

31

31

31

31

101 15

101 15

101 15

101 15

101 15

31

31

31

31

31

101 15

31

31

31

101 15

101 15

101 15

101 15

www.bblianmeng.com

www.vinafix.vn

IN

OUT

OUT

IN

IN

OUT

OUT

SYM_VER-1

IN

IN

SYM_VER-2




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518S0731

34 OF 110

051-7863

A.0.0


4

3 2

1

L3440

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

J34004 3

21

L3430

21

L3400

21

C3430

21

C3431

2

1C3402

2

1C3401

2

1C3400

PCIE_MINI_R2D_P

PCIE_MINI_R2D_L_N

PCIE_MINI_R2D_N

PCIE_CLK100M_MINI_CON_PPCIE_CLK100M_MINI_CON_N

PCIE_CLK100M_MINI_N

PCIE_MINI_D2R_N

MINI_RESET_LPCIE_WAKE_L

PP3V3_MINIVOLTAGE=3.3V


PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

MINI_CLKREQ_L

PCIE_MINI_D2R_P

=PP3V3_S3_MINI

PCIE_CLK100M_MINI_P

PCIE_MINI_R2D_L_P


PCI-E Wireless Connector

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

12-OHM-100MATCM1210-4SM

F-ST-SM20247-916E-01F

CRITICAL

102 17

102 17

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

90-OHM-100MADLP11S

FERR-120-OHM-1.5A

0402-LF

17 102

17 102

102 17

102 17

17

17

9

16VX5R

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

10%

402

0.1uF

402X5R

10%16V

0.1uF

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

10uF

X5R20%

6.3V

603

0.1uF10V

CERM20%

402

10V0.1uF

402

20%CERM

6

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051-7863

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36 OF 110

051-7863

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TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1

CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1]

MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1

LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

IN

IN

IN

IN

IN

IN

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN




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Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.

If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

Configuration Settings:

PHYAD = 01 (PHY Address 00001)

AN[1:0] = 11 (Full auto-negotiation)

TXDLY = 0 (No TXCLK Delay)

RXDLY = 0 (RXCLK transitions with data)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)

(19mA typ - Energy Detect)

(43mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

If internal switcher is not used, VDDREG and REGOUT can float.

per RealTek request.

Reserved for EMI

WF: Verify that ENET_RESET_L does not assert when WOL is active.

If false, ENET_RESET_L should be removed.

If true, RC and 0-ohm resistor should be removed.

37 OF 110

051-7863

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21R3780

2

1C3790

2

1C3714

2

1C3710

2

1C3711

2

1

L3715

2

1C3716

2

1C3715

2

1R3751

2

1R3750

2

1R3757

2

1R3752

2

1R3756

2

1R3755

21R3795

21R379421R379321R379221R3791

21R3790

2

1 C3702

2

1 C3701

2

1 C3700

2

1 C3706

45

44

26

25

24

23

27

22

18

17

16

14

13

19

46

48

29

31

11

12

8

9

4

5

1

2

30

38

35

34

47

33

207

3

39

37

21

15

36

28

32

43

42

41

6 40

10

U3700

2

1 C3705

2

1

L3705

2

1R3720

2

1R3725

2

1R3730

2

1 C3725

21

R3724

ENET_TXD<3>

RTL8211_PHYRST_L

RTL8211_RSET

=PP3V3_ENET_PHY

TP_RTL8211_CKXTAL2

TP_RTL8211_CLK125

ENET_TXD<0> ENET_RXD_R<0>

ENET_RXD_R<2>

ENET_MDI_P<0>

ENET_MDI_N<0>

RTL8211_PHYAD0

VOLTAGE=1.05V

PP1V05_ENET_PHYAVDDMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

RTL8211_CLK25M_CKXTAL1

ENET_RESET_L

ENET_MDC

=RTL8211_ENSWREG

ENET_MDI_N<2>

ENET_MDI_P<2>

RTL8211_RXDLY

ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_P<1>

ENET_MDI_N<1>

=PP1V05_ENET_PHY

ENET_CLK125M_RXCLK

ENET_RXD<0>

ENET_RXD<1>

ENET_RXD<2>

ENET_RXD<3>

ENET_RX_CTRL

ENET_TXD<2>

RTL8211_PHYAD1

ENET_RXCTL_R

ENET_RXD_R<3>

ENET_RXD_R<1>

ENET_CLK125M_RXCLK_R

=RTL8211_REGOUT

ENET_CLK125M_TXCLK_RENET_CLK125M_TXCLK

ENET_TX_CTRL

ENET_MDIO

ENET_TXD<1>


PP3V3_ENET_PHYAVDDMIN_LINE_WIDTH=0.6 MM

=PP3V3_ENET_PHY_VDDREG


Ethernet PHY (RTL8211CL)SYNC_MASTER=K22

18 104 5% MF-LF

224021/16W

402

5%

CERM50V

10PF

NO STUFF

16V10%

402X5R

0.1UF

0.1UF16VX5R402

10%0.1UF

16VX5R

10%

402 FERR-120-OHM-1.5A0402-LF

CRITICAL

16V

0.1UF

X5R402

10%0.1UF

16VX5R402

10%

MF-LF

4.7K5%1/16W

402

1/16W5%

4.7K

MF-LF402

402

4.7K

MF-LF

5%1/16W

MF-LF402

5%4.7K

1/16W

38

402

4.7K

MF-LF

5%1/16W

402

4.7K

MF-LF

5%1/16W

18 104

18 104

18 104

18 104

18 104

18 104

40222

MF-LF1/16W5%

40222

MF-LF1/16W5%

40222

MF-LF1/16W5%

402MF-LF1/16W5%22 402MF-LF1/16W5%22

MF-LF5% 1/16W22

402

39 104

39 104

39 104

39 104

39 104

39 104

39 104

39 104

38 104

18

18 104

18 104

18 104

18 104

18 104

18 104

18 104

0.1UF16VX5R402

10%16V

0.1UF

X5R402

10%0.1UF16VX5R402

10%

16V10%0.1UF

X5R402

CRITICAL

OMIT

RTL8211CLGRTQFP

10%0.1UF16VX5R402

CRITICAL

FERR-120-OHM-1.5A0402-LF

10K

MF-LF

5%1/16W

402

NOSTUFF

1/16W5%4.7K

402MF-LF

2.49K

MF-LF

1%1/16W

402

NOSTUFF

10V20%

CERM

0.1UF

402

100

1/16W5%

MF-LF402

38

104

104

38

104

104

104

104

38

38

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IN OUT

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

D SG

D S




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ENET ALIASES

NOTE: NOT USING THE BUILT-IN 1.05V REGULATOR OF THE PHY

RTL8211 25MHz ClockNOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

3.3V ENET FET

1.1V ENET FET

38 OF 110

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2

1

3

Q3850

2

1

3

Q3800

1

9

6

8

2

3

4

7

5

U3850

2

1 C3850

2

1 C3800

1

9

6

8

2

3

4

7

5

U3800

21

R3895

MAKE_BASE=TRUE

P3V3_ENET_EN

P1V1_ENET_EN

=PP3V3_S5_ENET_FET

=PP12V_S5_PWRCTL

PP3V3_RMGT


MAX_NECK_LENGTH=3 MMMIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V


=PP1V1_S5_ENET_FET

=PP12V_S5_PWRCTL

PP1V1_RMGTVOLTAGE=1.05VMIN_LINE_WIDTH=0.5 mm

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR


ENET_EN

ENET_EN

RTL8211_CLK25M_CKXTAL1

PP1V1_RMGTMAKE_BASE=TRUE

PP3V3_RMGTMAKE_BASE=TRUE

NO_TEST=TRUE

NC_PP3V3_ENET_PHY_VDDREGMAKE_BASE=TRUE

MAKE_BASE=TRUENC_RTL8211_REGOUT

NO_TEST=TRUE

=PP3V3_ENET_PHY_VDDREG


=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_PHY


=PP3V3_ENET_PHY

=RTL8211_REGOUT

MCP_CLK25M_BUF0_R

=RTL8211_ENSWREG


Ethernet Support

IRLML2502GPBFSOT23

CRITICAL

CRITICAL

SOT23IRLML2502GPBF

38 70

CRITICAL

SLG5AP001TDFN

0.1UF

X5R16V10%

402

38 70

16VX5R

10%0.1UF

402

CRITICAL

SLG5AP001TDFN

37 104

402

22


5%

MF-LF1/16W

18 104

6

6 38 70 78

38

6

6 38 70 78

38

38

38

37

18 25

25

37

18 25

37

37

37

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MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

TD1+

TCT1

TCT2

TD1-

TD2+

TD2-

TD3+

TCT3

TD3-

TD4+

TCT4

TD4-

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

ENET_MDITRAN_P0

TRAN_N0

TRAN_P1

TRAN_P2

TRAN_N2

TRAN_N1

TRAN_P3

TRAN_N3

PINSSHIELD




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514-0654

PLACE ONE CAP PER TCT PIN

NOTE: BOB SMITH TERMINATION FOR EMC.

NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.

39 OF 110

051-7863

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7

4

3

1

8

5

6

2

9

10

J3900

11

12

8

9

5

6

2

3

10

7

4

1

14

13

17

16

20

19

23

22

15

18

21

24

T3900

2

1 C3904

2

1 C3903

2

1 C3902

2

1 C3901

2

1 C3900

2

1R3903

2

1R3902

2

1R3901

2

1R3900

ENET_MDI_T_P<2>

ENET_MDI_T_P<2>

ENET_MDI_T_N<3>

ENET_MDI_T_N<1>

ENET_MDI_T_N<2>

ENET_MDI_T_P<1>

ENET_MDI_T_P<3>

ENET_MDI_T_N<0>

ENET_MDI_T_P<0>

ENET_TCT

ENET_MDI_T_N<2>

ENET_MDI_T_P<3>

ENET_MCT3

ENET_MCT1

ENET_MCT2

ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_N<0>

ENET_MDI_P<0>

ENET_MDI_T_N<3>

ENET_MDI_T_N<1>

ENET_MDI_T_P<1>

ENET_MDI_T_N<0>

ENET_MDI_T_P<0>

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MMENET_MCT_BS

ENET_MCT0

ETHERNET CONNECTORSYNC_MASTER=MASTER SYNC_DATE=N/A

CRITICAL

F-ANG-THRJ45-10/100TX-K22

CRITICAL

LFE9287APFSOI

CERM10V

0.1UF20%

402CERM10V

0.1UF20%

402CERM10V

0.1UF20%

402CERM

0.1UF20%

402

10V

CERM2KV

NOSTUFF

10%1000PF

1206

755%1/16W

402MF-LF

5%

402MF-LF1/16W

751/16W5%

402

75

MF-LF1/16W

402MF-LF

5%75

39 104

104 39

104 39

104 39

104 39

104 39

104 39

104 39

104 39

39 104

39 104

104 37

104 37

104 37

104 37

104 37

104 37

104 37

104 37

39 104

39 104

39 104

39 104

39 104

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40 OF 110

051-7863

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OUT TRI-ST/NC

VCC

GND

NC

NCNC

NCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNC

NCNCNC

NCNCNCNCNCNCNCNC

OUT

IN

IN

OUT

IN

OUT

OUT

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

RSVD_19

LKON_DS2_P

XI

CNA

CPS

PD

R1

R0

D6

D5

D4

D3

D2

D1

D0

CTL0

CTL1

LREQ_P

LREQ_L

LPS_P

LPS_L

PINT_P

PCLK_P

PINT_L

LCLK_P

LCLK_L

LINKON_L

DS1

DS0

PC2

PC0

PC1

PHY_RESET*

TPB2_N

TPB2_P

TPB1_N

TPB1_P

TPB0_N

TPB0_P

TPA2_N

TPA2_P

TPA1_N

TPA1_P

TPA0_N

TPA0_P

TPBIAS2

TPBIAS1

TPBIAS0

SE

TESTW_VREG_PD

SM

TESTM

BMODE

PLLGNDGND

DVDD_3_3

PLLVDD_3_3

VDDA_33 AVDD_3_3 VDD_15 VDDA_15 DVDD_CORE

VDD_15_COMB

VDD_33_COM_IO

VDD_33_COMB

VDD_33

PLLVDD_CORE

PCLK_L

VSSA_PCIEVSSAVSS

REF0_PCIE

REF1_PCIE

PERST*

RXN

RXP

TXN

TXP

CLKREQ*

REFCLK_P

REFCLK_M

REFCLK_SEL

SCL

SDA

GPIO0

GPIO2

GPIO1

GPIO3

GPIO4

GPIO5

GPIO7

GPIO6

OHCI_PME*

GRST*

RSVD_1

RSVD_0

RSVD_3

RSVD_2

RSVD_4

RSVD_6

RSVD_5

RSVD_9

RSVD_7

RSVD_8

RSVD_10

RSVD_11

RSVD_14

RSVD_12

RSVD_13

RSVD_16

RSVD_17

RSVD_18

RSVD_15

D7

CYCLEOUT

PCI EXPRESS

1394B OHCI & PHY

IN

IN

IN




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Strap DSx high on unused ports.

page assumes no more than

Alias =FWPHY_PC0

(JTAG_TCK)

(JTAG_TDI)

(JTAG_TDO)

(JTAG_TMS)

(IPU)

(IPU)

Ground TPBx_P/TPBx_N

PC[0:2] = ’100’

Multiple-ports:

Unused Ports:

TP/NC TPAx_P/TPAx_N

TP/NC TPBIASx

Single-port:

DS2 hard-strapped to 1,

2 FW800 connectors

PC[0:2] = ’000’

as appropriate

(VDD_33_AUX)

Power Aliases:

FWRS0_FWXIO nets are OHCI/PCIe power, and

can be S0.

5K pull-down device detect circuit.

For single-port systems, all FW power should

be tied together and powered by S0 or by the

FW_FWPHY nets are PHY power, and for

multi-port systems must come from bus power.

(IPU)

(JTAG_TRST)

(Snoop Enable, for FireBug)

41 OF 110

051-7863

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2

1R4189

2

1R4135

2

1C41904

13

2

Y4190

2

1R4190

2

1R4125

2

1C4120

2

1C4130

2

1C4125

2

1C4131

2

1C4132

2

1C4121

2

1C4122

2

1C4123

2

1C4126

2

1C4127

2

1C4128

2

1C4124

2

1R4171

21

R4191

2

1C4135

2

1 C4139

21

R4170

2

1R4175

2

1 C4138

2

1C4137

P4

C7

C6

C5

C4

B6

C10

F5

A7

A14

A10

C3

B5

B7

B9

B10

B11

C11

B12

M5

J10

H10

G10

E3

C12

B8

P7

M6

K10

H3

G3

A9

A8

E13

G13

K13

D14

E14

H14

J14

M14

N14

B14

C14

F14

G14

K14

L14

A6

B2

P14

P13

H12

J13

A4

A3

M12

M11

M8

L13

L12

K12

G12

F13

P3

D13

D12

P11

P10

N13

N12

N11

N10

M13

F12

E12

H13

A1

B1

A12

A13

M1

N1

M7

N7

N5

D3

D2

B4

B13

B3

F1

G1

A11

E8

E9

P8

E2

F2

C2

C1

D1

E1

H2

G2

C13

N6

P6

P5

N4

N3

P2

N2

P1

G8

G7

G6

G5

F9

F8

F7

K8

K7

K6

K5

F6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

E7

E6

M9

F3

C9

K3

J3

C8

P9

N9

M3

M2

L3

L2

L1

K1

K2

J2

N8

J1

H1

P12

A2

J12

A5

M4

M10

K9

J9

F10

E10

U4100

2

1R41862

1R4185

2

1 C4189

2

1C4105

2

1C4104

2

1C4103

2

1C4108

2

1C4115

2

1C4107

2

1C4106

2

1C4114

2

1C4113

2

1C4102

2

1C4101

2

1C4100

2

1C4112

2

1C4111

2

1C4110

2

1R4110

2

1R4117

2

1R4119

2

1C4119

2

1C4118

2

1R4140

2

1C4117

2

1R4141

21C4140

21C4141

2

1R4152

2

1R4151

21C4145

21C4146

2

1R4150

2

1R4153

2

1R4160

2

1R4180

2

1R4182

2

1R4181

FWPHY_TESTW

=PP3V3_FW_FWPHY

FWPHY_BMODE

FWPHY_TESTM

TP_FWXIO_JTAG_TDI

FWXIO_SNOOP_EN

=PP1V5_FWRS0_FWXIO

VOLTAGE=1.5VMIN_NECK_WIDTH=0.2 mm

PP1V5_FW_VDDAMIN_LINE_WIDTH=0.3 mm


MIN_LINE_WIDTH=0.3 mmPP1V96_FW_PLLVDD

FWXIO_VDD15COMB

FWXIO_VDD33COMB

FWXIO_VDD33COMIO

PP1V95_FW_FWPHYMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V3_FW_AVDD

VOLTAGE=3.3V

PCIE_FW_R2D_P

PCIE_FW_R2D_N

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP1V96_FW_XTAL

VOLTAGE=1.96V

=PP3V3_FWRS0_FWXIO

MIN_LINE_WIDTH=0.3 mmPP3V3_FW_PLLVDD

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm

TP_FWPHY_CNA

FWPHY_CPS

FWPHY_R0

FWPHY_R1

FWPHY_CLK98M_PCLK

FWOHCI_CLK98M_LCLK

FWPHY_PINT

FWOHCI_LPS

FWOHCI_LINKON_L

=FWPHY_PC0

=PP3V3_FW_FWPHY

FWPHY_LKON_DS2

CLK98M_FW_XI_R

FWXIO_CYCLEOUT

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

=FW_PME_L

PCIE_CLK100M_FW_N

PCIE_CLK100M_FW_P

=FW_CLKREQ_L

FW_P1_TPA_N

FW_P0_TPA_N

FW_P0_TPBIAS

FWXIO_REF0_PCIE

=FWPHY_DS0

=FWPHY_DS1

TP_FWOHCI_XO

PCIE_FW_D2R_C_N

PCIE_FW_D2R_C_P

FWXIO_REF_PCIE

FWXIO_REF1_PCIE

FW_P0_TPA_P

=PPVP_FW_PHY_CPS

FW_P1_TPA_P

FW_P2_TPA_P

FW_P2_TPA_N

FW_P2_TPBIAS

FW_P1_TPBIAS

FWXIO_SCL

FWXIO_SDA

FWXIO_REFCLK_SEL

FW_RESET_L

TP_FWXIO_GRST_L

TP_FWXIO_JTAG_TMS

TP_FWXIO_JTAG_TDO

CLK98M_FW_XI

FWOHCI_LREQ

=PP3V3_FW_FWPHY


PP3V3_FW_VDDA

VOLTAGE=3.3V

FWPHY_RESET_L

FW_P0_TPB_N

FW_P0_TPB_PSYNC_DATE=09/02/2009SYNC_MASTER=K22

FireWire LLC/PHY (XIO2213B)

CERM402

1UF10%6.3V6.3V

10%

402

1UF

CERM

CERM402

1UF10%6.3V

10%

402CERM

1UF

6.3V10%1UF

6.3V

402CERM

1UF

402

10%

CERM6.3V

402CERM6.3V

1UF10%

CERM

1UF

6.3V10%

402

402CERM6.3V10%1UF

MF-LF1/16W5%

402

470

22

MF-LF

5%

402

1/16W

10%6.3VCERM402

1UF

10%6.3VCERM402

1UF

42

42

1K

1/16WMF-LF

5%

402

42

402

1/16W5%10K

MF-LF

6.3V10%

402

1UF

CERM

10%

CERM6.3V

402

1UF

XIO2213B

BGA

OMIT

CRITICAL

390K

402

1/16WMF-LF

5%

MF-LF1/16W

402

6.34K1%

102 17

402CERM-X5R6.3V

0.22UF10%

42

42

42

42

42

42

42

42

42

102 17

42

42

10%6.3VCERM402

1UF10%6.3VCERM402

1UF10%6.3VCERM402

1UF

102 17

10%6.3VCERM402

1UF

1UF10%6.3VCERM402

10%6.3VCERM402

1UF10%6.3VCERM402

1UF

6.3VCERM402

1UF10%10%

6.3V

402

1UF

CERM

10%6.3VCERM402

1UF10%6.3VCERM402

1UF10%6.3VCERM402

1UF

10%

CERM402

1UF

6.3V

102 17

402

10%6.3VCERM

1UF

6.3V10%

CERM402

1UF

402

1/16W5%1

MF-LF

402

1/16WMF-LF

5%1

402

1/16W5%1

MF-LF

10%6.3VCERM402

1UF10%6.3VCERM402

1UF

402MF-LF1/16W

1%14.3K

9

1K5%

402

1/16WMF-LF

42

102 17

102 17

10%6.3VCERM402

1UF

2321%1/16W

402MF-LF

0.1uFX5R 40210% 16V

PLACEMENT_NOTE=Place C4140 close to U1400

X5R 40210% 16V0.1uF

PLACEMENT_NOTE=Place C4141 next to C4140

220

MF-LF402

5%1/16W

220

MF-LF402

5%1/16W

1K

1/16WMF-LF

5%

402

0.1uF X5R 40210% 16V

PLACEMENT_NOTE=Place C4145 close to UA2000.1uF

X5R 40210% 16V

PLACEMENT_NOTE=Place C4146 next to C4145

MF-LF1/16W

402

5%1K

42

MF-LF

1K5%

402

1/16W

NO STUFF

47K5%

402

1/16WMF-LF

NO STUFF

1/16W

1K

MF-LF402

5%

402

1/16WMF-LF

5%1

0.22UF

402CERM-X5R

6.3V10%

SM98P3040MHZ

402

1/16W5%

MF-LF

4.7

5%1/16WMF-LF

1

402

CERM

1UF

402

6.3V10%

10%6.3VCERM

1UF

402

1UF10%

402

6.3VCERM

1/16W

402

5%1K

MF-LF

43 42 41 6

6

42

102

102

6

43 42 41 6

102

102

42

43 42 41 6

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OUTINNR

NC THRML

EN

GND PAD




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8 7 5 4 2 1

Peak Current: 100mA

FireWire Aliases For Connectivity

1394 PHY STRAPPING OPTIONS

IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.

2ND & 3RD TPA/TPB PAIR UNUSED

Place close to FireWire PHYTermination

iMacs are now one port only and have Power Code "000"

THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT

TI PHY requires 1UF, not 0.33uF spec value.

TI PHY "Peaking Inductors" To improve Data Eye.

1394 PHY 1.95V SUPPLY

42 OF 110

051-7863

A.0.0


21

L4251

21

L4250

21

L4253

21

L4252

2

1C4200

2

1C4201

2

1 C42027

1

2

5

6

3

4

U4200

2

1R4257

2

1R4258

2

1C4254

2

1R4254

2

1R4252

2

1R4253

2

1R4250

2

1R4251

2

1 C4250

2

1R4256

2

1R4255

PP1V95_FW_FWPHY

VOLTAGE=1.95VMAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmMAKE_BASE=TRUE

FW_P0_TPA_L_PNO_TEST=TRUEVOLTAGE=1.86V

NO_TEST=TRUEVOLTAGE=0V

FW_P0_TPB_L_P

NO_TEST=TRUEVOLTAGE=1.86VFW_P0_TPA_L_N

FW_P0_TPB_L_N

NO_TEST=TRUEVOLTAGE=0V

FW_P0_TPB_N

FW_P0_TPA_NFW_P0_TPA_P


FW_P0_TPBIAS

MIN_NECK_WIDTH=0.08MM

VOLTAGE=1.86V

FW_PORT0_TPA_PMAKE_BASE=TRUE

=PPVP_FW_PHY_CPS PPVP_FW_PHY_CPSMAKE_BASE=TRUE

MAKE_BASE=TRUEFW_PME_L=FW_PME_L

=PP3V3_FW_FWPHY

=FWPHY_DS0

=FWPHY_DS1

MAKE_BASE=TRUEFW_PHY_PC0=FWPHY_PC0

=PP3V3_FW_FWPHY

=FW_CLKREQ_L

NO_TEST=TRUEMAKE_BASE=TRUE

NC_FW_PORT1_TPBIASFW_P1_TPBIAS

NO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPA_PFW_P1_TPA_P

NO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPA_NFW_P1_TPA_N

MAKE_BASE=TRUENC_FW_PORT2_TPBIAS

NO_TEST=TRUE

NC_FW_PORT2_TPA_PNO_TEST=TRUEMAKE_BASE=TRUE

NC_FW_PORT2_TPA_NNO_TEST=TRUEMAKE_BASE=TRUE

FW_P2_TPA_N

P1V95_FW_NR

FW_PHY_DS0MAKE_BASE=TRUE

FW_PHY_DS1MAKE_BASE=TRUE

FW_P0_TPA_C

FW_PORT0_TPA_NMAKE_BASE=TRUE

FW_PORT0_TPB_NMAKE_BASE=TRUE

FW_P0_TPB_P FW_PORT0_TPB_PMAKE_BASE=TRUE

FW_CLKREQ_LMAKE_BASE=TRUE

FW_P2_TPBIAS

FW_P2_TPA_P

FW: 1394B MISCSYNC_MASTER=K22 SYNC_DATE=09/02/2009

0402

18NH-250MA

0402

18NH-250MA

18NH-250MA

0402

18NH-250MA

0402

10%1UF

CERM6.3V

402

10%

CERM16V

402

0.01UF

X5R

2.2UF20%4V

402

TPS799195SON

CRITICAL

10K

402MF-LF

5%1/16W

10K

402MF-LF

5%1/16W

402

220PF

CERM

5%25V MF-LF

1/16W1%4.99K

402

56.21%

MF-LF402

1/16W

56.21%1/16W

402MF-LF

1%

MF-LF402

1/16W

56.2

MF-LF402

1%1/16W

56.2

CERM

1UF6.3V10%

402

10K5%1/16WMF-LF402

10K1/16W5%

NOSTUFF

MF-LF402

41

105

105

105

105

41

41

41

41

43 105

41 43

1941

6 41 42 43

41

41

41

6 41 42 43

41

41

41

41

41

43 105

43 105

41 43 105

17

41

41

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GND

V+

SHIELDPINS

VGTPA-

TPA(R)

TPB- TPB(R)

TPB+ VP

TPA+

SC/NC




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8 7 5 4 2 1

7 WATTS MAX PER PORT

POUR COPPER TO SINK HEAT

"Snapback" & "Late VG" Protection

IT IS HERE FOR SAFETY ONLYTHIS FUSE WILL NOT BLOW

FAST NON-RESETABLE FUSE

SHOULD BE DONE AS A POWER STRIP(SUBPLANE)

1394B

5.1VNC

PLACE CLOSE TO COMPARATOR

ESD Rail

IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP

CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V

[ LATE VG NOTES ]

514-0656

PORT 0

12 VOLTS

5.1V

PLACE CLOSE TO COMPARITOR

INRUSH RESETABLE PTC

43 OF 110

051-7863

A.0.0


8

6

9

2

1

5

4

3

7

11

10

J4300

21XW4300

21

F4300

21

R43053 1

D4303

2

1C4305

2

1R4306

21

R4304

8

1

7

3

5

2

6

4

U4300

2

1 C4304

31

D4302

2

3

1Q4302

2

1R4301

2

1 C4302

2

1R4307

2

1R4302

2

1R4303

21

D4300

21

R4352

2 3

1 Q4301

21

R4300

4

3

65

21

Q4300

21

F4301

3

1

D4301

2

1 C4300

2

1R4335

2

1 C4335

2

1C4332

21

L4300

2

1C4311

2

1C4310

2

1C4313

2

1C4312

21

R4390

31

D4390

6

2

1

DP4311

6

2

1

DP4310

3

5

4

DP4311

3

5

4

DP4310PP3V3_FW_ESD


VOLTAGE=12V

PPVP_FW_PHY_CPS

VOLTAGE=12VMIN_NECK_WIDTH=0.5MMMIN_LINE_WIDTH=1.7MMP12V_S5_FW_CL

FW_TURN_ON_V

FW_CURRENT_LIMIT_Q

FW_FET_LINEAR_LIMIT_OUT

FW_FET_LINEAR_LIMIT_IN

FW_PORT0_TPB_N

FW_PORT0_TPB_P

FW_PORT0_TPA_RFW_PORT0_TPA_P

FW_PORT0_TPA_N

FW_CURRENT_LIMIT_RD

FW_FET_LINEAR_LIMIT_FB

=PP3V3_FW_FWPHYVOLTAGE=3.3VMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm

PP3V3_FW_ESD

FW_CURRENT_LIMIT_R

FW_FET_LINEAR_LIMIT_INFW_FET_LINEAR_LIMIT_OUT

FW_CURRENT_LIMIT

=PP12V_S5_FW

FW_CURRENT_LIMIT

VOLTAGE=12V


FW_PORT0_VP_FMIN_LINE_WIDTH=1.7MM

VOLTAGE=12VMIN_NECK_WIDTH=0.5MM

FW_PORT0_VP

VOLTAGE=12V

MIN_LINE_WIDTH=1.7MMP12V_S5_FW_DMIN_NECK_WIDTH=0.5MM

PP3V3_FW_ESD

MIN_NECK_WIDTH=0.5MMVOLTAGE=12V

P12V_S5_FW_RMIN_LINE_WIDTH=1.7MM

=PP12V_S5_FW

FIREWIRE CONNECTORSYNC_MASTER=K22 SYNC_DATE=09/02/2009

1394B-K22

CRITICAL

F-ANG-TH

PLACEMENT_NOTE=PLACE CLOSE TO F4300

SM CRITICAL

603

3AMP-32V

5%

MF-LF402

1/16W

100K

MMBZ5231BXG

SOT23

603

2.2UF10%

X5R16V 402

5%

MF-LF1/16W

200K

100K

5%1/16WMF-LF402

LM393SOI-HF

X7R-CERM

0.1UF

402

16V10%

SOT23

BAS40XG

MMBT2222A7FSOT23

402MF-LF

10K1/16W5%

0.01UF16V

402CERM

20%20K5%1/16WMF-LF402

15K

MF-LF

5%1/10W

603

20K5%

402

1/16WMF-LF

CRS08-1.5A-30V

CRITICAL

SM

402

51.1K

1/16W1%

MF-LF

MMBT2907AXG60V-600MASOT23

2512

1WMF

0.33

5%

CRITICAL

FDC610PZSSOT6

SMD030F-SM

CRITICAL

0.3AMP-60V

SOT23MMBZ5231BXG

603-1

0.01UF

X7R50V10%

1M1/16WMF-LF

1%

402 X7R50V10%0.1UF

603-1

NOSTUFF

50VCERM

0.001UF

402

10%

FERR-250-OHM

CRITICAL

SM

X7R

10%

402

50V

0.01UF

X7R

10%50V

0.01UF

402

10%

402

50V

0.01UF

X7R

0.01UF10%50V

402X7R

332

402

1%

MF-LF1/16W

CRITICAL

SOT23

MMBZ5227BLT1H

SOT-363BAV99DW-X-G

CRITICAL

SOT-363

CRITICAL

BAV99DW-X-G

SOT-363

CRITICAL

BAV99DW-X-G

BAV99DW-X-GSOT-363

CRITICAL43

42

43

43

42 105

42 105

42 105

42 105

6 41 42 43

4343

43

6 43

43

43

6 43

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A

D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

44 OF 110

051-7863

A.0.0



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OUTKEY

GNDGND

MD

+5V

+5VDP

B-B+

GND

GND

A-A+GND

IN

IN

OUT

OUT

IN

IN

OUT




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C

A

D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518-0361

SATA PORT A1 FOR SLIMLINE ODD

SATA PORT A0 FOR HDD

518S0251

SATA Activity LED

45 OF 110

051-7863

A.0.0


P3

P2

P4

15

14

S7

S4

S1

P6

P5

P1

S6

S5

S2

S3

J4520

7

6

5

4

3

2

1

J4510

2

1R4530

2

1C4531

2

1C4530

21C4519

21C4520

21C4517

21C4518

2

1

DS4599

2

1R4599

21C4516

21C4515

21C4511

21C4510

SATA_ODD_R2D_C_N

SATA_HDD_R2D_P

SATA_HDD_D2R_C_N

SATA_HDD_D2R_C_P

SATA_ODD_D2R_P

=PP3V3_S0_ODD

SATA_ODD_R2D_C_P

MCP_SATALED_R_L

=PP3V3_S0_SATALED

SMC_EXCARD_OC_L

SATA_HDD_D2R_N

TP_MCP_SATALED_LMAKE_BASE=TRUE

MCP_SATALED_L

SATA_HDD_R2D_C_P

SATA_ODD_D2R_N

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_R2D_N

SATA_ODD_D2R_C_P

SMC_ODD_DETECT

=PP5V_S0_SATA

SATA_ODD_D2R_C_N

SATA_ODD_R2D_N

SATA_ODD_R2D_P

SATA ConnectorsSYNC_DATE=09/02/2009SYNC_MASTER=K22

20 102

20 102

20 102

SILK_PART=SATA ACTIVE

DEVELOPMENT


MF-LF603

3305%

1/10W

DEVELOPMENT

20 102

20 102

20 102

20 102

16V10% 402CERM0.01UF

0.01UF 16V CERM10% 402

10% 16V0.01UF 402CERM

0.01UF 16V10% 402CERM

1735574M-ST-TH

CRITICAL

M-ST-SMEP00-081-91

33K5%

1/10WMF-LF603

X5R25V10%

402

0.1UF0.1UF10%25V

402X5R

16V CERM 4020.01UF 10%

16V CERM 40210%0.01UF

16V CERM 4020.01UF 10%

16V0.01UF CERM 40210%

20 102

102110

102110

102110

6

6

49 50

20

102110

102 110

49 110

6

102 110

102 110

102 110

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EN1*

OC1*

IN OUT1

GND TPAD

OUT2

OC2*

EN2*

G S

D

EN1*

OC1*

IN OUT1

GND TPAD

OUT2

OC2*

EN2*

IO

IO

NC

GND

VBUS

NC

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

VBUS

DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

IO

IO

NC

GND

VBUS NC

IO

IO

NC

GND

VBUS

NC

IO

IO

NC

GND

VBUS NC

TABLE_5_ITEM






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A

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Apple Inc.

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8 7 5 4 2 1

514-0659

514-0659

514-0672

514-0672

(PUT CAP ON CONNECTOR SIDE)


SEL=0: CHOOSE SMC

PORT 3

D+

USB/SMC DEBUG MUX

D+

GND

D-

VDD

PORT 2

D+

D-

VDD

VDD

D-

D+

GND

GND

VDD

D-

PORT 0

GND


SEL=1: CHOOSE USB


PORT 1

46 OF 110

051-7863

A.0.0


1

6

5

4

3

2

J4620

1

6

5

4

3

2

J4630

1

6

5

4

3

2

J4610

1

6

5

4

3

2

J4600

1

2

9

108

5

4

3

7

6

U4650 4 3

21

L4631

4 3

21

L4621

4 3

21

L4611

4 3

21

L4601

2

1 C4600

2

1 C4610

2

1 C4620

2

1 C4606

2

1 C4621

21

L4630

6

32 45

1

D4630

2

1 C4630

2

1 C46319

6

7

5

8

2

1

4

3

U4601

2

1 C4611

2

1 C4603

2

1 C4601

2

1 C4605

2

1R4600

2

1

3Q4600

2

1 C4602

9

6

7

5

8

2

1

4

3

U4600

21

R4652

21

R4651

2

1 C4650

6

32 45

1

D4600

6

32 45

1

D4610

6

32 45

1

D4620

21

L4600

21

L4610

21

L4620

USB_EXTD_OC_L

USB_EXTC_OC_L

USB_D_MUXED_P

USB_D_MUXED_N


PP5V_USB2_PORT2VOLTAGE=5VMIN_LINE_WIDTH=0.6MM

VOLTAGE=5V


PP5V_USB2_PORT3


=PP3V3_S5_SMCUSBMUX

USB_EXTC_P


VOLTAGE=5VMIN_LINE_WIDTH=0.6MM

PP5V_USB2_PORT0

USB_EXTC_N

USB_EXTB_N

USB_EXTB_P

USB_EXTA_N

USB_EXTA_P

PM_EN_USB_PWR

USB_EXTA_OC_L

USB_EXTB_OC_LVOLTAGE=5VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

PP5V_USB2_PORT1

USB_EXTD_P

USB_DEBUGPRT_EN_L

SMC_TX_L

SMC_RX_L

USB_PWR_ENA_L

USB_EXTD_N

USB_PORT0_P

USB_PORT0_N

VOLTAGE=5VPP5V_USB2_PORT0_F

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

USB_PORT1_P

USB_PORT1_N

PP5V_USB2_PORT1_F



USB_PORT3_P

USB_PORT3_N

PP5V_USB2_PORT3_F



USB_PORT2_P

USB_PORT2_N

PP5V_USB2_PORT2_F

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=5V

=PP5V_S3_USB

=PP5V_S3_USB


EXTERNAL USB CONNECTORS

128S0238 1 330UF, TANT-POLY BULK CAP C4602 CRITICAL K23

128S0225 1 150UF, TANY-POLY BULK CAP C4606 CRITICAL K22

CRITICAL

RCLAMP0502NSLP1210N6

RCLAMP0502N

CRITICAL

SLP1210N6

CRITICAL

SLP1210N6RCLAMP0502N

FERR-250-OHM

CRITICAL

SM

F-ANG-TH

CRITICAL

USB-K22

F-ANG-THUSB-K22

CRITICAL

F-ANG-TH1

CRITICAL

USB-K22

F-ANG-TH1USB-K22

CRITICAL

TQFN

MOJOMUX

PI3USB102ZLE

CRITICAL

120-OHM-90MADLP0NS

CRITICAL

CRITICAL

120-OHM-90MADLP0NS

120-OHM-90MADLP0NS

CRITICAL

CRITICAL

120-OHM-90MADLP0NS

20%16V

402CERM

0.01uF

0.01uF20%16V

CERM402

402CERM16V

0.01uF20%

150UF20%

POLY-TANTCASE-D2-SM

CRITICAL

6.3V

OMIT CERM10V

402

20%0.1UF

CRITICAL

FERR-250-OHM

SM

CRITICAL

RCLAMP0502NSLP1210N6

0.01uF20%

CERM16V

402

CERM402

10V20%0.1UF

MSOP

TPS2060

CRITICAL

0.1UF10V20%

CERM402

10V

402

20%0.1UF

CERM

10V20%

402CERM

0.1UF

20%

CERM

0.1UF

402

10V

10K

402

1/16WMF-LF

5%

2N7002SOT23-HF1

POLY-TANTCASE-D3L-SM1

20%

CRITICAL

330UF6.3V

OMIT

CRITICAL

TPS2060

MSOP

1/16W

402

5%

MF-LF

0

PRODUCTION

402

0

5%

MF-LF1/16W

PRODUCTION

10V

0.1UF20%

CERM402

FERR-250-OHM

SM

CRITICAL

CRITICAL

SM

FERR-250-OHM

9

9 20

103

103

6

20 103

20 103

20 103

20 103

20 103

20 103

70

20

20

20 103

49 50

49 50 51

49 50 51

20 103

103

103

103

103

103

103

103

103

6 46

6 46

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SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

D

SG

D

SG




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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

IR RECEIVER CONNECTOR

518S0668

PLACE C4700, C4701 & L4700NEAR J4700 PINS 4 AND 5 IN THE

CAMERA CONNECTOR & FILTER

BOTH SIDES OF THE PIN.ORDER LISTED, AND NOT ON

LAYOUT NOTE:

518S0688

K37L (BLUETOOTH) CONNECTOR

SD Card Reader Board Connector

518S0690

47 OF 110

051-7863

A.0.0


6

5

4

3

2

1

8

7

J4750

5

4

3

2

1

7

6

J4720

45

3Q4700

12

6Q4700

4 3

21

L4720

21

L4721

2

1C475021

L4751

4 3

21

L4750

4

3

2

1

6

5

J4780

5

4

3

2

1

7

6

J4700

4 3

21

L4702

21

L4703

4 3

21

L4701

2

1 C4720

2

1 C4721

2

1 C4781

2

1 C4700

2

1C4701

21

L4700

CARDREADER_RESET_L

USB_SDCARD_L_N

USB_SDCARD_L_P


VOLTAGE=3.3VPP3V3_S3_SDCARD

USB_BT_P

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MMVOLTAGE=3.3VPP3V3_S3_BT

USB_BT_L_P

USB_BT_L_N

CARDREADER_PLT_RST

CARDREADER_PLT_RST_L

CARDREADER_RESET

USB_IR_N

USB_SDCARD_P

=PP3V3_S3_SDCARD

USB_SDCARD_N

=PP5V_S3_CAMERA

USB_CAMERA_L_N

USB_CAMERA_L_P


PP5V_S3_CAMERAVOLTAGE=5V


USB_CAMERA_P

USB_CAMERA_N

PP5V_S3_IR


=PP5V_S3_IR

=PP3V3_S3_BT

USB_BT_N

USB_IR_L_P

USB_IR_L_N

USB_IR_P

Internal USB ConnectionsSYNC_DATE=09/02/2009SYNC_MASTER=K22

CRITICAL

M-RT-SM53261-8606

53261-8605M-RT-SM

CRITICAL

SOT563SSM6N15FEAPE

SOT563SSM6N15FEAPE

DLP0NS

CRITICAL

120-OHM-90MA

FERR-250-OHM

CRITICAL

SM

402CERM6.3V

1UF10%

CRITICAL

FERR-250-OHM

SM

CRITICAL

DLP0NS120-OHM-90MA

CRITICAL

M-RT-SM53261-8604

CRITICAL

53780-8605M-RT-SM

120-OHM-90MADLP0NS

CRITICAL

FERR-250-OHM

CRITICAL

SM

CRITICAL

120-OHM-90MADLP0NS

20%

805-1

6.3VCERM

10UF 0.1UF20%10VCERM402

402

1UF

CERM6.3V10%

CERM

10UF6.3V20%

805-1CERM402

10V20%

0.1UF

SM

CRITICAL

FERR-250-OHM

103 110

103 110

20 103

103 110

103 110

9

17

20 103

20 103

6

20 103

6

103 110

103 110

20 103

20 103

6

6

20 103

103 110

103 110

20 103

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A

D

2 1


Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

48 OF 110

051-7863

A.0.0


BLANK PAGESYNC_DATE=12/02/2008SYNC_MASTER=K22

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IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

IN

OUT

ININ

BI

BI

OUT

IN

OUT

OUT

NC

OUT

OUT

OUTNC

NC

NCNC

NCNCNC

NC

NC

NC

NC

NCNC

IN

OUT

OUT

OUT

OUT

P13

P14

P15

P16 P66

P10

P11

P12

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P36

P37

P40

P41

P42

P43

P44

P45

P46

P47

P50

P51

P52

P60

P61

P62

P63

P64

P65

P67

P70

P71

P72

P73

P74

P75

P76

P77

P80

P81

P84

P85

P86

P90

P91

P92

P93

P94

P95

P96

P97

P35

P83

P82

(1 OF 3)

PH5

PH4

PH3

PH2

PH1

PH0

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PE0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PB2

PB1

PB0

PA7

PA6

PA3

PA2

PA1

PA0

PA4

PA5

PB3

PB4

PB5

PB6

PB7

PC1

PC0

PE4*

PE3*

PE2*

PE1*

(2 OF 3)

AVCC AVREF

AVSS

MD1

MD2

VCC VCL

VSS

NMI

XTAL

RES*

EXTAL

ETRST*

(3 OF 3)

IN

IN

IN

IN

OUT

OUT

OUT

OUT

NC

OUT

OUT

NC

OUT

NC

BI

BI

BI

BI

IN

IN

IN

BI

IN

IN

IN

IN

BI

BI

IN




36

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DRAWING NUMBER SIZE

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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

those designated as inputs require pull-ups.

(OC)

If SMS interrupt is not used, pull up to SMC rail.

(OC)

(OC)

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OC)

(OC)

(DEBUG_SW_1)

(DEBUG_SW_2)

(OC)

(OC)

(OC)

pins designed as outputs can be left floating,

NOTE: P94 and P95 are shorted, P95 could be spare.

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

49 OF 110

051-7863

A.0.0


143

139

111

95

427

13

86

36

1

8

11

25

9

144

27

67

77

76

U4900

142

141

140

26

12

10

51

52

53

54

55

56

57

58

43

44

45

46

47

48

49

50

28

29

30

31

32

59

60

61

62

63

64

65

66

87

88

89

90

91

92

93

94

113

114

115

116

117

118

119

120

33

34

35

37

38

39

40

41U4900

17

18

19

20

21

22

23

24

135

134

133

132

131

130

129

75

74

73

72

71

70

69

68

85

84

83

82

81

80

79

78

14

15

16

6

5

4

3

2

138

137

136

128

127

126

125

124

123

122

121

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

112U4900

2

1R4998

2

1R4903

2

1R4902

2

1R4901

2

1R4909

2 1

XW4900

21

R4999

2

1C49202

1C4907

2

1 C4906

2

1 C4905

2

1 C4904

2

1 C4903

2

1C4902

SMC_RUNTIME_SCI_L

SMC_PA5

PM_BATLOW_L

SMC_GFX_THROTTLE_L

SMB_MGMT_DATA

SMS_ONOFF_L

SMC_TX_L

SMC_RX_L

SMB_0_S0_CLK

SMC_P41

LPC_SERIRQ

PP3V3_S5_AVREF_SMC

=PP3V3_S5_SMC

SMC_TX_L

SMC_RX_L

SMC_ONOFF_L

LPC_PWRDWN_L

SMC_GPU_ISENSE

SMC_GPU_VSENSE

SMC_DCIN_ISENSE

SMC_BATT_ISENSE

SMC_WAKE_SCI_L

SMC_BC_ACOK

PM_SLP_S4_SMC_L

PM_SLP_S5_L

SMB_0_S0_DATA

SMC_NB_MISC_ISENSE

PM_SLPS3_BUF2_L

SMC_BS_ALRT_L

PM_CLKRUN_L

SMB_MGMT_CLK

BIDIVI_BKL_ON

ALS_GAIN

SMC_SYS_LED

SMC_EXCARD_CP BIDIVI_BKL_PWM

MEM_EVENT_L

USB_DEBUGPRT_EN_L

SMC_MCP_SAFE_MODE

SMC_PA0

PM_SYSRST_L

NC_SMC_PB3

LPC_AD<1>

LPC_AD<0>

SMC_FAN_1_TACH

SMC_PA1

SMC_EXCARD_OC_LSMC_PNL_BL_PWM

=SMC_SMS_INT

SMB_BSA_DATA

SMB_BSA_CLK

SMB_A_S3_DATA

SMS_Y_AXIS

SMS_X_AXIS

AUXCH_N_STATE

PM_RSMRST_L

SMC_PBUS_VSENSE

PM_EN_PVCORE_CPU

RSMRST_PWRGD

SMC_EXCARD_PWR_EN

PM_PWRBTN_L

ESTARLDO_EN

SMC_EXTAL

SMC_RESET_L

SMC_XTAL

SMC_NMI

SMC_VCL

SMC_KBC_MDE

SMC_MD1

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MMPP3V3_S5_SMC_AVCC

GND_SMC_AVSS

SMC_TRST_L

SMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMC_ADAPTER_EN

SMC_PM_G2_EN

SMC_PROCHOT_3_3_L

SMC_FAN_0_CTL

SMC_FAN_1_CTL

SMC_GFX_OVERTEMP_L

SYS_ONEWIRE

SMC_FAN_2_CTL

SMC_FAN_3_CTL

SMC_FAN_0_TACH

SMC_FAN_2_TACH

SMC_FAN_3_TACH

SMS_Z_AXIS

SMC_ANALOG_ID

SMC_NB_CORE_ISENSE

SMC_NB_DDR_ISENSE

ALS_LEFT

ALS_RIGHT

SMB_A_S3_CLK

SMB_B_S0_DATA

SMB_B_S0_CLK

SMC_PROCHOT

SMC_THRMTRIP

SMC_PH2

SMC_CPU_VSENSE

BIDIVI_AUDIO_MUX_SEL

LPC_CLK33M_SMC

AUXCH_P_STATE

SMC_VIDEO_ON

SMC_ODD_DETECT

SMC_RSTGATE_L

PM_CLK32K_SUSCLK

BIDIVI_PNL_PWR_EN

SMC_DP_HPD

ALL_SYS_PWRGD_SMC

SMC_CASE_OPEN

SMC_LRESET_L

LPC_FRAME_L

DPMUX_VIDEO_IN_SEL

LPC_AD<2>

LPC_AD<3>

SMC_TMS

SMC_LID

BIDIVI_AUX_TERM_EN

SMC_TDO

SMC_TDI

SMC_TCK

SYNC_MASTER=MARKVIDEO SYNC_DATE=03/12/2009

SMC

50

52

52

103 9

50

50 70

70 50 9 6

52

103 9

9

51 103 19

103 51 19

103 51 19

103 51 19

103 51 19

91 95

95

50

95

95

95

95

95

95

95

95

OMIT

TQFPHS82117

TQFP

OMIT

HS82117

HS82117

OMIT

TQFP

50

50

50

50

50

50 21

50

50

19 51

21

51

28

55 32 31 21

51 19

5050

51 50 49 46

50 49 51 46

50

50

50

50

52

52

52

52

52

52

95 50

50 51

50 51

50 51

50

50 51

50

50

50

50

50

50

50

56

56

57

50

50

57

56

56

50 45

21

55

110 45

21

50

50 46

1/16W

402

10K

MF-LF

5%

NO STUFF

0

MF-LF

5%1/16W

402

1/16WMF-LF

5%10K

402

MF-LF

10K5%1/16W

402

51

51

10K

MF-LF

5%1/16W

402

52

50

50 49 51 46

51 50 49 46

50

50

50

50

50

50

53 108

108 53

108 53

108 53

20%

CERM402

10V

0.1UF

50

70

70

21

20%

CERM402

10V

0.1UF

71

21

SM

20%

CERM402

10V

0.1UF

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

4.7

1/16W5%

MF-LF402

20%

CERM

0.1UF

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

402

10V

20%

CERM

0.1UF

402

10V

6.3V

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

0.47UF

CERM-X5R402

10%

50

51 50

51 19

22UF20%6.3V

CERM-X5R805-3

50

50

50

50 6

50

50

50

50

54 53 50

50

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G

D

S

IN OUT

GND

OUT

IN

BI

OUT

G S

D

G

D

S

OUT

IN

ING

D

S

G

D

S

CD

GNDNC

OUTIN

OUT

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM




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C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

SMC PROCHOT 3.3V LEVEL SHIFTING

UNUSED TP/NC ALIASES - PORT D - INTERNAL PULLUPS

UNUSED TP/NC ALIASES

FOR <RDAR://PROBLEM/5925345>

FROM SMC

TO CPU

TO SMC

FROM SMC

PULL-UP ON PAGE 14

NC

SIL: FOR DEVELOPMENT USE ONLY

FROM MXM

SMC AVREF Supply

518S0665

SMC & MXM THERMTRIP LEVEL SHIFTING

MISC. SIGNAL ALIASES

ANALOG SENSORS

SMC Reset Button / Brownout Detect

POWER BUTTON

SMC Crystal Circuit

50 OF 110

051-7863

A.0.0


43

21

S5010

43

21

S5000

21R5087

2

1

4

3

J5010

2

1R5050

1

4 2

3

5

U5000

2

1R5068

21

R5020

21

R5019

2

1R5069

4

5

3

Q5096

1

2

6

Q5096

21R5099

21

R5018

1

2

6

Q5095

21R509821R504921R504721R509721R5095

21R5093

21R5092

21R5089

2

1

3

Q5075

2

1

LED5075

2

1R5075

21R5096

21R5091

21R5090

2

1R5078

2

1R5070

4

3

5Q5077

21

R5071

1

6

2Q5077

21R5043

21

R5010

2

1 C501021R5094

2

1Y5020

21R5046

21R504221R504121R504021R503921R503821R503721R503621R503521R503421R503321R5032

21

3

VR5065

2

1C5066

2

1 C5067

2

1 C5065

4

5

3

Q5095

21

C5021

21

C5020

2

1C5001

2

1R5000

2

1C5000

POWER_BUTTON_L

SMC_MANUAL_RST_L

SMC_EXCARD_OC_L

SMC_SMS_INTMAKE_BASE=TRUE

SMC_LID

SMC_FAN_3_CTL

USB_DEBUGPRT_EN_L

SMC_PNL_BL_PWM

SMC_TX_L

SMC_RX_L

SYS_ONEWIRE

ESTARLDO_ENMAKE_BASE=TRUETP_ESTARLDO_EN

SMC_P41

TP_SMC_EXCARD_PWR_ENMAKE_BASE=TRUE

MAKE_BASE=TRUETP_SMC_RSTGATE_L

SMS_ONOFF_L

MAKE_BASE=TRUESMC_CPU_INPUT_ISENSE

SMC_MCP_CORE_ISENSEMAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

SMC_MCP_SAFE_MODE

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSS

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

SMC_RSTGATE_L

SMC_NB_DDR_ISENSE

PM_THRMTRIP_L

CPU_PROCHOT_L

MXM_PWR_LEVELMAKE_BASE=TRUE

SMC_GFX_OVERTEMP_L

NO_TEST=TRUENC_SMC_ANALOG_ID

MAKE_BASE=TRUE

SMC_EXCARD_PWR_EN

SMC_PM_G2_EN TP_SMC_PM_G2_ENMAKE_BASE=TRUE

ALS_GAINMAKE_BASE=TRUENC_ALS_GAIN

NO_TEST=TRUE

SMC_NB_MISC_ISENSE

SMC_NB_CORE_ISENSE

SMC_BATT_ISENSE

SMS_X_AXISMAKE_BASE=TRUESMC_1V5_S0_VSENSE

SMS_Y_AXIS SMC_MCP_CORE_VSENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_1V5_S0_ISENSE

SMC_PBUS_VSENSEMAKE_BASE=TRUESMC_CPU_INPUT_VSENSE

SMC_DCIN_ISENSE

MAKE_BASE=TRUESMC_UNUSED_ADC_PORT7

SMC_ONOFF_L

CPU_PROCHOT_BUF

MXM_OVERT_L

=PP3V3_S0_SMC_LS

PM_SLP_S5_L

=PP5V_S5_AVREF

SYS_LED_CATH

SMC_SYS_LED

SYS_LED_AN

SMC_XTAL

PP3V3_S5_AVREF_SMC



SMC_EXTAL

=PP3V3_S3_SMC

SMC_ONOFF_L

SMC_PH2

=PP3V3_S0_SMC

MXM_THRMTRIP_L

SMC_THRMTRIPMXM_THRMTRIP

=PP3V3_S0_SMC_LS

=PPVTT_S0_CPU

SMC_PROCHOT_3_3_L

CPU_PROCHOT_L_R

SMC_PROCHOT

NC_SMS_Z_AXISNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUENC_ALS_LEFT

MAKE_BASE=TRUEALS_LEFT

SMS_Z_AXIS

SMC_IG_THROTTLE_LMAKE_BASE=TRUE

MCP_SPKR

MXM_ALERT_LMAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_RESET_L

SMC_ANALOG_ID

TP_SMC_P41MAKE_BASE=TRUE

MAKE_BASE=TRUETP_SMS_ONOFF_L

ALS_RIGHT NC_ALS_RIGHTNO_TEST=TRUEMAKE_BASE=TRUE

SMC_TCK

SMC_PA1

SMC_PA0

SMC_TDI

SMC_TDO

SMC_TMS

SMC_BS_ALRT_L

=PP3V3_S5_SMC

SMC_GFX_OVERTEMP_L

SMC_ADAPTER_EN

SMC_FAN_3_TACH

SMC_BIL_BUTTON_L

SMC_BC_ACOK

=SMC_SMS_INT

SMC_PA5

SMC_CASE_OPEN

PM_SLPS3_BUF2_L

PM_SLP_S4_SMC_L MAKE_BASE=TRUE


SMC Support

Intersil ISL60002-33353S1278 ALL353S1381

10%

CERM

0.01UF16V

402

22PF

CERM50V

402

5%

CERM50V

22PF

5%

402

50 49

SMNTC020-CC1J-B260T

DEVELOPMENT

SILK_PART=SYS POWER

SMNTC020-CC1J-B260T

DEVELOPMENT

SILK_PART=SMC RESET

40210K

MF-LF1/16W5%

CRITICAL

SILK_PART=PWR BTN

M-RT-SM53261-8602

5%10K

1/16WMF-LF402

CRITICAL

SOT23-5-HFNCP303LSN

402MF-LF1/16W5%10K

MXM

IG

51

MF-LF

5%1/16W

402

MF-LF

0

1/16W

402

5%

1/16WMF-LF402

5%3.3K

MXM

2N7002DW-X-GSOT-363

MXM

2N7002DW-X-GSOT-363

MXM

5% 402

10K1/16W MF-LF

1/16WMF-LF

5%

0

402

MXM

85

49

14 100 11

SOT-3632N7002DW-X-G

10K1/16W 402MF-LF5%

5% MF-LF10K

4021/16W

MF-LF 4021/16W5%10K MF-LF1/16W 4025%100K

100K4025% MF-LF1/16W

5% 40210K

1/16W MF-LF

MF-LF 4025% 1/16W10K

5% 1/16W100K

MF-LF 402PLACEMENT_NOT=PLACE CLOSE TO U4900(SMC)

SOT23-HF12N7002

DEVELOPMENT

DEVELOPMENT

SILK_PART=SIL


402MF-LF

5%

DEVELOPMENT

1/16W

1K

5%10K

4021/16W MF-LF

1/16WMF-LF402

1K5%

402MF-LF1/16W5%10K

MF-LF10K

1/16W5% 402

49

100 14 11

402

1/16WMF-LF

5%470

1/16WMF-LF402

5%3.3K

MMDT3904-X-GSOT-363-LF

MF-LF1/16W5%

402

3.3K

SOT-363-LFMMDT3904-X-G

NO STUFF5% 402

10K1/16W MF-LF

1K

402

1/16WMF-LF

5%

402CERM

20%10V

0.1UF

49

49 51

1/16W MF-LF 402100K

5%

20.000M

CRITICAL

SM-4

MF-LF 40210K

1/16W5%

5%

10KMF-LF 4021/16W

5% MF-LF 4021/16W10K

10K1/16W5% MF-LF 402

5% 4021/16W MF-LF10K 402MF-LF1/16W5%100K 1/16W2.0K

MF-LF5% 402

MF-LF 402100K

5% 1/16W

5% MF-LF 40210K

1/16W

MF-LF1/16W10K

5% 402

402MF-LF1/16W5%100K MF-LF1/16W10K

4025%

SOT23-3REF3133

CRITICAL

6.3V

603

10uF20%

X5R

0.01UF10%

CERM402

16V

10%6.3VCERM-X5R402

0.47UF

2N7002DW-X-GSOT-363

CERM

0.1uF20%10V

402

49 45

49

49

49 46

95 49

51 49 46

49 51 46

49

49

49

49

53

108 54

49

49

54 53 49

49

49

85

50 49

49

49

49

49

49

49

49 54 108

49 54 108

54 108

49 53

49

55 50 6

49

6

49

49

49

49

6

49 50

49

54 53 6

55 50 6

71 55 10 6

49

49

21

21

85

50 49 6

49

49

49 51

49

49

49 51

51 49

49 51

49

50 49 6

50 49

21 49

49

49

49

49

49

49

70 49 9 6

49 70

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IN

BI

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

INOUT

INOUT

OUTIN

OUT

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL




36

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A

D

2 1


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PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

516S0573

FRANK CONNECTOR

LPC+SPI Connector

SPI Bus Series Resistance Option

Alternate SPI ROM Support

Pull-up on debug card

51 OF 110

051-7863

A.0.0


9

87

65

4

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J5100

21

R5145

2

1 C5144

21

R5146

2

1R5144

5

6

2

1

3 4

U51002

1R5140

21

R5158

21

R5157

21

R5156

=PP3V3_S5_LPCPLUS

SPI_CLK_R

SPI_ALT_MOSI

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

SPI_MOSI_R

SPI_MISO

=PP3V3_S5_LPCPLUS=PP5V_S0_LPCPLUS

LPC_CLK33M_LPCPLUS

SPIROM_USE_MLB

SMC_RESET_LSMC_NMISMC_RX_L

LPC_AD<0>

SPI_ALT_MOSISPI_ALT_MISO

SMC_TMSDEBUG_RESET_LSMC_TDOSMC_TRST_LSMC_MD1SMC_TX_L

SPI_ALT_CLK

LPCPLUS_GPIO

SMC_TCKSMC_TDILPC_PWRDWN_LLPC_SERIRQSPI_ALT_CS_LSPI_ALT_CLK

LPC_AD<3>LPC_AD<2>

LPC_AD<1>

LPC_FRAME_LPM_CLKRUN_L

SPIROM_USE_MLBMAKE_BASE=TRUE

SPI_ALT_CS_L SPI_CS0_L

=PP3V3_S5_ROM

SPI_MLB_CS_L

SPI_CS0_R_L

=SPI_CS1_R_L_USE_MLB

LPC+SPI Debug ConnectorSYNC_DATE=09/02/2009SYNC_MASTER=K22

PLACEMENT_NOTE=PLACE NEXT TO U51001/16W

402

0

MF-LF

5%

PRODUCTION

20K5%

1/16WMF-LF

402

LPCPLUS

PATH=I96

CRITICAL

SC70NC7SB3157P6XG

61

51

100K

1/16W5%

402MF-LF

51

LPCPLUS

0

MF-LF

5%1/16W

402

PLACEMENT_NOTE=Place next to R6105

21 61 103

51

LPCPLUS

1/16W5%

MF-LF

0

402

PLACEMENT_NOTE=Place next to R6152

21 61 103

51

1/16W

0

MF-LF

5%PLACEMENT_NOTE=Place next to R6150

402

LPCPLUS

21 61 103

9 103

19 49 103

19 49 103

51

51

51

19 49

19 49

49 50

49 50

49 50

49

46 49 50

18

M-ST-SM

LPCPLUSCRITICAL

55909-0374

19 49 103

51

19 49 103

19 49 103

51

19 49

49 50

9

49

49 50

49

46 49 50

21

21 103 0

MF-LF1/16W5%

402

LPCPLUS

PLACEMENT_NOTE=Place near U1400

402

20%10VCERM

0.1UF

6 51

6 51

6 51

6

51

103

6 61

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36

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A

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Apple Inc.

PAGE


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C

345678

D

B

8 7 5 4 2 1

(MASTER)

SMCU4900

SMC "MANAGEMENT" SMBUS CONNECTIONS

U2901

(WRITE: 0X30 READ: 0X31)

MARGINGING CONTROL

U2900

(Write: 0x98 Read: 0x99)

VREF DAC

(MASTER)SMC SLAVE ADDRESS TBD

DP RX MASTER FOR MCCS

DISPLAY TCON

POTENTIAL SMC SLAVE SMBUS CONNECTIONS

NV INSIDE (WRITE: 0X9E READ: 0X9F)MXM CARD (WRITE: 0X98 READ: 0X99)

Also reserve 0x56 and 0x32 per spec

MXM TEMPGPU ON CARD - J8400

DIODE2: CPU


(WRITE: 0X9A READ: 0X9B)

(WRITE: 0XA2 READ: 0XA3)

CPU - PECI DTS

3

2

1

4

6

5

DIODE

(MASTER)

ODD TEMP

LCD TEMP

FUNCTION

SMCU4900

OUTPUT VOLTAGE, CURRENT, POWER

AC/DC PS TEMPS


MAX6618 - U5570

SMC "0" SMBus Connections

SMBUS 0 ALSO GOES TO THE XDP CONNECTOR

EMC1403-2: U5535

DIODE1: MCP

DIE TEMPSSO-DIMM "B"

U4900

SMC

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE

MIKEYMCP79U1400

(MASTER)

J3200

SO-DIMM "A"J3100

MCP79U1400

(MASTER) (MASTER)

SMCU4900

SMC "A" SMBus Connections

U4900

(Write: 0xA0 Read: 0xA1) (MASTER)

SMC

MCP79 SMBUS "0" CONNECTIONS

DP TX EQ CONTROL

(WRITE: 0X9C READ: 0X9D)

DP RX EQ CONTROLU9200


J9800

U9100

(WRITE: 0X80, READ: 0X81))

INA219: ACDC THRU J600

(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)


EMC1047-2, U5500, SEE TABLE

REMOTE TEMPS

3 SENSE POINTS - PRIMARY, SECONDARY, AMB

EMC1403-[1,2]: ACDC THRU J600

SMC "B" SMBus Connections

AC/DC PS POWER

EMC1047-2 HEX DIODE SENSOR

CPU HEATSINK

MCP HEATSINK

MXM HEATSINK

AMBIENT TEMP

MCP79 SMBUS "1" CONNECTIONS

52 OF 110

051-7863

A.0.0


2

1R5202

2

1R5203

2

1R5250

2

1R5251

2

1R5270

2

1R5271

2

1R5260

2

1R5261

2

1R5290

2

1R5291

2

1R5281

2

1R5280

2

1R5201

2

1R5200

MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL

=SMB_ACDC_SCL

=SMB_REMOTE_TEMP_SCL

MAKE_BASE=TRUESMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCLMAKE_BASE=TRUE

=I2C_DP_EQLZ_SDA

=SMB_ACDC_SDA

MAKE_BASE=TRUESMBUS_SMC_B_S0_SDA

=I2C_DP_DRV_SDA

=I2C_SODIMMB_SDA

=I2C_DP_DRV_SCL

=I2C_DP_EQLZ_SCL

=PP3V3_S0_SMBUS_SMC_MGMT

=PP3V3_S0_SMBUS_SMC_B_S0

=SMB_MCP_CPU_THRM_SCL

SMB_A_S3_DATA

SMB_A_S3_CLK=I2C_SODIMMA_SCL

MAKE_BASE=TRUESMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

=SMB_MCP_CPU_THRM_SDA

=I2C_SODIMMB_SCL

SMBUS_MCP_0_DATAMAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S5_SMBUS_SMC_BSA

SMB_BSA_DATA

SMBUS_MCP_1_CLKMAKE_BASE=TRUE

=I2C_AUDIO_SCL

=I2C_AUDIO_SDA

SMB_0_S0_CLK

=SMB_CPU_PECI_SDA

=SMB_CPU_PECI_SCL

=PP3V3_S0_SMBUS

=SMB_REMOTE_TEMP_SDASMB_B_S0_DATA

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_MCP_1_DATA

=PP3V3_S0_SMBUS

=I2C_SODIMMA_SDA SMB_0_S0_DATAMAKE_BASE=TRUESMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUESMBUS_MCP_0_CLK

SMB_B_S0_CLK

=SMB_MXM_THRM_SCL

=SMB_MXM_THRM_SDA

=SMB_DP_TCON_SDA

=SMB_DP_TCON_SCLSMB_BSA_CLKMAKE_BASE=TRUESMBUS_SMC_BSA_SCL

MAKE_BASE=TRUESMBUS_SMC_BSA_SDA

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCLSMB_MGMT_CLK

SMB_MGMT_DATA

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

SMBus ConnectionsSYNC_MASTER=MASTER SYNC_DATE=N/A

1/16WMF-LF

5%2.2K

402

1/16WMF-LF

5%2.2K

402

402

5%4.7K

MF-LF1/16W

402

5%

MF-LF1/16W

4.7K

402

5%

MF-LF1/16W

100K

MF-LF

5%1/16W

100K

402

5%2.2K

MF-LF1/16W

402

2.2K

1/16W5%

402MF-LF

5%

402

1/16WMF-LF

4.7K

MF-LF402

1/16W5%4.7K

402

5%1/16WMF-LF

100K

MF-LF

5%

402

1/16W

100K

5%4.7K

1/16W

402MF-LF

402

1/16W5%

4.7K

MF-LF

106

6

55

106

106

92

6

106

91

32

91

92

6

6

55

49

4931

106

106

6

55

32

106 21 13

6

6

49

21 68

68

49

55

55

52 6

5549

106

21

52 6

31 49 106

106 21 13

49

85

85

90

9049 106

106

29

2949

49

29

29

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RS_P

RS_M

OUTGND

VCC

IN

OUT

IN

V+

REFIN+

IN- OUT

GND

OUT






36

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REVISION

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C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

CPU CURRENT SENSE AMP & FILTER

CPU Voltage Sense / Filter

CPU CORE INPUT SIDE CURRENT & VOLTAGE SENSE

PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)

AMPLIFIED AND FILTERED ISNS TO SMC

Place RC close to SMC MXM PWRSRC (GPU CORE & MEM) CURRENT SENSE

GAIN = 20

353S2291

K51 SET FOR APPROX 1.98V AT 5.5A ON PWRSRC

COUNT.0087518 A/COUNT2.778 A/V2 A/V

4 V/V

MXM PWRSRC VOLTAGE SENSE

.0129 V/COUNTCOUNT

0 TO 3.3V

(SCALING 12V INPUT VOLTAGE TO SMC)

PCB: PLACE C5359 WITHIN 1" OF SMC (U4900)

0 TO 3.3V

0 TO 3.3VADC IS 10BIT 0 TO 1023

SCALE

K50 SET FOR APPROX 2V AT 4A ON PWRSRC

COUNT.0064453 A/COUNT

SCALE

ADC IS 10BIT 0 TO 1023

SCALE

ADC IS 10BIT 0 TO 1023

PLACE RC CLOSE TO SMC

53 OF 110

051-7863

A.0.0


2

1R5361

5

2

4

1

3

U5360

2

1R5331

2

1 C5330

2

1R5330

3

1

6

4

5

2

U5320

2

1 C5321

2

1C5320

21

R5321

21

R5360

21

R5363

21

C5360

21

R5364

2

1 C5362

3

4

5

1

2

U5380

2

1 C5381

4321

R5380

2

1 C5380

2

1R5354

2

1R5353

2

1 C5359

2

1 C5309

21

R5309

SMC_CPU_INPUT_IOUT

GND_SMC_AVSS

SMC_GPU_ISENSE

=PPV_S0_MXM_PWRSRC

=PP3V3_S0_SMC

GND_SMC_AVSS

MXM_PWRSRC_SENSOR_N

MAKE_BASE=TRUE



VOLTAGE=12V

PPV_S0_MXM_PWRSRC


MXM_PWRSRC_SENSOR_P

=PPV_S0_MXM_PWR

CPU_VCC_SENSE

GND_SMC_AVSS

SMC_GPU_VSENSE

PPV_S0_MXM_PWRSRC

GND_SMC_AVSS

SMC_CPU_VSENSE

GND_SMC_AVSS

=PP5V_S0_ISENSE

SMC_CPU_ISENSE

VR_CPU_IOUT

GND_SMC_AVSS

PP12V_S0_CPU_FLTRD

=PP3V3_S0_SMC

SMC_CPU_INPUT_VSENSE

CPU_INPUT_ISENSE_P

CPU_INPUT_ISENSE_N

VR_ISNS_CPU_N

VR_ISNS_CPU_P

SNS_PS_CPU_ISNS

SMC_CPU_INPUT_ISENSE

RES, 0-Ohm, 0402 PRODUCTION116S0004 1 C5321

K22_MXMCRITICAL25 MILLIOHM R53801107S0063

K23_MXMCRITICALR538018 MILLIOHM1107S0111

132S0242 1 CAP,0.082UF,402 MXMC5381

116S0090 RES,10KOHM,5%,402 IGC53811


CPU/MXM CURRENT AND VOLTAGE SENSE

CAP, 0.22UF, 0402 DEVELOPMENTC5321132S0080 1

402

6.3V20%

X5R

0.22UF

1/16W1%

MF-LF402

4.53K108 49

10K1%1/16WMF-LF402 CRITICAL

SC70-5OPA348

MF-LF

6.04K

402

1%1/16W

20%

402X5R6.3V

0.22UF

MF-LF

1%1/16W

18.2K

402

SC70

CRITICAL

DEVELOPMENT

INA210

402

6.3V20%

X5R

0.22UF

OMIT

20%

CERM

DEVELOPMENT

0.1UF10V

402

DEVELOPMENT

1/16W1%

402

4.53K

MF-LF

108 71

MF-LF402

1/16W

10K

1%

MF-LF1/16W1%

402

21K

402CERM

0.01UF

20%16V

MF-LF1/16W5%

402

5.1K

402

6.3V0.22UF10%CERM-X5R

108 49

108 12

CRITICAL

SC70MAX4073TAXK+G65

MXM

OMIT

0.082UF

402CERM-X7R

10%16V

OMIT

MF

0.0251W

2512-1

1%

MXM

20%

402

6.3VX5R

0.22UF

1%

402MF-LF

6.04K1/16W

MXM

1%18.2K

402MF-LF1/16W

MXM

X5R

20%6.3V

0.22UF

402

54 53 50 49

108 49

84

54 53 50 6

54 53 50 49

108

53

108

6

54 53 50 49

108 49

53

54 53 50 49

54 53 50 49

6

54 53 50 49

72 71

54 53 50 6

50

71

71

108

50

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V+

REFIN+

IN- OUT

GND

OUTIN



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM






36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Place RC close to SMC

MCP CORE CURRENT SENSE

GAIN = 200V/V

MCP CORE VOLTAGE SENSE

SCALE IS 0.116 V/A

TRANSFER RATIO = 0.4V/A

1.5V S0 VOLTAGE SENSE

1.5V S0 CURRENT SENSE

353S2073

54 OF 110

051-7863

A.0.0


2

1R5405

2

1 C5404

21

R5404

21

R5403

2

1 C5403

2

1 C5402

21

R5402

2

1 C5400

2

1 C5401

4321

R5400

21

R5401

3

1

6

4

5

2

U5400

=PP3V3_S0_SMC

SMC_1V5_S0_ISENSE_R SMC_1V5_S0_ISENSE

PP1V5_S0

MCPCORES0_IMON

SENSE_1V5_S0_N

SMC_MCP_CORE_VSENSE

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

GND_SMC_AVSS

SMC_1V5_S0_VSENSE

GND_SMC_AVSS

PP1V5_S0_FET PP1V5_S0

SENSE_1V5_S0_P

GND_SMC_AVSS

PPMCPCORE_S0_REG

MCP CURRENT AND VOLTAGE SENSESYNC_MASTER=K22 SYNC_DATE=09/02/2009

CRITICAL1 R5400 PRODUCTION101S0414 RES,0 OHM,1206,20MILLIOHM MAX

1 CRITICALR5400 MCP_PWR_SENSE104S0018 RES,2 MILLIOHM,1206

PRODUCTION1116S0004 C5401RES, 0 OHM, 0402

1 MCP_PWR_SENSE132S0080 C5401CAP, 0.22UF, 0402

0.22UF20%

402X5R6.3V

MF-LF1/16W

402

4.53K

1%

0.22UF20%6.3VX5R402

MCP_PWR_SENSE

X5R

0.22UF20%

OMIT

402

6.3V

OMIT

MF-LF

1%

1206

0.0021/4W

MCP_PWR_SENSE

MF-LF402

4.53K

1%1/16W

1%

MF-LF

4.53K

NOSTUFF

402

1/16W

74 108

0.22UF20%6.3VX5R402

4.53K

MF-LF402

1/16W1%

50 108

MF-LF1/16W

402

4.53K

1%

20%0.22UF

402X5R6.3V

INA210SC70

MCP_PWR_SENSE

6 50 53

108 50 108

6 54

108

50 108

49 50 53 54

49 50 53 54

50 108

49 50 53 54

78 6 54

108

49 50 53 54

6 74

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BI

BIDN2/DP3

DP1

DN1

DP2/DN3

SMCLKGND

THERM*

SMDATA

VDD

ALERT*

BI

BI

DP2/DN3

DN2/DP3

DP1/DN6

DN1/DP6

GND

SMDATA

SMCLK

DN4/DP5

DP4/DN5

VDD

BI

BI

AGND

VREF

PECISDA

SCL

AD0

AD2

AD1

GND

VCC

OUT

OUT

GND

V+




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8 7 5 4 2 1

518S0677

SENSOR CH2 SENSOR CH3

is on csa 70 with power sequencingpower/gnd and ref for this dual part

Must pull high to 2.5V for compatibility with all drives

Cannot pull low because some drives use this bit todetermine 1.5 Gbps vs. 3.0 Gbps SATA

Drive disconnected = pulled highDrive asleep = HDD drives HDD_OOB_TEMP lowDrive active = valid signal protocol

FROM DRIVE:

LOW: -0.3V TO 0.5V

HIGH: 2.0V TO 3.6V

TO SMC

HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING

CPU PECI DTS OPTIONS

PLACEMENT NOTE: PLACE U5535 NEAR MCP, TOP SIDE UNDER HEATSINK

PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU

518S0678

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

SENSOR CH4

353S2224

SENSOR CH1SENSOR CH6

MCP & CPU T-Diode Thermal Sensor

SENSOR CH5

REMOTE THERMAL SENSORS

Consider 3rd option - direct to SMC

518S0678

HEATSINKS, AMBIENT, PANEL AND ODD

REMOTE THERMAL SENSORS (HEATSINKS AND ODD)

518S0698

518S0698

518S0698

518S0678

55 OF 110

051-7863

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8

1

3

2

4

U7030

2

1

4

3

J5535

2

1

4

3

J5550

2

1R5553

21

R5550

2

1R5554

2

1R5551

21

L5536

21

L5535

2

1C5580

21

R5571

2

1 C5571

2

1C5570

10

6

4

5

1

72

8

9

3

U5570

21

R5570

1

9

10

6

8

4

2

7

5

3

U5500

3

2

1

5

4

J5521

2

1 C5535

21

R5535

2

1

4

3

J5511

21

L5511

21

L5510

21

L5521

21

L5520

2

1

4

3

J5510

21

L5513

21

L5512

21

L5523

21

L5522

2

1

4

3

J5520

21

L5554

21

L5553

2

1

4

3

J5551

21

L5552

2

1C5536

1

7

9

10

6

4

2

5

3 8

U55352

1R5537

2

1R5536

21

R5538

2

1C5501

21

R5500

2

1C5502

2

1C5503

2

1C5504

SNS_T_DP1_DN6

CPU_PECI_L

SMB_PECI_L

MCP_THMDIODE_N

=PP3V3_S0_MCPTHMSNS

SNS_T_DP1_DN6DIFFERENTIAL_PAIR=SNS_T1

DIFFERENTIAL_PAIR=SNS_T2SNS_T_DN2_DP3

DIFFERENTIAL_PAIR=SNS_T3SNS_T_DP4_DN5

SNS_ODD_P

SNS_CPU_H_P

SNS_T_DN4_DP5

SNS_CPU_H_N

SNS_T_DN2_DP3

SNS_T_DP2_DN3

SNS_T_DP1_DN6

SNS_T_DN1_DP6

MCPTHMSNS_THERM_L

=SMB_MCP_CPU_THRM_SDA

MCP_THMDIODE_P

SNS_T_DP2_DN3DIFFERENTIAL_PAIR=SNS_T2

SNS_T_DN2_DP3

MCPTHMSNS_ALERT_L

SNS_T_DP2_DN3

DIFFERENTIAL_PAIR=SNS_T3SNS_T_DN4_DP5

MEM_EVENT_L

=PPVTT_S0_CPU

SNS_T_DP4_DN5

SNS_T_DN1_DP6

SNS_T_DN1_DP6DIFFERENTIAL_PAIR=SNS_T1

=PP3V3_S0_TSENS

=SMB_REMOTE_TEMP_SCL

SNS_MXM_P

SNS_MXM_N

VOLTAGE=3.3V


PP3V3_S0_TSENS_R


=SMB_REMOTE_TEMP_SDA

SNS_T_DN4_DP5

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP3V3_S0_MCPTHMSNS_R

CPU_THERMD_P

CPU_THERMD_N

=SMB_CPU_PECI_SCL

SNS_MCP_P

SNS_MCP_N=SMB_MCP_CPU_THRM_SCL

SNS_T_DP4_DN5

SNS_ODD_N

HDD_OOB_TEMP_FILT

=SMB_CPU_PECI_SDA

CPU_PECI_MCP

=PP3V3_S0_TSENS

HDD_OOB_TEMP

12VS5_1V60_REF

HDD_OOB_TEMP_R

=PP3V3_S0_SMC_LS

MAKE_BASE=TRUESMC_HDD_OOB_TEMP SMC_EXCARD_CP

SNS_LCD_N

SNS_LCD_P SNS_AMB_P

SNS_AMB_N


Thermal Sensors

CRITICAL

SOI-HFLM393

SILK_PART=MCP HSK

M-ST-SM53398-8602

CRITICAL

CRITICAL

M-RT-SM53780-8602

SILK_PART=HDD TEMP

402

200K

1/16W5%

MF-LF

3.3K

1/16W5%

402MF-LF

402

62K

1/16W5%

MF-LF 402

1K5%1/16WMF-LF

0402

FERR-220-OHM

FERR-220-OHM

0402

108 11

108 11

MCP_CPU_TDIODE

0.0022UF10%50VCERM402

SIGNAL_MODEL=EMPTY

PECI_SMB

20

5%1/16WMF-LF402

CERM402

0.1UF20%10V

PECI_SMBPECI_SMB

CERM402

0.1UF20%10V

PECI_SMB

USOP-HFMAX6618

108 14

PECI_MCP

402

1/16W5%

MF-LF

20108 11

TSSOP

EMC10472AIZL

CRITICAL

SILK_PART=AMBIENT TEMP

M-RT-SM53780-8603

CRITICAL

MCP_CPU_TDIODE

1UF

402-1X5R10V10%

1/16W

22

5%

MF-LF402

MCP_CPU_TDIODE

SILK_PART=MXM HSK

MXM

53398-8602

CRITICAL

M-ST-SM

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

FERR-220-OHM

FERR-220-OHM

0402

M-ST-SM53398-8602

SILK_PART=CPU HSK

CRITICAL

FERR-220-OHM

MXM

0402

MXM

0402

FERR-220-OHM

0402

FERR-220-OHM

FERR-220-OHM

0402

53780-8602

SILK_PART=LCD TEMP

M-RT-SM

CRITICAL

0402

FERR-220-OHM

0402

FERR-220-OHM53780-8602

CRITICAL

M-RT-SM

SILK_PART=ODD TEMP

FERR-220-OHM

0402

108 21

108 21

MCP_CPU_TDIODESIGNAL_MODEL=EMPTY

0.0022UF50V10%

402CERM

TSSOP

CRITICAL

EMC1403-2-AIZL

MCP_CPU_TDIODE

52

52

MCP_CPU_TDIODE

10K

MF-LF

5%1/16W

402

MCP_CPU_TDIODE

402

100K5%

1/16WMF-LF

1/16W

0

MF-LF402

5%

1UF10%

402-1X5R10V

402

22

1/16WMF-LF

5%

402CERM50V10%

0.0022UF

SIGNAL_MODEL=EMPTY

50VCERM402

10%0.0022UF

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

402

50VCERM

0.0022UF10%

108 55

108

6

108 55

108 55

108 55

110 108

108

108 55

108

108 55

108 55

108 55

108 55

108 55

108 55

108 55

108 55

49 32 31 21

71 50 10 6

108 55

108 55

108 55

55 6

52

108

108

52

108 55

52

108

108

108 55

110 108

108

52

55 6

70

108

50 6

108 49

110 108

110 108 110 108

110 108

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8 7 5 4 2 1

FAN 0

518S0592

GND

TACH

MOTOR CONTROL

518S0592

GND

TACH

MOTOR CONTROL

FAN 1

ODD FAN

NOTE: ADDED TO PROTECT SMC

HD FAN

12V DC

12V DC

56 OF 110

051-7863

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2

1 C5605

2

1 C5628

2

1R5630

2

1R5620

21

L5640

21

L5630

21

L5620

21

L5610

21

L5601

21

L5600

2

1 C5608

2

1 C5609

2

1 C5606

2

1 C5607

4

3

2

1

6

5

J5600

4

3

2

1

6

5

J5601

2

1 C5602

2

1

3

Q5605

2

1

3

Q5602

21

R5698

21

R5699

2

1R5611

2

1R5610

3

1

D5601

21

R5609

2

1 C5603

2

1R5607

5

4

876321

Q5603

2

1R5606

21

R5605

2

1 C5601

3

1

D5600

2

1R5603

5

4

876321

Q5600

2

1R5602

2

1R5601

2

1R5600


PP12V_S0_FAN1_LMIN_LINE_WIDTH=0.5MM

VOLTAGE=12V


FAN_1_PWR_L

FAN_TACH1_L


PP12V_S0_FAN0_LMIN_LINE_WIDTH=0.5MM

VOLTAGE=12V

FAN_0_PWR_L


FAN_TACH0_L

SMC_FAN_0_CTL

FAN_TACH1

=PP3V3_S0_FAN

=PP3V3_S0_FAN

=PP3V3_S0_FAN

SMC_FAN_0_TACH

SMC_FAN_1_TACH

=PP3V3_S0_FAN

FAN_TACH0

SMC_FAN_1_CTL

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMFAN_0_GND

MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMFAN_1_GND

=PP12V_S0_FAN


FAN_0_PWR

MIN_LINE_WIDTH=0.5MMF0_VOLTAGE8R5


F0_GATESLOWDN

=PP12V_S0_FAN


FAN_1_PWRMIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MMF1_VOLTAGE8R5


F1_GATESLOWDN


HD AND OD FAN

100UF

6.3X5.5-SM1-HFELEC16V20%

CRITICAL

X5R603

2.2UF10%16V

PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3

5%1/10WMF-LF603

0


603

05%1/10WMF-LF

CRITICAL

0603

220-OHM-1.4A

0603

220-OHM-1.4A

CRITICAL

CRITICAL

0603

220-OHM-1.4A

0603

CRITICAL

220-OHM-1.4A

CRITICAL

FERR-220-OHM

0402

FERR-220-OHM

CRITICAL

0402

2.2UF16V10%

603X5R CERM

402

0.01UF20%16V

4.7UF16V

1206-1CERM20%

0.01UF16VCERM20%

402

CRITICAL

53780-8604M-RT-SM

M-RT-SM53780-8604

CRITICAL

CRITICAL

100UF

6.3X5.5-SM1-HFELEC16V20%

SOT23-HF12N7002

SOT23-HF12N7002

402MF-LF1/16W5%

47K

402

1/16W

47K

5%

MF-LF

1/16W5%

402MF-LF

10K1.5K

MF-LF

5%

1206

1/4W

SOT23MMBD914XG

3.9K

MF-LF1/8W5%

805

16VX7R805

10%0.47UF

1/8W5%

MF-LF805

1.5K

1206A-03-HF

CRITICAL

NTHS5443T1H

MF-LF1/16W

10K

402

5%

3.9K

MF-LF

5%1/8W

805

805

16V10%X7R

0.47UF

MMBD914XGSOT23

1.5K

MF-LF1/8W

5%

805

1206A-03-HF

CRITICAL

NTHS5443T1H

5%1.5K1/4WMF-LF1206

402

1/16W

10K5%

MF-LF

5%10K1/16WMF-LF402

110

110

110

110

110

110

49

57 56 6

57 56 6

57 56 6

49

49

57 56 6

49

110

110

57 56 6

57 56 6

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8 7 5 4 2 1

518S0592

MOTOR CONTROL

FAN 2

CPU FAN

12V DC

GND

TACH

57 OF 110

051-7863

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4

3

2

1

6

5

J5700

2

1R5720

21

L5720

21

L5710

21

L5701

2

1 C5709

2

1 C5708

2

1 C57022

1

3

Q5702

21

R5797

2

1R5705

2

1R5704

21

R5703

2

1 C5701

2

1R5701

3

1

D5700

5

4

876321

Q5700

2

1R5700

=PP3V3_S0_FAN

SMC_FAN_2_TACH

=PP3V3_S0_FAN

SMC_FAN_2_CTL

FAN_TACH2


FAN_2_GND


FAN_2_PWR_L


FAN_TACH2_L

PP12V_S0_FAN2_L


VOLTAGE=12V

=PP12V_S0_FAN

FAN_2_PWR


F2_VOLTAGE8R5MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

F2_GATESLOWDN

CPU FANSYNC_MASTER=K22 SYNC_DATE=09/02/2009

402MF-LF1/16W5%

47K

1/16W5%

402

10K

MF-LFMF-LF1206

1.5K1/4W5%

1/8W5%

3.9K

MF-LF805

805X7R16V10%0.47UF

MF-LF

1.5K5%

805

1/8W

MMBD914XGSOT23

1206A-03-HFNTHS5443T1H

CRITICAL

10K5%

402MF-LF1/16W

CRITICAL

53780-8604M-RT-SM


MF-LF

05%1/10W

603

220-OHM-1.4A

CRITICAL

0603

CRITICAL

220-OHM-1.4A

0603

CRITICAL

FERR-220-OHM

0402

20%16V0.01UF

CERM402

20%16VCERM1206-1

4.7UF

CRITICAL

6.3X5.5-SM1-HFELEC16V20%100UF

2N7002SOT23-HF1

6 56 57

49

6 56 57

49

110

110

110

110

6 56

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051-7863

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BLANK PAGE

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051-7863

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SO

VDD

CE*

SCK

VSSHOLD*

SI

WP* OUTIN

IN IN




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8 7 5 4 2 1

0

SPI_CLK

0

1

1

SST25VF016B max speed for READ command is 25MHz.

MCP79 SPI Frequency Select

SPI_MOSI

NOTE: MCP79 only issues ’READ’ (0x03) commands

frequency and part selection.

not ’READ_FAST’ (0x0B). Limits SPI bus

0

Frequency

31 MHz

1

1

25 MHz

1 MHz

42 MHz 0

61 OF 110

051-7863

A.0.0


2

1R6191

2

1R6190

21

R615021

R6152

21

R6105

3

4

8

2

56

7

1

U61002

1R6100

2

1R6101

2

1C6100

SPI_MISOSPI_MISO_R

SPI_MOSI_RSPI_CLK_R

SPI_MLB_CS_L

SPI_MOSISPI_CLK

SPI_HOLD_L

SPI_WP_L

=PP3V3_S5_ROM

SYNC_MASTER=K22

SPI ROMSYNC_DATE=09/02/2009

402

10K

1/16W5%

MF-LF

10K

1/16W5%

MF-LF402

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%1/16W

0

402

PLACEMENT_NOTE=PLACE CLOSE TO U6100

402

0

1/16W5%

MF-LF

402

0

1/16W5%

MF-LF

21 51 103 21 51 103

5121 51 103

16MBITSOI

OMIT

SST25VF016B

CRITICAL

402

3.3K

MF-LF

5%1/16W

402MF-LF

3.3K5%1/16W

402

20%

CERM

0.1UF10V

103

103103

6 51

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IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

NR/FB

NC

IN

EN

GND

IN

OUT

IN

IN

OUT

IN

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC

FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+

MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI

SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+

LINEOUT_L2-

LINEOUT_R2+

/SPDIF_OUT2IN




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APPLE P/N 353S2592AUDIO CODEC

K23 LOW = S/PDIF IN, HIGH = DP SPDIFK22 = NC

NC

NC

NC

NC

NC

NCNC

DAC2/3 FSOUTPUTDIFF= 2.67VRMSDAC1 FSOUTPUT= 1.34VRMSSE FSINPUT= 1.22VRMSDIFF FSINPUT= 2.45VRMS

HP OUT ZOBEL NETWORK

DAC2/3 FSOUTPUTSE= 1.34VRMS

NC

4.5V POWER SUPPLY FOR CODECAPPLE P/N 353S2456

62 OF 110

051-7863

A.0.0


2

1 C6207

2

1 C6202

2

1 C6205

27

1

3

44

41

9

28

29

24

46

25

49

10

48

47

13

5

8

1119

20

18

17

16

32

33

36

37

31

30

35

34

23

21

22

39

40

38

15

14

12

2

45

42

43

4

7

6

26

U6201

2

1C6204

2

1R6295

2

1C6297

2

1C6298

2

1R6297

2

1R6296

21

R6257

2

1R6298

2

1R6299

2

1C6266

1

3

5

6

2

4

VR6201

2

1C6259

2

1C6260

2

1 C6262

2

1 C6263

2

1C6261

21

R6254

2

1R6267

2

1R6263

2

1R6255

2

1C62652

1 C6258

2

1C6264

2

1 C6201

21

R620121

L6201

2

1 C62132

1C6203

2

1C6211

2

1 C6208

2

1C6206

21

XW6201

GND_AUDIO_HP_AMP_L

=PP1V5_S0_AUD_DIG

AUD_HP_PORT_LMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

PP4V5_AUDIO_ANALOGMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.10MM

VOLTAGE=4.5V

VBIAS_DAC

CS4206_FLYC

CS4206_FPCS4206_FN

GND_AUDIO_CODEC


VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM

AUD_SPDIF_CHIPAUD_SPDIF_IN_CODEC

=PP3V3_S0_AUDIO

4V5_REG_EN

VOLTAGE=5V

4V5_REG_IN


=PP3V3_S0_AUDIO

AUD_HP_PORT_RMIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM AUD_HP_PORT_REF

GND_AUDIO_CODEC

=PP5V_S0_AUDIO

AUD_GPIO_1


AUD_HP_PORT_L


AUD_Z_R

4V5_NR

AUD_LI_N_RHDA_SDIN0


AUD_HP_PORT_R

=PP5V_S0_AUDIO

=PP3V3_S0_AUDIO

AUD_LI_N_L

AUD_Z_L


GND_AUDIO_HP_AMP_L

GND_AUDIO_HP_AMP_L

GND_AUDIO_HP_AMP_LVOLTAGE=0V

AUD_SPDIF_OUT

CS4206_VREF_ADC

AUD_MIC_INP_RAUD_MIC_INN_R

HDA_BIT_CLK

AUD_SDI_R

TP_AUD_DMIC_CLK

HDA_SYNC

AUD_MIC_INN_LAUD_MIC_INP_L

AUD_LI_P_R

CS4206_FLYN

AUD_LO2_P_L

HDA_RST_LHDA_SDOUT

PP4V5_AUDIO_ANALOG

CS4206_FLYP TP_AUD_LO2_N_L

AUD_CODEC_MICBIAS

TP_AUD_LO2_N_RAUD_LO2_P_R

TP_AUD_LO1_N_R

CS4206_VCOM

AUD_LI_P_L

MAKE_BASE=TRUE AUD_LI_COM

AUD_LO1_P_RTP_AUD_LO1_N_L

AUD_LO1_P_L

AUD_SENSE_A

AUD_GPIO_3AUD_GPIO_2AUD_GPIO_1AUD_MUX_CNTRL

AUDIO: CODEC/REGULATORSYNC_MASTER=K22 SYNC_DATE=09/02/2009

10V10%

X5R

1UF

402-110V10%

X5R

1UF

402-1

603

20%6.3VX5R

10UF

62

CS4206ACNZCQFN

CRITICAL603

10UF20%

6.3VX5R

MF-LF

1%100K

402

1/16W

9

66 103

62 63

62 63

10%

402

16V

0.1UF

X7R-CERM402

16V10%

X7R-CERM

0.1UF

395%

1/16WMF-LF

402

1/16W

402

395%

MF-LF

MF-LF

5%1/16W

22

402

62

6 62 64 65 66 67 68

402

10K5%

MF-LF1/16W

EDUCATION

1/16W

BETTER

100K5%

402MF-LF

0.1UF10%

402X7R-CERM

16V

TPS71745SON

CRITICAL

X5R10V10%

402-1

1UF

6 62 68

6 62 64 65 66 67 68

62

66

62

62

6 62 64 65 66 67 68

6 62 68

POLY-TANTCASE-B2-SM

20%10UF

16V 10UF

POLY-TANT

20%16V

CASE-B2-SM

16V20%

POLY-TANTCASE-B2-SM

10UF

CRITICAL

0.47UF

402

10V10%

X5R

1/16W

22

MF-LF

5%

402

1/16WMF-LF402

5%100K

NOSTUFF

402

5%0

MF-LF

NOSTUFF

1/16W

1%1/16W

2.67K

402MF-LF

10V10%

0.47UF

402X5R

0.47UF10%

X5R10V

402

402X5R10V10%

0.47UF

10V10%

X5R

1UF

402-1

2.21K

1%

402MF-LF1/16W

0402

FERR-220-OHM

63

63

X5R603

6.3V

10UF

CRITICAL

20%

67

67

68

68

63

63

67

65

65

64

64

62 63

62 63

64 68

64 65 68

67

21 103

21 103

21 103

21 103

21 103

20%

402X5R4V

4.7UF

CRITICAL

10%1UF

TANT20V

CASE-P3-HF

CERM6.3V20%

402-LF

2.2UF

CERM

20%

402-LF

2.2UF6.3V

SM

62 63 66

6

62 63 64 65 67 68

62 63 64 65 67 68

103

62 63 64 65 67 68

62 63 66

62 63 66

62 63 66

103

9

www.bblianmeng.com

www.vinafix.vn

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CODEC Nom SE RIN = 20K OHMS

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

1ST ORDER DAC FILTER PLACEHOLDER

FC = 5 HZ Max

NET RIN = 18K OHMS

63 OF 110

051-7863

A.0.0


2

1 C6301

2

1 C6304

21

R6306

2

1R6305

2

1R6301

21

R6300

2

1R6303

21

C6305

21

C6303

21

C6302

21

C6300

21

R6325

2

1C6321

2

1C6320

21

R6324

AUD_LI_N_R

MIN_NECK_WIDTH=.2MMMIN_LINE_WIDTH=.3MM


AUD_LI_N_L

MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM

AUD_LI_P_LAUD_LI_L


GND_AUDIO_CODEC


AUD_HP_R

GND_AUDIO_HP_AMP_L

AUD_HP_PORT_R


AUD_HP_LAUD_HP_PORT_L


AUD_LI_R



AUD_LI_P_R

AUD_LI_LF


AUD_LI_GND


AUD_LI_RF

MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM

AUD_LI_GND


SYNC_MASTER=SKIPAUDIO SYNC_DATE=04/20/2009

AUDIO: FILTER/BUFFER

402CERM

NOSTUFF

50V

820PF10%

402

NOSTUFF

50VCERM

820PF10%

7.87K

1%1/16WMF-LF402

1/16W

402MF-LF

1%21.5K

1/16W

21.5K

402MF-LF

1%

1%

MF-LF

7.87K

1/16W

402

MF-LF1/16W1%10

402

63 66

66

68 65 64 67 62

63 66

66

10%

805-1

3.3UF

10V

CRITICAL

CERM-X5R

10V10%

CERM-X5R

3.3UF

805-1

CRITICAL

CRITICAL

10V

805-1

10%

3.3UF

CERM-X5R

805-1CERM-X5R

10%10V

3.3UF

CRITICAL

62

62

62

62

66 62

603MF-LF

0

5%1/10W

66

66

62

62

603

CRITICAL

2200PF

C0G-CERM50V5%

NOSTUFF

2200PF

C0G-CERM

5%50V

603

CRITICALNOSTUFF

0

MF-LF1/10W5%

603

www.bblianmeng.com

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

REG

VS

C1P

BOOT

C1N

OUTL1-

OUTL1+

OUTL2-

OUTL2+

OUTR1-

OUTR1+

OUTR2-

OUTR2+

NC1

NC2

NC3

FBL

COM

INL

INR

FBR

MONO

SHDN*

MOD

REGEN

MUTE*

THMPGNDAGND

PVDD

PAD




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

CODEC OUT = 1.335VRMS

TWEETER SPEAKER AMPLIFIERMAX9736B APN:353S2042

GAIN = -4.8(20K/17.4K)

AMP VOUT = 7.355VRMSFC = 19.5 HZ

TURN ON DELAY: 150MSTURN ON TIME: 110MS

RIN = 17.4 OHMS

64 OF 110

051-7863

A.0.0


21

R6407

21

R6405

2

1R6406

2

1C6499

21

C6495

21

C6496

21

R6404

21

R6402

2

1 C6404

21

R6403

21

C6413

2

1 C6405

21

R640121

R6400

21

C64122

1C6403

2

1C6402

16

10

11

15

30

27

29

28

26

24

25

23

32

2

31

1

17

8

7

9

4

20

18

6

19

5

33

12

22

21

3

14

13

U6400

2

1 C6410

21

L6403

2

1 C6407

2

1C6406

2

1C6401

2

1 C6411

21

L6401

21

L6402

2

1C6408

2

1 C6409

21

L6400

AUD_SPKR_OUTLO1R_NOUT

AUD_SPKR_OUTLO1R_POUT

AUD_SPKR_OUTLO1L_NOUT

AUD_SPKR_OUTLO1L_POUTAUD_L_P1


AUD_L_N10.5MM0.2MM

AUD_BOOT1


MAX9736_INT_1REG

AUD_SPKRAMP_1MUTE_L

AUD_GPIO_2

AUD_GPIO_3

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO AUD_SPKRAMP_1SHDN_L

AUD_MAX9736_1FBL

AUD_MAX9736_1COM

=PP3V3_S0_AUDIO

GND_AUDIO_SPKRAMP_PLANE


VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM



AUD_LO1_P_R


AUD_LO1_P_L

L01_P_R


AUDSAMPCPP1


MIN_LINE_WIDTH=0.2MMAUDSAMPCPN1




PP12V_AUD_SPKRAMP_PLANE


AUD_R_N1MIN_LINE_WIDTH=0.5MM

AUD_R_P1 0.2MM0.5MM


AUD_MAX9736_1VREG

AUD_MAX9736_1INL

AUD_MAX9736_1INRAUD_MAX9736_1FBR

L01_P_L


SYNC_DATE=04/20/2009SYNC_MASTER=SKIPAUDIO

AUDIO: Tweeter Amp 1

1/16WMF-LF

17.4K

1%

402

1%

402MF-LF1/16W

20.0K

402

0.001UF

X7R50V10%

NOSTUFF

402-1X5R

10%1UF10V

402-1X5R

1UF10V10%

TQFNCRITICAL

MAX9736BETJ+

X7R25V

1UF10%

805

180-OHM-1.5A

0603-LF

CRITICAL

NP0-C0G

5%1000PF25V

402

25V

402NP0-C0G

5%1000PF

0.1UF

CERM603

16V20%

X7R50V10%

603-1

0.1UF

0603-LF

CRITICAL180-OHM-1.5A

0603-LF

180-OHM-1.5ACRITICAL

1000PF5%

NP0-C0G402

25V

402

25V

1000PF5%

NP0-C0G

CRITICAL

0603-LF

180-OHM-1.5A

66

66

66

66

68 620

MF-LF402

5%1/16W

NOSTUFF1/16W5%

402MF-LF

0

402

100K5%1/16WMF-LF

16VELEC

SM-CASE-C1-HF

220UF20%

65 64 67

65 68 62

68 67 66 65 64 62 6

68 67 66 65 64 62 6

62

0.47UF

X5R10V10%

402

62

65 64 67

X5R

10%

0.47UF

402

10V

65 64 67

65 67

MF-LF1/16W5%

0

402

MF-LF1/16W

17.4K

1%

402

402

50VCERM

5%100PF

1%

MF-LF402

1/16W

20.0K

402

0.001UF

X7R50V10% NOSTUFF

402-1

10%

X5R

1UF10V

68 65 63 67 62

www.bblianmeng.com

www.vinafix.vn

REG

VS

C1P

BOOT

C1N

OUTL1-

OUTL1+

OUTL2-

OUTL2+

OUTR1-

OUTR1+

OUTR2-

OUTR2+

NC1

NC2

NC3

FBL

COM

INL

INR

FBR

MONO

SHDN*

MOD

REGEN

MUTE*

THMPGNDAGND

PVDD

PAD

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AMP VOUT = 7.355VRMS

TURN ON TIME: 110MSGAIN = -4.8(20K/17.4K) TURN ON DELAY: 150MS

FC = 19.5 HZCODEC OUT = 1.335VRMS

POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

MAX9736B APN:353S2042WOOFER SPEAKER AMPLIFIER

RIN = 17.4 OHMS

65 OF 110

051-7863

A.0.0


2

1R6506

2

1C6599

2

1 C6505

2

1C6503

21

C6595

21

C6596

21

C6513

21

C6512

21

R650321

R6502

21

R650021

R6501

2

1 C6507

2

1C6508

21

L650221

L6501

2

1 C650921

R6504

2

1 C6511

21

L6503

21

L6500

2

1C6502

2

1C6501

21

R6505

2

1 C6504

16

10

11

15

30

27

29

28

26

24

25

23

32

2

31

1

17

8

7

9

4

20

18

6

19

5

33

12

22

21

3

14

13

U6500

2

1 C65102

1C6506




AUD_SPKR_OUTLO2L_POUT


VOLTAGE=12V







GND_AUDIO_CODEC

AUD_GPIO_3

=PP3V3_S0_AUDIO

AUD_SPKRAMP_MUTE_L

AUD_MAX9736_INL

AUD_R_POUT 0.2MM0.5MM

AUD_SPKRAMP_SHDN_L=PP3V3_S0_AUDIO

AUDSAMPCPNMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.15MM


AUD_LO2_P_L


AUDSAMPCPPMIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.2MM

AUD_R_NOUT



L02_P_R


AUD_LO2_P_R

AUD_L_NOUT0.5MM0.2MM

AUD_L_POUT



MAX9736_INT_REG

AUD_MAX9736_VREG



L02_P_L

AUD_MAX9736_FBL

AUD_MAX9736_COM

AUD_MAX9736_INRAUD_MAX9736_FBR

AUD_BOOT

AUDIO: Woofer AmpSYNC_DATE=04/20/2009SYNC_MASTER=SKIPAUDIO

402MF-LF1/16W5%100K

16VELEC

SM-CASE-C1-HF

220UF20%

402-1

10%

X5R

1UF10V

402-1X5R

10%1UF10V

0.47UF

X5R10V

402

10%

X5R

10%

0.47UF

402

10V

65 64 67

65 64 67

65 64 67

64 68 62

68 67 66 65 64 62 6

68 67 66 65 64 62 6

62

62

64 67

0.001UF

402X7R50V10% NO STUFF

402X7R

10%

NO STUFF

0.001UF

50V

1%

MF-LF402

1/16W

20.0K

MF-LF1/16W

17.4K

1%

402

1%

402MF-LF1/16W

20.0K17.4K

1%

402MF-LF1/16W

NP0-C0G

5%1000PF25V

402

1000PF5%

NP0-C0G402

25V

CRITICAL

0603-LF

180-OHM-1.5A0603-LF

180-OHM-1.5ACRITICAL

66

66

66

66

NP0-C0G

5%1000PF25V

402402

0

5%1/16WMF-LF

X7R50V10%

603-1

0.1UF

180-OHM-1.5A

0603-LF

CRITICAL

CRITICAL

0603-LF

180-OHM-1.5A

402-1

10%

X5R

1UF10V

0.1UF

603

16V20%

CERM

1/16W5%

402MF-LF

0

402

50VCERM

5%100PF

TQFNMAX9736BETJ+

CRITICAL

805

10%1UF25VX7R

25V

402NP0-C0G

5%1000PF

68 64 63 67 62

www.bblianmeng.com

www.vinafix.vn

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

INOUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AUD_HP_GND_JACK

AUD_LI_GND_JACK

PP3V3_AUDIO_SPDIF_JACK

APPLE P/N 518S0723

NCTWEETER (SECONDARY)

PROPERTIES FOR ALL SPKR NETS

WOOFER (PRIMARY)WOOFER (PRIMARY)

TWEETER (SECONDARY)

REMOTE I/O CONNECTOR

SPEAKER CABLE CONNECTORSAPPLE P/N 518S0656APPLE P/N 518S0748INTERNAL MIC CON

APPLE P/N 518S0677

PROPERTIES FOR ALL SPKR NETS

66 OF 110

051-7863

A.0.0


4

3

2

1

J6602

5

4

3

2

1

J6603

21

L661821

L6616

21

R6610

21

R661721

XW6617

21

L661321

L6612

21

L6606

21

R6601

21

L6605

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J6600

3

2

1

5

4

J6601

21

L6615

2

1C6600

2

1

DZ66032

1

DZ6615

2

1

DZ66062

1

DZ6608 2

1

DZ6610 2

1

DZ6612 2

1

DZ6614

21

L660921

L6608

21

L6607

2

1 C6601

2

1R6600

2

1

DZ6607

2

1

DZ6604

21

L6614

2

1

DZ66092

1

DZ66052

1

DZ6611 2

1

DZ6613

2

1

DZ66012

1

DZ6600

21

L6604

21

L6601

21

L6603

21

L6600

21

L6602

AUD_SPKR_OUTLO2R_POUTAUD_SPKR_OUTLO2R_NOUT


AUD_IP_PERPH_JACKMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_HP_R_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

AUD_MIC_IN1_N_CONN


AUD_MIC1_IN_P

=PP3V3_S0_AUDIO


AUD_MIC1_IN_N

AUD_MIC_IN1_P_EMI


AUD_MIC_IN1_N_EMI

AUD_SPDIF_IN


HS_MIC_HI


AUD_LI_L

AUD_HP_TYPE


AUD_SPDIF_OUT

MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MMVOLTAGE=0VHS_MIC_LO

AUD_IP_PERPH_DETMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

AUD_LI_GNDMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

AUD_LI_TIP_DET


AUD_LI_R


AUD_HP_TIP_DET


AUD_HP_LMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0VAUD_HP_R

AUD_HP_TYPEDET_JACKMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

AUD_HP_PORT_REF


MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMGND_AUDIO_HP_AMP_L


AUD_MIC_IN1_P_CONN

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_LI_R_JACKMIN_LINE_WIDTH=0.3MM AUD_LI_GND_JACKMIN_NECK_WIDTH=0.2MM


AUD_SPDIFIN_JACK

GND_AUDIO_MIC1_CONN

MIN_LINE_WIDTH=0.2MMVOLTAGE=0VMIN_NECK_WIDTH=0.1MM

NC_J6702_3NO_TEST






MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM AUD_LI_L_JACK

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_LI_DET_JACK

AUD_SPDIF_OUT_JACK



MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM HS_MIC_LO_JACKMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM HS_MIC_HI_JACK

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM AUD_HP_TIPDET_JACK

MIN_LINE_WIDTH=0.2MM PP3V3_AUDIO_SPDIF_JACKMIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

AUD_HP_L_JACKMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_HP_GND_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

Audio: MLB to I/O Conn.SYNC_MASTER=K22 SYNC_DATE=09/02/2009

CRITICAL

78048-0473M-RT-SM

78048-0573M-RT-SM

CRITICAL

0402

220-OHM-0.7A-0.28-OHM0402

220-OHM-0.7A-0.28-OHM

MF-LF1/10W

0

5%

603

1/10W

0

5%

603MF-LF

SM

63

63

63

67

62

FERR-1000-OHM

0402

FERR-1000-OHM

0402

0402

FERR-1000-OHM

67

9 103

MF-LF

22

402

1/16W5%

FERR-1000-OHM

0402

F-RT-SM

CRITICAL

20143-020E-20F

M-RT-SM

CRITICAL

53780-8603

0402

FERR-1000-OHM

10%1UF

402-1X5R10V

CRITICAL

4026.8V-100PF

6.8V-100PF402

CRITICAL

CRITICAL

4026.8V-100PF

CRITICAL

4026.8V-100PF

CRITICAL

4026.8V-100PF 6.8V-100PF

402

CRITICAL

6.8V-100PF

CRITICAL

402

67

62 63

68

68

0402

FERR-1000-OHM

63

0402

FERR-1000-OHM

63

0402

FERR-1000-OHM

402

0.47UF10%

X5R10V

5%

MF-LF402

01/16W

67

67

65

65

64

64

64

65

65

64

6 62 64 65 67 68

67

62 103

6.8V-100PF402

CRITICAL

6.8V-100PF

CRITICAL

402

0402

FERR-1000-OHM

402

CRITICAL

6.8V-100PF6.8V-100PF402

CRITICALCRITICAL

4026.8V-100PF 6.8V-100PF

402

CRITICAL

CRITICAL

4026.8V-100PF

4026.8V-100PF

CRITICAL

0402

FERR-1000-OHM

0402

FERR-1000-OHM

FERR-1000-OHM

0402

FERR-1000-OHM

0402

0402

FERR-1000-OHM

110

110

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G

S

D

G

S

D

G

S

D

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN OUT

OUT

OUT

IN

OUT

OUT

G

S

D

IN

IN

G

S

D

G

S

D

IN

G

S

D

G

S

D

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Place Across Ground Split

NC NC

DP Audio Enable

Headphone OutDigital Out LI Insert Detect

Internal Microphone Impedance Matching

IPHS HS Detect Debounce CKT

Audio Ground Returns

67 OF 110

051-7863

A.0.0


21

R6749

21

R6748

4

5

3

Q6703

1

2

6

Q6701

2

1R6768

2

1R6762

4

5

3

Q6700 1

2

6

Q6703

2

1R6730

2

1R6731

21

R6732

2

1 C6740

21

R6700

2

1R6797

4

5

3

Q6701

2

1R6792

2

1R679321

R67472

1C6751

2

1R6798

2

1R6791

21

C6796

2

1R6701

21

R6796

2

1 C6797

21

R6799

2

1R6794

2

1R6744

2

1C6750

2

1R6795

2

1R6790

4

5

3

Q6702

1

2

6

Q6702

1

2

6

Q6700

21

L6739

21

L6738

21

XW670421

XW6703

21

R6743

21

XW6705

21

XW6702

21

C6795

AUD_LI_TIP_DET_INV

AUD_HP_TYPE_INV

AUD_HP_TIP_DET_INV

AUD_HP_TYPE

MUX_CNTRL

AUD_LI_TIP_DET AUD_LI_TIP_D

AUD_IP_PERPH_DET_R

=PP3V3_S0_AUDIO

AUD_MIC_INP_RMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

GND_AUDIO_CODEC


AUD_INTMICBIAS



AUD_CODEC_MICBIAS



AUD_MIC1_IN_N


AUD_MIC1_IN_G

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_Q6701_D6AUD_Q6702_D3

GND_AUDIO_CODEC

AUD_SENSE_A

=PP3V3_S0_AUDIO

AUD_HP_TIP_DET

=PP3V3_S0_AUDIO


MIN_NECK_WIDTH=0.2MMVOLTAGE=12V




=PP12V_S0_AUDIO_SPKRAMP

AUD_IP_PERIPHERAL_DET

AUD_IP_PERPH_DET_INV

AUD_IP_PER_DEBAUD_IP_PERPH_DET

=PP3V3_S0_AUDIO


AUD_MIC1_IN_P

AUD_IP_PERPH_DET_DB

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_SENSE_AAUD_SENSE_A


AUD_MIC_INN_R

GND_AUDIO_CODEC

SYNC_MASTER=SKIPAUDIO SYNC_DATE=04/20/2009

AUDIO: Detects/Grounding

402

5%

0

MF-LF

NOSTUFF

1/16W

1/16W

NOSTUFF

MF-LF

0

5%

402

95SOT-563-HFNTZD3154NT1H

SOT-563-HFNTZD3154NT1H

1/16W5%

MF-LF402

100K

68 67 66 65 64 62 6

MF-LF1/16W5%100K

402

NTZD3154NT1HSOT-563-HF


68 67 66 65 64 62 6

100K1/16W

402MF-LF

5%

05%1/16WMF-LF402

1/16WMF-LF

0

5%

402

NOSTUFF

66

0.1UF10%

402X5R16V

17.4K

402MF-LF1/16W1%

1/16W

402

100K5%

MF-LF


MF-LF

1%1/16W

402

3.40K

402

1%1/16WMF-LF

3.40K

62

62

1/16W

NOSTUFF

MF-LF

0

5%

402

CRITICAL

4.7UF

TANT

20%6.3V

603-HF

62

1/16W5%

MF-LF

100K

402

68 65 64 63 67 62

65 64

65 64 6

67 62

66

67 62

6867 66 65 64 62 6

66

66

68 67 66 65 64 62 6

67 62

66

66

100K5%1/16W

402MF-LF 0.1UF

16V

402X5R

10%

MF-LF

10K1%

402

1/16W

5%

402MF-LF1/16W

0

X5R

NOSTUFF

10%16V

0.1UF

402

402

0

5%1/16WMF-LF

17

0.1%

402

1/16W

20K

CRITICAL

MF402

1%

MF-LF

39.2K1/16W

X7R

0.0082UF25V10%

402

MF-LF

100K1/16W

402

5%

402

100K5%1/16WMF-LF




FERR-250-OHM

SM-1

FERR-250-OHM

SM-1

OMITSM

OMITSM

1/16WMF-LF402

5%

2.2KSM OMIT

SM

10%

X5R16V

402

0.1UF

68 67 66 65 64 62 6

68 65 64 63 67 62

68 65 64 63 67 62

68 65 64 63 67 62 68 65 64 63 67 62

68 65 64 63 67 62

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IN

BI

OUT

IN

IN

IN

OUT

OUT

IN

INOUT

OUTIN

IN

GND THMENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASSINT*

SCL




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

APN 353S2256

MIKEY RECEIVER CKTWRITE: 0X72 READ: 0X73

0X0C

GPIO 3CNTRL

FHP = 80 HZ

MIKEY

FLP = 8.82 KHZ

MICBIAS 80%

N/A

0X04

N/A

PIN

0X0A

0X100X0F

FUNCTIONPRIMARYSECONDARY

0X0B

0X09

LINE INPUTBUILT-IN MICROPHONEHEADSET MICROPHONE

0X0D(13,B,RIGHT)

TYPE DETECT/INTERRUPTN/A

N/ALINE IN

N/A

N/AMCP GPIO_5

0X09 (A)

GPIO 3

ENABLE/VOLUME

0X05

N/AN/A

0X06

0X03

N/A

0X06

0X02

N/A

0X080X060X06

0X020X030X04

N/A0X07

0X05

CONVERTER

0X0D (13,V22,B,LEFT)SPDIF OUTSPDIF IN

HEADPHONES

MIKEY

MIKEYN/AN/AMCP GPIO_38

0X0C (B)

68 OF 110

051-7863

A.0.0


11

5

6 1

7

4 9

8

2

10

3

U6806

21

C6802

21

C6801

2

1D6800

2

1 C6853

21

R6810

2

1R6808

2

1 C6852

2

1 C6854

21

R6805

21

R6804

21

R6803

21

R6802

2

1R6806

2

1R6807

21

L6840

2

1 C6899

2

1R6852

2

1R6809

2

1 C6857

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_IPHS_SWITCH_EN

HS_RSTAUD_I2C_INT_L

HS_INT_L

=I2C_AUDIO_SDA

HS_SDA

HS_SCL

=I2C_AUDIO_SCL

=PP5V_S0_AUDIO

AUD_GPIO_2


HS_MIC_HIMIN_NECK_WIDTH=0.1MM

AUD_GPIO_3

AUD_MIC_INP_L



AUD_MIC_INF

AUD_MIC_INN_L


=PP3V3_S0_AUDIO


HS_MIC_LO


HS_RX_BP


HS_SW_DET


PP3V3_S0_HS_FVOLTAGE=3.3V


HS_MIC_BIAS

AUDIO: MikeySYNC_DATE=09/02/2009SYNC_MASTER=K22

0.01UF10%

402X7R25V

MF-LF

1K

402

5%1/16W

5%

402

1/16W

2.2K

MF-LF

10%1UF

X5R10V

402-1

CD3275DRC

CRITICAL

0.1UF

402

16V10%

X5R

0.1UF

402

16VX5R

10%

NOSTUFF

SOD-323-HF1N4148WS-X-G

62 64 65

62 64 62 64

62 64 65

0.0082UF10%

X7R25V

402

1/16WMF-LF

5%

402

2.2K

5%

402MF-LF1/16W

100K

10UF6.3V

603

20%

CRITICAL

X5R

6 62 64 65 66 67

6 62

62

62

66

66

CRITICAL

TANT

20%6.3V

603-HF

4.7UF

19

21

52

52

1/16W

402MF-LF

0

5%

MF-LF402

1/16W5%

0

5%

0

1/16W

402MF-LF

1/16W

0

5%

MF-LF402

NOSTUFF

402

5%

MF-LF1/16W

47K

100K5%

MF-LF402

1/16W

0402

FERR-1000-OHM

62 63 64 65 67 68

62 63 64 65 67 68

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36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

12V_S0 SUPPLIED BY AC/DC, GATED BY PM_SLP_S3_L

5V_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT

3V3_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT; SLOWER THAN 5V_S0

1V8_S0 LDO SOURCED FROM 5V_S0, ENABLED BY 5V_S0 WITH RC DELAY

1V5_S0 FET SOURCED FROM 1V5_S3, GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

MCP_VCORE REGULATOR INTERNAL LOGIC POWERED FROM 5V_S3, SOURCED FROM 12V_S5,

1V05_S0 REGULATOR SHARES INTERNAL LOGIC POWER WITH 3V3_S5 REG, SOURCED FROM 12V_S0ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

CPU_VCORE

VTT_S0_DDR_LDO

1V05_S0

MCP_VCORE

1V5_S0

1V8_S0

MCP: PM_SLP_RMGT_L

1V05_RMGT FET SOURCED FROM 1V05_S5, ENABLED BY PM_SLP_RMGT_L

PM_SLP_RMGT_L FOLLOWS PM_SLP_S4_L TIMING CLOSELY

3V3_RMGT FET SOURCED FROM 3V3_S5, ENABLED BY PM_SLP_RMGT_L

12V_S5

3V3_RMGT

1V05_RMGT

RMGT POWER RAIL SEQUENCING

3V3_S5

1V05_S5

S5 POWER RAIL SEQUENCING

3V3_S5 SWITCHER LOGIC POWERED BY INTERAL LDO, SOURCED FROM 12V_S5

12V_S5 SUPPLIED BY AC/DC MAX RAMP TIME < 50MS MAX RAMP RATE 10V/MS

1V05_S5 SWITCHER SOURCED FROM 3V3_S5 AND ENABLED FROM 3V3_S5_PGOOD

OUTPUT SOURCED FROM 12V_S5 AND ENABLED BY PM_SLP_S4_L + LDO OUTPUT GOOD

5V_S3 SWITCHER LOGIC POWERED BY INTERNAL LDO (EN BY SLP_S4_L)

5V3_S3

3V3_S3

3V3_S3 FET GATED BY PM_SLP_S4_L

1V5_S3 SWITCHER LOGIC POWERED BY 5V_S3 SO ENABLED BY PGOOD_5V_S3

MCP: PM_SLP_S4_L


SB: PM_SLP_S3_L

COUNT


SOURCED BY 12V_S5; MUST RAMP IN < 2MS

NOTE: NO SEQUENCING REQUIREMENTS FOR THESE 3 RAILS

Soft-Off (S5/M-Off)

Sleep (S3/M-Off)

Soft-Off (S5/M1)

Sleep (S3/M1)

Run (S0/M0)

State

Battery Off (G3Hot)

On

N/A

On

Off

Off

N/A

Manageability

1

1

1

1

0

1

SMC_PM_G2_ENABLE

1

0

1

0

0

1

PM_S4_STATE_L

0

0

0

1

PM_SLP_S3_L

0

0

0

0

1

PM_SLP_S4_L

1

1

1

PM_SLP_M_L

0

0

1

1

1

0

SB: PM_SLP_S4_L

12V_S0

5V_S0

STARTUP (BOOT OR WAKE) TIMINGBOOT UP

SMC: IMVP_VR_ON

SMC STARTS

SHUT DOWN (SHUTDOWN OR SLEEP) TIMING

POWER RAILS SHUT DOWNCPU VTT_PWRGD LOW

POWER RAILS ON DURING THIS TIME

SLEEP OR SHUTDOWNSUSPEND SOONSB SAYS

SB: PM_SLP_S3_L

SB: PM_SUS_STAT#

VREGS: ALL_SYS_PWR_GD

OS COMMANDSVREG IN RESPONSE TOSMC SAYS SHUTDOWN CPU

SB PWROK DISABLE

CLK GEN DISABLED

CPU_PWRGD DISABLEDCPU VCORE OFF

IMVP6: VR_PWRGOOD_DELAY

SMC: IMVP_VR_ON

SB: PM_SLP_S3_L

3V3_S0

SB: PM_SLP_S4_L

VREGS: ALL_SYS_PWRGD

IMVP6 ON

99 MS

IMVP: VR_PWRGOOD_DELAY

AND GATE: MCP_PS_PGOOD

ALL_SYS_PWRGD * VR_PWRGOOD_DELAY

AND GATE: MCP_PS_PGOOD

MCP: CPUPWRGD

1V5_S3

69 OF 110

051-7863

A.0.0


SYNC_MASTER=K22

POWER SEQUENCING BLOCK DIAGRAMSYNC_DATE=09/02/2009

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IN

OUT

OUT

OUT

OUT

Y

B

A

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

Y

B

A

IN

OUT

IN

OUT

OUT

OUT

GND

V+

OUT

IN

IN

IN

OUTIN

GND

V+

IN OUT

IN

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

USING COMPARTOR INSTEAD OF REGULATOR

NO INTERNAL POWER TO PULL PGOOD

(PM_SLP_S3_L_BUF)

12V_S0 NEED TO BE ON BEFORE MCP REG AND 1.05_S0 REG EN

Enable FET

DELAY OF ~15MS FROM PM_SLP_S3_L



(PM_S4_STATE_L)

FROM COMPARATOR

FROM COMPARATOR

Enable regulator

PGOOD Comparators

(9.91V/9.58V; 330MV HYSTERESIS)

IRF7410

IRF7413

3.7A

PLACE RESISTORS CLOSE TO U7020

18mOHM

35mOHM

5.8A

9.6A

I

1V05V_S0 DERIVES FROM 3.3V_S5

PM_MXM_PGOOD IS PULLED UP TO IT

WHICH GOES INTO PGOOD_SB OF MCPFROM THIS SMC GENERATES PM_RSMRST_L

DELAY IS ABOUT 200MS

To SMC (2)

Rds(on)

7mOHM

25V

20V

PM_SLP_S4_L

1

1

PM_SLP_S3_L

0

1

0

0 0

0

8V

8V

Vgs +/-

12V

20V

70mOHM

115mOHM

65mOHM

1.6A

13A

8.8A

IRF7406

IRF6402

SI2302

FDS4435

Battery Off (G3Hot)

Sleep (S3)

Soft-Off (S5)

State

Run (S0)

1

1

1

0

SMC_PM_G2_ENABLE (PORTABLES)

From SMC (6)

1.5V_S3 NEED TO BE ON BEFORE S0 FET ON

Enable regulator

AND GATE BY THE FACT THATALL_SYS_PWRGD IS ALSO AN INPUT TO THIS

S0 RAILS PGOOD

Enable FET

PLACE SHORTS CLOSE TO PLANE CUTS

NOT COME UP, PPDDR REGULATOR HAS

LOW

HYSTERESIS NUMBERS CALCULATED BASED ON OUPTPUT PULL UP OF 3.3V

PGOOD OUTPUT BECAUSE IF 5V_S3 DOES



(PULLUPS ARE NEAR LOADS)

PM_MXM_PGOOD IS OPEN DRAIN SIGNAL, IT’S PULLED UP TO ALL_SYS_PWRGD

MXM CARD INPUT POWER ARE 12V_S0, 3V3_S0, 5V_S0

MXM POWER SEQUENCE

ALL_SYS_PWRGD ENABLES MXM REGULATORS

Enable regulator

USB Port Switch

Power Control Signals3.3V,5V S3 enable

Enable FET

To SMC

FROM MCP (6)

(PM_SLP_S3_L)

ENABLE REGULATOR

Enable FET

70 OF 110

051-7863

A.0.0


2

1 C7083

21

R7083

21

R7085

21

R7054

21

R7053

21

R7052

21

R7051

21

R7050

8

7

5

6

4

U70302

1R70222

1 C7025

2

1R7020

2

1R7006

8

1

7

3

5

2

6

4

U7010

21

R7099

21

R7098

2

1R7007

21

XW700121

R7001

21

XW7000

2 1

XW7002

2

1R7040

2

1R7033

2

1 C7031

2

1R7031

21

R7002

21

R7000

2

1R7014

2

1R7019

2

1R7021

2

1R7013

2

1R70182

1 C7010

2

1R7008

4

5

3

1

2

U7059

2 1

C7058

2

1 C7080

2

1 C7081

2

1 C7082

2

1

R7080 2

1

R7081 2

1

R7082

2

1R70304

5

3

1

2

U7020

2

1 C7020

2

1R7072

5

4

1

2

3

U7056

21

C7056

=P5VS0_ENMAKE_BASE=TRUE

P5VS0_EN

=P3V3S0_EN

PM_SLPS3_BUF2_L

PGOOD_12V_S0 S0_RDYMAKE_BASE=TRUE

5VREG_EN

PGOOD_5V_S3 PM_EN_USB_PWR

=DDRREG_ENPGOOD_5V_S3MAKE_BASE=TRUE

=PP5V_S3_PWRCTL

=PM_MXM_PGOOD_PULLUP

PM_MXM_ENMAKE_BASE=TRUE

ALL_SYS_PWRGD_R

=PP1V8_S0_PGCMP 1V8S0_COMP_REF

PGOOD_1V8_S0

12VS5_1V60_REF

12VS0_PG_CMP

1V8S0_PG_CMP

1V5S3_COMP_REF1V5S3_PG_CMP

12VS0_COMP_REF

PGOOD_5V_S0

=PP3V3_S0_PWRCTL

=PP3V3_S5_PWRCTL

PP12V_S0

=PP3V3_S5_PWRCTL

PGOOD_1V8_S0

PGOOD_1V5_S0

=PP3V3_S5_PWRCTL

S0_PWR_REG_PGOODMAKE_BASE=TRUE=PPDDR_S3_PGCMP

PM_MXM_PGOOD

PM_PGOOD_PVCORE_CPU

ALL_SYS_PWRGD_SMC

ALL_SYS_PWRGD

PGOOD_1V5_S3

=MCPDDR_EN

MCP_PS_PWRGD

=PP3V3_S5_PWRCTL

PGOOD_1V1_S5 RSMRST_PWRGD

PGOOD_1V05_S0

ALL_SYS_PWRGD_R

=MCPCORES0_EN

12VS5_1V27_REF

S0_PWR_CMP_PGOODMAKE_BASE=TRUE

PGOOD_MCPCORE_S0

PGOOD_12V_S0

=PP12V_S5_PWRCTL

12VS5_9V00_REF

PGOOD_1V5_S3

ENET_ENPM_SLP_RMGT_L

PM_SLP_S4_SMC_L

P3V3S3_EN

PM_SLP_S4_L

MAKE_BASE=TRUEMCPDDR_EN

=PP3V3_S5_PWRCTL

MCPCORES0_ENMAKE_BASE=TRUE

MAKE_BASE=TRUE

CPUVTTS0_EN =PVTT_S0_EN

MAKE_BASE=TRUEP3V3S0_EN

PM_SLP_S3_L_AND_S0_RDY

=PP12V_S0_VRD

PGOOD and Power SequencingSYNC_DATE=09/02/2009SYNC_MASTER=K22

402

0.47UF

6.3V10%

CERM-X5R

2.2K

1/16WMF-LF

5%

402


33

49 50


33

73

78


33


33

21 102

38

NOSTUFF

33


210

LM393

CRITICAL

SOI-HF

100K5%

MF-LF1/16W

402

MXM

70 46

70

78

78

603CERM16V20%0.1UF

MF-LF1/16W1%64.9K

402

402MF-LF1/16W1%49.9K

70

LM393

CRITICAL

SOI-HF

6 70

MF-LF1/16W

402

33

5%

5%

33

MF-LF1/16W

402

70

1%

MF-LF402

49.9K

1/16W

OMITSM

1%

MF-LF402

1/16W

1.21K

85

85

OMITSM

SMOMIT

5%

MF-LF1/16W

402

10K

402

10K

1/16W1%

MF-LF

10%16VX5R402

0.1UF

5%

MF-LF

402

1K

1/16W

MF-LF

2.0K

1/16W

IG

1%

402

4.99K

1/16W

402

1%

MF-LF

MF-LF402

1/16W1%

100K 10K1%

402

1/16WMF-LF

402MF-LF1/16W1%10K

1%33.2K

1/16W

402MF-LF

402MF-LF

84.5K1%

1/16W

0.1UF20%16VCERM603

49.9K

MF-LF402

1/16W1%

70

85

SOT665TC7SZ08AFEAPE

6 9 49 50

402

20%

0.1UF

10VCERM

0.47UF

402

CERM-X5R

6.3V10% 10%

402

CERM-X5R

6.3V

0.47UF

CERM-X5R

10%6.3V

402

0.47UF

402

1/16W5%

MF-LF39K

402MF-LF4

3K

1/16W5%

MF-LF1/16W

402

5%

10K

74

76

78

78

78

76

74

1/16W

MF-LF

10K5%

402

SOT665

TC7SZ08AFEAPE

CERM402

10V

0.1UF20%

49

1/16W

402

5%

100K

MF-LF

75

49

21

11 71

SOT23-5-HFMC74VHC1G08

402

10VCERM

20%

0.1uF

70

70

6

6 70

6

55

6

6 70

6

6 70

6 70

6

70

6 70

79

6 38 78

6 70

6 71

www.bblianmeng.com

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IN

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

ISEN4-

EN_VTT

THRM_PAD

VR_HOT

VR_FAN

ISEN4+

ISEN3-

ISEN3+

ISEN2-

ISEN2+

ISEN1+

PWM2

FB

PWM1

TCOMP

PSI*

IMON

OFS

VCC

VID0

VR_RDY

VID7

VID5

VID4

VID3

VID2

VID6

VID1

SS

FSPWM3

PWM4TM

REF

DAC

EN_PWR

RGND

VSEN

VDIFF

ISEN1-

COMP SYM_VER_2

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

INPUT SENSE & FILTER

1.25 mOhm loadline

and LOW when VTM/VCC > 33%.

LAYOUT: PLACE RT7101 NEAR HOT SPOT.

70A AVE

75A PEAK

VR_HOT goes HIGH when VTM/VCC < 28%

K22/K23 65W

CPU CORE

71 OF 110

051-7863

A.0.0


2

1

RT7101

5678

4321

RP71915678

4321

RP7190

21

XW7130

21

XW7120

4321

R7169

21

L7160

2

1 C7160

2

1 C7161

21

R7133

21

R7129

21

R7128

21

R7127

21

R7135

21

R7134

2

1R7146

21

R7145

2 1

R7143

2 1

R7139

2 1

R7167

2 1

R7166

2 1

R71652

1 C7152

2

1 C7151

2

1 C7150

2

1R7162

2

1R7161

2

1R7160

2

1R7116

2

1 C7130

2

1R7164

2

1R7130

21

R7103

17

36

38

37

40

1

2

3

4

5

6

7

15

19

39

41

18

35

16

12

25

31

20

26

8

9

23

24

29

30

22

21

28

27

10

34

14

33

32

11

13

U7100

2

1R7104

21

R7140

2

1 C7116

2

1 C7117

2 1

R7121

2

1 C71182 1

R7122

2

1 C7119

2

1 C7120

2 1

R7123

2

1 C71212 1

R7124

2

1 C7113

2

1 C7114

2 1

R7119

2

1 C71152 1

R7120

2

1R7106

2

1R7100

2

1R7105

2

1R7107

2

1R7108

2

1R710921

C7109

21

R7110

2

1 C7101

2

1 C7102

2

1 C7103

21

R7111

2

1 C7110

2

1R7112

2

1R7114

2

1R7115

2

1R7117

2

1 C7112

21

R7131

2

1C713121

XW7101

2

1R7132

21

R710121

C7105

2

1 C7107

21

C7104

21

R7163

21

C7106

21

R7102

2 1

R7118


MAX_NECK_LENGTH=3MM

CPU_INPUT_ISENSE_P

PM_PGOOD_PVCORE_CPU

VR_CPU_EN_PWR

VR_CPU_TM

VR_CPU_VSNS_PL

VR_CPU_VSNS_MI

VR_CPU_ISNS2_R_N

VR_CPU_ISNS3_R_P

CPU_INPUT_ISENSE_N

PP12V_S0_CPU_FLTRD

VOLTAGE=12VNET_PHYSICAL_TYPE=POWER

CPU_PSI_L

=PPVTT_S0_CPU

CPU_VCC_PKG_SENSE_P

CPU_VCC_PKG_SENSE_N VR_CPU_VSNS_R_N

VR_CPU_TCOMP

VR_CPU_OFS

VR_CPU_PWM3_R

VR_CPU_ISNS3_RR_P

VR_CPU_REF

VOLTAGE=0VVR_CPU_VSNS_GND

NET_PHYSICAL_TYPE=POWER

PP5V_S0_CPU_VCORE_VCC


VR_CPU_VSNS_VCCVOLTAGE=1.1V VR_CPU_COMP_R

VR_CPU_VDIFF_R2

VR_CPU_EN_VTT

VR_CPU_IOUT_PD

VR_CPU_ISNS1_RR_P

VR_CPU_ISNS2_P

VR_CPU_ISNS1_N

PP12V_S0_CPU_FLTRD

=PP5V_S0_VRD

=PP3V3_S0_VRD

=PP12V_S0_VRD

VR_CPU_VRDHOT

VR_CPU_FAN

VR_CPU_ISNS2_N

VR_CPU_COMP

VR_CPU_DAC

VR_CPU_ISNS1_R_NVR_CPU_ISNS1_R_P

VR_CPU_ISNS3_PVR_CPU_VDIFF

VR_CPU_PWM2_R

VR_CPU_ISNS2_R_P

VR_CPU_PWM3

VR_CPU_ISNS3_R_N

PM_EN_PVCORE_CPU

VR_CPU_COMP_RC

VR_CPU_PWM2

VR_CPU_ISNS3_N


NET_PHYSICAL_TYPE=POWERVOLTAGE=12V

PP12V_S0_CPU_FLTRD_R

VR_CPU_ISNS2_RR_P

VR_CPU_ISNS1_P

VR_CPU_PWM1PPVCORE_S0_CPU

VR_CPU_VSNS_R_P

VR_CPU_SS

VR_CPU_FB

VR_CPU_PWM4

VR_CPU_IMON

VR_CPU_FB_R

VR_CPU_FS


MIN_LINE_WIDTH=0.6MMVOLTAGE=5V

MIN_NECK_WIDTH=0.3MMMAX_NECK_LENGTH=3MM

VR_CPU_VDIFF_R1

CPU_VID<7..0>


VREG: PPVCORE_S0_CPUSYNC_MASTER=K22

1/16W1%

402MF-LF

10.7K

CERM402

560PF

50V10%

402

10VX5R

1UF10%

47PF

5%50VCERM402

402

1/16W5%

0

MF-LF

CERM402

470PF

10%50V

1%1/16W

402MF-LF

1.5K AGND_CPU

805MF-LF

2.2

5%1/8W

0603

6.8K

5%1/16W

680

SM-LF1/16W5%680

SM-LF

SM

SM

CRITICAL

1206MF

1/4W

0.0021%

TH-VERT-HF

1UH-20A-4.5MOHM

CRITICAL

20%16VELEC8X12-TH-HF

270UF

CRITICAL

270UF20%16V

8X12-TH-HFELEC

CRITICAL

12 100

5%

402

1K

1/16WMF-LF

MF-LF

5%

402

1/16W

0

MF-LF1/16W

402

0

5%

1/16W

402

1K

MF-LF

5%

402

1/16WMF-LF

5%

10

10

1/16W5%

MF-LF402

12 100

5%

402MF-LF1/16W

1M

NOSTUFF

47.5

402

1%

MF-LF1/16W

0

5%1/16W

402MF-LF

1/16WMF-LF

0

402

5%

402

1/16W

0

5%

MF-LF

MF-LF

5%

0

402

1/16W

402

5%

0

MF-LF1/16W

15PF

402

1%

NOSTUFF

50VC0G

C0G402

15PF1%

NOSTUFF

50V

402

50VC0G

15PF

NOSTUFF

1%

MF-LF402

5%1/16W

01/16W

NOSTUFF

0

402MF-LF

5%

NOSTUFF

5%

MF-LF402

1/16W

0

1/16W

402MF-LF

5%0

402

20%CERM10V0.1UF

402

01/16WMF-LF

5%

NOSTUFFNOSTUFF

MF-LF1/16W

5%0

402

402

1%1/16WMF-LF

150

QFN

ISL6334

CRITICAL

12 100

1/16WMF-LF

05%

402

5%1/16WMF-LF402

0

11

CERM402-1

68PF5%50V

AGND_CPU

402X5R

0.1UF16V10%

MF-LF

1%1/16W

383

402

SIGNAL_MODEL=EMPTY

20%0.1UF10V

402CERM

1/16W1%

MF-LF402

4.75K72108

72

72108

5%50VCERM

68PF

402-1

AGND_CPU

0.1UF

402

10%16VX5R

1/16W

383

MF-LF 402

1%

SIGNAL_MODEL=EMPTY

0.1UF10VCERM402

20%MF-LF402

1%1/16W

4.75K72108

72

72108

AGND_CPU

CERM402-1

5%68PF50V

10%

402

16V0.1UF

X5R

402

1%1/16W

MF-LF

383

0.1UF

SIGNAL_MODEL=EMPTY

20%10VCERM402

402

1%1/16WMF-LF

4.75K72108

72108

72

AGND_CPU

1%100K

MF-LF1/16W

402

MF-LF402

1/16W

1.02K1%

20.0K1/16W

402

1%

MF-LF

1/16W1%

MF-LF402

22.1K 5%1/16W

402MF-LF

75K

402

1%

MF-LF1/16W

100K

CERM

10%

402

0.0022UF

50V1%

1/16W

1K

402MF-LF

0.0022UF

NOSTUFF

50V

402

10%CERM

SIGNAL_MODEL=EMPTY

AGND_CPU

0.0022UF

402

10%CERM50V 10%

CERM402

50V0.0022UF

53 108 VR_CPU_IOUT

11 70

49

5%

MF-LF402

1/16W

10K

0.01UF10%16VCERM402

402MF-LF

5%1/16W

2.0K

AGND_CPU

1%

402MF-LF

49.9K1/16W

49.9K

MF-LF

1%1/16W

402

MF-LF402

1%1/16W

20.0K

33NF

CERM25V10%

402

0

1

2

3

4

5

6

7

MF-LF

10K

5%1/16W

402

CERM402

50V10%

0.001UF

SM

MF-LF

1K1/16W

5%

402

53

108

108

53

53 71 72

6 10 50 55

71

53 71 72

6

6

6 70

108

108

108

108

71

6 72

71

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OUT

OUT

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GNDTHRML

PHASE

LVCCUVCC

PAD

IN

OUT

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GNDTHRML

PHASE

LVCCUVCC

PAD

IN

IN

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GNDTHRML

PHASE

LVCCUVCC

PAD

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM



PHASE 2

PHASE 3

PHASE 1

THESE TWO CAPS ARE FOR EMC



OUTPUT CAPS

72 OF 110

051-7863

A.0.0


321

4

5

Q7243

321

4

5

Q7223

321

4

5

Q7203

321

4

5

Q7241

321

4

5

Q7221

321

4

5

Q7201

2

1 C7292

2

1 C7293

2

1 C7294

2

1 C7296

2

1 C7295

2

1 C7297

2

1 C7298

2

1 C7299

2

1 C7280

2

1 C7281

2

1 C7282

2

1 C7283

2

1 C7284

2

1 C7285

2

1 C7286

2

1 C7287

2

1 C7291

2

1 C7290

2

1 C7289

2

1 C7288

2

1 C7249

2

1 C7229

2

1 C7205

2

1 C7215

2

1 C7211

2

1 C7210

2

1 C7207

2

1C7260

2

1C7261

2

1C7262

2

1C7263

2

1C7264

2

1C7265

2

1R7247

9 8

1

11

4

10

7

6

5

3 2

U7241

2

1C7242

2

1 C7240

2

1R7242

2

1R7245

2

1R7241

2

1 C7241

2

1R7244

2

1 C7243

2

1 C7248

2

1R7246

2

1 C7245

5

4321

D7240

2

1 C7246

2

1 C7247

2

1

XW7241

2

1 C7250

21

L7241

2

1 C7251

2

1

XW7242

2

1R7227

9 8

1

11

4

10

7

6

5

3 2

U7221

2

1C7222

2

1 C7220

2

1R7222

2

1R7225

2

1R7221

2

1 C7221

2

1R7224

2

1 C7223

2

1 C7228

2

1R7226

2

1 C7225

5

4321

D7220

2

1 C7226

2

1 C7227

2

1

XW7221

2

1 C7230

21

L7221

2

1 C7231

2

1

XW7222

5

4321

D7200

2

1 C7200

2

1R7205

2

1R7207

2

1R7202

2

1R7201

2

1 C7201

2

1C7202

9 8

1

11

4

10

7

65

3 2

U72012

1R7204

2

1 C7203

2

1 C7208

2

1R72062

1

XW7201

21

L7201

2

1 C7206

2

1

XW7202

PPVCORE_S0_CPU

DIDT=TRUE

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_LGATE

VR_CPU_SW1NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

VR_CPU_DRV2_VCCNET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV2_UVCC

VR_CPU_PWM2

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_PVCC

PP12V_S0_CPU_FLTRD

PP12V_S0_CPU_FLTRD

NET_PHYSICAL_TYPE=POWERVR_CPU_BOOT2_RC

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV2_PVCC

VR_CPU_DRV1_GDSEL

VR_CPU_ISNS3_P

PPVCORE_S0_CPU

VR_CPU_PWM3

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_VCC

VR_CPU_ISNS1_N

VR_CPU_ISNS3_N


VR_CPU_ISNS1_P

VR_CPU_DRV2_GDSEL

VR_CPU_DRV3_GDSEL

VR_CPU_ISNS2_P

VR_CPU_PH1_SNUB

DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY


DIDT=TRUE

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV2_BOOT

VR_CPU_PH3_SNUB

DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_ISNS2_N

VR_CPU_PH2_SNUBNET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE


PPVCORE_S0_CPU

PPVCORE_S0_CPU

DIDT=TRUE


VR_CPU_DRV1_PVCCNET_PHYSICAL_TYPE=POWER

PP12V_S0_CPU_FLTRD

DIDT=TRUE



VR_CPU_DRV1_VCCNET_PHYSICAL_TYPE=POWER

VR_CPU_PWM1

VR_CPU_DRV1_UGATE DIDT=TRUE



DIDT=TRUEVR_CPU_DRV2_UGATE

PP12V_S0_CPU_FLTRD

DIDT=TRUE

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_UGATE

PP12V_S0_CPU_FLTRD

VR_CPU_DRV1_LGATENET_PHYSICAL_TYPE=POWER

DIDT=TRUE


DIDT=TRUEVR_CPU_DRV2_LGATENET_PHYSICAL_TYPE=POWER

DIDT=TRUEVR_CPU_SW2

DIDT=TRUE

NET_PHYSICAL_TYPE=POWERVR_CPU_SW3

DIDT=TRUEPP12V_S0_CPU_FLTRD

IC,ISL6612,SYNC,FETDRV,DFN10,LF CRITICALU7221,U72412353S1733

VREG: PPVCORE_S0_CPUSYNC_MASTER=K22 SYNC_DATE=09/02/2009

1UF10%16VX5R603

1/10W5%

603

0

MF-LF

5%1/10WMF-LF603

NOSTUFF

0

MF-LF603

1/10W5%10

1/10W5%10

MF-LF603

NOSTUFF

16VX5R

1UF10%

603

108 71

16V1UF

603X5R10%

DFNISL6622

CRITICAL

71

1/10W5%

MF-LF

0

603 603X7R16V0.22UF10%

WPAKRJK0348DPA

CRITICAL

CRITICAL

RJK0348DPAWPAK

CRITICAL

RJK0348DPAWPAK

RJK0353DPAWPAK

CRITICAL

CRITICAL

WPAKRJK0353DPA

CRITICAL

WPAKRJK0353DPA

critical

805-3

20%22UF

CERM-X5R6.3V

22UF

805-3

critical

20%CERM-X5R6.3V

805-3

critical

22UF20%6.3VCERM-X5R

805-3

critical

20%22UF6.3VCERM-X5R

critical

22UF

805-3

20%6.3VCERM-X5R

805-3

critical

20%CERM-X5R6.3V22UF

805-3

critical

20%22UF

CERM-X5R6.3V

805-3

critical

20%22UF

CERM-X5R6.3V

805-3

critical

22UF20%6.3VCERM-X5R

805-3

critical

22UF20%6.3VCERM-X5R

805-3

critical

22UF20%6.3VCERM-X5R

805-3

critical

22UF20%6.3VCERM-X5R

805-3

critical

22UF20%CERM-X5R6.3V

805-3

critical

22UF20%CERM-X5R6.3V

805-3

critical

22UF20%CERM-X5R6.3V

805-3

critical

22UF20%CERM-X5R6.3V

805-3

critical

22UF20%6.3VCERM-X5R

critical

805-3

6.3VCERM-X5R

22UF20%

805-3

critical

22UF20%6.3VCERM-X5R

805-3

critical

22UF20%CERM-X5R6.3V

CRITICAL

0805

10%10UF16VX5R-CERM

X5R-CERM16V10UF10%

0805

CRITICAL

270UF

CRITICAL

16VELEC8X12-TH-HF

20%

0805

10%10UF16VX5R-CERM

CRITICAL

CERM16V0.01UF

402

20%0.01UF16VCERM402

20%X5R16V1UF

603

10%

CASE-D2E-SM

2.5V20%

330UF

POLY-TANT

critical

CASE-D2E-SM

2.5V20%

330UF

critical

POLY-TANTCASE-D2E-SM

2.5V20%

critical

330UF


critical

2.5V20%

330UF


2.5V20%

330UF

POLY-TANT

critical

CASE-D2E-SM

critical

2.5VPOLY-TANT

20%330UF

71

5%1/10WMF-LF603

NOSTUFF

0

OMIT

ISL6622DFN

CRITICAL

1UF

603X5R16V10%

10%16V1UF

X5R603

NOSTUFF

1/10WMF-LF

5%10

603603

MF-LF

01/10W

5%

NOSTUFF

603

1/10WMF-LF

5%10

50V10%CERM402

0.001UF

603X5R16V1UF10%

05%

1/10WMF-LF

60316V10%X7R603

0.22UF

50VCERM10%

402

0.001UF

805

1/8W5%

MF-LF

2.2

5%

805MF-LF1/8W

2.2

16VELEC8X12-TH-HF

270UF20%

CRITICAL

TLM833

CTLSH3-30M833

16V10UF10%

CRITICAL

0805X5R-CERM X5R

16V1UF10%

603

SM

SIGNAL_MODEL=EMPTY

16V0.01UF

CERM402

20%

MMD10EE-SM

0.36UH

CRITICAL

16V0.01UF

CERM402

20%

SIGNAL_MODEL=EMPTY

SM

108 71

SM

SIGNAL_MODEL=EMPTY

108 71

71

1/10W5%

MF-LF603

0

NOSTUFFCRITICAL

ISL6622DFN

OMIT

603X5R

1UF16V10%

10%16V1UF

X5R603

NOSTUFF

10

603MF-LF

5%1/10W

MMD10EE-SM

0.36UH

CRITICAL

603MF-LF

01/10W

5%

NOSTUFF

603MF-LF

105%1/10W

603X5R16V10%1UF

603

1/10W

05%

MF-LF603X7R

0.22UF16V10%

402

50V10%CERM

0.001UF

0805

10%

CRITICAL

X5R-CERM16V10UF

5%

805MF-LF1/8W

2.2

CRITICAL

16VELEC8X12-TH-HF

270UF20%

CTLSH3-30M833

TLM833

0805

10%

CRITICAL

10UF

X5R-CERM16V

603

10%1UF

X5R16V

SM

SIGNAL_MODEL=EMPTY

20%0.01UF16V

402CERM

MMD10EE-SM

0.36UH

CRITICAL

20%

402CERM

0.01UF16V

SM

SIGNAL_MODEL=EMPTY

108 71

108 71

SM

SIGNAL_MODEL=EMPTY

TLM833

CTLSH3-30M833

108 71

72 71 6

108

72 71 53

72 71 53

72 71 6

72 71 6

72 71 6

72 71 53

72 71 53

72 71 53

108

108

72 71 53

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G

D

S

G

D

S

IN

INTVCC

MODE/PLLIN

TG

VIN

SW

BOOST

FB

ITH

TK/SS

RUN

FREQ/PLLFLTR

ILIM

GND

SENSE-

SENSE+

BG

THRMPAD

D

SG




36

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8 7 5 4 2 1

AVE=3.19A

PEAK=3.31A

K22/K23

EMC: C7304,C7356

OSCILLATED AT APPR. 330KHZ

SOFT START TIME 8MS

BURST MODE

POWER BUDGET

PLACE AT L7320.1

PLACE XW CLOSETO L7320

(5VS3_VOUT)

PM_SLP3_BUF1_L

RB

RA

5V_S3

LTCMODESTATE

1

0

0

1

1

0

CONT MODE

S3

S0

(5VS3_FB)

Mode

TO L7320PLACE XW CLOSE

5VREG_PS_L

PLACE AT Q7330EMC: C7353,C7354

5V S3 REGULATOR

73 OF 110

051-7863

A.0.0


2

1

3

Q7303

2

1C7331

2

1 C7307

2

1R7302

2

1 C7306

2

1C7303

2

1C7316

2

1C7334

2

1 C7325

2

1C7317

2 1

R7304

2

1R7307

2

1R7336

2

1 C7363

2

1R7362

2

1 C73222

1C7315

21

D7301

2

1C7345

11

2

17

13

14

6

5

1

15

3

10

7

8

16

4

12

9

U7300

2

1

XW7300

2

1R7312

2 1

R7310

2

3

1Q7360

2

1R7301

2

1R7311

2 1

R73242 1

C7326

321

4

5

Q7335 5

4

3

2

1

D7300

321

4

5

Q7330

2 1

L7320

2

1C7309

2

1R7306

2

1R7305

2

1 C7305

2

1

XW7301

2

1 C7301

2

1C7356

2

1 C7342

2

1C7354

2

1C7300

2

1C7335

2

1C7353

2

1C7332

2

1C7302

2

1C7304

MIN_NECK_WIDTH=0.4MMDIDT=TRUEMIN_LINE_WIDTH=0.4MM

5V_SNUBBER

DIDT=TRUE

5VS3_BG


PP5V_S3_REG

5VS3_SENSEP

LTCINTVCC

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM

5V_BOOT1

=PPVIN_S5_P5VS3

DIDT=TRUE=PPVIN_S5_P5VS3

5VS3_SENSEN_R

5VS3_FB

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM5VS3_TG

DIDT=TRUE

5VS3_SENSEN

5VS3_TK_SS

5VS3_ITH


5V_BOOT1_RMIN_LINE_WIDTH=0.25MM

PM_SLPS3_BUF1_L PM_SLPS3_BUF1_R_L

5VS3_ITH_R

LTCMODE

5VS3_SENSE

5VREG_PS_L

LTCMODE

LTCINTVCC

5VREG_EN

5VS3_FREQ

DIDT=TRUE

5VS3_SWMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

SWITCHNODE


5V_S3 REGULATOR

SM-HFCRITICAL

SI2301BDS

X5R16V10%

0.1UF

402

5%

402CERM50V

100PF

1%1/16W

402MF-LF

24.9K

0.001UF

CERM402

50V10%

X5R25V

402

10%0.1UF

0.01UF

CERM

10%16V

402

0.001UF

CERM50V10%

402

0805X5R-CERM

10%4.7UF

35V

50V

402

20PF

CERM

5%

0.22UF10%10VCERM402

MF-LF1/16W5%

402

0

402MF-LF

1.24K1/16W

1%

1.5K

MF-LF

1%1/16W

402

50VC0G-CERM

1000PF5%

603

1

MF-LF603

1/10W5%

6.3V20%

CERM

10UF

805-1

402CERM

100PF5%

50V

B0530WXGSOD-123-HF

10%10UF

16VX5R-CERM

0805

X5R16V

603

10%2.2UF

QFN

CRITICAL

LTC3851EUD

SM

OMIT

402MF-LF

5%1/16W

100K

5%

10K

MF-LF402

1/16WSOT23MMBT3904G

0805

16V

10UF10%

X5R-CERM

402

25V

0.1UF10%

X5R

5%

402MF-LF1/16W

100K

73

10UF

0805

10%16V

X5R-CERM

402MF-LF

5%1/16W

100K

330UF6.3V

POLY-TANT

20%

CRITICAL

CASE-D3L-SM

603

5%

MF-LF

1

1/10W

0.1UF

25V10%

402X5R

CRITICAL

MLP5X6-LFPAK-Q5ACSD58856Q5A

TLM833CTLSH3-30M833

CRITICAL

CRITICAL

CSD58856Q5AMLP5X6-LFPAK-Q5A

CRITICAL

2.2UH-10A-11.6M-OHM

SM

5%100PF

402CERM50V

8.06K1%

1/16WMF-LF

402

43.2K1%

MF-LF402

1/16W

6.3VPOLY-TANTCASE-D3L-SM

330UF

CRITICAL

20%

SMOMIT

10UF

805-1CERM

20%6.3V

X5R

0.1UF25V10%

402

CRITICAL

16V

8X12-TH-HF

20%

ELEC

270UF

0.1UF25VX5R

10%

402

6 110

73

6 73

6 73

9 94

73

73

108

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G

D

S

G

D

S

OUT

IN

IN

IN

IN

SOFT

RBIAS VIN

UGATE

VW

VSS

VSEN

VR_ON

VO

VID1

VID0

THRM_PAD

RTN

PVCC

PHASEPGOOD

PGND

FDE

FB

BOOT

VDD

VID2

VID3

IMON

AF_EN

VDIFF

COMP

LGATE

ICOMP

ISN

OCSET

ISP

NC




36

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PAGE TITLE

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Apple Inc.

PAGE


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C

345678

D

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8 7 5 4 2 1



TABLE_5_ITEM

PLACE AT L7460

EMC: C7467,C7457

1.1V DEFAULT, OTHER VALUES TBD

VID<2:0> Voltage

000 +1.100V

(MCPCORES0_ICOMP)

CONNECT SENSE LINES TO CLOSEST

F = 200-300 KHZ

(MCPCORES0_VO)

(=PPMCPCORE_S0_REG)

MCP CORE

MAX CURRENT: 20A

Vout = See below

EMC:

(MCPCORES0_ISN)

(MCPCORES0_LGATE)

OF MCPMCPCORE AND GND BALL

PLACE XW NEAR THE MCP,

(MCPCORES0_COMP)

(MCPCORES0_FB)

(MCPCORES0_VDIFF)

(MCPCORES0_RTN)

(MCPCORES0_ISP)

(MCPCORES0_VSEN)

(MCPCORES0_VW)

(MCPCORES0_UGATE)

PLACE AT Q7460

(MCPCORES0_PHASE)

74 OF 110

051-7863

A.0.0


2

1R7485

2

1R7484

4

15

8

29

12

14

27

26

25

24

7

16

18

33

2

9

1

22

1931

20

3

23

21

13

11

28

10

32

6

5

17

30

U7401

2

1R7483

2

1C7483

2

1C7484

2

1 C7467

21

XW7462

21

XW7463

21

R7479

21

R7477

21

R7478

21

C7480

21

C7481

21

C7482

2

1C7479

2

1R7471

2

1R7476

2

1R7472

2

1C7476

21

R7468

21

R7466

2

1 C7470

21

R7492

2

1R7463

21

R7490

21

R7491

2

1R7461

2

1C7461

21

XW7461

2

1R7475

2

1R7473

21

R7474

2

1 C7462

2

1R7469

321

4

5

Q7465

2

1 C7455

2

1 C7472

21

C7464

21

R7460

2

1 C7477

2

1 C7473

321

4

5

Q7460

2

1 C7478

2

1R7470

2

1R7464

21

R7465

2

1 C7463

2

1R7462

2

1

XW7460

2

1R7467

21

L7460

2

1C7471

2

1 C7460

2

1 C7474

2

1 C7475

2

1 C7457

2

1

XW7402

2

1C7465

2

1 C7469

2

1C7466

2

1 C7468

MCPCORES0_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MMSWITCH_NODE=TRUE

SWITCHNODE

5V_S3_MCPREG_VINVOLTAGE=5V0.6 mm0.2 MM

MCP_VID0_R

DIDT=TRUE=PPVIN_S0_MCPCORE

MCP_VID3

MCPCORES0_OCSET

MIN_LINE_WIDTH=0.6 mmVOLTAGE=0V


GND_MCPCORES0_AGND

=PP3V3_S3_MCPREG

MCPCORES0_RBIAS

MCPCORES0_ICOMP

MCPCORES0_VW

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM


DIDT=TRUEMCPCORES0_LGATE

MCPCORES0_ISP

MCPCORES0_VO

MCPCORES0_VDIFF

MCP_VID<1>

MCP_VID<0>

MCPCORES0_ISN

PPMCPCORE_S0_REG

MCPCORES0_RSEN_H

MCPCORES0_RSEN_L

PPMCPCORE_S0_REG

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

MCPCORES0_ISN_R

MCPCORES0_ISP_R

MCPCORES0_BOOT_R

0.2 MM0.25 MM

DIDT=TRUE

MCPCORES0_BOOT0.2 MM0.25 MM

MCPCORES0_IMON

MCP_VID1_R

MCPCORES0_FB

MCPCORES0_COMP

MCPCORES0_RTN

=MCPCORES0_EN

MCPCORES0_FDE

MCPCORES0_VSEN

MCPCORES0_SOFT

MCP_VID2_R

MCP_VID<2>

MCP_ISL6263D_OFFSET0

PGOOD_MCPCORE_S0

MIN_NECK_WIDTH=0.2 MMGATE_NODE=TRUE


DIDT=TRUE

MCPCORES0_UGATE


DIDT=TRUEMIN_NECK_WIDTH=0.4MM

MCPCORES0_SNUBBER

PPMCPCORE_S0_REG

=PP5V_S3_MCPREG

CRITICAL1 U7401353S2303 INTERSIL ISL6263D MCP_ISL6263D

353S2497 1 INTERSIL ISL9563A CRITICAL MCP_ISL9563AU7401


MCP CORE REGULATOR

805

10%

X5R25V

10UF

20.0K1%

MF-LF1/16W

402

MCP_ISL6263D

402

1/16WMF-LF

20.0K1%

MCP_ISL6263D

ISL9563A

CRITICAL

OMIT

QFN

1%

402

1/16WMF-LF

20.0K

10UF20%4V

X5R603

10UF

603X5R4V

20%

402

25V10%

X5R

0.1UF

OMIT

SM

OMIT

SM

10%0.1UF25VX5R402

21

21

21

1%1/16W

2.21K

MF-LF402

133K

402MF-LF1/16W1%

100

402MF-LF1/16W1%

402-1

5%

CERM50V

68PF

10%

560PF

50V

402CERM

560PF

10%50VCERM402

0.001UF50VX7R402

10%

SM

OMIT

MF-LF

100

402

1/16W1%

6.98K

MF-LF1/16W1%

402

1/16W

150K

MF-LF

1%

40216V10%

402X7R-CERM

0.1UF

20

1%

MF-LF402

1/16W

MF-LF1/16W1%

402

20

0.001UF50V

402X7R

10%

1/16W

402

5%

MF-LF

0

100

1/16W

402MF-LF

1%

MF-LF

0

402

1/16W

MCP_ISL9563A

5%

CASE-D2E-SM

20%330UF

POLY-TANT2.5V

CRITICAL

5%

0

MF-LF402

1/16W

70

70

5%

402

1/16WMF-LF

1K

10%

X5R

1UF

402

16V

OMIT

SM

59.0K1%

402

1/16WMF-LF

1%

402

10K

1/16WMF-LF

MF-LF

5%

603

1/10W

0

1UF10%

X5R16V

402

1%

MF-LF402

1/16W

10K

CRITICAL

MLP5X6-LFPAK-Q5CSD58857Q5

0.1UF10%25VX5R402

10%

402

25VX5R

0.1UF

50V10%

402

0.0027UF

CERM

16V603

0.22UF

X7R

10%

603MF-LF

5%

2.2

1/10W

402

0.1UF10%25VX5R

10%

402

10.0VCERM-X5R

0.12UF

CRITICAL


10%0.1UF25VX5R402

402

10K

1/16W1%

MF-LF

402

1%1/16WMF-LF

11.3K

10KOHM-5%

0603-LF

CRITICAL

20%10UF

X5R4V

603

0.0022UF50VCERM402

10%

1%

MF603

1/10W

0.499

SM

OMIT

1K1%

402

1/16WMF-LF

MMD12EZ-SM

CRITICAL

1.0UH-29A-2.5MOHM

CRITICAL

16V20%

ELEC

270UF

8X12-TH-HF 805

10%25VX5R

10UF

X5R25V

805

10%10UF

CASE-D2E-SM

330UF

2.5VPOLY-TANT

CRITICAL

20%

108

6

6

6 54 74

6 54 74

54 108

6 54 74

6

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MODE

VDDQSNSCOMP

NC0

NC1

VTTSNS

VTT

VTTREF

PGOOD

S3

S5

VTTGND THRM_PAD GND CS_GNDPGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILTV5IN

SYM (2 OF 2)

IN

IN

NCNC

G

D

S

G

D

S




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8 7 5 4 2 1

PEAK = 11.28AAVG = 6.72A

FEEDBACK THROUGH SHORT

14.75A MAX OUTPUT

<Rb>

<Ra>

EMC CAPS

f = 400 kHz

(Q7335 limit)

PLACE CLOSE TO L7530

VTTREFS3 VDDQ

1.5 V DDR SUPPLY

VTT Enable

S0

S5S3 LO HI

S5 VTTHI ON

ONOFF OFF

ONON

OFFOFF

LO

ON

PPDDR_S3_REG

VOUT = 1.5V

(DDRREG_DRVH)

VDDQ/VTTREF Enable

SHOULD NOT NEED TP

VOUT = 1.50V

(DDRREG_FB)

Vout = 0.75V * (1 + Ra / Rb)

LO

HISTATE

EMC CAPSPLACE CLOSE TO FET

Vout = VDDQSNS/2

Vout = VTTREF

(DDRREG_VDDQSNS)

(DDRREG_CSGND)

(DDRREG_LL)

(DDRREG_DRVL)

10mA max load

VDDQ PGOOD

75 OF 110

051-7863

A.0.0


2

1

XW7501

2

1 C7563

2

1R7562

2

1 C7512

2

1 C7513

2

1 C7511

2

1 C7510

321

4

5

Q7530

321

4

5

Q7535

21

R752521

L7530

2

1 C7545

2

1 C7540

2

1C7541

2

1

XW7500

2

1 C7555

2

1

XW7545

2

1C7531

2

1C7530

2

1R75102

1C7500

2

1C7550

21

XW7535

21

XW7560

2

1C7560

2

1 C7561

21

R7505

2

1C7505

2

51

24

23

8

9

22

15

14

25

11

10

13

18

12

7

4

20

3

19

21

17

16

6

U7500

2

1C7520

2

1 C7532

2

1R7521

2

1R7520

21

C7525

VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmGND_DDRREG_SGND

=DDRREG_EN

PPVTT_S0_DDR_LDO

PPVTT_S3_DDR_BUF

DDRREG_CS


DDRREG_DRVLDIDT=TRUEGATE_NODE=TRUE


DDRREG_CSGND


DDRREG_VDDQSNS


GATE_NODE=TRUEDIDT=TRUE

DDRREG_DRVH

SWITCHNODE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDIDT=TRUE

DDRREG_LLSWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.4MMDIDT=TRUE

1V5_SNUBBERMIN_LINE_WIDTH=0.4MM

DDRREG_FB

TP_PGOOD_DDRREG_S3

DDRREG_PGNDMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

NO_TEST=TRUEDDRREG_VTTSNS

DIDT=TRUE


DDRREG_VBST

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDDRREG_VBST_R

=PP5V_S3_DDRREG

DIDT=TRUE=PPVIN_S5_DDRREG

DDRVTT_EN

PP5V_S3_DDRREG_V5FILTMIN_LINE_WIDTH=0.6 mm

VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm

PPDDR_S3_REG


1.5V DDR SUPPLY

SM

NOSTUFF

402

25VNP0-C0G

1000PF5%

NOSTUFF

1/10W

603

0.4991%

MF

20%0.1UF

CERM16V

603

20%0.1UF

603CERM16V

0.1UF

CERM16V20%

603

0.1UF20%

603CERM16V


CRITICAL

CSD58857Q5

CRITICAL

MLP5X6-LFPAK-Q5

0

MF-LF1/10W

603

5% MSQ12111R5LF-TH

1.5UH-22A-4MOHM

CRITICAL

603X5R

10UF20%6.3V

CRITICAL

POLY

20%2V

330UF-0.009OHM

CASE-D2-HF1

20%2V

CRITICAL

POLY

330UF-0.009OHM

CASE-D2-HF1

SM

603

6.3V20%

X5R

10UF

SM

PLACEMENT_NOTE=PLACE NEXT TO L7530

8X12-TH-HF

CRITICAL

270UF20%16VELEC

8X12-TH-HF

CRITICAL

20%16VELEC

270UF

1/16W

402

1%

MF-LF

5.90K

70

4.7UF6.3V20%

CERM603

9 78

402X5R

0.033UF16V10%

PLACEMENT_NOTE=Place next to Q7335SM

SM

805-3CERM-X5R

6.3V

22UF20%

CRITICAL

805-3CERM-X5R

CRITICAL

6.3V

22UF20%

402

4.7

5%1/16WMF-LF

402-1

10%1UF

X5R10V

TPS51116QFN

CRITICAL

NO STUFF

50V5%

CERM402

100PF

16VX5R-CERM0805

10UF10%

1/16WMF-LF

1%

402

15.0K

402

1%1/16WMF-LF

15.0K

25VCERM603

20%

0.1UF

6

6

6 30

6

6

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OUT

ILIM1

NC

GND PGNDTHRM_PAD

ILIM2

REFIN2

EN2

OUT2

VIN

POK1

REF

TON

EN_LDO

LDO

LDOREFIN

BYP

FB1

EN1

PVCC

LGATE2

BOOT2

PHASE2

UGATE2

POK2

SKIP*

VCC

OUT1

LGATE1

PHASE1

UGATE1

BOOT1

IN

D1

G1

S2

G2

S1/D2

D1

G1

S2

G2

S1/D2




36

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REVISION

DRAWING NUMBER SIZE

DR


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AVE=0.46A

PEAK=0.69A

K22/K23

AVE=2.88A

PEAK=5.28A

K22/K23

POWER BUDGET

VTT_FSB_S0

FSB VTT AND 3.3V S5 RAILS

EN1 (PPVTT_S0) CONTROLLED SEPARATELY

Vout = 1.212V for Wolfdale

f = 200 kHz

(R7614 LIMIT)

6.7A MAX OUTPUT

PLACE CLOSE TO FETEMC CAPS

(PVTTS0_LGATE)

(P1V05S0_UGATE)

EN REG ASAPAFTER LDO OUT

EN_LDO TIED TO 12V_S5 TO EN LDO FIRST & REGULATOR INTERNAL LOGIC GETS POWEREN2 (3V3_S5) IS TIED TO VCC, TIED INTERNALLY TO PVCCTIED EXTERNALLY TO LDO OUT. SO REGULATOR IS ENABLEDAS SOON AS LDO OUTPUT IS GOOD

<Rb>

INPUT POWER OF 12V_S5

NC

Vout = 0.7V * (1 + Ra / Rb)

(PVTTS0_PHASE)

(=PVTTS0_EN)

SELECTS SWITCHING FREQUENCY

(3.3V NOMINAL)

SEL A3V3 S5

NC

EMC CAPSPLACE CLOSE TO FET

TO LPLACE CLOSEEMC CAPS

POWER BUDGET

EN LDO ASAP

<Ra>

TO LPLACE CLOSEEMC CAPS

INPUT POWER OF 12V_S0

76 OF 110

051-7863

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543

7

6

1

2

Q7660

5 4 3

7

6

1

2

Q7610

2

1C7678

2

1C7679

2

1C7608

2

1C7609

2

1R7663

2

1 C76622

1 C7663

2

1R7662

21

L7660

2

1 C7694

2

1 C7626

2

1 C7625

2

1 C7624

2

1 C7623

2

1 C7611

2

1 C7622

2

1C7613

2

1 R7622

2

1R7643

2

1

XW7651

2

1C7615

2

1C7617

2

1C7612

2

1C7610

2

1C7680

21

R7610

2

1C7601

2

1 C7614

2

1R7614

2

1C7620

21

L76102 1

XW7616

2

1R7620

2

1 C7616

2

1C7621

2

1R7621

2

1 C7683

2

1C7681

6

3

2615

2

33

29

32

1

19

28

13

2516

22

3010

20

5

2318

8

7

3112

21

11

4

2714

9

2417

U7600

21

XW7650

2

1C7685

2

1R7667

2

1C7670

2

1 R7650

21

R7666

2

1 C7689

2

1 R7675

2

1 C7666

2

1 C7675 2

1C7691

2

1 C7692

2

1C7693

PVTTS0_PHASEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMSWITCH_NODE=TRUE

DIDT=TRUESWITCHNODE

PVTTS0_VSNS

=PVTT_S0_EN

PVTTS0_ILIM

PVTTS0_FBDIDT=TRUEMIN_NECK_WIDTH=0.4MMMIN_LINE_WIDTH=0.4MM3V3_SNUBBER


PVTTS0_BOOT_R

3V3_BOOT2

0.2MM0.25MMDIDT=TRUE

3V3_BOOT2_R0.25MM0.2MM

=PP12V_S5_REG

3V3S5_REF

3V3REG_TON

3V3REG_VCC

3V3S5_REF

3V3S5_ILIM

PVTTS0_BOOT


DIDT=TRUE

3V3REG_TON

PP5V_S5_LDO

DIDT=TRUEMIN_NECK_WIDTH=0.4MM

PVTT_SNUBBERMIN_LINE_WIDTH=0.4MM

PGOOD_3V3_S5

PGOOD_1V05_S0

3V3S5_OUT

3V3REG_VCC

MIN_LINE_WIDTH=0.4 MMVOLTAGE=5V


PPVIN_S5_3V3_VTT_RVOLTAGE=12VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.20 MM

DIDT=TRUEPVTTS0_LGATE

MIN_NECK_WIDTH=0.2MMGATE_NODE=TRUE


GATE_NODE=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

DIDT=TRUEPVTTS0_UGATE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm3V3S5_SW

MIN_NECK_WIDTH=0.20 MMSWITCHNODE

VOLTAGE=0V

GND_PP3VREG_SGND

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

3V3S5_BG

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm3V3S5_TG


DIDT=TRUE

=PPVIN_S5_P3V3S5DIDT=TRUE

PP3V3_S5_REG

DIDT=TRUE=PPVIN_S0_PPVTT_FSB

PPVTT_S0_FSB_REG

CRITICALL7610IND,PWR,1.5UH,20%,9A,12mOHM1152S1078

FSB VTT/3.3V S5 SUPPLIESSYNC_MASTER=K22 SYNC_DATE=09/02/2009

RJK0384DPA

CRITICAL

WPAK

CRITICAL

RJK0384DPAWPAK

0805

10UF

X5R-CERM16V10%10%

16VX5R-CERM

10UF

0805

10UF16V

0805X5R-CERM

10%10UF

10%16V

0805X5R-CERM

NOSTUFF603

0.499

1/10WMF

1%

NOSTUFF

1000PF

NP0-C0G25V5%

402

NOSTUFF

402NP0-C0G25V5%1000PF

NOSTUFF603MF

1%1/10W

0.499

2.2UH-10A-13.6MOHM

MMD06EZ-SM

CRITICAL

805-1

10UF

CERM

20%6.3V

16V20%0.1UF

CERM603

16VCERM603

0.1UF20%

16VCERM603

0.1UF20%

0.1UF16VCERM603

20%

16VCERM603

20%0.1UF

CERM

0.1UF16V

603

20%10%

X5R-CERM0805

10UF16V

0

MF-LF1/16W

402

5%

NOSTUFF

05%1/16WMF-LF402

OMIT

SM

10UF

0805

16V10%

X5R-CERM

10%10UF

X5R-CERM0805

16V

X5R-CERM0805

16V10%

10UF 10UF16V10%

X5R-CERM0805

X5R-CERM

10%16V

10UF

0805

603MF-LF

0

5%1/10W

10%10UF

X5R1206

16V

0.1UF

603-1X7R

10%50V

1/16W

402MF-LF

1%110K

NO STUFF

402CERM

5%100PF

50V

OMIT

MMD06EZ-SM

1.5UH-12A

CRITICAL

OMIT

PLACEMENT_NOTE=Place next to C7516

SM

7.32K

1/16WMF-LF402

1%

603

20%

CERM16V

0.1UF

CRITICAL

CASE-D2E-SM

20%330UF

POLY-TANT2.5V

10.0K

MF1/16W0.5%

402

70

X5R-CERM0805

10UF16V10%

6.3X9-THPOLY

20%

CRITICAL

100UF

16V

CRITICAL

QFN

ISL6237

SM

OMIT

402X7R-CERM

16V10%

0.1UF1/16W1%

402MF-LF

110K

X5R

1UF16V

603

10%

MF-LF1/8W5%

805

2.2

5%

0

1/10WMF-LF603

6.3VCERM

4.7UF20%

603

200K1/16WMF-LF402

5%

0.1UF

402X5R

10%25V

X5R603

1UF16V10%

70

603

0.1UF

CERM16V20%

805-1

6.3VCERM

10UF20%

CASE-D3L-SMPOLY-TANT

6.3V

CRITICAL

20%330UF

108

6

76

76

76

76

76

6

76

108

6

6

6

6

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77 OF 110

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BLANK PAGE

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IN

D

SG

D

SG

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

SD

D

GS

D

GS

D

GS

OUT

OUT




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60mA max load @ 0.75V

45mW max power

LOW THROUGH VTT TERMINATION RESISTORS.

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE

MUST GUARANTEE MEM_CKE SIGNALS ARE LOW

5V S0 FET 3.3V S0 FET 3.3V S3 FET

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS

WILL EXIT SELF-REFRESH PREMATURELY.

MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

MCP79 DDRVTT FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

1.5V S0 FET

78 OF 110

051-7863

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1

4

5

Q78501

4

5

Q7825

1

4

5

Q78003

2

1

4

5

Q7853

1

9

6

8

2

3

4

7

5

U7853

2

1 C7853

1

9

6

8

2

3

4

7

5

U7850

2

1 C7850

1

9

6

8

2

3

4

7

5

U7825

2

1 C7825

1

9

6

8

2

3

4

7

5

U7800

2

1 C7800

12

6Q7875

2

1C7876

2 1

R7875

2

1R7876

45

3Q7875

PGOOD_1V5_S0

=PPDDR_S3_S0FET

P3V3S3_EN

=PP12V_S5_PWRCTL

PP1V5_S0_FETMAKE_BASE=TRUEVOLTAGE=1.5V



P3V3_S0_EN

VTTCLAMP_EN

=PP5V_S3_VTTCLAMP

=PPVTT_S0_VTTCLAMP

DDRVTT_EN

VTTCLAMP_L

=PP12V_S5_PWRCTL

PP3V3_S0

=PP3V3_S5_S0FET

=MCPDDR_EN

=PP12V_S5_PWRCTL

P5V_S0_EN

P1V5_S0_EN

=PP12V_S5_PWRCTL

P3V3_S3_EN

PP3V3_S3

=PP3V3_S5_S3FET

=P5VS0_EN

=PP5V_S3_S0FET

PGOOD_5V_S0

PP5V_S0

=P3V3S0_EN


S3 & S0 FETs

70

70

PQFN

IRFH7914PBF

CRITICAL

PQFN

IRFH7914PBF

CRITICAL

CRITICAL

IRFH7914PBFPQFN

FDMC8296POWER33

CRITICAL

70

SLG5AP001TDFN

CRITICAL

16VX5R

10%0.1UF

402

70

CRITICAL

TDFNSLG5AP001

16VX5R

10%0.1UF

402

CRITICAL

TDFNSLG5AP001

70

16V

402

10%0.1UF

X5R

70

TDFNSLG5AP001

CRITICAL

16VX5R

10%0.1UF

402

SSM6N15FEAPESOT563

NO STUFF

0.001UF

402

20%50VCERM

10

5%1/10W

MF-LF603

100K

MF-LF1/16W

5%

402

SSM6N15FEAPESOT563

9 75

6

6 38 70 78

54

6

6

6 38 70 78

6

6

6 38 70 78

6 38 70 78

6 110

6

6

6 110

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THRM_PAD

PVINAVIN

PGMODE

OVT FB

AGND PGND

SWEN




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<Ra>

MAX Current = 0.55A

Vout = 1.1V

<Rb>

(ENABLED AT 2,8V MINIMUM)

MCP 1.1V_S5 AUXC SUPPLY

VOUT = 0.6V * (1 + Ra / Rb)

FREQ = 1Mhz

79 OF 110

051-7863

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2

1 C7901

2

1 R7923

2

1 C79832

1R7980

2

1 R7981

21

L7920

2

1 C7982

2

1 C7920

2

1 R7922

2

1 C7981

11

1

10

2

8

5

7

4

6

93

U7950 DIDT=TRUEMIN_LINE_WIDTH=0.3MM

1V1S5_SWSWITCHNODEMIN_NECK_WIDTH=0.1MM

=PP3V3_S5_P1V1S5

1V1S5_AVIN


PGOOD_1V1_S5

P1V1_S5_EN

1V1S5_FB

PP1V1_S5_REG


1V1 S5 POWER SUPPLY

402X5R16V10%

0.1UF

NOSTUFF

1/16W

402MF-LF

1%23.2K

22UF6.3V20%

CERM-X5R805-3

51.1K1%

MF-LF1/16W

402

60.4K

MF-LF

1%1/16W

402

IHLP1616BZ-SM2.2UH-3.25A

CRITICAL

22PF

CERM

5%50V

402

22UF20%6.3VCERM-X5R805-3

1/16W

1

402MF-LF

5%

402

16V10%

0.1UF

X5R

TPS62510

CRITICAL

BQA

6

70

6

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3V3

5V

PWR_SRC

(4 OF 4)

PCI-E

DP

(2 OF 4)

PEX_TX15*

DP_A_AUX*

PEX_TX1*

PEX_TX13

PEX_TX11*

PEX_TX7*

PEX_TX8*

PEX_TX9

PEX_TX10

PEX_STD_SW*

PEX_TX15

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX12*

PEX_TX12

PEX_TX11

PEX_TX10*

PEX_TX9*

PEX_TX8

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4*

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2*

PEX_TX2

PEX_TX1

PEX_TX0*

PEX_TX0

PEX_REFCLK*

PEX_REFCLK

PEX_RST*

DP_C_HPD

DP_D_HPD

DP_B_HPD

DP_A_HPD

PEX_RX15*

PEX_RX15

PEX_RX14*

PEX_RX14

PEX_RX13*

PEX_RX13

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7*

PEX_RX7

PEX_RX6*

PEX_RX6

PEX_RX5*

PEX_RX5

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2*

PEX_RX2

PEX_RX1*

PEX_RX1

PEX_RX0*

PEX_RX0

CLK_REQ*

DP_C_L0*

DP_C_L0

DP_C_L1*

DP_D_L0*

DP_C_L1

DP_D_L0

DP_C_L2*

DP_D_L1*

DP_C_L2

DP_D_L1

DP_C_L3*

DP_D_L2*

DP_C_L3

DP_D_L2

DP_D_L3*

DP_D_L3

DP_B_L0*

DP_B_L0

DP_B_L1*

DP_A_L0*

DP_B_L1

DP_A_L0

DP_B_L2*

DP_A_L1*

DP_B_L2

DP_A_L1

DP_B_L3*

DP_A_L2*

DP_B_L3

DP_A_L2

DP_A_L3*

DP_A_L3

DP_C_AUX*

DP_C_AUX

DP_D_AUX*

DP_D_AUX

DP_B_AUX*

DP_B_AUX

DP_A_AUX




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Page Notes


APPLE P/N: 516S0699


- =PP3V3_S0_MXM

PLATFORM DEPENDENT

(NOT NECESSARILY THE SAME FOR EVERY MODULE)

MXM SPEC POWER REQUIREMENTS

VOLTAGE

PWR (7-20V)

- =PP5V_S0_MXM

(NONE)

12.5 W

3.3 W

POWERCURRENT

UP TO 10 A

2.5 A

1.0 A3V3

5V


- =PPV_S0_MXM_PWRSRC

- MXM

84 OF 110

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84

86

90

92

96

98

102

104

108

110

114

116

120

122

136

138

48

50

54

56

60

62

66

68

72

74

78

80

142

144

148

150

19

85

87

91

93

97

99

103

105

109

111

115

117

121

123

135

137

49

51

55

57

61

63

67

69

73

75

79

81

141

143

147

149

156

153

155

224

226

218

220

212

214

206

208

236

230

232

217

219

211

213

205

207

199

201

234

223

225

264

266

258

260

252

254

246

248

274

270

272

271

273

265

267

259

261

253

255

276

277

279

154

J8400

E2

E1

9

7

5

3

1

280

278

J8400

2

1 C8415

2

1 C84162

1R8400

2

1 C8414

2

1 C8413

2

1 C8412

2

1 C8410

2

1 C8401

2

1 C8400

=PP5V_S0_MXM

=PP3V3_S0_MXM

=PPV_S0_MXM_PWRSRC

MXM_DP_A_AUX_P

MXM_DP_A_AUX_N

=PP3V3_S0_MXM

MXM_DP_B_AUX_N

MXM_DP_D_AUX_P

MXM_DP_D_AUX_N

MXM_DP_C_AUX_N

MXM_DP_A_ML_P<3>

MXM_DP_A_ML_N<3>

MXM_DP_B_ML_P<3>

MXM_DP_B_ML_N<3>

MXM_DP_B_ML_P<2>

MXM_DP_B_ML_N<2>

MXM_DP_B_ML_P<1>

MXM_DP_A_ML_N<0>

MXM_DP_B_ML_N<1>

MXM_DP_D_ML_P<3>

MXM_DP_D_ML_N<3>

MXM_DP_D_ML_P<2>

MXM_DP_C_ML_P<3>

MXM_DP_D_ML_N<2>

MXM_DP_C_ML_N<3>

MXM_DP_D_ML_P<1>

MXM_DP_C_ML_P<2>

MXM_DP_D_ML_N<1>

MXM_DP_C_ML_N<2>

MXM_DP_D_ML_P<0>

MXM_DP_C_ML_P<1>

MXM_DP_D_ML_N<0>

MXM_DP_C_ML_N<1>

MXM_DP_C_ML_P<0>

MXM_DP_C_ML_N<0>

MXM_DP_A_HPD

MXM_DP_D_HPD

MXM_DP_C_HPD

CLK_100M_MXM_P

CLK_100M_MXM_N

MXM_DP_B_ML_P<0>

MXM_DP_B_HPD

MXM_DP_B_AUX_P

MXM_CLKREQ_L

MXM_DP_B_ML_N<0>

MXM_DP_C_AUX_P

MXM_PCIE_R2D_N<0>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_N<12>

MXM_PCIE_R2D_N<13>

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_N<15>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_P<14>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_N<11>

MXM_PCIE_R2D_P<0>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<10>

MXM_PCIE_R2D_P<10>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_P<8>

MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<5>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_N<2>

MXM_PCIE_D2R_N<0>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_P<3>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_N<15>

MXM_PCIE_D2R_P<14>

MXM_PCIE_D2R_N<14>

MXM_PCIE_D2R_P<13>

MXM_PCIE_D2R_P<11>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_P<15>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_N<12>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_P<6>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_N<2>

MXM_DP_A_ML_P<2>

MXM_DP_A_ML_N<2>

MXM_DP_A_ML_P<1>

MXM_DP_A_ML_N<1>

MXM_DP_A_ML_P<0>

MXM_PCIE_D2R_N<11>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_P<1>

MXM_RESET_L

MXM_PCIE_STD_SWING_L


MXM PCIe, DP & Power

CRITICAL

F-RT-SM

MXM

B35P101-0121

F-RT-SM

MXM

B35P101-0121MXM

10%

X7R402

50V

0.001UF

805-3CERM-X5R

MXM

6.3V20%22UF

100K

402

1/16W5%

MF-LF

MXM

MXM

X7R

10%

402

50V

0.001UF

MXM

402X7R

10%50V

0.001UF

MXM

X7R

10%

402

50V

0.001UF

0.001UF

MXM

10%

X7R402

50V

805-3CERM-X5R

MXM

6.3V20%22UF

22UF35VELEC6.3X5.5-SM1

20%

MXM

6

6 84 85

53

93 107

93 107

6 84 85

87

87

87

87

91 107

91 107

87

87

87

87

87

91 107

87

87

87

87

87

87

87

87

87

87

87

87

87

87

87

87

87

91

87

87

87

87

87

87

87

87

87

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

86 102

91 107

91 107

91 107

91 107

91 107

86 102

86 102

86 102

86 102

87

85

www.bblianmeng.com

www.vinafix.vn

WC*

SDA

SCL

E2/NC2

E1/NC1

E0/NC0

VSS

VCC

GPIO0

VGA_DISABLE*

TH_OVERT*

TH_PWM

LVDS_DDC_CLK

LVDS_UTX1

LVDS_UTX2*

RSVD1

PNL_PWR_EN

LVDS_UTX1*

RSVD2

LVDS_UTX2

LVDS_UTX3*

LVDS_LCLK

PRSNT_R*

LVDS_LTX3

DVI_HPD

PWR_EN

SMB_CLK

LVDS_LTX0

LVDS_LTX0*

LVDS_LTX1

LVDS_LTX2

LVDS_LTX2*

LVDS_LTX3*

LVDS_UTX0

LVDS_UTX0*

LVDS_UTX3

PNL_BL_EN

PRSNT_L*

PWRGOOD

VGA_BLUE

VGA_GREEN

VGA_HSYNC

VGA_RED

VGA_VSYNC

VGA_DDC_DAT

GPIO1

GPIO2

HDMI_CEC

OEM0

OEM1

OEM2

OEM3

OEM4

OEM5

OEM7

VGA_DDC_CLK

RSVD3

RSVD4

RSVD5

RSVD7

RSVD8

RSVD9

RSVD10

RSVD11

RSVD12

RSVD13

RSVD14

RSVD15

RSVD16

RSVD17

RSVD18

RSVD19

RSVD21

SMB_DAT

TH_ALERT*

LVDS_UCLK*

LVDS_UCLK

RSVD20

LVDS_LCLK*

LVDS_LTX1*

RSVD6

RSVD0

RSVD22

RSVD23

PWR_LEVEL

LVDS_DDC_DAT

PNL_BL_PWM

OEM6

WAKE*

SYSTEM MANAGEMENT

(1 OF 4)

LVDS

ANALOG DISPLAY

POWER/THERMAL

MANAGEMENT

GNDGND

(3 OF 4)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

FLOAT = LOW SWINGGND = HIGH SWING


- =PP3V3_S0_MXM

Page NotesPower aliases required by this page:

- =PM_MXM_PGOOD_PULLUP

STUFF FOR WRITE PROTECT


PULLED TO GROUND ON MXMWE DON’T USE CARD DETECT

PLACE CLOSE TO J7800

MXM SYSTEM INFORMATION ROM

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR

SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

I2C ADDRESS: AC

- =SMB_MXM_THRM_CLK

- =SMB_MXM_THRM_DATA PULLUPS & PULLDOWNS AT MXM CONNECTOR

FLOAT = NORMAL VGA MODEGND = SECONDARY DISPLAY CARD

85 OF 110

051-7863

A.0.0


2 1

R8510

2 1

R8504

53

52

283

282

E4

275

269

268

263

47

262

257

256

251

250

E3

244

228

222

221

46

216

215

210

209

204

203

198

197

192

191

37

186

185

180

179

174

173

166

157

152

151

36

146

145

140

139

134

133

125

124

119

118

17

113

112

107

106

101

100

95

94

89

88

15

83

82

77

76

71

70

65

64

59

58

13

11

J8400

4

162

168

164

170

21

158

160

172

24

20

22

32

34

231

229

227

167

165

163

161

16

14

249

247

12

245

243

242

241

240

239

238

237

235

233

159

10

6

18

8

2

281

23

27

25

45

44

43

42

41

40

39

38

175

177

181

183

187

189

193

195

169

171

182

184

188

190

194

196

200

202

176

178

33

35

29

30

28

2631

J8400

2 1

R8503

21

R8501

7

4

8

5

6

3

2

1

U8570

2

1 C8570

2

1R8570

21

R8500

MXM_VGA_DISABLE_L

MXM_PCIE_STD_SWING_L

TP_MXM_VGA_GREEN

TP_MXM_VGA_HSYNC

MXM_PNL_BL_EN

=PP3V3_S0_MXM

MXM_DETECT_R

=PP3V3_S0_MXM

MXM_LVDS_A_DATA_N<0>

MXM_LVDS_A_DATA_P<0>

MXM_VGA_DISABLE_L

MXM_LVDS_DDC_CLK

MXM_ROM_WP

MXM_LVDS_DDC_DAT

MXM_DETECT_L

PM_MXM_EN

PM_MXM_PGOOD

MXM_PWR_LEVEL

=SMB_MXM_THRM_SCL

=SMB_MXM_THRM_SDA

MXM_ALERT_L

MXM_OVERT_L

MXM_DETECT_L

MXM_DETECT_R

TP_MXM_WAKE_L






MXM_LVDS_B_CLK_P

MXM_LVDS_B_CLK_N

MXM_LVDS_B_DATA_P<3>

MXM_LVDS_B_DATA_N<3>







PM_MXM_PGOOD


TP_MXM_VGA_BLUE

TP_MXM_VGA_VSYNC

TP_MXM_VGA_RED

TP_MXM_VGA_DDC_DAT

TP_MXM_VGA_DDC_CLK

TP_MXM_TH_PWM

MXM_LVDS_A_CLK_P

MXM_LVDS_A_CLK_N

TP_MXM_DVI_HPD

MXM_LVDS_DDC_DAT

MXM_LVDS_DDC_CLK

TP_MXM_GPIO0

TP_MXM_GPIO1

TP_MXM_GPIO2

TP_MXM_HDMI_CEC

=PM_MXM_PGOOD_PULLUP

MXM_PNL_PWR_EN

MXM_PNL_BL_PWM


MXM I/O

1/16WMF-LF

402

5%

0

NOSTUFF

1/16WMF-LF 5%

402

0

MXM

B35P101-0121

MXM

F-RT-SMF-RT-SM

MXM

B35P101-0121

1/16W

10K

5%MF-LF

402

4021/16WMF-LF 5%

100K

MXM

CRITICAL

SO8M24C02-WMN6TPHF

MF-LF4025% 1/16W

100K

MXM

0.1UF10V20%

CERM402

MF-LF1/16W

5%

402

0

NOSTUFF

85

84

89

85 84 6

85

85 84 6

89

89

85

89 85

89 85

85 9

70

85 70

50

52

52

50

50

85 9

85

89

89

89

89

89

89

89

89

89

89

89

89

89

89

89

85 70

89

89

89

89 85

89 85

70

89

89

www.bblianmeng.com

www.vinafix.vn

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MXM RX CAPSMXM TX CAPS

86 OF 110

051-7863

A.0.0


21C8631

21C8629

21C8630

21C8627

21C8628

21C8626

21C8625

21C8624

21C8623

21C8621

21C8622

21C8619

21C8620

21C8617

21C8618

21C8616

21C8615

21C8614

21C8613

21C8612

21C8611

21C8610

21C8609

21C8608

21C8607

21C8606

21C8605

21C8603

21C8604

21C8601

21C8602

21C8600

21C8661

21C8659

21C8660

21C8663

21C8662

21C8658

21C8656

21C8657

21C8655

21C8654

21C8650

21C8651

21C8653

21C8652

21C8649

21C8648

21C8647

21C8646

21C8645

21C8644

21C8643

21C8642

21C8640

21C8641

21C8639

21C8638

21C8637

21C8636

21C8634

21C8635

21C8633

21C8632

PEG_R2D_C_N<1>

PEG_R2D_C_P<2>

PEG_R2D_C_N<3>

PEG_R2D_C_P<3>

PEG_R2D_C_N<4>

PEG_R2D_C_N<0>

PEG_D2R_N<8>

PEG_D2R_P<8>

MXM_PCIE_D2R_P<6>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_N<7>

PEG_D2R_P<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

MXM_PCIE_D2R_P<15>

MXM_PCIE_D2R_N<4>

PEG_D2R_N<3>

MXM_PCIE_R2D_N<13>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_N<6>

PEG_D2R_P<11>

PEG_D2R_N<5>

PEG_D2R_P<5>

PEG_D2R_P<14>

PEG_D2R_N<15>

PEG_D2R_P<15>

PEG_D2R_P<13>

PEG_D2R_N<13>

PEG_D2R_N<11>

PEG_D2R_P<9>

PEG_D2R_N<9>

PEG_D2R_N<4>

PEG_D2R_N<14>

PEG_D2R_P<10>

PEG_D2R_N<7>

PEG_D2R_P<6>

PEG_D2R_P<12>

PEG_D2R_P<7>

MXM_PCIE_D2R_P<11>

MXM_PCIE_D2R_N<11>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_P<3>

MXM_PCIE_R2D_P<0>

MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<0>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_N<2>

MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<5>

PEG_R2D_C_N<7>

PEG_R2D_C_N<9>

PEG_R2D_C_P<9>

PEG_R2D_C_P<11>

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

PEG_R2D_C_P<5>

PEG_R2D_C_N<11>

PEG_R2D_C_N<10>

PEG_R2D_C_N<13>

PEG_R2D_C_N<12>

PEG_R2D_C_P<12>

PEG_D2R_P<4>

MXM_PCIE_R2D_P<8>

MXM_PCIE_R2D_P<5>

PEG_R2D_C_P<10>

MXM_PCIE_R2D_P<10>

MXM_PCIE_R2D_P<9>

MXM_PCIE_D2R_P<14>

MXM_PCIE_D2R_N<14>

PEG_R2D_C_P<1>

PEG_R2D_C_P<4>

MXM_PCIE_R2D_N<12>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<15>

PEG_R2D_C_P<15>

PEG_R2D_C_N<15>

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

PEG_R2D_C_P<13>

MXM_PCIE_R2D_N<10>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_P<12>

PEG_R2D_C_N<2>

MXM_PCIE_R2D_P<14>

PEG_R2D_C_P<0> MXM_PCIE_R2D_N<15>

MXM_PCIE_D2R_N<12>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<13>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<0>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<4>

PEG_R2D_C_N<5>

PEG_D2R_N<10>

PEG_D2R_N<12>

PEG_D2R_P<3>

PEG_D2R_N<0>

MXM_PCIE_D2R_N<15>

MXM_PCIE_R2D_N<11>

MXM_PCIE_R2D_P<11>


MXM PCIE CAPS

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

MXM X5R0.1UF 10% 40216V

84 102

84 102

84 102

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 10% 402X5R16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 16V0.1UF 402X5R10%

MXM X5R0.1UF 40210% 16V

MXM 10%0.1UF 402X5R16V

MXM 4020.1UF X5R10% 16V

MXM 4020.1UF X5R10% 16V

84 102

84 102

84 102

84 102

84 102

84 102

84 102

MXM X5R16V10% 4020.1UF

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

MXM X5R16V10% 4020.1UF

MXM 402X5R10% 16V0.1UF

MXM 402X5R10% 16V0.1UF

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF X5R10% 16V 402

MXM 402X5R10% 16V0.1UF

MXM X5R 40216V10%0.1UF

MXM 16V10% X5R 4020.1UF

MXM 0.1UF 16V10% X5R 402

MXM 16V10% X5R 4020.1UF

9 102

MXM 0.1UF 16V10% X5R 402

MXM 16V10% X5R 4020.1UF

MXM 16V X5R10% 4020.1UF

MXM 10% X5R 40216V0.1UF

MXM 16V10% X5R 4020.1UF

MXM 16V 40210% X5R0.1UF

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

MXM 16V10% X5R 4020.1UF

MXM 16V10% X5R 4020.1UF

MXM 16V10% X5R 4020.1UF

MXM 16V10% X5R 4020.1UF

9 102

MXM 0.1UF 16V10% X5R 402

MXM 16V10% X5R 4020.1UF

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 16V10% X5R 4020.1UF9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

9 102

MXM 16V 402X5R0.1UF 10%

9 102

9 102

9 102

MXM 0.1UF 402X5R10% 16V

MXM 16V10% X5R 4020.1UF

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

84 102

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 0.1UF 402X5R10% 16V

MXM 16V 4020.1UF X5R10%

MXM 0.1UF 402X5R10% 16V

MXM 4020.1UF X5R10% 16V

MXM 0.1UF 10% 402X5R16V

MXM 16V10%0.1UF 402X5R

MXM 402X5R0.1UF 16V10%

MXM X5R0.1UF 40216V10%

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102

84 102 MXM 16V X5R0.1UF 40210%

9 102

9 102

84 102

9 102

9 102

9 102

MXM 16V10% X5R 4020.1UF

MXM 16V 402X5R0.1UF 10%

MXM 40210% X5R16V0.1UF

MXM 0.1UF 16V10% X5R 402

MXM 10% X5R0.1UF 16V 402

84 102

84 102

MXM 16V 4020.1UF X5R10%

9 102

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D

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PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(NONE)

(NONE)




Page Notes- =PP3V3_S0_DP

MCP Connections

Unused MXM DP InterfacesUnused LVDS Interfaces

Unused MCP Interfaces

Unused MXM Interfaces

87 OF 110

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2

1R8711

2

1R8710

2

1R8701

2

1R8700

NO_TEST=TRUENC_MXM_LVDS_B_CLK_PMAKE_BASE=TRUE

DP_IG_CA_DETMAKE_BASE=TRUE NO_TEST=TRUENC_MXM_LVDS_B_DATA_P<2>

DP_IG_HPDMAKE_BASE=TRUE

=MCP_HDMI_HPD

=MCP_HDMI_DDC_DATA

DP_IG_AUX_CH_NNO_TEST=TRUEMAKE_BASE=TRUE

NC_DP_IG_AUX_CH_N

DP_IG_AUX_CH_PNO_TEST=TRUEMAKE_BASE=TRUE

NC_DP_IG_AUX_CH_P

LVDS_IG_BKL_PWM

CLK_100M_MXM_N

MXM_RESET_L

MXM_LVDS_B_DATA_P<3>NO_TEST=TRUE

NC_MXM_LVDS_B_DATA_P<3>MAKE_BASE=TRUE


MXM_LVDS_B_DATA_N<3>NO_TEST=TRUE

NC_MXM_LVDS_B_DATA_N<3>MAKE_BASE=TRUE









MXM_LVDS_B_DATA_N<0> NC_MXM_LVDS_B_DATA_N<0>NO_TEST=TRUEMAKE_BASE=TRUE

MXM_LVDS_B_CLK_N NC_MXM_LVDS_B_CLK_NMAKE_BASE=TRUE NO_TEST=TRUE

MXM_LVDS_B_CLK_P

MXM_LVDS_A_DATA_P<3>NO_TEST=TRUE

NC_MXM_LVDS_A_DATA_P<3>MAKE_BASE=TRUE

MXM_LVDS_A_DATA_N<3>NO_TEST=TRUE

NC_MXM_LVDS_A_DATA_N<3>MAKE_BASE=TRUE











MXM_LVDS_A_CLK_PNO_TEST=TRUE

NC_MXM_LVDS_A_CLK_PMAKE_BASE=TRUE



MXM_LVDS_A_CLK_NNO_TEST=TRUE

NC_MXM_LVDS_A_CLK_NMAKE_BASE=TRUE

LVDS_IG_DDC_DATA NC_LVDS_IG_DDC_DATANO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_DDC_CLKNO_TEST=TRUE

NC_LVDS_IG_DDC_CLKMAKE_BASE=TRUE

LVDS_IG_B_DATA_P<3>MAKE_BASE=TRUENC_LVDS_IG_B_DATA_P<3>

NO_TEST=TRUELVDS_IG_B_DATA_N<3> NC_LVDS_IG_B_DATA_N<3>

NO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_B_DATA_N<2>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1> NC_LVDS_IG_B_DATA_N<1>NO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_B_DATA_P<2> NC_LVDS_IG_B_DATA_P<2>NO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_B_DATA_N<0> NC_LVDS_IG_B_DATA_N<0>NO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_B_DATA_P<1> NC_LVDS_IG_B_DATA_P<1>NO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_B_CLK_NNO_TEST=TRUE

NC_LVDS_IG_B_CLK_NMAKE_BASE=TRUE

LVDS_IG_B_DATA_P<0>NO_TEST=TRUE

NC_LVDS_IG_B_DATA_P<0>MAKE_BASE=TRUE

LVDS_IG_B_CLK_PNO_TEST=TRUE

NC_LVDS_IG_B_CLK_PMAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>NO_TEST=TRUE

NC_LVDS_IG_A_DATA_P<3>MAKE_BASE=TRUE

LVDS_IG_A_DATA_N<3>NO_TEST=TRUE

NC_LVDS_IG_A_DATA_N<3>MAKE_BASE=TRUE











LVDS_IG_A_CLK_N NC_LVDS_IG_A_CLK_NMAKE_BASE=TRUE NO_TEST=TRUE



=MCP_HDMI_DDC_CLKMAKE_BASE=TRUEDP_IG_DDC_CLKMAKE_BASE=TRUEDP_IG_DDC_DATA

=MCP_HDMI_TXC_NMAKE_BASE=TRUENC_MCP_HDMI_TXC_N

NO_TEST=TRUE

=MCP_HDMI_TXC_PMAKE_BASE=TRUENC_MCP_HDMI_TXC_P

NO_TEST=TRUE

=MCP_HDMI_TXD_N<0..2>MAKE_BASE=TRUENC_MCP_HDMI_TXD_N<0..2>

NO_TEST=TRUE

=MCP_HDMI_TXD_P<0..2> NC_MCP_HDMI_TXD_P<0..2>NO_TEST=TRUEMAKE_BASE=TRUE

LVDS_IG_PANEL_PWRNO_TEST=TRUEMAKE_BASE=TRUE

NC_LVDS_IG_PANEL_PWRNO_TEST=TRUEMAKE_BASE=TRUE

NC_LVDS_IG_BKL_PWM

LVDS_IG_BKL_ONNO_TEST=TRUEMAKE_BASE=TRUE

NC_LVDS_IG_BKL_ON

MXM_DP_D_HPDMAKE_BASE=TRUENC_MXM_DP_D_HPD

NO_TEST=TRUE

MXM_DP_D_AUX_NMAKE_BASE=TRUENC_MXM_DP_D_AUX_N

NO_TEST=TRUE

MXM_DP_D_AUX_PMAKE_BASE=TRUENC_MXM_DP_D_AUX_P

NO_TEST=TRUE

MXM_DP_D_ML_N<0..3>MAKE_BASE=TRUENC_MXM_DP_D_ML_N<0..3>

NO_TEST=TRUE

MXM_DP_D_ML_P<0..3>MAKE_BASE=TRUENC_MXM_DP_D_ML_P<0..3>

NO_TEST=TRUE

MXM_DP_B_HPDMAKE_BASE=TRUENC_MXM_DP_B_HPD

NO_TEST=TRUE

MXM_DP_B_AUX_NMAKE_BASE=TRUENC_MXM_DP_B_AUX_N

NO_TEST=TRUE

MXM_DP_B_AUX_PMAKE_BASE=TRUENC_MXM_DP_B_AUX_P

NO_TEST=TRUE

MXM_DP_B_ML_N<0..3>MAKE_BASE=TRUENC_MXM_DP_B_ML_N<0..3>

NO_TEST=TRUE

LVDS_IG_A_CLK_P NC_LVDS_IG_A_CLK_PMAKE_BASE=TRUE NO_TEST=TRUE

MXM_DP_B_ML_P<0..3> NC_MXM_DP_B_ML_P<0..3>MAKE_BASE=TRUE NO_TEST=TRUE

=PP3V3_S0_DP

MAKE_BASE=TRUEGPU_CLK100M_PCIE_N

MAKE_BASE=TRUEPEG_RESET_L

CLK_100M_MXM_PMAKE_BASE=TRUE

GPU_CLK100M_PCIE_P

SYNC_DATE=03/12/2009SYNC_MASTER=MARKVIDEO

Display: Aliases

402MF-LF1/16W5%1M

402MF-LF1/16W5%22K

402

1/16W5%2.7K

MF-LF402

1/16W5%2.7K

MF-LF

18

18

18

18

18

18

84

84

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

84

84

84

84

84

84

84

84

84

18 84

92 91 90 95 6

102 9

9

84 102 9

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A

D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

88 OF 110

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BLANK PAGESYNC_DATE=01/05/2009SYNC_MASTER=K23_DAVE

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A

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C

345678

D

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8 7 5 4 2 1

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GND

GND

IN

IN

IN

IN

IN

IN

IN

IN

OUT

Y

B

A

14

OUT

G S

D




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A

D

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PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE NEAR J9002

used by diag LED

BACKLIGHT CONTROL SUPPORTonly on when Panel has valid video

Options for GPU or MLB HW controlled backlight enable are included

guarantee backlight is

PANEL POWER CONTROL


Page NotesPower aliases required by this page:

I2C MASTER ON TCON

518S0685

INTERNAL DP INTERFACE

IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR

- =PP12V_S0_LCD

- =PP3V3_S0_VIDEO


(NONE)

buffers are multiple parts, other parts are on csa 95

90 OF 110

051-7863

A.0.0


21

R9072

21

R9071

144

7

3

U9500

2

1 C9011

4

5

3

1

2

U9050 21

R9012

4

5

2

3

U95202

1 C9005

21

R9011

21

R9009

31

D9000

21C904721C9046

21C9045

21C9043

21C9044

21C9041

21C9042

21C9040

21

R9051

21

R9050

2

1C9010

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9002

4

3

6

5

2

1

Q9000

21

L9050

2

1R9002

21

R9081

2

1R9000

21

R900121

C9000 21

L9000

2

1C9020

2

1C9001

2

1R90702

1

3

Q9001

=PP3V3_S0_DP

SOT886

CERM

TC7SZ08AFEAPE

LCD_PANEL_PWR_L

LCD_PANEL_PWR_L_RC

LCD_BKL_ON_DLY

=PP3V3_S0_DP

LCD_PANEL_PWR

VIDEO_ON

=PP12V_S0_LCD

PP12V_LCD

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=12V

LCD_PANEL_PWR_G

LCD_BKL_MLB_EN

LCD_BKL_ON_MUX

VIDEO_ON

VIDEO_ON_L

DP_INT_LINK_P<0>

DP_INT_LINK_N<0>

DP_INT_LINK_P<1>

DP_INT_LINK_N<1>

LCD_PANEL_PWR_L_DIV

VIDEO_ON

DP_HPD_INT

SPDIF_DP_AUDIO_OUT

NO_TESTDP_INT_LINK_CONN_N<1>

LCD_PWM_FILTBACKLIGHT_PWM LCD_PWM

DP_INT_LINK_N<3>

DP_INT_LINK_N<2>

DP_INT_LINK_P<2>

I2C_TCON_SDA

DP_INT_AUXCH_P

DP_INT_AUXCH_N

=PP3V3_S0_VIDEO

NO_TESTDP_INT_LINK_CONN_P<2>


I2C_TCON_SCL


VIDEO_ON


VOLTAGE=12VPP12V_LCD_CONN


VIDEO_ON_L_DLY

=PP3V3_S0_DP

LCD_BKL_ON

=SMB_DP_TCON_SDA

=SMB_DP_TCON_SCL


NO_TESTDP_INT_LINK_CONN_N<0>NO_TESTDP_INT_LINK_CONN_P<0>

DP_INT_LINK_P<3>



Display: Int DP Connector

402MF-LF

5%1/16W

100K

SOT23-HF12N7002

402

100K

1/16W5%

MF-LF

29.4K

1/16W1%

MF-LF402

603-1

0.1UF

10%

X7R50V

FERR-250-OHM

SM

0

603

1/10W5%

MF-LF

MF-LF

5%

0

1/10W

603

NOSTUFF

6

TSSOP-HF

74LVC14

NOSTUFF

0.1UF20%

CERM10V

402

NOSTUFF

SOT665NOSTUFF

MF-LF

5%1/16W

1K

402

74AUP2G14GM

22UF6.3V20%

805

61K

5%

402MF-LF1/16W

MF-LF1/16W1%

402

19.1K

BAT54XG

SOT23

16V

10UF10%

0805X5R-CERM

107 92

107 92

107 92

107 92

107 92

107 92

107 92

50V20%

402

0.001uF

CERM

107 92

0.1uFX5R 40216V10%

4020.1uF

16V X5R10%

10%0.1uF

402X5R16V

10% 16V 402X5R0.1uF

10%0.1uF

X5R 40216V

16V0.1uF

402X5R10%

10% 16V X5R 4020.1uF

4020.1uF

10% X5R16V

MF-LF402

0

5%1/16W

NOSTUFF

NOSTUFF

MF-LF1/16W5%

0

402

20%

CERM50V

0.001uF

402

F-RT-SM20389-Y30E-01

CRITICAL

FDC638P_GSM

CRITICAL

CRITICAL

FERR-250-OHM

SM

100K

1/16WMF-LF

402

5%

402

47

MF-LF1/16W5%

92 91 90 95

92 91 90 87 95 6

95

95 90

6

95

95 90

95 90

92

95

107

95 6

107 92

107 92

6

107

107

107

95 90

92 91 90 87 95 6

87 6

52

52

107

107

107

107

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BI

BI

IN

XSD*

HPD_1

DIN1_0-

DIN1_1+

DIN1_2-

DAUX1+

DIN1_3+

DDC_DAT2

DAUX2-

DDC_CLK2

HPD_2

GPU_SEL

TST0

DIN1_2+

DIN1_1-

DOUT_0-

DOUT_1+

DDC_CLK1

DDC_DAT1

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-DIN2_1+

DDC_AUX_SEL

DIN2_1-

AUX+

AUX-

HPDIN

DIN2_2+

DIN2_2-

DIN2_3+

DIN2_3-

DAUX2+

DIN2_0-

DIN2_0+

DIN1_0+

DAUX1-

DOUT_1-

DOUT_0+

DIN1_3-

VDD

GND

NCNC

IN

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

VCC

NCCFGX

PC0/I2C_ADDR0

PC1/I2C_ADDR1

GND

REXT

AUX+

AUX-

CEXT

OUT4N

OUT4P

OUT3N

OUT3P

OUT2N

OUT2P

OUT1N

OUT1P

OE*

CA_DET

CFGY

SDA_CTL

SCL_CTL

MODE

IN1P

IN1N

IN2P

IN2N

IN3P

IN3N

IN4P

IN4N

THRM_PAD

I2C_CTL_EN*

HPD HPD_SINKIN

OUT

BI

IN




36

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PAGE TITLE

C

A

D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

From external source

EQ & Re-Driver for DP source

Common mode bias for Tx EQ AUX interception

NC

NC

DisplayPort Mux 1Analog mux at External Connector

LO=AUX_CH

INT_PD

INT_PD

To External connector

NC

INT_PD

INT_PD

NC

HI=DDCHI=PORT2LO=PORT1

From iMac GPU

to internal display via EQ

91 OF 110

051-7863

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2

1R9151

2

1R9150

21C9150

21C9151

21

C91062 1R9103

2 1R9102

2 1R91012 1R9100

21C9123

21C9124

21C9125

21C9126

21C9127

21C9120

21C9121

21C9122

46

40

33

21

15

11

49

34

35

6

4

3

14

13

17

16

20

19

23

22

25

29

28

136

47

48

44

45

41

42

38

39

26

307

43

37

31

24

18

125

32

2

1027

8

9

U9100

2

1 C9100

2

1 C9101

2

1 C9102

2

1 C9103

2

1 C9104

2

1 C9105

21C9136

21C9137

21C9134

21C9135

21C9133

21C9131

21C9132

21C9130

21

R9309

2

1R9130

21C913921C9138

B7

J4

A2

G2

J1

H3

J2

A1

H7

H4

G8

C8

B3

F2

F1

E2

E1

D2

D1

B2

B1

F8

F9

E8

E9

D8

D9

B8

B9

A8

A9

B6

A6

B5

A5

B4

A4

J5

J8

H5

H8

C2

H6

J6

H9

J9

H2

H1

U9120

2

1 C9323

2

1 C9322

DP_CA_DET

MXM_DP_A_HPD

=PP3V3_S0_DP

MXM_DP_A_AUX_NNO_TEST

DP_MUX_N<2> NO_TESTDP_MUX_P<2> NO_TEST

DP_MUX_HPD

NO_TESTDP_MUX_N<3>

NO_TESTMXM_DP_A_ML_N<3>

=PP3V3_S0_DP

NO_TESTMXM_DP_A_ML_N<0>

NO_TESTDP_MUX_P<0>

DP_HPD_EXT_R

DP_EXT_LINK_N<0>NO_TEST

DP_EXT_LINK_P<0>NO_TEST

NO_TESTDP_EXT_LINK_N<2>


NO_TESTMXM_DP_A_ML_C_P<0>

MXM_DP_A_ML_C_N<1> NO_TEST

MXM_DP_A_ML_C_N<2> NO_TESTMXM_DP_A_ML_N<2> NO_TEST


NO_TESTDP_EXT_LINK_C_N<2>

DP_MUX_AUXCH_N NO_TEST

DP_EXT_AUXCH_NNO_TEST

DP_EXT_LINK_N<3>NO_TEST

=PP3V3_S0_DP

DP_MUX_P<1> NO_TEST

NO_TESTMXM_DP_A_ML_P<1>

DP_EXT_AUXCH_PNO_TEST

DP_HPD_EXT

MXM_DP_A_ML_P<2> NO_TEST

DPMUX1_ENABLE

DP_CA_DET

DP_EXT_LINK_C_P<2>NO_TEST



DP_MUX_AUXCH_P NO_TEST

DP_MUX_P<3> NO_TEST

DP_MUX_N<1> NO_TEST



PS8121_REXT

PS8121_I2C_EN_L

PS8121_PC1

PS8121_CEXT

MXM_DP_A_HPD_EQ


PS8121_PC0

MXM_DP_A_AUX_C_N NO_TEST

NO_TESTMXM_DP_A_ML_EQ_P<0>

MXM_DP_A_ML_EQ_P<1> NO_TEST

DP_TX_EQ_AUXCH_N

DP_TX_EQ_AUXCH_P

MXM_DP_A_ML_EQ_P<2> NO_TESTMXM_DP_A_ML_EQ_N<2> NO_TEST

NO_TESTMXM_DP_A_ML_EQ_P<3>

NO_TESTDP_EXT_LINK_N<1>

NO_TESTDP_EXT_LINK_P<1>


NO_TESTDP_EXT_LINK_C_P<3>

DP_MUX_N<0> NO_TEST

MXM_DP_A_AUX_C_P NO_TEST

MXM_DP_A_ML_EQ_N<0> NO_TEST

=PP3V3_S0_DP

NO_TESTDP_TX_EQ_AUXCH_N

NO_TESTDP_TX_EQ_AUXCH_P

MXM_DP_A_AUX_C_NNO_TEST

MXM_DP_A_AUX_C_PNO_TEST

=PP3V3_S0_DP

MXM_DP_A_AUX_PNO_TEST

=I2C_DP_DRV_SCL

=I2C_DP_DRV_SDA

DP_EXT_LINK_C_N<3>NO_TEST

MXM_DP_A_ML_P<3> NO_TEST

MXM_DP_A_ML_C_P<2> NO_TEST

NO_TESTMXM_DP_A_ML_C_P<3>

MXM_DP_A_ML_C_P<1> NO_TEST

DPMUX_VIDEO_IN_SEL

MXM_DP_A_ML_EQ_N<3> NO_TEST

=PP3V3_S0_DP

NO_TESTMXM_DP_A_ML_P<0>

NO_TESTMXM_DP_A_ML_N<1> NO_TESTMXM_DP_A_ML_EQ_N<1>

Display: BiDiVi Mux1SYNC_MASTER=MARKVIDEO SYNC_DATE=03/12/2009

100K1/16W5%

402MF-LF

1/16W5%

402MF-LF

100K

40210%0.1uF

X5R16V

16V 402X5R10%0.1uF

52

52

20%

402 X5R-CERM

6.3V4.7UF

84

91 94

MF-LF

499

1%1/16W

4021/16W

10KNOSTUFF

MF-LF5%

402MF-LF1/16W 5%

10K 402NOSTUFF

1/16W 5%

NOSTUFF

MF-LF

40210K

0.1uF16V 402X5R10%

0.1uFX5R16V 40210%

0.1uFX5R10% 16V 402

10% X5R 40216V0.1uF

40216V10% X5R0.1uF

10%0.1uF

40216V X5R

16V10% 4020.1uF

X5R

16V0.1uF

10% 402X5R

PS8121EDQFN

0.1UF

402CERM10V20%

402CERM

0.1UF10V20%

402CERM10V20%0.1UF

402CERM

0.1UF10V20%

0.1UF

402CERM10V20%

402CERM10V20%0.1UF

107 84

107 84

107 84

107 84

107 84

107 84

107 84

107 84

94 107

94 107

94 107

94 107

94 107

94 107

94 107

94 107

0.1uF16V 402X5R10%

X5R10% 16V 4020.1uF

10% 40216V X5R0.1uF

4020.1uF

16V10% X5R

10% 16V 402X5R0.1uF

10% 16V 4020.1uF

X5R

10%0.1uF

16V 402X5R

0.1uF16V10% X5R 402

95

107 84

107 84

107 92

107 92

92 107

92 107

92 107

92 107

92 107

92 107

92 107

92 107

91 94

95 94

1%

402

1/16WMF-LF

1K

NOSTUFF

MF-LF402

10K5%

1/16W

10% 40216V X5R0.1uF

40210%0.1uF

X5R16V

92

BGA

CRITICAL

CBTL06141EE

402

20%10V

0.1UF

CERM

95 49

20%10VCERM402

0.1UF

95 107 94

95 107 94

92 91 90 87 95 6

92 91 90 87 95 6

107

107

107

107

92 91 90 87 95 6

107

107

107

107

107

107

91107

107

107

91 107

91 107

107

107

107

107

107

91107

107

92 91 90 87 95 6

107 91

107 91

107 91

107 91

92 91 90 87 95 6

107

107

107

107

107

92 91 90 87 95 6

107

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IN

BI

BI

BI

BI

OUT

OUT

NCNC

OUT

NC

IN

IN

IN

OUT

IN

NC

OUT

NC

NCNC

NC

NCNC

NCNC

OUT

NC

NCNC

NC

IN2_D2N

IN2_D3P

IN2_D3N

IN2_PEQ/SCL_CTL

MODE0

CEXT

VDD

IN1_CADET

IN1_HPDX

IN2_CADET

IN2_D1N

IN2_HPDX

IN2_D2P

IN2_AUXP_SCL

IN2_AUXN_SDA

IN1_AUXP_SCL

IN1_AUXN_SDA

DP_AC_AUXP

DP_AC_AUXN

DP_AUXP_SCL

DP_AUXN_SDA

TMDS_SCL

TMDS_SDA

TMDS_PC0

TMDS_CLKN

TMDS_CLKP

TMDS_HPD

TMDS_CH0P

TMDS_PC1

TMDS_CH1N

TMDS_CH1P

TMDS_CH2N

TMDS_CH2P

DP_D3N

DP_D3P

DP_HPD

DP_D2N

DP_D2P

DP_D1N

DP_D1P

PD

DP_D0N

DP_D0P

MODE1

SW/I2C_ADDR

MODE2

REXT

PIO

THRM_PAD

IN1_D0P

IN1_D1P

IN1_D2P

IN1_D3P

IN1_D3N

IN1_D0N

IN1_D1N

IN2_D0P

IN2_D0N

IN2_D1P

DP_CADET

GND

TMDS_CH0N

IN1_PEQ/SDA_CTL

IN1_D2N

NC

OUT

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

BI

BI

IN

IN

IN

IN

IN

OUT

IN

IN

BI

BI

OUT

BI

BI




36

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2 1


Apple Inc.

PAGE


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C

345678

D

B

8 7 5 4 2 1

MODE[2..0] = 111 SELECTS I2C CONTROL MODE

see below

To Internal display

TO EXTERNAL SOURCE VIA MUX1INT_PD

TO IMAC GPU

From iMac GPU

To Internal display

DisplayPort

on this pin of >=100 kOhms

Note: INT_PD = Internal Pulldown

Equalizer & MUX 2

INT_PD

From Internal display

From iMac GPU

via MUX 1

via MUX 1From external input

INT_PD

Pulls for AUX_CHfrom DisplayPort Mux #2

INT_PD

From external input

AC caps for EQ AUX interception

INT_PD

INT_PD

INT_PD

92 OF 110

051-7863

A.0.0


21C9291

21C9290

2

1R9213

2

1R9212

2

1R9221

2

1R9215

2

1R9220

21C924921C9248

21R9281

62

47

38

22

4

35

34

44

37

41

40

39

49

48

46

45

43

42

73

66

70

71

59

69

65

64

67

19

23

24

20

21

17

18

14

15

16

25

26

68

10

11

12

8

9

5

6

2

3

7

28

29

72

63

50

36

27

13

53

52

51

55

54

58

57

61

60

56

32

33

30

31

1

U9200

21R9280

21R9222

21C9247

21C9246

21C9245

21C9244

21C9243

21C9242

21C9241

21C9240 2

1 C9200

2

1 C9201

2

1 C9202

2

1 C9203

2

1 C9204

21

C9212

=PP3V3_S0_DP

NO_TESTDP_INT_AUXCH_N

DP_INT_AUXCH_P NO_TEST

DP_EQLZ_AUXCH_P NO_TEST

NO_TESTDP_EQLZ_AUXCH_N

NO_TESTMXM_DP_C_AUX_P

NO_TESTMXM_DP_C_AUX_N

=PP3V3_S0_DP

MXM_DP_C_AUX_C_P

=PP3V3_S0_DP

MXM_DP_C_AUX_C_N

MXM_DP_C_ML_N<3>NO_TEST

MXM_DP_C_ML_P<3>NO_TEST


MXM_DP_C_ML_P<2>NO_TEST



NO_TESTMXM_DP_C_ML_P<0>

NO_TESTMXM_DP_C_ML_P<1>

=I2C_DP_EQLZ_SDA

DP_EQLZ_CADET

DP_MUX_N<0>

DP_MUX_P<0>

NO_TESTMXM_DP_C_ML_C_N<3>

MXM_DP_C_ML_C_P<3> NO_TEST

DP_EQLZ_EXTR

DP_EQLZ_ADDR

NO_TEST DP_INT_LINK_P<0>

NO_TEST DP_INT_LINK_N<0>


NO_TEST DP_INT_LINK_N<1>


DP_HPD_INT


DP_INT_LINK_N<3>NO_TEST

NO_TESTMXM_DP_C_AUX_C_NNO_TESTMXM_DP_C_AUX_C_P

DP_MUX_HPD

DP_MUX_N<1>

MXM_DP_C_HPD

=PP3V3_S0_DP

DP_EQLZ_AUXCH_PNO_TEST

DP_MUX_AUXCH_N NO_TEST

DP_MUX_AUXCH_P NO_TEST

DP_EQLZ_EXTC

DP_INT_LINK_N<2>NO_TEST

DP_INT_AUXCH_NNO_TEST

DP_INT_AUXCH_PNO_TEST

DP_EQLZ_AUXCH_NNO_TEST

DP_EQLZ_MODE2

DP_MUX_P<2>

DP_MUX_P<1>

MXM_DP_C_ML_C_N<2> NO_TEST


NO_TESTMXM_DP_C_ML_C_P<1>




DP_MUX_N<2>

DP_MUX_P<3>

DP_MUX_N<3>

=I2C_DP_EQLZ_SCL

DP_EQLZ_MODE0

DP_EQLZ_MODE1

SYNC_DATE=N/A

BIDIVI DP MUX2SYNC_MASTER=MASTER107 92

90 107 92

90 107

90 107 92

107 92

0.1uF16V10% 402X5R

10% 40216V X5R0.1uF

MF-LF1/16W

402

1%100K

402MF-LF1/16W

100K1%

402

1/16W

1K5%

MF-LF

107 84

107 84

90 107

107 84

107 84

107 84

107 84

107 84

1K

402

1/16WMF-LF

5%

107 91

1K5%

402MF-LF1/16W

107 84

107 91

90 107

107 84

107 91

107 91

107 91

107 91

107 91

90

52

0.1uF40210% 16V X5R

90 107

40210% 16V X5R0.1uF

1/16W5%

1MMF-LF 402

PS8325

CRITICAL

QFN

NOSTUFF

4025% 1/16W

0MF-LF

90 107

MF-LF 4021%

4.99K1/16W

90 107

X5R10%0.1uF

40216V

4020.1uF

10% X5R16V

0.1uF402X5R10% 16V

0.1uF16V10% 402X5R

16V 40210% X5R0.1uF

0.1uFX5R16V10% 402

0.1uF402X5R16V10%

0.1uF16V X5R 40210%

107 91

90 107

107 91

107 91

52

0.1UF

CERM402

10V20% 20%

CERM402

0.1UF10V

20%

402

0.1UF10VCERM

0.1UF

CERM10V

402

20%0.1UF10VCERM

20%

402

90 107

91

84

90 107 92

90 107 92

107 92

10792

4.7UF

20%

402X5R-CERM6.3V

107 84

92 91 90 87 95 6

92 91 90 87 95 6

107 92

92 91 90 87 95 6

107 92

107

107

92 107

92 107

92 91 90 87 95 6

107

107

107

107

107

107

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345678

D

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8 7 5 4 2 1

93 OF 110

051-7863

A.0.0



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IN

OC*

OUT

EN

GND

IN

IN

IN

IN

ML_LANE2P

ML_LANE2N

RETURN

GND

ML_LANE1N

ML_LANE0N

GND

ML_LANE1P

ML_LANE0P

GND

AUX_CHP

AUX_CHN

DP_PWR

GND

ML_LANE3N

ML_LANE3PGND

HPD

CONFIG1

CONFIG2

SHIELD PINS

IN

IO

NC NC

IO

GND

IO

NC NC

IO

GND

2E

1E

1Y 1Z

2Z

GND

VCC

2Y

IN

IN

OUT

IO

NC NC

IO

GND

IO

NC NC

IO

GND

IN

IN

IN

IN

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2




36

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PAGE TITLE

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A

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2 1


Apple Inc.

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C

345678

D

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8 7 5 4 2 1

APPLE PART NO 514-0686

94 OF 110

051-7863

A.0.0


21R9407

21R9406

21R9405

21R9404

21R9403

21R9402

21R9401

21R9400

2

1 C9450

2

1R9421

8

4

65

3

21

7

U9450

109

12

3

D9410

76

45

3

D9410

19

10

12

15

17

9

11

3

5

22

21

2

1413

87

1

20

6

4

16

18

J9400

2

1 C94852

1 C9481

2

1 C94801

3

5

2

4

U9400

4

3 2

1

FL9403

4

3 2

1

FL9402

4

3 2

1

FL9401

4

3 2

1

FL9400

2

1R9422

21

L9400

2

1 C9400

109

12

3

D9411

2

1R9425

76

45

3

D9411

52

6

43

1

D9400

2

1R9420

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

DP_ML_CONN_N<3>

DP_ML_CONN_P<3>

NO_TEST

SOT23

NO_TEST DP_ML_CONN_N<0>NO_TEST DP_ML_CONN_P<0>

0

DP_ML_CONN_N<1>NO_TEST

0

0

NOSTUFF

NOSTUFF

NOSTUFF

DP_EXT_LINK_N<0>

DP_EXT_LINK_P<0>

12-OHM-100MA

TCM1210-4SM

91

TCM1210-4SM

73 9 CRITICAL

6.3V

0.1UF

0

NO_TEST


0

0

0

NO_TEST DP_ML_CONN_P<2>

DP_ML_CONN_N<2>NO_TEST

DP_EXT_LINK_N<2>

DP_EXT_LINK_P<2>

CRITICAL

SLP2510P8

RCLAMP0524P

91 107

91 107


0

DP_ML_CONN_P<1>NO_TEST

TPS2051B

CRITICAL

X5R

20%10UF

603CERM

20%

402

10V

91 107

CRITICAL

20%

X5R6.3V

603

10UF

91 107

91 107

CRITICAL

MDP-K22F-ANG-TH1

91 95

SLP2510P8RCLAMP0524P

SLP2510P8

CRITICAL

CRITICAL

NX3L2G66GD

SOT996-2

1%

402MF-LF1/16W

100K

91 107

CERM

20%

402

10V

0.1UF

95

1%1/16W

402MF-LF

100K

CRITICAL

RCLAMP0504FSC70-6-1

CRITICAL

SLP2510P8RCLAMP0524P

1/16W5%

MF-LF402

1M

91 107

91 107

603CERM50V20%0.01UF

SM-1

400-OHM-EMI

12-OHM-100MA

Display: Ext DP ConnectorSYNC_MASTER=MARKVIDEO SYNC_DATE=03/12/2009

=PP3V3_S0_DPCONN

PM_SLPS3_BUF1_L

DP_EXT_LINK_N<3>

DP_SRC_AUX_TERM_EN

DP_EXT_LINK_P<3>

DP_HPD_EXT

=PP3V3_S0_DPCONN

DP_EXT_LINK_N<1>

DP_EXT_LINK_P<1>


VOLTAGE=3.3V

PP3V3_S0_DPAUX

GND_DPAUX

VOLTAGE=0V



PP3V3_S0_DPFUSEMIN_LINE_WIDTH=0.38 MM

DP_CA_DET

PP3V3_S0_DPPWRMIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

HDMI_CEC

DP_EXT_AUXCH_P

DP_EXT_AUXCH_N

TP_DP_OC

1/16W

1M

MF-LF

5%

402

RCLAMP0524P

107

107

107 107

107

107

107

107

6 94

6 94

91 107 95

91 107 95

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IN

IN

OUT

IN

Y

B

A

OUT

IN

IN

IN

OUTIN

Y

A

B 08

OUT

OUT

OUT

14

Y

A

B 08IN

OUT

E

Z Y

VCC

GNDNC

Y

B

A

OUT

14IN

IN

OUT

OUT

OUT

OUT

OUT

1I1

1I0

2I1

2I0

3I0

4I0

GND

4Y

3Y

2Y

1Y

4I1

3I1

E*

S

VCC

PADTHM

IN

IN

IN

IN

IN

IN

OUT

S GND

OUTPUT

MUXSELECTOR

I1

I0Y

VCC

IN

IN

IN

14

14

IN

IN

14

IN

IN

Y

B

A




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2 1


Apple Inc.

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C

345678

D

B

8 7 5 4 2 1

PANEL/BACKLIGHT CONTROL MUX

PLACE NEAR U6201

AUX Bias Enable

*Some inputs listed below come up as outputs driven low under the SMC flasher

Series R should prevent any issues on the inputs

Ouptuts are OK as low by default

SMC Signals for BiDiVi

BiDiVi MUX Enable

DisplayPort

External AUX Channel and HPD Buffers & filters

enables weak sink-like aux termination

so that one bi-directional system can find the otherP25*

Inputs

PG0

S0

0

Default ValuesS5/S3

0

X

0

0

0

X

0

X

0

SMC

PF4

PF3

PF7

P22*

P23*

P27

Outputs

P26

enables 100k dp aux source termination

0

XPF6

P21*

AUDIO MUX

95 OF 110

051-7863

A.0.0


31

D9503

142

7

1

U9500 2

1C9550

4

5

3

1

2

U95502 1

6

5 3

4

U9540

21

R9543

1

8

4

6

7

U9502

146

7

5

U9500

21

R9542

2

1 C9562

6

5

2

1

U9520

2

1 C9561

2

1 C9560

5

8

4

2

3

U9502

2

1R9521

2

1R9520

4

5

2

3

U9510

6

5

2

1

U9510

21

R9523

5

8

4

2

3

U9501

21

R95111

8

4

6

7

U9501

21

R9509

2

1C9504

3 1

D9502

21

R9508

2

1R9507

21

R9541

148

7

9

U9500

21

R9540

21

R9510

21

R9506

2

1C9503

1410

7

11

U950021

R9505

3 1

D9501

21

R9503

2

1C95012

1 C9500

31

D9500

1412

7

13

U950021

R9502

4

5

6

1

3

2

U9524

16

17

1

815

12

13

14

910

11

76

5

4

3

2

U9522

NOSTUFF

NOSTUFF

62 AUD_MUX_CNTRL

DP_AUXP_L

=PP3V3_S0_DP

DP_AUXN_L

SOT23

BACKLIGHT_PWM





VOLTAGE=3.3V

VOLTAGE=3.3V

49 95 91

95

402MF-LF

5%1/16W

091

49 95 91

SOT90274LVC2G32

49 91 95

95

49 95

49 95

49 95

0

MF-LF

5%

402

1/16W

SOT88674AUP2G14GM

49 95

74AUP2G14GMSOT886

1/16W

402MF

4.75M1%

4.75M

MF

1%

402

1/16W

74LVC2G08SOT902

402CERM

0.1UF10V20%

94

CERM

20%

402

10V

0.1UF

SOT886

0.1UF10V20%

CERM402

95

402MF-LF

0

5%1/16W

49 95

TSSOP-HF

74LVC2G08SOT902

49 95 91

95

402

1/16WMF-LF

1%

499K

SOT886NX3L1G66

CRITICAL

TC7SZ08AFEAPESOT665

402CERM

0.1UF20%10V

49 95

TSSOP-HF

74LVC1449 95

49 95 91

49 95

49 95

90

90

90

74LVC157ADHVQFN

49 95

85 95

49 95

85

49 95

85

62

SOT88674LVC1G157

90

66 103

49 95

402

5%

MF-LF1/16W

1K 74LVC14

TSSOP-HF

SOT23

BAT54XG

20%

402

10V

0.1UF

CERM

402

10%

CERM

1UF6.3V

1/16WMF-LF

5%

402

3.3K

BAT54XG

SOT23

1K

1/16WMF-LF

5%

402

TSSOP-HF

74LVC14

6.3V

1UF10%

CERM402

5%

402MF-LF1/16W

3.3K

MF-LF1/16W5%

402

3.3K90

85 95 3.3K

1/16W5%

402MF-LF

74LVC14

TSSOP-HF

0

1/16W

402MF-LF

5%

MF-LF

5%1M

1/16W

402

MF-LF402

5%1/16W

4.7K

1UF

CERM6.3V

402

10%

3.3K

1/16W

402

5%

MF-LF

49 95

74LVC2G32SOT902


Display: BiDiVi Support


MUX_CNTRL

AUD_SPDIF_INSPDIF_DP_AUDIO_OUT

DPMUX_VIDEO_IN_SEL

BIDIVI_BKL_MUX_SEL

=PP3V3_S0_DP

MXM_PNL_BL_EN

AUD_SPDIF_IN_CODEC

=PP3V3_S0_DP

=PP3V3_S0_DP

BIDIVI_AUX_TERM_EN_L

BIDIVI_BKL_ON

BIDIVI_PNL_PWR_EN

BIDIVI_BKL_PWM=PP3V3_S0_DP

MXM_PNL_PWR_EN

LCD_BKL_ON_MUXLCD_PANEL_PWR

HPD_FILT

DPMUX1_OROUT_L DPMUX1_ENABLE

=PP3V3_S0_DP

DP_HPD_EXT_L

AUXCH_P_STATE

DP_EXT_AUXCH_N

BIDIVI_AUX_TERM_EN

DP_AUXN_DLY_L

DP_SINK_AUX_TERM_EN

DPMUX_VIDEO_IN_SEL

AUX_TERM_OR_OUT

HPD_FILT

DP_HPD_PULS_EAT_L

=PP3V3_S0_DP

DP_HPD_EXT

BIDIVI_BKL_PWM


VIDEO_ON

AUXCH_N_STATE

AUXCH_P_STATE

SMC_PNL_BL_PWM

SMC_DP_HPD

MXM_PNL_BL_PWM

HPD_FILT

DPMUX_VIDEO_IN_SEL DPMUX_VIDEO_IN_SEL_L

=PP3V3_S0_DP

DP_SRC_AUX_TERM_EN

=PP3V3_S0_DP

=PP3V3_S0_DP

DPMUX_VIDEO_IN_SEL

BIDIVI_AUX_TERM_EN

BIDIVI_PNL_PWR_EN

SMC_VIDEO_ON

BIDIVI_BKL_ON

=PP3V3_S0_DP

SMC_DP_HPD

=PP3V3_S0_DP

AUXCH_N_STATEAUXCH_N_R

DP_AUXP_DLY_L AUXCH_P_R

DP_SINK_AUX_TERM_EN

DPMUX_VIDEO_IN_SEL

BIDIVI_BKL_MUX_SEL

BIDIVI_AUX_TERM_EN

PP3V3_S0_DPAUXP_SINK

DP_EXT_AUXCH_P

=PP3V3_S0_DP

74LVC14

74AUP2G14GM

BAT54XG

SOT23

BAT54XG

PP3V3_S0_DP_D=PP3V3_S0_DP

NOSTUFF

MXM_PNL_BL_PWM

92

94

67

95

6 95 87 90 91 92

6 95 87 90 91 92

6 95 87 90 91 92

6 95 87 90 91 92

6 95 87 90 91 92

49 95

91 94 107

6 95 87 90 91 92

91 94

49 50

6 95 87 90 91 92

6 95 87 92

6 95 87 90 91 92

49

6 95 87 90 91 92

49 95

6 95 87 90 91 92

49 95

6 95 87 90 91 95

95

91107

6 87 90 91 92 95

90 91

6 95 87 90 91 92

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MINIMUM LINE WIDTHALLOW ROUTEON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM


LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM







TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM





























FSB 1X Signals

Group 1

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

CPU Signal Constraints

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

Group 0

Group 0

Group 1

Group 3

Group 2

FSB 4X Signal Groups

FSB (Front-Side Bus) Constraints

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

Signals within each 4x group should be matched within 5 ps of strobe.

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 90 ps. (Tighther than MCP79)

All 4x FSB signals with impedance requirements are 42-ohm single-ended.

FSB 2X signals / groups shown in signal table on right.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

FSB 1X signals shown in signal table on right.

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Intel Design Guide recommends FSB signals be routed only on internal layers.

FSB 4X signals / groups shown in signal table on right.

All 2x/1x/Async FSB signals with impedance requirements are 50-ohm single-ended.

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET PHYSICAL

FSB Clock Constraints

MCP FSB COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5


FSB 2X

Signals

NET_TYPE

SPACING

Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MOST CPU SIGNALS WITH IMPEDANCE REQUIREMENTS ARE 50-OHM SINGLE-ENDED.

SR DG recommends at least 25 mils, >50 mils preferred

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CPU_50S CPU_ITP XDP_CPURST_L

VR_CPU_VSNS_R_PCPU_VCCSENSECPU_27P4S

VR_CPU_VSNS_R_NCPU_VCCSENSECPU_27P4S

CPU_XDP_BPMB<3..0>CPU_ITPCPU_50S

CPU_XDP_BPM_L<5..0>CPU_50S CPU_ITP

CPU_XDP_TRST_LCPU_50S CPU_ITP

CPU_XDP_TCKCPU_50S CPU_ITP

CPU_XDP_TMSCPU_ITPCPU_50S

CPU_XDP_TDOCPU_50S CPU_ITP

CPU_XDP_TDICPU_ITPCPU_50S

CPU_27P4S CPU_COMP CPU_COMP<0>

CPU_8MILCPU_50S CPU_FERR_L

CPU_50S CPU_A20M_LCPU_AGTL

FSB_50S FSB_LOCK_LFSB_1X

FSB_50S FSB_HIT_LFSB_1X

FSB_50S FSB_DEFER_LFSB_1X

CLK_FSB_100D FSB_CLK_CPU_PCLK_FSB

FSB_CLK_CPU_NCLK_FSBCLK_FSB_100D

FSB_CLK_ITP_NCLK_FSBCLK_FSB_100D

FSB_DSTB FSB_DSTB_L_P<1>FSB_DSTB_42S

FSB_DSTB_L_N<2>FSB_DSTBFSB_DSTB_42S

FSB_BREQ1_LFSB_50S FSB_1X

FSB_50S FSB_DBSY_LFSB_1X

FSB_1XFSB_50S FSB_DRDY_L

CPU_IERR_LCPU_50S CPU_AGTL

FSB_CLK_ITP_PCLK_FSBCLK_FSB_100D

FSB_CLK_MCP_NCLK_FSB_100D CLK_FSB

CLK_FSBCLK_FSB_100D FSB_CLK_MCP_P

MCP_FSB_COMP MCP_CPU_COMP_GNDMCP_50S

CPU_50S CPU_DPRSTP_LCPU_AGTL

CPU_DPSLP_LCPU_50S CPU_AGTL

FSB_CPUSLP_LCPU_AGTLCPU_50S

PM_THRMTRIP_LCPU_50S CPU_8MIL

FSB_1X FSB_CPURST_LFSB_50S

FSB_50S FSB_RS_L<2..0>FSB_1X

FSB_50S FSB_TRDY_LFSB_1X

FSB_ADSTB FSB_ADSTB_L<0>FSB_50S

FSB_REQ_L<4..0>FSB_50S FSB_ADDR

FSB_A_L<16..3>FSB_50S FSB_ADDR

FSB_ADS_LFSB_50S FSB_1X

FSB_DSTBFSB_DSTB_42S FSB_DSTB_L_P<2>FSB_42S FSB_DINV_L<2>FSB_DATA

FSB_DSTB_L_N<3>FSB_DSTB_42S FSB_DSTB

CPU_STPCLK_LCPU_50S CPU_AGTL

MCP_FSB_COMP MCP_BCLK_VML_COMP_VDDMCP_50S

CPU_SMI_LCPU_50S CPU_AGTL

MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_GND

CPU_PWRGDCPU_AGTLCPU_50S

CPU_50S CPU_PROCHOT_LCPU_AGTL

CPU_50S CPU_AGTL CPU_BSEL<2..0>

FSB_BREQ0_LFSB_50S FSB_1X

FSB_DSTB_L_P<3>FSB_DSTB_42S FSB_DSTB

FSB_DINV_L<3>FSB_DATAFSB_42S

FSB_D_L<63..48>FSB_DATAFSB_42S

FSB_D_L<47..32>FSB_DATAFSB_42S

FSB_D_L<15..0>FSB_42S FSB_DATA

FSB_DSTB_L_P<0>FSB_DSTBFSB_DSTB_42S

FSB_DINV_L<0>FSB_42S FSB_DATA

FSB_BPRI_LFSB_50S FSB_1X

FSB_50S FSB_HITM_LFSB_1X

CPU_50S CPU_INIT_LCPU_AGTL

CPU_AGTLCPU_50S CPU_IGNNE_L

CPU_50S CPU_INTRCPU_AGTL

MCP_FSB_COMP MCP_CPU_COMP_VCCMCP_50S

CPU_50S CPU_NMICPU_AGTL

FSB_A_L<35..17>FSB_ADDRFSB_50S

FSB_ADSTB_L<1>FSB_ADSTBFSB_50S


FSB_DATA FSB_D_L<31..16>FSB_42S

FSB_DINV_L<1>FSB_DATAFSB_42S

FSB_BNR_LFSB_50S FSB_1X


CPU_50S CPU_GTLREF CPU_GTLREF0

CPU_50S CPU_GTLREF CPU_GTLREF1

CPU_27P4S CPU_COMP CPU_COMP<8>

CPU_27P4S CPU_COMP<2>CPU_COMP


CPU_8MIL CPU_VID<7..0>CPU_50S

CPU_VCC_PKG_SENSE_NCPU_VCCSENSECPU_27P4S

CPU_VCC_PKG_SENSE_PCPU_27P4S CPU_VCCSENSE


CPU/FSB ConstraintsSYNC_MASTER=K22 SYNC_DATE=09/02/2009

=50_OHM_SE =50_OHM_SE=50_OHM_SECPU_50S =STANDARD* =STANDARD=50_OHM_SE

=27P4_OHM_SE =27P4_OHM_SECPU_27P4S * =27P4_OHM_SE 0.175 MM 0.175 MM=27P4_OHM_SE

* ?CPU_AGTL =STANDARD

?CPU_8MIL * 0.2 MM

*CPU_COMP ?0.6 MM

TOP,BOTTOMCLK_FSB ?=4x_DIELECTRIC

FSB_1X ?TOP,BOTTOM =3x_DIELECTRIC

FSB_ADSTB TOP,BOTTOM ?=4x_DIELECTRIC

?FSB_ADDR =3x_DIELECTRICTOP,BOTTOM

?=5x_DIELECTRICFSB_DSTB TOP,BOTTOM?FSB_DSTB * =3x_DIELECTRIC

FSB_DATA * ?=2x_DIELECTRIC

?* =STANDARDFSB_1X

=42_OHM_SE=42_OHM_SE=42_OHM_SEFSB_DSTB_42S =1:1_DIFFPAIR* =1:1_DIFFPAIR=42_OHM_SE

?FSB_DATA =4x_DIELECTRICTOP,BOTTOM

FSB_ADSTB * ?=2x_DIELECTRIC

*CLK_FSB ?=3x_DIELECTRIC

* =STANDARD=STANDARDFSB_42S =42_OHM_SE=42_OHM_SE =42_OHM_SE=42_OHM_SE

* =STANDARD=50_OHM_SE=50_OHM_SEFSB_50S =STANDARD=50_OHM_SE=50_OHM_SE

?CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC

MCP_FSB_COMP * ?0.2 MM

*FSB_ADDR ?=STANDARD

?*CPU_GTLREF 0.6 MM

?*CPU_ITP =2:1_SPACING

CPU_VCCSENSE ?0.6 MM*

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFFCLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

=50_OHM_SE =STANDARD=STANDARD*MCP_50S =50_OHM_SE =50_OHM_SE=50_OHM_SE

13

71

71

11 13

11 13

11 13

11 13

11 13

11 13

11 13

11

10 14

10 14

10 14

10 14

10 14

10 14

10 14

13 14

10 14

10 14

14

10 14

10 14

10

13 14

14

14

14

11 14

11 14

11 14

11 14 50

10 13 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

14

10 14

14

11 13 14

11 14 50

11 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 14

10 11 29

10 11 29

11

11

11

12 71

12 71

12 71

11

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TABLE_SPACING_ASSIGNMENT_ITEM







AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD















































Memory Net Properties

Memory Net PropertiesNET_TYPE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SETNeed to support MEM_*-style wildcards!

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

SPACINGPHYSICAL

DDR2:

DDR3:

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.

No DQS to clock matching requirement.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.

All DQS pairs should be matched within 100 ps of clocks.

A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Constraints

DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.

MCP MEM COMP Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair.

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MEM_70D MEM_A_DQS_N<1>MEM_DQS

MEM_DQSMEM_70D MEM_B_DQS_P<1>

MEM_DQSMEM_70D MEM_B_DQS_N<3>

MEM_B_ODT<3..0>MEM_CTRLMEM_40S_VDD

MEM_B_CS_L<3..0>MEM_CTRLMEM_40S_VDD

MEM_B_CKE<3..0>MEM_CTRLMEM_40S_VDD

MEM_B_WE_LMEM_CMDMEM_40S_VDD

MEM_B_CAS_LMEM_CMDMEM_40S_VDD

MEM_CMDMEM_40S_VDD MEM_B_BA<2..0>

MEM_B_RAS_LMEM_CMDMEM_40S_VDD

MEM_B_A<14..0>MEM_CMDMEM_40S_VDD

MEM_B_DM<1>MEM_40S MEM_DATA

MEM_40S MEM_DATA MEM_B_DQ<15..8>

MEM_DATAMEM_40S MEM_B_DM<0>

MEM_B_DQ<7..0>MEM_40S MEM_DATA

MEM_B_DM<3>MEM_DATAMEM_40S



MEM_B_DQ<23..16>MEM_DATAMEM_40S


MEM_B_DQ<47..40>MEM_DATAMEM_40S





MEM_40S MEM_DATA MEM_B_DM<6>MEM_40S MEM_DATA MEM_B_DQ<55..48>

MEM_B_CLK_P<4..3>MEM_70D_VDD MEM_CLK

MEM_A_DQS_P<7>MEM_DQSMEM_70D

MEM_DQS MEM_B_DQS_N<4>MEM_70D



MEM_B_DQS_N<6>MEM_DQSMEM_70D

MEM_B_DQS_P<7>MEM_DQSMEM_70D

MEM_B_DQS_N<7>MEM_DQSMEM_70D

MEM_B_CLK_N<4..3>MEM_CLKMEM_70D_VDD

MEM_B_CLK_P<1..0>MEM_70D_VDD MEM_CLK

MEM_B_CLK_N<1..0>MEM_70D_VDD MEM_CLK

MEM_A_DQS_N<5>MEM_DQSMEM_70D

MEM_A_CLK_N<4..3>MEM_CLKMEM_70D_VDD

MEM_40S_VDD MEM_CTRL MEM_A_ODT<3..0>

MEM_40S MEM_DATA MEM_A_DQ<15..8>

MEM_A_DM<2>MEM_DATAMEM_40S


MEM_A_DQS_P<2>MEM_70D MEM_DQS




MEM_A_DQS_P<0>MEM_70D MEM_DQS


MEM_70D MEM_A_DQS_P<6>MEM_DQS

MEM_70D MEM_A_DQS_P<5>MEM_DQS


MEM_DATA MEM_A_DM<7>MEM_40S

MEM_DATAMEM_40S MEM_A_DQ<63..56>

MEM_40S MEM_DATA MEM_A_DM<6>MEM_DATAMEM_40S MEM_A_DQ<55..48>

MEM_A_DQ<47..40>MEM_DATAMEM_40S

MEM_40S MEM_DATA MEM_A_DM<4>MEM_40S MEM_DATA MEM_A_DQ<39..32>

MEM_DATAMEM_40S MEM_A_DQ<23..16>

MEM_DATAMEM_40S MEM_A_DM<1>

MEM_A_DQ<7..0>MEM_40S MEM_DATA

MEM_CMD MEM_A_WE_LMEM_40S_VDD

MEM_CMD MEM_A_CAS_LMEM_40S_VDD

MEM_40S_VDD MEM_CMD MEM_A_RAS_LMEM_40S_VDD MEM_A_BA<2..0>MEM_CMD

MEM_A_A<14..0>MEM_40S_VDD MEM_CMD

MEM_A_CS_L<3..0>MEM_40S_VDD MEM_CTRL

MEM_40S_VDD MEM_A_CKE<3..0>MEM_CTRL

MEM_A_CLK_P<4..3>MEM_70D_VDD MEM_CLK

MEM_70D_VDD MEM_CLK MEM_A_CLK_P<1..0>




MEM_A_DQS_N<3>MEM_DQSMEM_70D

MEM_40S MEM_A_DM<5>MEM_DATA

MEM_40S MEM_DATA MEM_A_DQ<31..24>


MEM_70D_VDD MEM_CLK MEM_A_CLK_N<1..0>

MCP_MEM_COMP_VDDMCP_MEM_COMPMCP_MEM_COMP

MEM_DQSMEM_70D MEM_B_DQS_N<0>MEM_DQSMEM_70D MEM_B_DQS_P<0>



MEM_DQSMEM_70D MEM_B_DQS_P<3>MEM_DQSMEM_70D MEM_B_DQS_N<2>

MEM_70D MEM_DQS MEM_B_DQS_P<4>


MCP_MEM_COMP_GNDMCP_MEM_COMPMCP_MEM_COMP

Memory ConstraintsSYNC_MASTER=K22 SYNC_DATE=09/02/2009

MEM_40S =STANDARD* =STANDARD=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

=40_OHM_SE =40_OHM_SE=40_OHM_SE=40_OHM_SE*MEM_40S_VDD =STANDARD=STANDARD

=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF* =70_OHM_DIFF =70_OHM_DIFFMEM_70D

* MEM_2OTHERMEM_DQS *

MEM_2OTHERMEM_DATA * *

MEM_2OTHERMEM_CMD **

MEM_2OTHERMEM_CTRL * *

=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF* =70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFFMEM_70D_VDD

=4:1_SPACINGMEM_CLK2MEM * ?

MEM_CMD2CMD * ?=1.5:1_SPACING

MEM_CLK2MEMMEM_CLK MEM_CLK *

MEM_CLK2MEMMEM_CLK MEM_DATA *

MEM_DQSMEM_CTRL * MEM_CTRL2MEM

MEM_CTRL2CTRL =2:1_SPACING* ?

=1.5:1_SPACINGMEM_DATA2DATA * ?

MEM_CMD2MEM*MEM_CMD MEM_CTRL

*MEM_CMD MEM_CMD2MEMMEM_DATA

MEM_CMD2MEMMEM_CMD *MEM_DQS

*MEM_DATA MEM_CLK MEM_DATA2MEM

MEM_DATA * MEM_DATA2MEMMEM_CTRL

MEM_DATA MEM_DATA2DATAMEM_DATA *

MEM_CMD *MEM_CMD MEM_CMD2CMD

MEM_DATA2MEM =3:1_SPACING* ?

=3:1_SPACINGMEM_DQS2MEM * ?

=2.5:1_SPACINGMEM_CTRL2MEM * ?

MEM_CLK MEM_CTRL MEM_CLK2MEM*

0.2 MM ?MCP_MEM_COMP *

MCP_MEM_COMP =STANDARD=STANDARDY* =STANDARD0.175 MM 0.175 MM

MEM_2OTHERMEM_CLK **

MEM_CTRL * MEM_DQS2MEMMEM_DQS

MEM_CMD2MEMMEM_CMD *MEM_CLK

MEM_CMDMEM_DQS MEM_DQS2MEM*

MEM_CLK * MEM_DQS2MEMMEM_DQS

MEM_DATA2MEMMEM_DATA *MEM_CMD

MEM_DATA MEM_CTRL2MEM*MEM_CTRL

MEM_CMD * MEM_CTRL2MEMMEM_CTRL

MEM_DATA * MEM_DQS2MEMMEM_DQS

MEM_DQSMEM_DQS MEM_DQS2MEM*

=3:1_SPACINGMEM_CMD2MEM * ?

=3:1_SPACINGMEM_2OTHER * ?

MEM_CMD MEM_CLK2MEMMEM_CLK *

MEM_CLK2MEMMEM_CLK MEM_DQS *

MEM_CTRL MEM_CTRL2MEMMEM_CLK *

MEM_CTRL2CTRLMEM_CTRL *MEM_CTRL

MEM_DATA2MEMMEM_DATA *MEM_DQS

15 33

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15 33

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15 33

15 33

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16 33

15 33

15 33

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15 33

15 33

16 33

15 33

15 33

15 33

16 33

15 16 31

15 33

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15 16 31

15 16 31

16 33

15 33

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15 33

15 33

15 33

15 33

15 33

15 33

16

15 33

15 33

15 33

15 33

15 33

15 33

15 33

15 33

16

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TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM















PCIE REF CLOCKS

SATA

PCIE GRAPHICS

PCI-ExpressNET_TYPE

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

PCIE I/OSATA Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

MISC

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PCIE_MINI_R2D_L_NPCIEPCIE_90D

PCIE_MINI_R2D_C_NPCIE_90D PCIE

PCIE_MINI_R2D_L_PPCIEPCIE_90D

PCIEPCIE_90D PCIE_MINI_D2R_P

PCIE_90D PCIE PCIE_MINI_D2R_N

PCIE_90D PCIE_FW_R2D_PPCIE

PCIE_FW_R2D_NPCIEPCIE_90D

PCIE_FW_R2D_C_PPCIE_90D PCIE

PCIEPCIE_90D PCIE_FW_R2D_C_N

PCIE_90D PCIE PCIE_FW_D2R_P

PCIEPCIE_90D PCIE_FW_D2R_N

PCIE_90D PCIE PCIE_FW_D2R_C_P

PCIE PCIE_FW_D2R_C_NPCIE_90D

PCIEPCIE_90D PCIE_MINI_R2D_C_P

CLK_PCIE PCIE_CLK100M_FW_PCLK_PCIE_100D

CLK_PCIE_100D PCIE_CLK100M_FW_NCLK_PCIE

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CON_N

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CON_P

CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P

GPU_CLK100M_PCIE_NCLK_PCIE_100D CLK_PCIE

GPU_CLK100M_PCIE_PCLK_PCIECLK_PCIE_100D

MCP_SATA_TERMPSATA_TERMPMCP_50S

SATASATA_100D SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_NSATASATA_100D

SATASATA_100D SATA_ODD_D2R_NSATASATA_100D SATA_ODD_D2R_PSATASATA_100D SATA_ODD_R2D_N

SATA_100D SATA SATA_ODD_R2D_PSATA SATA_ODD_R2D_C_NSATA_100D

SATA SATA_ODD_R2D_C_PSATA_100D

SATA_100D SATA SATA_HDD_D2R_C_N

SATA_HDD_D2R_C_PSATA_100D SATA

SATA_HDD_D2R_NSATASATA_100D

SATA_HDD_D2R_PSATASATA_100D

SATA_HDD_R2D_NSATASATA_100D

SATA SATA_HDD_R2D_PSATA_100D

SATA SATA_HDD_R2D_C_NSATA_100D

SATA SATA_HDD_R2D_C_PSATA_100D

PCIE_90D MXM_PCIE_D2R_N<15..0>PCIE

PCIE_90D PCIE MXM_PCIE_D2R_P<15..0>

MCP_IFPAB_VPROBEMCP_50S MCP_PEX_COMP

MCP_IFPAB_RSETMCP_DV_COMP MCP_PEX_COMP

PCIE PCIE_MINI_R2D_NPCIE_90D

PCIE PCIE_MINI_R2D_PPCIE_90D

PCIE_90D PEG_D2R_N<15..0>PCIE

PCIEPCIE_90D PEG_R2D_C_N<15..0>

PCIEPCIE_90D PEG_D2R_P<15..0>

PCIE MXM_PCIE_R2D_P<15..0>PCIE_90D

PCIE MXM_PCIE_R2D_N<15..0>PCIE_90D

PCIE PEG_R2D_C_P<15..0>PCIE_90D

PM_SLP_S4_L

PM_SLP_S3_L

MCP_PEX_COMPMCP_50S MCP_PEX_CLK_COMP


MCP Constraints 1

=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFF

=4X_DIELECTRIC ?PCIE TOP,BOTTOMPCIE * ?=3X_DIELECTRIC

MCP_PEX_COMP ?0.2 MM*

CLK_PCIE * ?0.5 MM

=100_OHM_DIFF* =100_OHM_DIFFSATA_100D =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

0.2 MMSATA_TERMP ?*

=4x_DIELECTRIC*SATA ?

* =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFFPCIE_90D

?SATA TOP,BOTTOM =3x_DIELECTRIC

34

17 34

34

17 34

17 34

41

41

17 41

17 41

17 41

17 41

41

41

17 34

17 41

17 41

34

17 34

34

17 34

9 87

9 87

20

45 110

45 110

20 45

20 45

45 110

45 110

20 45

20 45

45 110

45 110

20 45

20 45

45 110

45 110

20 45

20 45

84 86

84 86

18 26

18 26

34

34

9 86

9 86

9 86

84 86

84 86

9 86

21 70

9 21

17

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PCI Bus Constraints

XTAL Constraints


SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints


HD Audio Interface Constraints




USB 2.0 Interface Constraints

NET_TYPE

PHYSICAL SPACING


SMBus Interface Constraints


LPC Bus Constraints

103 OF 110

051-7863

A.0.0


HDA_SDOUTHDAHDA_55S

AUD_SPDIF_INHDA

CLK_MCP_XTAL XTAL MCP_CLK25M_XTALIN

USB_IR_L_PUSBUSB_90D

USB_SDCARD_NUSB_90D USB

SPI_CLK_RSPIMCP_50S

USB_IR_NUSBUSB_90D

USBUSB_90D USB_BT_L_PUSB USB_BT_NUSB_90D

USB_BT_PUSBUSB_90D

USB_SDCARD_L_NUSBUSB_90D

USB_SDCARD_L_PUSB_90D USB

USB_SDCARD_PUSBUSB_90D

USB_IR_L_NUSB_90D USB

USB_D_MUXED_PUSBUSB_90D

USB_90D USB_PORT3_NUSB

USBUSB_90D USB_CAMERA_N

PCI_CLK33M_MCPCLK_PCI_55S CLK_PCI

PCI_CLK33M_MCP_RCLK_PCICLK_PCI_55S

PCI_REQ1_LPCIPCI_55S

LPC LPC_AD<3..0>LPC_55S

LPCLPC_55S LPC_AD_R<3..0>

LPC_FRAME_LLPC_55S LPC

USBUSB_90D USB_EXTA_P

USBUSB_90D USB_EXTA_N

USBUSB_90D USB_PORT0_P

USB_CAMERA_L_NUSBUSB_90D

USBUSB_90D USB_CAMERA_L_P

USB_90D USB USB_CAMERA_P

USB_EXTD_PUSBUSB_90D

USB_EXTD_NUSBUSB_90D

USB_D_MUXED_NUSBUSB_90D

USB_PORT3_PUSB_90D USB

USB_PORT1_NUSBUSB_90D

USB_PORT2_PUSBUSB_90D

USB USB_PORT1_PUSB_90D

USB USB_PORT0_NUSB_90D

USB_90D USB USB_EXTB_P

USB_90D USB_EXTC_NUSB

CLK_LPC_55S CLK_LPC PM_CLK32K_SUSCLK

LPC_55S LPC_FRAME_R_LLPC

LPC LPC_RESET_LLPC_55S

CLK_LPCCLK_LPC_55S LPC_CLK33M_SMC_R

MCP_USB_RBIAS_GNDMCP_USB_RBIAS

CLK_LPCCLK_LPC_55S PM_CLK32K_SUSCLK_R

CLK_LPC LPC_CLK33M_SMCCLK_LPC_55S

PCI_55S PCI_REQ0_LPCI

USB_EXTC_PUSB_90D USB

USB USB_PORT2_NUSB_90D

SPI_MISO_RMCP_50S SPI

USB_90D USB USB_EXTB_N

HDA HDA_RST_R_LHDA_55S

SPI_CS0_LSPIMCP_50S

HDA_55S HDA_SYNCHDA

HDA HDA_RST_LHDA_55S

HDA_55S HDA HDA_SDOUT_R

HDA_55S HDA_BIT_CLKHDA

SPIMCP_50S SPI_MISO

CLK_LPCCLK_LPC_55S LPC_CLK33M_LPCPLUS

USB_IR_PUSBUSB_90D

USBUSB_90D USB_BT_L_N

SPI_MOSISPIMCP_50S

SPI_MOSI_RSPIMCP_50S

SPI_CLKSPIMCP_50S

HDA_SDIN0HDAHDA_55S

MCP_HDA_COMP MCP_HDA_PULLDN_COMP

HDA_BIT_CLK_RHDA_55S HDA

AUD_SDI_RHDAHDA_55S

SPI_CS0_R_LSPIMCP_50S

HDA_SYNC_RHDA_55S HDA

AUD_SPDIF_OUTHDA

CLK_MCP_XTAL RTC_CLK32K_XTALOUTXTAL

HDA AUD_SPDIF_CHIP

CLK_MCP_XTAL XTAL RTC_CLK32K_XTALIN

XTALCLK_MCP_XTAL MCP_CLK25M_XTALOUT


MCP Constraints 2

=STANDARDCLK_PCI_55S =55_OHM_SE=55_OHM_SE* =STANDARD=55_OHM_SE=55_OHM_SE

=STANDARDPCI * ?

=55_OHM_SE =55_OHM_SECLK_LPC_55S * =STANDARD=55_OHM_SE =55_OHM_SE =STANDARD

0.15 MM* ?LPC

MCP_USB_RBIAS * =STANDARD=STANDARD =STANDARD =STANDARD0.2 MM 0.2 MM

CLK_MCP_XTAL =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFF

XTAL =4X_DIELECTRIC ?*

* ?0.2 MMSPI

=2x_DIELECTRICUSB ?*

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SEHDA_55S =STANDARD =STANDARD*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFFUSB_90D * =90_OHM_DIFF=90_OHM_DIFF

?*SMB =2x_DIELECTRIC

MCP_HDA_COMP * ?0.2 MM

?USB TOP,BOTTOM =4x_DIELECTRIC

CLK_LPC 0.2 MM ?*

?*HDA =2x_DIELECTRIC

=STANDARD*SMB_55S =55_OHM_SE=55_OHM_SE =STANDARD=55_OHM_SE =55_OHM_SE

=55_OHM_SELPC_55S =55_OHM_SE=55_OHM_SE* =55_OHM_SE =STANDARD =STANDARD

=STANDARD=STANDARD* =55_OHM_SE =55_OHM_SESPI_55S =55_OHM_SE =55_OHM_SE

=55_OHM_SEPCI_55S =STANDARD=STANDARD=55_OHM_SE=55_OHM_SE =55_OHM_SE*

0.2 MMCLK_PCI * ?

21 62

9 66

21 28

47 110

20 47

21 51 61

20 47

47 110

20 47

20 47

47 110

47 110

20 47

47 110

46

46

20 47

19

19

19

19 49 51

19

19 49 51

20 46

20 46

46

47 110

47 110

20 47

20 46

20 46

46

46

46

46

46

46

20 46

20 46

9 49

19

9 19

9 19

20

9 21

9 49

19

20 46

46

61

20 46

21

51

21 62

21 62

21

21 62

21 51 61

9 51

20 47

47 110

61

21 51 61

61

21 62

21

21

62

21 51

21

62 66

21 28

62

21 28

21 28

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NET_TYPE

SPACING

MCP RGMII (Ethernet) Constraints


SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

RTL8211CLGR (ETHERNET PHY) CONSTRAINTS

104 OF 110

051-7863

A.0.0


ENET_MDI ENET_MDI_T_N<3..0>ENET_MDI_100D

ENET_MDI_T_P<3..0>ENET_MDIENET_MDI_100D

ENET_MDI_N<3..0>ENET_MDI_100D ENET_MDI

ENET_MDI_P<3..0>ENET_MDI_100D ENET_MDI

MCP_MII_COMP MCP_MII_COMP_GND

ENET_MIIENET_MII_55S ENET_CLK125M_TXCLK

ENET_MII_55S ENET_MII ENET_TX_CTRLENET_MIIENET_MII_55S ENET_TXD<3..1>ENET_MIIENET_MII_55S ENET_TXD<0>

ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK_R

ENET_MII_55S ENET_MII ENET_MDC

ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0_R

ENET_MII_55S ENET_RXD_R<3..1>ENET_MII

MCP_MII_COMP_VDDMCP_MII_COMP

ENET_MIIENET_MII_55S ENET_RXD<0>

ENET_RXCTL_RENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S ENET_RX_CTRL

ENET_MII_55S ENET_RXD<3..1>ENET_MII

ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK

ENET_MII_55S MCP_BUF0_CLK RTL8211_CLK25M_CKXTAL1

ENET_MIIENET_MII_55S ENET_RXD_R<0>

ENET_MII_55S ENET_MII ENET_MDIO

Ethernet Constraints

FIT;


=STANDARDMCP_MII_COMP * =STANDARD=STANDARD=STANDARD 0.2 MM0.2 MM

ENET_MDI * ?0.6 MM

=100_OHM_DIFF*ENET_MDI_100D =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

ENET_MII * ?0.3 MM

=55_OHM_SE* =STANDARD=STANDARD=55_OHM_SE =55_OHM_SEENET_MII_55S =55_OHM_SE

MCP_BUF0_CLK ?* =3:1_SPACING

39

39

37 39

37 39

18

18 37

18 37

18 37

18 37

37

18 37

18 38

37

18

18 37

37

18 37

18 37

18 37

37 38

37

18 37

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FireWire Interface ConstraintsNET_TYPE

PHYSICAL

PORT 1 & 2 NOT USED

ELECTRICAL_CONSTRAINT_SET SPACING

FireWire Net Properties

105 OF 110

051-7863

A.0.0


FW_PORT0_TPA_PFW_TPFW_110D

FW_110D FW_TP FW_P0_TPB_L_P

FW_110D FW_TP FW_P0_TPA_L_P

FW_TPFW_110D FW_PORT0_TPA_N

FW_110D FW_PORT0_TPB_PFW_TP

FW_110D FW_TP FW_PORT0_TPB_N

FW_110D FW_TP FW_P0_TPB_L_N

FW_110D FW_TP FW_P0_TPA_L_N

FW_TP ?=3:1_SPACING*

=110_OHM_DIFF* =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFFFW_110D =110_OHM_DIFF =110_OHM_DIFF

FireWire ConstraintsSYNC_MASTER=K22 SYNC_DATE=09/02/2009

42 43

42

42

42 43

42 43

42 43

42

42

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SMBus Interface Constraints

SMC SMBus Net Properties

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

106 OF 110

051-7863

A.0.0


SMB_55S SMBUS_SMC_B_S0_SCLSMB

SMBUS_SMC_B_S0_SDASMBSMB_55S

SMBUS_SMC_BSA_SDASMBSMB_55S

SMBUS_MCP_0_CLKSMBSMB_55S

SMBUS_MCP_0_DATASMBSMB_55S

SMBUS_SMC_A_S3_SCLSMBSMB_55S

SMB_55S SMB SMBUS_SMC_MGMT_SDASMB_55S SMB SMBUS_SMC_MGMT_SCL

SMB_55S SMBUS_SMC_A_S3_SDASMB

SMB SMBUS_SMC_0_S0_SCLSMB_55S

SMB SMBUS_SMC_BSA_SCLSMB_55S

SMBUS_SMC_0_S0_SDASMBSMB_55S

SMB_55S SMB SMBUS_SMC_MGMT_SDASMB_55S SMBUS_SMC_MGMT_SCLSMB

SMC ConstraintsSYNC_MASTER=K22 SYNC_DATE=09/02/2009

=STANDARD*SMB_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE =STANDARD=55_OHM_SE

=2x_DIELECTRIC ?*SMB

52

52

52

13 21 52

13 21 52

52

52 106

52 106

52

52

52

52

52 106

52 106

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SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

ASSINGED IN CONT. MGR.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

PHYSICALDigital Video Signal Constraints

SPACING

NET_TYPE

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.


107 OF 110

051-7863

A.0.0


DP_100D DP_INT_AUXCH_PDISPLAYPORT

DP_100D DP_MUX_N<3..0>DISPLAYPORT

DP_MUX_AUXCH_PDP_100D DISPLAYPORT

DISPLAYPORTDP_100D DP_MUX_AUXCH_NDISPLAYPORTDP_100D DP_MUX_AUXCH_P

DP_INT_AUXCH_NDP_100D DISPLAYPORT

DP_MUX_AUXCH_NDP_100D DISPLAYPORT

MXM_DP_C_AUX_C_NDP_100D DISPLAYPORT

DP_INT_LINK_CONN_P<3..0>DP_100D DISPLAYPORT

DP_INT_LINK_CONN_N<3..0>DISPLAYPORTDP_100D

DP_100D DP_MUX_P<3..0>DISPLAYPORT

DP_INT_LINK_P<3..0>DP_100D DISPLAYPORT

DP_100D MXM_DP_A_ML_N<3..0>DISPLAYPORT

DP_100D DISPLAYPORT MXM_DP_A_ML_C_P<3..0>

DISPLAYPORTDP_100D MXM_DP_A_ML_C_N<3..0>

DISPLAYPORTDP_100D MXM_DP_A_ML_EQ_P<3..0>

MXM_DP_A_AUX_NDISPLAYPORTDP_100D

MXM_DP_A_AUX_C_PDISPLAYPORTDP_100D

MXM_DP_A_AUX_C_NDISPLAYPORTDP_100D

DP_100D DISPLAYPORT DP_ML_CONN_N<3..0>

DISPLAYPORTDP_100D MXM_DP_C_AUX_P

DISPLAYPORTDP_100D MXM_DP_C_ML_N<3..0>

DISPLAYPORTDP_100D MXM_DP_A_AUX_P

MXM_DP_A_ML_EQ_N<3..0>DP_100D DISPLAYPORT

DP_INT_LINK_N<3..0>DP_100D DISPLAYPORT

DISPLAYPORTDP_100D DP_EXT_AUXCH_N

MXM_DP_A_ML_P<3..0>DISPLAYPORTDP_100D

MXM_DP_C_AUX_C_PDISPLAYPORTDP_100D

MXM_DP_C_AUX_NDISPLAYPORTDP_100D

DP_100D DISPLAYPORT MXM_DP_C_ML_C_N<3..0>DISPLAYPORTDP_100D MXM_DP_C_ML_C_P<3..0>

DP_100D DISPLAYPORT MXM_DP_C_ML_P<3..0>

DISPLAYPORTDP_100D DP_ML_CONN_P<3..0>

DISPLAYPORTDP_100D DP_EXT_AUXCH_PDP_100D DP_EXT_LINK_C_N<3..0>DISPLAYPORT

DP_EXT_LINK_C_P<3..0>DISPLAYPORTDP_100D

DISPLAYPORTDP_100D DP_EXT_LINK_N<3..0>DISPLAYPORTDP_100D DP_EXT_LINK_P<3..0>

DISPLAYPORTDP_100D DP_TX_EQ_AUXCH_N

DP_100D DISPLAYPORT DP_EQLZ_AUXCH_P

DP_100D DISPLAYPORT DP_EQLZ_AUXCH_N

DISPLAYPORTDP_100D DP_TX_EQ_AUXCH_P

MCP_HDMI_VPROBEMCP_DV_COMP

MCP_DV_COMP MCP_HDMI_RSET

SYNC_DATE=N/ASYNC_MASTER=MASTER

Graphics Constraints

=100_OHM_DIFFDP_100D =100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF0.08MM

=3x_DIELECTRIC*DISPLAYPORT ?

DISPLAYPORT GND * GND_P2MM

PWR_P2MMPOWERDISPLAYPORT *

=4x_DIELECTRICTOP,BOTTOM ?DISPLAYPORT

*DISPLAYPORT * 3:1_SPACING

=STANDARD0.5 MMY 0.5 MM =STANDARD=STANDARD*MCP_DV_COMP

90 92

92 91

107 92 91

107 92 91

107 92 91

90 92

107 92 91

92

90

90

92 91

90 92

91 84

91

91

91

91 84

91

91

94

92 84

92 84

91 84

91

90 92

95 94 91

91 84

92

92 84

92

92

92 84

94

95 94 91

91

91

94 91

94 91

91

92

92

91

26 18

26 18

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TABLE_PHYSICAL_ASSIGNMENT_ITEM


PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD












OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
























K50/K51 SPECIFIC NET PROPERTIES


NET_TYPE

SPACING

108 OF 110

051-7863

A.0.0


THERMAL SENSE_1V5_S0_PTHERM_DIFF

THERMAL SENSE_1V5_S0_NTHERM_DIFF

PPDDR_MEM =PP1V5_S3_MEM_A

=PP1V5_S3_MEM_BPPDDR_MEM

SWITCHNODE VR_CPU_SW1


THERM_DIFF SNS_T_DP2_DN3THERMAL

SWITCHNODE 3V3S5_SW


5VS3_SWSWITCHNODE

THERMALTHERM_DIFF SNS_T_DN2_DP3

SNS_T_DN1_DP6THERMALTHERM_DIFF

THERM_DIFF THERMAL CPU_THERMD_NTHERMALTHERM_DIFF CPU_THERMD_P

SNS_T_DP1_DN6THERMALTHERM_DIFF

SWITCHNODE 1V8_SW

SWITCHNODE 1V1S5_SW

SWITCHNODE PVTTS0_PHASE

SWITCHNODE MCPCORES0_PHASE

THERM_DIFF MCP_THMDIODE_PTHERMAL

THERMAL SNS_T_DP4_DN5THERM_DIFF

THERMAL SNS_T_DN4_DP5THERM_DIFF

SNS_LCD_PTHERMALTHERM_DIFF

THERM_DIFF MXM_PWRSRC_SENSOR_PTHERMAL

THERM_DIFF MCP_THMDIODE_NTHERMAL

THERMAL VR_CPU_ISNS1_R_PSNS_DIFF

VR_CPU_ISNS1_R_NSNS_DIFF THERMAL

SNS_ODD_NTHERMALTHERM_DIFF

THERMAL SNS_LCD_NTHERM_DIFF

THERMALTHERM_DIFF SNS_CPU_H_NTHERMAL SNS_CPU_H_PTHERM_DIFF

THERMAL SNS_ODD_PTHERM_DIFF

VR_CPU_ISNS2_R_PTHERMALSNS_DIFF

VR_ISNS_CPU_NTHERMAL

CPU_VCC_SENSETHERMAL

SMC_GPU_VSENSETHERMAL

SMC_CPU_VSENSETHERMAL

VR_CPU_ISNS1_NSNS_DIFF THERMAL

VR_CPU_ISNS1_PSNS_DIFF THERMAL

SMC_1V5_S0_ISENSE_RTHERMAL

SMC_GPU_ISENSETHERMAL

THERMALSNS_DIFF VR_CPU_ISNS3_R_N

SMB_PECI_LTHERMAL

THERM_DIFF MXM_PWRSRC_SENSOR_NTHERMAL

THERM_DIFF SNS_MXM_NTHERMAL

SNS_MXM_PTHERMALTHERM_DIFF

SNS_AMB_NTHERM_DIFF THERMAL

THERM_DIFF THERMAL SNS_AMB_P

SNS_MCP_NTHERMALTHERM_DIFF

SNS_MCP_PTHERMALTHERM_DIFF

SMC_1V5_S0_ISENSETHERMAL

HDD_OOB_TEMP_FILTTHERMAL

HDD_OOB_TEMPTHERMAL

HDD_OOB_TEMP_RTHERMAL

VR_CPU_IOUTTHERMAL

SMC_CPU_ISENSETHERMAL

VR_CPU_ISNS2_R_NTHERMALSNS_DIFF

THERMALSNS_DIFF VR_CPU_ISNS3_R_P

VR_CPU_ISNS3_NTHERMALSNS_DIFF

VR_CPU_ISNS3_PTHERMALSNS_DIFF

VR_CPU_ISNS2_NTHERMALSNS_DIFF

VR_CPU_ISNS2_PTHERMALSNS_DIFF

SMC_HDD_OOB_TEMPTHERMAL

CPU_PECI_MCPTHERMAL

SMC_1V5_S0_VSENSETHERMAL

THERMAL SNS_PS_CPU_ISNS

CPU_PECI_LTHERMAL

VR_ISNS_CPU_PTHERMAL

THERMAL SMC_MCP_CORE_ISENSE

SMC_MCP_CORE_VSENSETHERMAL

THERMAL MCPCORES0_IMON

AUDIOAUDIO * *

SWITCHNODE**SWITCHNODE

THERMAL *GND GND_P2MM

THERMAL ** 4:1_SPACING

THERMAL PWR * PWR_P2MM

CLK_PCIE PWR * PWR_P2MM

K22/K23 SPECIFIC CONSTRAINTSSYNC_MASTER=K22 SYNC_DATE=09/02/2009

GND_P2MMSATA GND *

GNDCLK_PCIE * GND_P2MM

PPDDR_MEMMEM_DQS PWR_P2MM*

MEM_CTRL GND_P2MM*GND

MEM_CLK *PPDDR_MEM PWR_P2MM

GND_P2MM*GNDMEM_CMD

PWR_P2MM 10000.20 MM*

GND_P2MM 0.20 MM 1000*

MEM_CTRL * PWR_P2MMPPDDR_MEM

GND_P2MM*USB GND

GNDPCIE * GND_P2MM

PWR_P2MM*MEM_DATA PPDDR_MEM

PPDDR_MEM *MEM_CMD PWR_P2MM

GND *MEM_DQS GND_P2MM

=STANDARD ?*GND

1:1_DIFFPAIR*THERM_DIFF

* 1:1_DIFFPAIRSNS_DIFF

=STANDARD*PPDDR_MEM ?

GND *FSB_DSTB GND_P2MM

*CPU_VCCSENSE GND_P2MMGND

*GNDMEM_CLK GND_P2MM

*GNDMEM_DATA GND_P2MM

CPU_GTLREF GND * GND_P2MM

GNDCPU_COMP * GND_P2MM

GND GND_P2MM*CLK_FSB

PCIE_90D 500 MILTOP

USB_90D TOP 500 MIL

MEM_40S_VDD 0.1 MM 600 MILTOP

0.1 MMMEM_40S TOP 600 MIL

MEM_70D 600 MIL0.1 MMTOP

MCP_DV_COMP 250 MIL* 0.25 MM

MCP_DV_COMP 0.1 MMTOP 500 MIL

CPU_27P4S BOTTOM 100 MIL0.23 MM

MCP_USB_RBIAS TOP 0.1 MM 500 MIL

MCP_MII_COMP 500 MIL0.1 MMTOP

TOP 500 MILMCP_MEM_COMP 0.1 MM

I230

I229

I228

I227

I226

I225

I224

I223

I222

I221

I220

I219

I218

I217

I216

I215

I214

I213

I212

I211

I210

54

54

6 30 31

6 30 32

72

72

55

76

72

73

55

55

11 55

11 55

55

80

79

76

74

21 55

55

55

55 110

53

21 55

71

71

55 110

55 110

55

55

55 110

71

53

12 53

49 53

49 53

71 72

71 72

54

49 53

71

55

53

55

55

55 110

55 110

55

55

50 54

55

55

55

53 71

49 53

71

71

71 72

71 72

71 72

71 72

55

14 55

50 54

53

11 55

53

50 54

50 54

54 74

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PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD










TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

















CONSTRAINTS ARE BASED ON MCP79 DESIGN GUIDE DG-03328-001_V06PCI,LPC,SMB,HDA,SPI,RGMII,SMBUS ARE ROUTED AS 55 OHM SE SIGNALS

PHYSICAL CONSTRAINTS

CONSTRAINTS FOR BGA AREA

SPACING RULE SET

K50/K51 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

109 OF 110

051-7863

A.0.0


=STANDARD* N =STANDARD =STANDARD=STANDARD =STANDARD100_OHM_DIFF

0.085 MM100_OHM_DIFF Y 0.25 MM=STANDARD 0.1 MM0.081 MMISL3,ISL6

0.25 MM0.091 MM 0.085 MM 0.1 MMY =STANDARD100_OHM_DIFF TOP,BOTTOM

=STANDARD =STANDARD =STANDARDN =STANDARD110_OHM_DIFF * =STANDARD

0.085 MM=STANDARD 0.1 MMY*1:1_DIFFPAIR =STANDARD =STANDARD

=STANDARD=STANDARD3.0 MM0.600 MM 0.200 MMPOWER_WIDTH Y*

0.320 MM0.075 MMY 0.15 MM110_OHM_DIFF =STANDARDTOP,BOTTOM 0.085 MM

0.085 MMISL3,ISL6 Y 0.1 MM90_OHM_DIFF 0.200 MM12 MM0.099 MM

0.130 MM0.085 MM0.165 MM70_OHM_DIFF TOP,BOTTOM 0.1 MM=STANDARDY

*90_OHM_DIFF =STANDARD =STANDARD =STANDARD=STANDARDN =STANDARD

BGA_P1MM* BGA_P2MMMCP_PEX_COMP

0.085 MMTOP,BOTTOM =STANDARDY55_OHM_SE 0.085 MM

=STANDARD0.085 MM*27P4_OHM_SE Y =STANDARD=STANDARD0.275 MM

BGA_P1MMBGA_P1MM*CLK_LPC

=STANDARD =STANDARD70_OHM_DIFF * N =STANDARD =STANDARD=STANDARD

0.165 MM 0.085 MM40_OHM_SE YTOP,BOTTOM =STANDARD

BGA_P1MM* BGA_P2MMMCP_MEM_COMP

BGA_P1MM*MCP_FSB_COMP BGA_P2MM

BGA_P1MMCLK_PCI * BGA_P1MM

FSB_DSTB BGA_P1MMFSB_DSTB BGA_P1MM

BGA_P2MMCLK_FSB * BGA_P1MM

BGA_P2MMMEM_CLK * BGA_P1MM

BGA_P1MMCLK_PCIE * BGA_P1MM

BGA_P1MM* * BGA_P1MM

0.2 MM*BGA_P2MM ?

BGA_P1MM * ?=DEFAULT

1000* 0.2 MMPWR_P2MM

0.6 MM* ?CLK_SPACING_0.6MM

5X_DIELECTRIC ?* 0.380 MM

TOP,BOTTOM ?5X_DIELECTRIC 0.400 MM

4X_DIELECTRIC ?TOP,BOTTOM 0.320 MM

15 MM0.1 MM 0.085 MMY50_OHM_SE TOP,BOTTOM

=STANDARD* 0.085 MM50_OHM_SE =STANDARD=STANDARDY 0.1 MM

42_OHM_SE 0.136 MM =STANDARD0.085 MM =STANDARDY =STANDARD*

=STANDARD0.15 MM 0.085 MM =STANDARDY =STANDARD*40_OHM_SE

0.300 MM =STANDARDY27P4_OHM_SE TOP,BOTTOM 0.085 MM

3X_DIELECTRIC ?TOP,BOTTOM 0.240 MM

4X_DIELECTRIC 0.300 MM* ?

0.5 MMCLK_SPACING_0.5MM ?*

0.6 MM 1000*SWITCHNODE

0.151 MM 0.085 MMYTOP,BOTTOM =STANDARD42_OHM_SE

0.076 MM =STANDARD0.075 MM55_OHM_SE * =STANDARDY =STANDARD

0.200 MM0.110 MM 0.1 MMTOP,BOTTOM 0.085 MMY =STANDARD90_OHM_DIFF


K22/K23 RULE DEFINITIONS

* POWER_WIDTHVR_CTL_PHY

* POWER_WIDTHPOWER

0.085 MM70_OHM_DIFF ISL3,ISL6 =STANDARD 0.1 MMY 0.135 MM0.155 MM

0.3 MMBGA_P3MM * ?

1000GND_P2MM 0.2 MM*

STANDARD * =DEFAULT ?

DEFAULT ?0.1 MM*

15.5.1NO_TYPE,BGA_P1MM MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM

* ?2X_DIELECTRIC 0.150 MM

?TOP,BOTTOM 0.160 MM2X_DIELECTRIC

?*3X_DIELECTRIC 0.220 MM

*1.5:1_SPACING 0.15 MM ?

2:1_SPACING 0.2 MM* ?

?0.25 MM2.5:1_SPACING *

0.3 MM3:1_SPACING * ?

*4:1_SPACING 0.4 MM ?

=DEFAULTY* 12.7 MMSTANDARD =DEFAULT=DEFAULT =DEFAULT

0 MMDEFAULT =50_OHM_SE 0 MM* Y =50_OHM_SE 100 MM

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IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN




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1 PP5V_S3_REG Testpoint near J4700

2 Ground Testpoints near J4700

J4750 USB CARD READER


FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

1 PP3V3_S3 Testpoint near J4750

1 PP3V3_S3 Testpoint near J4720

J4700 USB CAMERA


J4720 USB BLUETOOTHJ5551 ODD TEMP SENSOR

J5700 CPU FAN

J5600 ODD FAN

J5601 HD FAN


1 PP5V_S3_REG Testpoint near J4780

J4780 IR BOARD

J4520 SATA ODD (HIGH SPEED)


1 PP5V_S0 Testpoint near J4520

J4510 SATA HDD (HIGH SPEED)


J6601 AUDIO MICROPHONE

1 Ground Testpoint near J6601

J5520 ANALOG LCD TEMP SENSOR

J5521 AMBIENT TEMP SENSOR J6602 AUDIO RIGHT SPEAKER

J6603 AUDIO LEFT SPEAKER

2 TP’S

16 TP’S

2 TP’S

110 OF 110

051-7863

A.0.0


USB_BT_L_P FUNC_TEST=TRUE

FUNC_TEST=TRUEFAN_0_GND

USB_BT_L_N FUNC_TEST=TRUE

FUNC_TEST=TRUEUSB_SDCARD_L_P

FUNC_TEST=TRUEUSB_SDCARD_L_N

USB_CAMERA_L_P FUNC_TEST=TRUE

USB_CAMERA_L_N FUNC_TEST=TRUE SNS_LCD_N FUNC_TEST=TRUE

SNS_AMB_P FUNC_TEST=TRUE

SNS_AMB_N FUNC_TEST=TRUE

SNS_ODD_P FUNC_TEST=TRUE

SNS_ODD_N FUNC_TEST=TRUE

FAN_0_PWR_L FUNC_TEST=TRUE

PP12V_S0_FAN0_L FUNC_TEST=TRUE

FUNC_TEST=TRUEFAN_2_PWR_L

FUNC_TEST=TRUEFAN_TACH2_L

PP12V_S0_FAN2_L FUNC_TEST=TRUE

FUNC_TEST=TRUEFAN_2_GND

FUNC_TEST=TRUEFAN_TACH1_LFUNC_TEST=TRUEFAN_1_PWR_L

FUNC_TEST=TRUEFAN_1_GNDFUNC_TEST=TRUEPP12V_S0_FAN1_L

FUNC_TEST=TRUEUSB_IR_L_P

FUNC_TEST=TRUEUSB_IR_L_N

FUNC_TEST=TRUESATA_ODD_R2D_P

FUNC_TEST=TRUESATA_ODD_R2D_N

FUNC_TEST=TRUESATA_ODD_D2R_C_N

FUNC_TEST=TRUESATA_ODD_D2R_C_P

FUNC_TEST=TRUESMC_ODD_DETECT

SATA_HDD_R2D_P FUNC_TEST=TRUE

SATA_HDD_R2D_N FUNC_TEST=TRUE

SATA_HDD_D2R_C_N FUNC_TEST=TRUE

SATA_HDD_D2R_C_P FUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_MIC_IN1_N_CONN

FUNC_TEST=TRUEGND_AUDIO_MIC1_CONN

FUNC_TEST=TRUEAUD_MIC_IN1_P_CONN

SNS_LCD_P FUNC_TEST=TRUE

FUNC_TEST=TRUEAUD_SPKR_OUTLO1L_NFUNC_TEST=TRUEAUD_SPKR_OUTLO1L_PFUNC_TEST=TRUEAUD_SPKR_OUTLO2L_NFUNC_TEST=TRUEAUD_SPKR_OUTLO2L_P

FUNC_TEST=TRUEAUD_SPKR_OUTLO2R_NFUNC_TEST=TRUEAUD_SPKR_OUTLO2R_P

FUNC_TEST=TRUEAUD_SPKR_OUTLO1R_NFUNC_TEST=TRUEAUD_SPKR_OUTLO1R_P

FUNC_TEST=TRUEFAN_TACH0_L

MIN_ALLOWED_TPS=2FUNC_TEST=TRUEPP5V_S3_REG

MIN_ALLOWED_TPS=2FUNC_TEST=TRUEPP3V3_S3

PP5V_S0 FUNC_TEST=TRUEMIN_ALLOWED_TPS=1

GND FUNC_TEST=TRUEMIN_ALLOWED_TPS=16

K22/K23 ICT/FCTSYNC_MASTER=K22 SYNC_DATE=09/02/2009

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45 102

45 102

45 102

6 78

45 49

45 102

45 102

45 102

45 102

55 108

55 108

55 108

55 108

55 108

55 108

47 103

47 103

6 73

6 78

56

56

56

56

57

57

57

57

56

56

56

56

47 103

47 103

47 103

47 103

47 103

47 103

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APPle imac 27 #039 A1312 K23 051-7863-A cpu test & misc. 11 09/02/2009 k22 11 cpu power, gnd, decaps...

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Transcript of APPle imac 27 #039 A1312 K23 051-7863-A cpu test & misc. 11 09/02/2009 k22 11 cpu power, gnd, decaps...