APPENDIX A GROUP EMBEDDED FIGURE TEST -...
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141 APPENDIX A GROUP EMBEDDED FIGURE TEST
Transcript of APPENDIX A GROUP EMBEDDED FIGURE TEST -...
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APPENDIX A
GROUP EMBEDDED FIGURE TEST
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APPENDIX B
ATTITUDE SCALE FORM TO MEASURE ATTITUDE OF STUDENTS TO PEDAGOGY
___________________________________________________________
Note: 1. please mention your group (Traditional or PBL), however, you may choose not
to mention your name
1. Give your response to each of these questions in the questionnaire on a scale of 1
to 10, with 1 being the most negative
Q. No.
Survey Questions Your response (1 to 10)
1
What was your satisfaction level with the tutor of Analog Electronics?
2 How confident are you that you would be able to extrapolate the theoretical concepts and analytical skills learnt in AE to other subjects in higher classes?
3 On average how much of the class time did you use effectively?
4 Are you confident of performing well in the external exams? 5 Did you copy the assignments? (on a scale of 1 to 5) 6 Did you enjoy attending the classes? 7 Rate your practical skills in analog electronics (Assembling
the circuits, wiring, troubleshooting etc.)
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APPENDIX C
ASSIGNMENT CUM TUTORIAL SHEETS FOR ANALOG ELECTRONICS
_____________________________________________________________ Assignment cum Tutorial Sheet (ATS) - 1
Topic: Large Signal Amplifiers
1. Why power amplifiers are called large signal amplifiers?
2. For the circuit of following figure, calculate the input power, output power and
power handled by each output transistor and the circuit efficiency for an input of
12V rms
3. What do you understand by power dissipation capacity of a power transistor? Take 4
samples of power transistors available in the lab and find out their power dissipation
capacity for the specification sheets.
4. Does the transistor used in class-A amplifier get heated up in presence of a signal?
Why?
5. Why do we use transformer in the output stage of a transformer coupled amplifier?
6. For harmonic distortion reading of D2 = 0.1, D3 = 0.02 and D4 = 0.001, with I1 = 4A
and RC = 8Ω, calculate the total harmonic distortion, fundamental power component,
and total power.
7. Draw a table showing comparative statement of power amplifiers as per the format
given below:
C1
R1
VCC
25V
Q1
Q2C2
D1
R3
R2
RL4 ohm
V1
VEE
-25V
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Class of operation
Operating point located at ___ on the characteristics of transistor
Maximum efficiency
Harmonic distortion
Expression of output power
8. Draw a flow chart showing the distribution of input power in a power amplifier.
9. Under what conditions would the dc load line in a transformer-coupled amplifier not
be drawn vertically on the collector characteristics? Which way would it slope?
10. What principle factor contributes to the doubling of the conversion efficiency in a
transformer coupled load amplifier compared to a direct-coupled resistive load
amplifier?
11. What is cross over distortion? How can it be minimized?
12. What advantage does a phase inverter circuit have over a transformer phase splitter?
13. Determine the turns ratio of the transformer needed to couple an 8Ω load so that it
appears as an 8kΩ effective load?
14. (a) Calculate the input and output power for the given circuit. The input signal
results in a base current of 5mA rms.
(b) Calculate the input power dissipated by this circuit, if RB is changed to 1.5 kΩ
(c) What maximum output power can be delivered by the circuit, if RB is changed to
1.5kΩ
(d) If the transistor is biased at its center voltage and center collector operating
point, what is the input power for a maximum output power of 1.5W
Q1
beta=40
C1
100uF
Rb1.2 Kohm
VCC 18V
V1
Rc16 Ohm
Vo
15. Draw the schematic of following figure on MULTISM. Simulate the circuit using a
10mV pp sinusoidal input voltage.
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C1
R1
VCC
30V
Q1
Q2C2
D1
R2
RL8 Ohm
V1
Vee
-30V
VL
R350%
16. What is the average dissipation of a transistor in a class-B push-pull amplifier?
17. Explain the functioning of a class-AB push-pull amplifier, using circuit schematic,
theory of operation, input and output voltage and current waveforms. Derive the
expression for the efficiency of such amplifier.
18. Design a power amplifier using germanium 2N176 transistor with PT of 10W. The
power required at load is 3W. Assume an output transformer efficiency of 75%, Re
= 5Ω, Vcc = 20V, and a base emitter bias voltage of 0.4V. Use the stability factor, S
= 10. Specify
a) The primary impedance of transformer
b) The operating point
c) The values of R1 and R2
19. A 160W silicon power transistor operated with a heat sink (θSA = 1.5C/W) has θJC
= 0.5C/W and a mounting insulation of θCS = 0.8C/W. What maximum power can
be handled by the transistor at an ambient temperature of 80C? (The junction
temperature should not exceed 200C.)
20. For the power amplifier of following figure, calculate:
(a) Po(ac) (b) Pi(dc) (c) %η and
(d) Power dissipated by both output transistors
150
C1
100uF
R1100 Ohm
VCC
40V
Q1
Q2C2
100uF
D1
R3100 Ohm
R2100 Ohm
RL8 Ohm
V118V rms
Vee
-40V
VL
21. How is transformer saturation avoided in class-AB push-pull operation?
22. A transistor’s maximum average dissipation capability, PT, is 2.5W. When used in
class-A direct coupled operation, determine:
a) Maximum ac power deliverable to the load.
b) The minimum dc power needed from the supply.
c) The dc power dissipated in load and in transistor, with no input condition and
with input condition.
23. The conversion efficiency of a class-B push-pull amplifier is being determined
experimentally. An output meter on the secondary of the output transformer
indicates 5W. The transformer is known to be 70% efficient. An oscilloscope
connected across a 0.6Ω resistor in series with the power supply shows a full wave
rectified waveform of peak value 380mV. If Vcc = 24V determine the conversion
efficiency of the amplifier.
24. Explain the following terms in connection with power amplifier
a) Collector circuit Efficiency.
b) Collector dissipation rating.
c) Class-A, B, C operation.
d) Harmonic Distortion.
25. Discuss five-point method of computing harmonic distortion.
26. A single transistor working in class-A amplifier with transformer coupled load
produces the harmonic amplitudes in the output of A0 = 1.5mA, A1 = 120mA, A2 =
10mA, A3 = 4mA, A4 = 2mA, A5 = 1mA
a) Determine the percent total harmonic distortion.
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b) Assume that a second identical transistor is used along with a suitable
transformer to provide push-pull operation. Use the above amplitudes to
determine the new total harmonic distortion in the output.
27. A class-B push-pull amplifier is supplied with Vcc = 40V. The signal swings the
collector voltage down to Vmin = 8V. The dissipation in both transistors total 38W.
Determine the
a) Total power input.
b) Total power developed across the load.
c) Power rating of each transistor.
d) Overall efficiency.
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Assignment cum Tutorial Sheet (ATS) - 2 Topic: High Frequency analysis of transistor
1. The following low frequency parameters are known for a given transistor at Ic =
10mA, VCE = 10V, and at room temperature
hie = 500Ω hoe = 10-5 A/V hfe = 100 hre = 10-4
At the same operating point fT = 50MHz and cob = 3pf. Compute the values of all the
hybrid –π parameters.
2. Redraw the CE hybrid–π equivalent circuit with the base as the common terminal and
the output terminals - collector and base short circuited. Taking account of typical
values of the transistor parameters, show that Cc, rb’c and rce may be neglected.
3. The hybrid –π parameters of the transistor used in the circuit shown in the following
figure, are given as
Gm=50mA/V rbb’ = 100Ω rb’e = 1K rb’c = 4M
Rce = 80K Cc =3pf Ce = 100pf
Using Miller’s theorem and the approximate analysis, compute
A) The upper 3db frequency of the current gain AI = IL/Ii
B) The magnitude of the voltage gain AVs = Vo/Vs at the frequency of part A
Q1900 ohm
VCC
Vs
Rc1 Kohm
Vo
4. Describe various factors affecting the bandwidth of R-C coupled amplifier.
5. The output of single stage CE amplifier is out of phase with respect to the input
signal. Prove, graphically and analytically.
6. Explain how device capacitances play dominant role in CE amplifier in high
frequency region?
7. Consider a single a stage CE transistor amplifier with the load resistor RL shunted by
the capacitance CL.
a. prove that the internal voltage gain K=Vce/Vb’e is
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K = -gmRL/(1+jω(Cc+CL)RL)
b. Prove that the 3 dB frequency is given by
fH = 1/(2π(Cc+CL)RL
Provided following condition is satisfied:
Gb’eRL(Cc+CL)>>Ce+Cc(1+gmRL)
8. What is the effect of unbypassed emitter resistance on the input resistance of
amplifier? Use appropriate mathematical derivations and expressions to highlight the
effect.
9. Draw the frequency response of a two stage RC-Coupled amplifier. Define cut off
frequencies.
10. Describe the factors affecting the bandwidth of RC-Coupled amplifier.
11. What is alpha cut-off and beta cut off frequencies?
12. “In a multistage voltage amplifier, input impedance of an amplifier stage should be
very high, and output impedance must be very low” justify this statement.
13. Why is it not possible to use h-parameters at high frequencies?
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Assignment cum Tutorial Sheet (ATS) - 3
Topic: Multistage Amplifiers and Feed back in Amplifiers
1. Determine the lower cut off frequency for the network of following figure:
Q1Cs
R1
VCC
Vs
Rc
ReR2
Cz
RsVo
+
-
Take following values for the circuit elements:
Cs = 10µf, CE = 20µf, Cc = 1µf, RS = 1kΩ, R1 = 40kΩ, R2 = 10kΩ, RE = 2kΩ, RC =
4kΩ, RL = 2.2kΩ
Β = 100, ro = ∞, VCC = 20V
Sketch the frequency response using Bode plot.
2. For the amplifier with a bypassed emitter resistor as shown in the AE-ATS 3-Fig (a),
derive the expression for output voltage VO, Voltage Gain (AV), Mid Band gain Ao,
the zero and the pole for the ratio AV/AO
3. The bandwidth of an amplifier extends from 20Hz to 20kHz. Find the frequency
range over which the voltage gain is down less by 1db from its mid band value.
Assume that the low and high frequency response is given by
Vo(s) = Vi(s)R1/(R1+1/sC1) = sVi(s)/(s+1/R1C1)
AL (jf) = 1/[1-j(fL/f)], where fL = 1/2π R1C1
|AL(jf)| = 1/√[1+(fL/f)2] and θL = arctan fL/f
4. (a) For the transistor CE stage shown, with 1/hoe ≈ ∞, calculate the percentage tilt in
the output if the input current I is a 100Hz square wave.
(b) What is the lowest frequency square wave which suffers less than 1 percentage
tilt?
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Q1
VCC
3 Kohm
Vo
I
CL
10uF-POL
2 Kohm
5. The parameters of a transistors in the circuit shown are hfe = 50, hie = 1.1K, hre = hoe
= 0. Find
(a) The mid band gain,
(b) The value of Cb necessary to give a lower 3db frequency of 20Hz. Assume that
Cz represents a short circuit at this frequency,
(c) Find the value of Cb necessary to ensure less than 10 percent tilt for a 100Hz
square wave input.
Q1
50 Kohm
VCC
Vi
2 Kohm
2 Kohm50 Kohm
Ce
Cb
50 Kohm
50 Kohm 2 Kohm
2 Kohm
Q2
Cz
Vo
+
-
6. When negative feedback is applied in a voltage amplifier, what happens to its:
a) Voltage gain
b) Bandwidth
c) Harmonic Distortion
d) Stability
Prove your answers analytically.
7. Following are the given parameters of an amplifier: A = 10000, β = 0.03, input
impedance = 2kΩ, output impedance = 20kΩ. Determine the input and output
impedance of an amplifier with feedback.
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8. An amplifier has gain of 60db and output impedance of 12kΩ. It is required to
modify its output impedance to 500Ω by applying negative feedback. Determine the
value of feedback factor.
9. For the following circuits
Vo
+
VsR
Q1
VDD
-
-VCC
Rc
Vo
+
Re
Rb
------>Ii
Vs
-
Q1
a) Identify the feedback type
b) Derive an expression for voltage gain with feedback and the input resistance with
feedback.
10. With the negative feedback, an amplifier gives an output of 10V with an input of
0.5V. When the feedback is removed it requires 2.5V input for the same output.
Calculate gain without feedback and feedback fraction β.
11. Draw a table showing comparative statement of various types of negative feedback
under following heads:
Type of feedback
Feedback signal (xf)
Sampled Signal (xo)
Feedback factor (β)
Gain (A)
Desensitivity (D)
Gain with feedback (Af)
Input resistance with feedback (Rif)
Output Resistance with feedback (Rof)
12. An amplifier with input impedance of 2kΩ has a voltage gain of 1000. If a negative
feedback of β = 0.01 is applied to it, what shall be the input impedance of feedback
amplifier?
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13. A common emitter amplifier with collector feedback has the following
parameters: Re = 4kΩ, R’ = 40kΩ, Rs = 10kΩ and hie = 1.1K, hfe = 50 and hre = hoe
= 0. Find (a) Avf, (b) R if and (c) R’of
VCC
Rc
Vo
+
Rs
------>Ii
Vs
-
Q1R'
Vi
+
-
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Assignment cum Tutorial Sheet (ATS) - 4 Topic: Oscillators and Regulated Power Supplies
1. For the feedback network shown find (a) transfer function, (b) input impedance. If
this network is used in phase-shift oscillator, find the frequency of oscillation and the
minimum amplifier gain. Assume that the network does not load down the amplifier.
R
C
R R
C C
Vf +
-
Vo
+
-
2. For the Wein Bridge oscillator shown,
U1R1
R
C1
C
R2R
C2C
R3
300 KohmR4100 Kohm
VCC
+15V
VEE
-15V
OUTPUT
find the frequency of oscillation. What changes in the values of RC are required, if
the frequency of oscillation is to be changed to 10kHz?
3. In the following circuit,
LM358
VCC
12V
VEE
-12V
C1
1.0nF
C2
1.0nF
C3
1.0nF
R1
20 Kohm
R2
20 Kohm
R3
20 Kohm
OUTPUT
R4560 Kohm
1 Mohm
1 Mohm
D1
D2
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Show how the Barkausen criterion of sustained oscillations is being met. Also
calculate the frequency of oscillation. Simulate the circuit on MULTISIM™ and
attach the plots obtained.
4. Draw the circuit diagrams of (a) series operated and (b) shunt excited crystal
oscillators. Derive their formulae of frequency of oscillation
5. You must have designed and tested many positive feedback circuits (used for
producing oscillations) in the lab. Have you ever wondered why the dc output of the
power supply being used to supply voltage to the CUT (Circuit Under Test) has
overriding oscillations (though of small amplitude) when viewed on the oscilloscope.
What should be done to remove those oscillations?
6. What factors determine the maximum frequency of oscillations of a transistor?
7. Compare the three power supply regulator circuits on their power supply regulation,
current limiting and foldback limiting capabilities. Q1
Beta=50R1220 Ohm
RL
D112 V
Vin
+20V(Unregulated)
Vout
Q1Beta=50
R1220 Ohm
R220 Kohm
D1
8.3 V
J1
+20V(Unregulated)
Vou
R330 Kohm
R4
Q2
Beta=50
Q1Beta=50
R3R1
Vz
J1
+20V(Unregulated)
Vout
R2R5
Q2U1
R4
RL
Rsc
8. Determine the maximum value of load current at which regulation is maintained for
the circuit of:
transformerVm=12VMains
D1 D2
D3 D4
C1200uF
U1LM7805
LINE VREG
COMMON
VOLTAGE
C20.01uF
Vout
+5V
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APPENDIX D
MID SEMESTER TEST PAPERS FOR
ANALOG ELECTRONICS _____________________________________________________________
MID SEMESTER EXAMINATION - I
Max. Time Allowed: 90 min. Max. Marks: 24 _______________________________________________________________________
SECTION – A
(All FOUR Questions are Compulsory; each carries 2 marks) 1. What is cross over distortion in class-A push-pull amplifier? How can it be
minimized?
2. Distinguish between fα and fβ, fhfb and fhfe; fT and fα.
3. Out of the three cascaded stages in a multistage amplifier, the last one has the least
value of f2. Why?
4. State two equations that can be used to calculate the output power of an amplifier.
Under what condition will they give the same result?
SECTION – B
(Attempt any two Questions; each carries 4 marks)
5. A class-B push-pull amplifier is supplied with Vcc = 40 V. The signal swings the
collector voltage down to V min = 8V. The dissipation in both transistors total 38W.
Determine the (a) Total power input, (b) Total power developed across the load, (c)
Power rating of each transistor, (d) Overall efficiency.
6. For the network of given figure:
(a) Determine re,
(b) Find Avmid = Vo/Vi,
(c) Find Avsmid = Vo/Vs,
(d) Determine fLs, fLc, and fLE,
Stage 1 Stage 2 Stage 3
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(e) Determine the low cut off frequency,
(f) Sketch the asymptodes of the Bode Plot defined by the cutoff frequencies of
part (e),
(g) Sketch the low frequency response for the amplifier using the results of part (f).
Q1
beta=120
C1
0.47uF
Rb68 Kohm
VCC
14V
V1
Rc5.6 Kohm
R110 Kohm R2
1.2 Kohm
C2
0.47uF
C320uF
R33.3 Kohm
R4820 Ohm
Vo
7. A single stage CE amplifier is measured to have a voltage gain bandwidth fH of
5MHz with RL = 500 Ω. Assume hfe = 100, gm = 100mA/V, rbb’ = 100Ω, Cc = 1pf
and fT = 400 MHz.
a) Find the value of the source resistance that will give the required bandwidth
b) With the value of Rs found in part a, find the midband voltage gain Vo/Vs
SECTION-C
(Attempt any one Question; each carries 8 marks)
8. Explain the following term in connection with power amplifiers
a) Collector Circuit Efficiency
b) Collector dissipation rating
c) Class-A, B, C operation with particular reference to biasing point
d) Harmonic Distortion
9. Derive the following hybrid-π conductances in terms of low frequency h–
parameters.
a) Transistor conductance
b) Input conductance
c) Feedback conductance
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MID SEMESTER EXAMINATION - II
Max. Time Allowed: 90 min. Max. Marks: 24 _______________________________________________________________________
SECTION – A (All FOUR Questions are Compulsory; each carries 2 marks)
1. State qualitative reason of increase in Bandwidth of an amplifier with negative
feedback. No maths please.
2. You are given three wired circuits (on bread board) as oscillators, using discrete
components. One of them is Hartley Oscillator, the second one is Colpitts and the
third one is R-C phase shift oscillator. How would you recognize and tag them just by
observation?
3. What regulated output voltage will be produced by the circuit of Q1
Beta=50
R1220 Ohm
R220 Kohm
D1
8.3 V
J1
+20V(Unregulated)
Vout
R330 Kohm
R4
Q2
Beta=50
Take the values of R2 = 20kΩ, R3 = 30kΩ and Vz = 8.3V.
4. How can the loading of the R-C phase shift network be reduced in a phase shift
oscillator?
SECTION – B
(Attempt any two Questions; Each carries 4 marks)
5. A Transistor with hie = 1.5KΩ and hfe = 75 is used in an emitter follower circuit. If Re
= RL = 860Ω and R1||R2 = 20kΩ, calculate:
a) Ai b) Ri c) Ri’ d)Av e) Ro f) Ro’
Assume Rs = 1kΩ.
6. A three section R-C phase shift oscillator has R = 10kΩ and C = 0.001µf.
a) What is the frequency of oscillation?
b) If the oscillator is to be made variable, using the same values of R, what should be
the tuning range of the capacitors to obtain a frequency range of 1 to 100 kHz?
7. Calculate the regulated output voltage in the circuit of
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Q1
Beta=100
R3820 Ohm R1
12 Kohm
Vz10 V
Vin+40V(Unregulated)
Vo
R28.2 Kohm
U1
SECTION-C
(Attempt any one Question; each carries 8 marks)
8. Recognize the type of feedback in the following amplifier. Redraw it in a block
diagram form, showing the input signal, output signal and feedback signal clearly.
Then, deduce an expression for D, AVf, β, Rif, Rof’ (output resistance with feedback
taking RL into account) VCC
Rc
Vo
+
Rs
------>Ii
Vs
-
Q1
Vi
+
-Re
9. Deduce an expression for the frequency of oscillation of a Wein Bridge oscillator.
Use the active device as:
a) FET
b) Op-Amp
164
APPENDIX E
END SEMESTER KNOWLEDGE TESTS FOR ANALOG ELECTRONICS
____________________________________________________________ END SEMESTER KNOWLEDGE TEST
(USED BY FACILITATOR 1) Note:
1.Section A is compulsory. Attempt any four questions from Section B and any two from Section C
2.Each question in Section A carries two marks each. Each question in Section B carries 4 marks and each question in Section C carries 8 marks.
SECTION A
1. Which lumped parameters in the equivalent circuits of active devices, determine the
low frequency and high frequency response of the device?
2. For the network of following circuit
1.2 Kohm
0.068uF
Vi
+
Vo
+
- -
determine the phase angles at f = 100 Hz, 1kHz, 2kHz, 5kHz and at 10kHz. Plot the
resulting curve.
3. An active device in class-A direct coupled resistive load amplifier dissipates less
power when a signal is applied than with no signal. Why? Is this also true in a
transformer-coupled-load power amplifier?
4. Why may an amplifier be operated at a load resistance lower than the value that
would provide maximum output power?
5. A square wave is applied as input to a two stage R-C coupled amplifier. When the
output waveform is viewed on an oscilloscope, there was a tilt. What could be the
reason?
6. Why the total voltage gain of a cascaded amplifier is equal to product of the stage
gains, but the total current gain is not equal to product of the stage current gains?
165
7. Write the general equation for voltage gain of an amplifier with feedback? Does Avf
have to be necessarily smaller than Av? Why?
8. List 4 advantages of negative feedback, indicating any possible restriction or
disadvantages associated with each.
9. Define Positive feedback. What is the relationship between Af and A for positive
feedback?
10. List three reasons, why unregulated power supply is not good enough for some
applications.
SECTION B
11. Draw the equivalent circuit of a single stage CE amplifier using Miller’s effect. Not
assuming that K = Vce/Vb’e >> 1, prove that
K = (-gmRL+jωCcRL)/(1+jωCcRL)
Why may the term jωCcRL be neglected in the numerator and not in the
denominator?
12. The following low–frequency parameters are known for a given transistor at Ic =
10mA, VCE = 10V, and at room temperature
hie = 500Ω hoe = 10-5 A/V hfe = 100 hre = 10-4
At the same operating frequency, fT = 50MHz and Cob = 3pF, compute the values of
all the hybrid-π parameters.
13. Calculate the ac power delivered to the 8Ω speaker of the circuit in the following
figure. The circuit component values result in a dc base current of 6mA, and the
input signal result in a peak base current swing of 4mA
Q1
beta=400.1uF-POL
100uF
R1
VCC
10V
V1
due to Vi: Ibpeak=4mA
R2
Ib=6mA---->
Re Ce
T1
N1/N2=3:1 RL8 Ohm
VL
14. In the amplifier of following figure,. Q1 and Q2 are identical with hie = 4KΩ, hfe =
100 and hoe = 50µΩ. The transformers used, provides maximum power transfer.
• If Rs = 1kΩ and RL =4Ω, specify the primary and secondary
166
impedances of transformers T1, T2 and T3. Assume Ri = hie and hre = 0
• Determine the turns ratio of T1; hence obtain the current gain Ib1/Ii
• Obtain the current gain of the first stage Ib2/Ib1
V1 R1R2
C2
T2
RL VL
Rs
T1------>Ib1
Vin
+
-
Q1
C1
C3 R3
V212 V
Q2
C4
R11
T3
15. An amplifier employs collector to base biasing to provide bias point stabilization. No
bypass capacitor is used, so that negative voltage-shunt feedback results, as in
following figure, RB = 80kΩ and hfe = 75. If the source resistance is 1kΩ, calculate:
(a) Rif (b) Av (c) Rof (d) Rof’
Rb
<----If
Vo
+
Re
Rs
Vs
-
Q1
<------RofCc
------>Rif
Vi
+
-
RL
<----Rof'
VCC
C1
SECTION C
16. Draw four topologies for feedback in amplifiers. Deduce expressions of Input
resistance with feedback and output resistance with feedback. .
17. It is required to produce highly stabilized oscillations in the range 1MHz to 10MHz,
with less than .01% variation in frequency. What type of oscillator would you use for
this application? Explain in detail, the possible options and deduce an expression for
frequency of such an oscillator.
18. Draw the block diagram of a series regulated power supply, explain its operation and
deduce expression for output voltage, input regulation factor, and output resistance.
167
END SEMESTER KNOWLEDGE TEST
(USED BY FACILITATOR 2) Note:
1.Section A is compulsory. Attempt any four questions from Section B and any two from Section C
2.Each question in Section A carries two marks each. Each question in Section B carries 4 marks and each question in Section C carries 8 marks.
SECTION A 1. State Miller’s Theorem.
2. The potential variation inside a pnp transistor is as shown in the figure:
The shift of curve from smaller to larger slope, with increased reverse bias is evident
from the figure. What is this effect known as? Which lumped parameters in the high
frequency equivalent of the transistor are contributed by this effect?
3. (a) What type of bias is used in a true class-B push-pull amplifier? How is this
obtained in a transistor amplifier?
(b) If each transistor handles only half of the signal, what component combines the
two?
4. Identify the circuit in the figure:
What is the function of the diode in the figure? How does it perform this function?
W’B’WB
pn
d
Small reverse bias
Large revere bias
Q1
Q2
D1
RL8 Ohm
V118V rms
VL
C1
500uF
V244 V
0.8V
R1
100 Ohm/2W
R2
100 Ohm/2W
168
5. What is meant by the rise time? How would you measure an amplifier’s rise time? If
we want an amplifier with a very low rise time, what must be true about the
amplifier’s bandwidth?
6. What effect does the emitter bypass capacitor has on the mid frequencies? What is it
caused by? How does it modify the expression of voltage gain at mid frequencies?
7. State the three fundamental assumptions which were made in order that the
expression Af = A / (1+Aβ) be satisfied exactly.
8. What happens as the amount of positive feedback introduced to an amplifier is
increased? State Barkhauson criteria of sustained oscillation in that light.
9. Draw the circuit of a simple zener voltage regulator and calculate the value of
minimum zener current, which is required for regulation to take place-
10. Why a series voltage regulator is termed so?
SECTION B
11. For a class-B amplifier delivering a 20V peak signal to a 16Ω load (speaker) and a
power supply of Vcc = 30V, determine the input power, output power, and efficiency.
12. A single transistor, working in class-A amplifier with a transformer–coupled load
produces harmonic amplitudes in the output of Ao = 1.5mA, A2 = 10mA, A3 = 4mA,
A4 = 2mA, A5 = 1mA.
(a) Determine the percent total harmonic distortion.
(b) Assume a second identical transistor is used alongwith a suitable transformer to
provide push-pull operation. Use the above amplitudes to determine the new total
harmonic distortion in the output
13. For the given circuit, determine fHi and fHo. Assuming that Cb’e = Cbe and Cb’c = Cbc,
find fβ and fT . Take Cwi = 5pf, Cwo = 8pf, Cbc = 12 pf, Cbe = 40pf, Cce = 8pf.
Q1
beta=120
C1
0.47uF
Rb68 Kohm
VCC
14V
V1
Rc5.6 Kohm
R110 Kohm R2
1.2 Kohm
C2
0.47uF
C320uF
R33.3 Kohm
R4820 Ohm
Vo
169
14. Deduce the expressions for percentage tilt and rise time in a two stage Common
Emitter R-C coupled amplifier.
15. Two CE stages are operating from the same 30V power supply, which has an
internal resistance of 2Ω. The first stage operates at quiescent collector current of
0.5mA with a bias resistor R1 = 6kΩ and hie1 = 2kΩ. The current gain of the first
stage is 50 and of the second stage 100.
(a) Determine if above combination is in danger of breaking into oscillations.
(b) What values should be used in decoupling filter if the first stage can adequately
work at 25 V and the feedback is to be reduced to 10% of its original value (f =
50Hz).
SECTION C 16. Deduce an expression for fβ, fH, fL and fT for a CE transistor amplifier, with voltage
divider bias and collector and emitter resistors. Taking coupling capacitors as Cc and
emitter by pass capacitor as Ce.
17. Explain how the gain, distortion, input resistance and output resistance get affected
by negative feedback in voltage series and voltage shunt feedback topologies.
18. (a) Draw an indicative graph of variation of output power and distortion with load
resistance, in a transformer coupled amplifier.
(b) Give complete flow chart of design of a transformer coupled power amplifier.
170
APPENDIX F
END SEMESTER SKILL TEST FOR ANALOG ELECTRONICS
_________________________________________________________ The circuit of two stage amplifier as given the following figure was hard wired on a
bread board. The students were not given any schematic of this circuit. They were just
told that this is a two stage amplifier. The first stage is biased to work in class A mode
and the second one is biased to work in class B mode. Three faults were introduced in
the hard wired circuit – one, a missing signal connection; second, a wrong connection
and third a missing ground connection. The teams were required to find out what the
circuit does, draw its circuit diagram and rectify the faults and make it working. They
were also required to draw the response of the given circuit for an applied sinusoidal
input of 200mVp-p from 20Hz to 20kHz. The students were free to choose their team
mates and then perform the task within three hours. The evaluation was done by a panel
of three senior teachers.
Q1
50 Kohm
VCC
Vi
2 Kohm
2 Kohm50 Kohm
Ce
Cb
50 Kohm
50 Kohm 2 Kohm
2 Kohm
Q2
Cz
Vo
+
-
171
APPENDIX G
ASSIGNMENT CUM TUTORIAL SHEETS FOR DIGITAL ELECTRONICS
__________________________________________________________ ATS - 1 to ATS – 4 were developed and used by the facilitator to augment the analytical
skills of the students in Digital Electronics. Both the students in TG and CG were
required to solve them and submit the solutions as part of their evaluation scheme.
Assignment-Cum-Tutorial Sheet (ATS)-1 Topic: Number system and binary code and Minimization of Logic functions
1. Convert from Octal to Binary:
(i) 423 (ii) 10 (iii) 47 (iv) 600
2. Hexadecimal to Octal
(i) 4F4E (ii) 300 (iii) 4ABC (iv) 679A
3. Binary to BCD
(i) 01010001 (ii) 1000100 (iii) 1000010 (iv) 100010101
4. Decimal to binary
(i) 34.89 (ii) 12.098 (iii) 20.08 (v) 100001
5. Express each decimal number as an 8-bit number in 1’s and 2’s compliment forms
(a) +12 (b) +57 (c) -99 (d) -125
6. Determine the decimal value of each signed binary number in 2’s compliment from:
(a) 10011001 (b) 10111111 (c) 01110100
7. Perform each addition in 2’s compliment form
(a) 00010110+00110011 (b) 01110000+10101111
8. Express following binary numbers in gray code
(i) 110101 (ii) 1001011 (iii) 101
9. Convert following numbers in gray code to binary
(i) 1011 (ii) 110101 (iii) 101111
10. Change following numbers in decimal to excess-3 code
(i) 87 (ii) 430 (iii) 159
11. Use 2’s compliment method to perform following algebraic operations:
(i) 35+78 (ii) 90-23 (iii) -23+25
172
12. Find the range of signed decimal values which can be represented using
(i) 8 bits (ii) 12 bit
13. In a certain application a 4-bit binary sequence cycles from 1111 to 0000
periodically. There are four-bit changes, and because of circuit delays, these changes
may not occur at the same instant. For example, if the LSB changes first, the number
will appear as 1110 during the transition from 1111 to 0000 and may be
misinterpreted by the system. Illustrate how the Gray code avoids this problem.
14. Add the following BCD numbers:
(a) 0010 + 0001
(b) 0101 + 0011
(c) 0111 + 0010
(d) 1000 + 0001
(e) 00011000 + 00010001
(f) 01100100 + 00110011
(g) 01000000 + 01000111
(h) 10000101 + 00010011
15. Draw the logic circuit for ( )( )CBACBAY ++++=
16. A pulse is applied to each input of a 2-input NAND gate. One pulse goes HIGH at t
= 0 and goes back LOW at t = 1ms. The other pulse goes HIGH at t = 0.8ms and
goes back LOW at t = 3ms. The output pulse can be described as follows:
a) It goes LOW at t = 0 and back HIGH at t = 3ms.
b) It goes LOW at t = 0.8 ms and back HIGH at t = 3ms.
c) It goes LOW at t = 0.8 ms and back HIGH at t= 1ms.
d) It goes LOW at t = 0.8ms and back LOW at t = 1ms.
17. The output of a gate is LOW if and only if all its inputs are HIGH. It is true for
(a) AND
(b) XNOR
(c) NOR
(d) NAND
18. For the set of input waveforms in following figure, determine the output for the gate
shown and draw the timing diagram
173
19. Convert each of the following Boolean expressions to SOP form:
(a) )( EFCDBAB ++
(b) ))(( DCBBA +++
(c) CBA ++ )(
20. Draw the logic circuit given by this Boolean equation:
CBACABCBABCAY +++=
Use ICs 7404, 7411, and 7432. Also show the pin numbers in the schematic.
21. As part of an aircraft’s functional monitoring system, a circuit is required to
indicate the status of the landing gears prior to landing. A green LED display turns
‘ON’ if all three gears are properly extended & when the “gear down” switch has
been activated in preparation for landing. A red LED display turns ‘ON’ if any of the
gears fails to extend properly prior to landing. When a landing gear is extended, its
sensor produces a LOW voltage. When a landing gear is retracted, its sensor
produces a HIGH voltage. Implement a circuit to meet this requirement.
22. State and prove De Morgan’s Theorem
23. Simplify the following Boolean expression:
CABACAB ++
24. Using Boolean algebra, simplify the following expressions:
(a) ACABAB ++
(b) ABCBAAB +++ )(
25. Get simplified expression of Y = F (A, B, C, D) = ∑m (1, 2, 8, 9, 10, 12, 13, 14)
using Quine-McClusky method.
174
26. Two four bit binary numbers are to be compared. Write a flow chart and design a
combinational circuit to do the same. Find out a commercially available IC that
performs this operation.
27. Can a MUX be used as a decoder and vice versa? If yes, how? If not, why? Explain
by giving an example.
28. Convert each of the following POS expressions to minimum SOP expressions using
a Karnaugh map:
a) ( )( )( )CBACABA ++++
b) ( )( )( )( )DCBADCBCBABA ++++++++
29. Design a Excess-3-to BCD code converter using minimum number of NAND gates.
175
Assignment cum Tutorial sheet (ATS) – 2 Topic: Combinational Logic Circuit
1. The expression DBCADABCBCDA ++
(a) cannot be simplified
(b) can be simplified to BABCA +
(c) can be simplified to CBADABC +
(d) None of these answers is correct.
2. Develop the truth table for each circuit in following figure
A
B
X
C
D
U1A
7432N
U2A
7432N
U3A
7408N
U1A
7400N
A
B
X
U2A
7400N
C
D
U3A
7400NU4A
7402N
A
BX
C
D
U1A
7432N
U2A
7432N
U3A
7408N
U4A
7408N
E
3. Use AND gates, OR gates, and inverters to implement the following logic
expressions:
(a) CBABX +=
(b) )( GEFBABCX ++=
4. The 74LS83A is an example of a 4-bit parallel adder. To expand this device to an 8-bit
adder, you must
(a) use four adders with no interconnections
(b) use two adders and connect the sum outputs of one to the bit inputs of the other
(c) use eight adders with no interconnections
176
(d) use two adders with the carry output of one connected to the carry input of the
other
5. Which of the following codes exhibit even parity?
(a) 10011000 (b) 01111000 (c) 11111111 (d) 11010101
6. For the multiplexer in the figure, determine the output for the following input states:
7. Design a 2-bit comparator using gates.
8. Realize the logic function given in the following table using
(a) A 16:1 multiplexer IC 74150, and
(b) An 8:1 multiplexer IC 74152.
Inputs OutputA B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1
S0
S
D0
D1
D2
D3
MUX
0,1,0,1,1,0103210====== SSDDDD
177
10. Design a BCD-to-Gray code converter using
• 8:1 multiplexers,
• Quad 2:1 multiplexers and some gates,
11. Give the functional definition of MUX, DEMUX, DECODER, and ENCODER.
12. The waveforms in the following figure are applied to the comparator as shown.
Determine the output (A = B) waveform.
13. For the 4-bit comparator in following figure, plot each output waveform for the inputs
A0
A
B0
B
A
B
A=B
A0
A1
B1
B2
COMPARATOR 2 BIT
Vcc
A>B
A0
A1
A2
A3
B0
B1
B2
B3
A>B
A=
A<B
4 BIT COMPARATOR
A=
A<B
74HC85
A0
A1
A2
A3
B0
B1
B2
B3
178
14. For a four bit parallel adder, supplied with two four bit words – 1001 and 1110,
determine the complete sum by analysis of the logical operation of the circuit. Verify
your result by longhand addition of the two input numbers.
15. A 7-segment decoder/driver drives the display in the following figure. If the
waveforms are applied as indicated, determine the sequence of digits that appears on
the display.
U1
7447N
A7B1C2D6
OA 13
OD 10OE 9OF 15
OC 11OB 12
OG 14~LT3~RBI5~BI/RBO4
U2
A B C D E FG
CA
A0
A1
A2
A3
16. You wish to detect only the presence of the codes 1010, 1100, 0001, and 1011. An
active-HIGH output is required to indicate their presence. Develop the minimum
decoding logic with a single output that will indicate when any one of these codes is
on the inputs. For any other code, the output must be LOW.
A0
A1
A3
179
Q
CL
Q
CL
CLK
S
R
Assignment cum Tutorial Sheet (ATS) – 3
Topic: Sequential circuits
1. Two edge-triggered S-R flip-flops are shown.
If the inputs are as shown, draw the Q output of each flip-flop relative to the clock, and
explain the difference between the two. The flip-flops are initially RESET.
2. The Q output of an edge-triggered S-R flip-flop is shown in relation to the clock signal
in the following figure. Determine the input waveforms required on the S and R inputs
to produce this output if the flip-flop is a positive edge-triggered type.
180
3. Draw the Q output relative to the clock for a D flip-flop with the inputs as shown in
the following figure. Assume positive edge-triggering and Q initially LOW.
4. For the circuit shown, draw the Q output of flip-flop B, in proper relation to the clock.
The flip-flops are initially RESET.
U1A
7473N
1J141CLK1 1Q 12
1K3
~1CLR2~1Q 13
U1B
7473N
2J72CLK5 2Q 9
2K10
~2CLR6~2Q 8
CLK
VCC
5V
QaQb
Qa' Qb'
5. For the circuit shown here, determine the maximum frequency of the clock signal for
reliable operation if the set-up time for each flip-flop is 2 ns and the propagation
delays ( )PHLPLH andtt from clock to output are 5 ns for each flip-flop.
U1A
7473N
1J141CLK1 1Q 12
1K3
~1CLR2~1Q 13
U1B
7473N
2J72CLK5 2Q 9
2K10
~2CLR6~2Q 8
CLK
VCC
5V
QaQb
Qa' Qb'
181
CLK
Q
J
K
clk
6. The Q output of an edge-triggered S-R flip-flop is shown in relation to the clock signal
in the following figure. Determine the input waveforms on the S and R inputs that are
required to produce this output if the flip-flop is a positive edge-triggered type.
7. For a master-slave J-K flip-flop with the inputs as shown, develop the timing diagram
showing Q starting in the LOW state. Assume the clock is active-HIGH.
8. Design a 4-bit binary UP/DOWN ripple counter with a control for UP/DOWN
counting.
9. For the state diagram shown, obtain the state table and design the circuit using
minimum number of J-K FFs.
00
01
10
11
0
1
0
0
1
1
182
10. How does state transition diagram of Moore machine differ from Mealy machine?
11. Assume that the clock for the ripple counter in Fig. 10.1 is a 1-MHz square wave and
each flip-flop has a delay time of 0.25µs. Carefully draw the waveforms for the clock
and each flip-flop and the output-decoded signals. Do you see any sources of
difficulty?
12. Draw the logic diagram, truth table, and waveforms for a mod-9 counter using two
mod-3 counters connected in series.
U1A
7473N
1J141CLK1 1Q 12
1K3
~1CLR2~1Q13
U1B
7473N
2J72CLK5 2Q 9
2K10
~2CLR6~2Q8
U2A
7473N
1J141CLK1 1Q 12
1K3
~1CLR2~1Q 13
VCC5V
CLK
A
------------------OUTPUT--------------------
B C
U1A
7473N
1J141CLK1 1Q12
1K3
~1CLR2~1Q13
U1B
7473N
2J72CLK5 2Q9
2K10
~2CLR6~2Q8
U2A
7473N
1J141CLK1 1Q12
1K3
~1CLR2~1Q13
VCC5V
CLK
A B C
U2B
7473N
2J72CLK5 2Q9
2K10
~2CLR6~2Q8
U3A
7408N
D
183
Assignment Cum Tutorial Sheet (ATS) – 4
Topics: A/D and D/A converters, Semiconductor memories, Logic families
1. A 10-bit resistive divider is constructed such that the current through the LSB resistor
is 100µA. Determine the maximum current that will flow through the MSB resistor.
2. What is the conversion time of a 12-bit successive-approximation-type A/D converter
using a 1MHz clock?
3. What clock frequency must be used with a 10-bit counter-type A/D converter if it must
be capable of making at least 7000 conversions per second?
4. The time required for the analog output voltage to come to and settle to within
±1/2LSB of its final value after a input is applied is known as____________.
5. A dual-slope A/D converter has a resolution of 12 bits. If the clock rate is 100 kHz,
what is the maximum rate at which samples can be converted?
6. What is the bit storage capacity of a ROM with 512*8 organisation?
7. Use 16k X 4DRAMs to build a 64k X 8 DRAM. Show the logic diagram. What are the
word length and the word capacity of this memory?
8. Using a block diagram, show how 64k X 1 dynamic RAMs can be expanded to build a
256k X 4 RAM.
9. A certain gate draws 2 Aµ when its output is HIGH and 3.6 Aµ when its output is
LOW. What is its average power dissipation if Vcc is 5V and the gate is operated on a
50% duty cycle?
10. Gate A has more propagation delay than gate B. Which gate can operate at a higher
frequency and why?
11. A certain logic gate has a (min)OLV =0.45 V, and it is driving a gate with a (min)ILV = 0.75
V. Are these gates compatible for LOW-state operation? Why?
12. Select ECL, HCMOS, or the appropriate TTL series for each of the following
requirements:
(a) highest speed
(b) lowest power
(c) best compromise between high speed and low power (speed-power product)
13. Draw a the circuit of a typical ECL NOR gate.
184
APPENDIX H
MID SEMESTER TESTS FOR DIGITAL ELECTRONICS ____________________________________________________________
MID SEMESTER EXAMINATION - I
Max. Time Allowed: 90 min. Max. Marks: 24
SECTION A
1. Perform the subtraction (36-12) using 2’s complement method.
2. Differentiate between combinational and sequential circuits.
3. Simplify y = (C+ D)’ + A’CD’ + AB’C’ +A’B’CD + ACD’ using Boolean algebra.
4. Draw logic circuit for Y = A’BC’+D using basic logic gates.
SECTION B
5. Perform the following operations
a. Simplify F = X + X•Y•Z + X•Z using Boolean rules.
b. Convert (11001)2 = ( ? )10
c. Attach an even–parity bit to the data sequence 1011011.
d. Convert binary number 1001010 into its equivalent Gray code.
6. Explain a multiplexer in detail and realize the following function using 8:1
multiplexer:
f = Σ m (0,3,5,6,9,10)
7. Design a logic circuit that controls the passages of a signal A according to the
following requirements:
a. Output X will equal A when control inputs B and C are the same.
b. X will remain HIGH when B and C are different.
SECTION C
8. a. What is Decoder? How it is different from a Demultiplexer?
b. Design a full adder circuit using 3:8 decoder and logic gates.
9. a. Obtain the minimal expression for following expression using Karnaugh map
f = Σ m ( 0,1,2,4,6,9,11,12,13)
b. Implement the logic circuit for (9a) using NAND gates only.
185
MID SEMESTER EXAMINATION - II
Max. Time Allowed: 90 min. Max. Marks: 24
______________________________________________________________________
SECTION A
1. The modulus of a counter is
(a) The number of flip flops
(b) The actual number of states in a sequence
(c) The number of times it recycles in a second
(d) The maximum possible number states
2. Asynchronous counters are known as:
(a) Ripple counters
(b) Multiple clock counters
(c) Decade counters
(d) Modulus counters
3. Are RAM and ROM both random access memories? Why?
4. A TTL gate has following actual voltage level values: VIH(min) = 2.25V, VIL(max) =
0.65V. Assuming it is being driven by a gate with VOH(min) = 2.4V and VOL(max) = 0.4V,
what are the HIGH and LOW level noise margins?
SECTION B
5. Draw the circuit diagram of a 4 bit weighted resistor D/A converter and explain its
working.
6. Determine the output waveforms in relation to the clock for QA, QB and QC in the
given circuit and show the binary sequence represented by these waveforms.
U1A
7473N
1J141CLK1 1Q 12
1K3
~1CLR2~1Q 13
U1B
7473N
2J72CLK5 2Q 9
2K10
~2CLR6~2Q 8
CLK
VCC
5V
QaQb
Qa' Qb'
U2A
7473N
1J141CLK1 1Q 12
1K3
~1CLR2~1Q 13
Qc
QC'
186
7. Draw the circuit diagram of a CMOS inverter and explain its working, with special
reference to totem pole output.
SECTION C
8. With general block diagrams, show how to obtain the following frequencies from a
10MHz clock by using single F/Fs, modulus-5 counters and decade counters
(a) 5 MHz (b) 2.5 MHz (c) 2 MHz (d)1MHz
9. Why is a bidirectional shift register, called so? Explain the working of a four bit
bidirectional shift register.
187
APPENDIX I
END SEMESTER KNOWLEDGE TESTS FOR DIGITAL ELECTRONICS
____________________________________________________________ END SEMESTER KNOWLEDGE TEST
(USED BY FACLITATOR 1)
Note:
1. Section A is compulsory. Attempt any four questions from Section B and any two from
Section C
2. Each question in Section A carries two marks each. Each question in Section B carries
4 marks and each one in Section C carries 8 marks.
SECTION A
1. Express each decimal number in binary as an 8-bit sign magnitude number
(a) +29 (b) -85 (c) +100 (d) -123
2. Multiply following numbers in binary
(i) 1.1101 and 10.01 (ii) 0.111 and 101.001
3. The output of a 2-input gate is 1, if and only if its inputs are equal. It is true for
(a) XNOR (b) XOR (c) AND (d) OR
4. What is the sum of product circuit for the truth table given below:
0 1 2 3 10 11 12 13 14 15
A’B’(0,1,2,3) √ √ √ √
B’C’(2,3,10,11) √ √ √ √
AC(10,11,14,15) √ √ √ √
AB(12,13,14,15) √ √ √ √
5. Write the truth table for the circuit
A
BX
C
D
U1A
7432N
U2A
7432N
U3A
7408N
U4A
7408N
E
188
6. All the Boolean expression can be implemented with
(a) NAND gates only
(b) NOR gates only
(c) Combination of NAND and NOR gates
(d) Combinations of AND gates, OR gates, and inverters
(e) Any of the above
7. In a new number system X and Y are two successive digits such that (XY)r = 29 and
(YX)r = 34. Find X,Y and r.
8. How can a serial in – parallel out register be used as a serial in serial out register?
9. For the maximum quantization error of an A/D convertor to be ±1/2LSB, what fraction
will be the step size S, of the maximum analog voltage?
10. List four differences of ECL and TTL logic.
SECTION B
11. Express the decimal number 35 in
(i) Excess-3 code (ii) 7 bit even parity Hamming Code (iii) Gray code
(iv) BCD (v) Octal (vi) hex (vii)ASCII
(viii) binary
12. Use karnaugh map to minimize the following SOP expression:
B’C’D’+A’BC’D’+ABC’D’+A’B’CD+AB’CD+A’B’CD’+A’BCD’+ABCD’+AB’C
13. The serial data input waveform (Data IN) and data select inputs (S0 and S1) are shown
in the following figure. Determine the data input waveforms on D0 through D3 for the
demultiplexer.
189
14. Show the states of the 5-bit register for the specified data input and clock waveforms.
Assume that all the registers are initially cleared U1A
7474N
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4 U1B
7474N
2D12 2Q 9
~2Q 8
~2CLR
13
2CLK11
~2PR
10 U2A
7474N
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4 U2B
7474N
2D12 2Q 9
~2Q 8
~2CLR
13
2CLK11
~2PR
10 U3A
7474N
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4
CLK
DATA IN DATA OUT
15. A D/A converter has full scale analog output of 10V and accepts six binary bits as
inputs. Find the voltage corresponding to each analog step.
1 1 0 1 0
CLK
DATA
1
0
1 1
1
D
D1
D
D
S
S1
Data in
190
SECTION C
16. (a) Explain the difference between EPROM and PROM.
(b) Draw the circuit diagram of a TTL NOR gate and explain its operation.
17. (a) What is a 4of 16 decoder? Give its truth table.
(b) Which one is the commercially available IC for BCD to seven segment decoding?
Give the truth table for such an IC. Reduce the expressions for these by using
Karnaugh maps and design combinational circuits for the same.
18. Draw the circuit diagram of a 4 bit parallel-in, serial out register. Explain its operation,
with timing diagram.
191
END SEMESTER KNOWLEDGE TEST
(USED BY FACLITATOR 2)
Note:
3. Section A is compulsory. Attempt any four questions from Section B and any two from
Section C
4. Each question in Section A carries two marks each. Each question in Section B carries
4 marks and each one in Section C carries 8 marks.
SECTION A
1. Perform following subtractions using 1’s compliment:
(i) 25 from -34 (ii) 2 from 0
2. Add the following numbers after converting to BCD
(i) 74 and 23 (ii) 385 and 118
3. The input waveforms applied to a 4-input AND gate are as shown in the figure. Show
the output waveform in proper relation to the inputs with a timing diagram.
4. The output of a gate is HIGH when at least one of its inputs is LOW. It is TRUE for
(a) XOR (b) NAND (c) NOR (d) OR
5. Write the output expression for each circuit as it appears in the following figures:
192
6. For the given circuit of Decimal to BCD encode, assume that the 9 input and the 3-
input are both HIGH. What is the output code? Is it a valid BCD (8421) code?
7. A D-F/F is connected as shown in the following circuit. Determine the Q output in
relation to clock. What specific function does this device perform?
8. What care must be taken while handling CMOS devices?
9. Find the output voltage from a 4-bit ladder that has an input of 1101. Assume that 0 =
0V and 1 = +10V
U1
OR4
U2
OR4
U3
OR4
U4
OR2
1
2
3
6
4
5
7
8
9
A1
A3(MSB)
A0(LSB)
A2
U1A
7474N
1D2 1Q 5
~1Q6
~1CLR
1
1CLK3
~1PR
4
CLK
Q
2R
2R
R R R
2R 2R 2R
V+V
Va
193
10. What is a cache memory? How is it different from RAM?
SECTION B
11. In a certain application a 4-bit binary sequence cycles from 1111 to 0000 periodically.
There are four bit changes, and because of circuit delays, these changes may not occur
at the same instant. For example, if the LSB changes first, the number will appear as
1110 during transition from 1111 to 0000 and may be misinterpreted by the system.
Illustrate how the Gray code avoids this problem.
12. Determine the binary values for which the following standard SOP expression is equal
to 1:
ABCD+AB’C’D+A’B’C’D’
13. Can a DECODER be used as DMUX? If yes, how?
14. The given input waveforms are applied to a 2-bit adder. Determine the waveforms for
the sum and the output carry in relation to the inputs by constructing a timing diagram.
15. Design a 3-bit carry-look-ahead-adder.
SECTION C
16. For a particular application, it is required to use a 16*1 Multiplexer. But the
commercial available MUX IC available in the lab is 2*1 multiplexer. Is it is possible
to use the same to design 16*1 MUX. If yes, how?
17. Design a binary counter with the sequence as shown in the state diagram:
A1
A2
B1
B2
CARRYINN
194
18. (a) A certain gate draws a dc supply current from a +5V source of 2mA in the LOW
state and 3.5mA in the HIGH state and in LOW state? Assuming a 50% duty cycle,
what is the average power dissipation?
(b) Each gate in the given circuit has a tpLH and tpHL of 4ns. If a positive going pulse is
applied to the input as indicated, how long will it take the output pulse to appear?
0
11
9
7
3
5
U1A
7400N
U1B
7400N
U2A
7402N
U2B
7402N
U3A
7404N
U4A
7404N
HIGH/LOW
HIGH
LOW
HIGH
OUTP
195
APPENDIX J
END SEMESTER SKILL TEST FOR DIGITAL ELECTRONICS
_____________________________________________________________ The circuit of BCD to Seven segment decoder as given the following figure was hard
wired on a bread board. The students were not given any schematic nor were they told
what this circuit did. Three faults were introduced in the hard wired circuit – one, a
missing connection; second, a wrong connection and the third, a missing ground
connection. The teams were required to find out what the circuit does, draw its circuit
diagram and rectify the faults and make it working. The students were free to choose their
team mates and then perform the task within three hours. The evaluation was done by a
panel of three senior teachers.
B
U3
74151A
168
5
6
7
4321
15141312
11109
VCC
GND
Z
Z
E
I0I1I2I3I4I5I6I7
S0S1S2
VCC
b
JH1B 11
a
C
B
e
C
A
D'
U5
74151A
168
5
6
7
4321
15141312
11109
VCC
GND
Z
Z
E
I0I1I2I3I4I5I6I7
S0S1S2
<Doc> 01
BCD TO 7 SEGMENT DECORDERA
1 1Thursday, June 12, 2008
Title
Size Document Number Rev
Date: Sheet of
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74151A
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196
APPENDIX K
ASSIGNMENT CUM TUTORIAL SHEETS FOR PDSC _____________________________________________________________
ATS 1 to ATS 4 were developed and used by the facilitator to augment the analytical
skills of the students in PDSC. Both the students in TG and CG were required to solve
them and submit the solutions as part of their evaluation scheme.
Assignment cum Tutorial Sheet (ATS) – 1
Topics: Linear Wave shaping and wide band amplifiers
1. While analyzing the attenuator network it was assumed that source resistance of the
source supplying Vi was zero. Analyze the attenuator n/w if the source has a finite
resistance Rs.
1 M
C
1 MVi
+
-
Vo
+
-
50pF
2. Prove that the following networks work as high pass and low pass circuit respectively:
1/C(s)
R
------>I(s)
Vi(s)+
-
Vo(s)+
-
C
R
------>I(t)
Vi(t)+
-
Vo(t)+
-
3. For the RLC circuit given,
C
R
------>I(t)
Vi(t)+
-
Vo(t)+
-
L
197
Analyse the circuit for
Critical damping: k=1
Overdamping k<1
Underdamping k<1
4. Prove that the short circuit current gain AI for the circuit given
is given by: Ai = Ii/[gb’e+jω(Ce+Cc)]
5. Prove that the normalized current gain ‘y’ of the high frequency wideband
compensated amplifier is given by:
y ≡ Csi2i2(t) / gms0I = 1 – [1+sit(1-si/s0)]ε-sit
6. Show that for low frequency compensated wideband amplifier, the response is given
by:
y(t) = 1/λ [(λ-1) ε-x +1]
where, y ≡ Vo(t) Rσ/ IoRy Ri’ and x ≡ t/RσCσ and λ = RyCd/ RσCσ
7. Following limited ramp is applied to a Low pass circuit. Draw to scale, the output
waveform for cases (a) T = RC, (b) T = 0.2RC (c) T = 5RC
Under which condition the circuit works as integrator?
Slope α = V/T
V
T
Rbb'
gb'e Ce
gb'c
Cc
gce gmVb'e RL
B
Vbe(+)
E
-
C
Vce(+)
-
Vb'e(+)
-
198
The same input is now applied to a high pass circuit. Sketch the waveform under same
conditions on RC. Under which condition the circuit works as a differentiator?
8. The periodic waveform shown is applied to an RC integrating network whose time
constant is 10µs. Sketch the output. Calculate the maximum and minimum values of
output voltage with respect to ground.
What happens if the output is taken across the resistor?
9. A pulse is applied to a low pass circuit. Prove by direct integration that area under the
pulse is the same as the area under the output waveform across capacitor. Explain this
result physically.
10. Compute and draw to scale the output waveform for C = 50pf, C = 75pf and C = 25pf.
The input is a 2V step.
1 M
C
1 MVi
+
-
Vo
+
-
50pF
10µs 1µs
100 V
0V
199
Assignment cum Tutorial Sheet (ATS) – 2 Topics: Switching characteristics of Devices, Non Linear wave shaping
1. Sketch the transfer characteristics of following circuits :
Vi
+
R
D
Vr-
Vo
+
-
Vi
+R
D
Vr-
Vo
+
-
Vi
+R
D
Vr-
Vo
+
-
Vi
+R
D
Vr-
Vo
+
-
Also sketch their output waveforms for sinusoidal input.
2. How a transistor wired as a switch can work as a clipper. Explain with the help of
waveforms.
3. An unsymmetrical wave with T1 = 1ms, T2 = 1µs, Vp-p = 10V is applied to the
following circuit.
a) Determine where on the o/p waveform the zero level is located?
b) If T1 = 1µs and T2 = 1ms, where on the o/p waveform the zero level is located?
c) If the diode is reversed, where on the o/p waveform the zero level is located?
4. Prove that the diffusion capacitance for a diode is given by:
CD = τI / ηVT
And the transition capacitance is given by:
CT = εA/W
5. Sketch the typical transistor common emitter characteristics. Identify various regions
of the characteristics and show how VCE(sat) differs with different load resistances
200
6. For a CE transistor circuit VCC = 15V, RC = 1.5kΩ and IB = 0.3mA. (a) Determine the
value of hFE(min) for saturation to occur. (b) If RC is changed to 500Ω, will the transistor
still be saturated?
7. For a simple circuit of generating a sweep wave form by exponential charging and
discharging of a capacitor, derive an expression for:
a) sweep speed error (es)
b) transmission error (et)
c) displacement error (ed)
8. Calculate the output levels of circuit shown in
Q1
R220 Kohm
R1
5 Kohm
Vi-------->Ib
D-8V
Rc2 Kohm
-20V
Vbb
+8V
Vo
for inputs of 0V and -8 V and verify that the circuit is an inverter. What is the
minimum value of hFE required? Neglect junction saturation voltages and assume an
ideal diode.
201
Assignment cum Tutorial Sheet (ATS) – 3
Topic: Multivibrators
1. The fixed bias binary given in the circuit uses pnp transistors with worst case
maximum values VCE(sat) = -0.5V, VBE(sat) = -1.0V, ICBO = -10nA at 25˚C and at zero
base to emitter voltage at cut off. The circuit parameters are VCC = VBB = 6V, RC =
1.2kΩ, R1 = 4.7kΩ, and R2 = 27kΩ
a) Find hFEmin and verify that one transistor is OFF and the other is ON. Find the
stable current and voltages.
b) If reverse saturation current doubles every 10˚C, what is the maximum temperature
at which one transistor will remain OFF?
2. Regeneration is possible in fixed bias transistor flip flop if the base-to-base voltage
gain exceeds unity. Verify that this gain condition is satisfied provided that hfeRc>R1.
Assume that for each stage the current gain is |AI|≈ hfe>>1 and that the input resistance
Ri is smaller compared with either R1 or R2.
3. Consider the following triggering circuits:
Rc2.2 Kohm
Q1Q2
Rc=5 Kohm
R1=15 Kohm R1
R2=100 Kohm R2
VCC
-12V-Vcc
VBB
-12V
VC1+
Vb1
+
VC2+
VB2
+
)
202
a) Which one of the two has greater trigger sensitivity, that is, will be triggered by a
smaller pulse?
b) Which circuit will malfunction first as the trigger amplitude is increased? Explain.
4. a) A collector coupled monostable multivibrator has the following parameters: VCC =
12V, RC = 2K, R1 = R2 = R = 20K, hFE = 20, rbb’ = 200Ω and C = 1000pF. Neglect
forward biased junction voltages and ICBO. In the quasi stable state Q1 is to be in its
active region with a collector current of 4mA. Find VBE.
b) Why is one-shot designed so that Q1 saturates in the quasi stable state?
5. The emitter coupled monostable multi in the given circuit has the following
parameters: VCC = 6V, RC1 = RC2 = Re = 3kΩ, R = 50kΩ, V = 2.8V, and C = 0.01µf. Si-
npn transistors with hFE = 50 and rbb’ = 100Ω are used. A trigger is applied at t = 0.
Q1B1
Q2B2
Ci
positive
trigger
R1
R2 C2
Rb
V(5V)
-Re(4 K)
C
C1
Rc1(6 K)
R4(100 K) Rc2
(5 K)
VCC
(18 V)
Vcn2+
-
Ven+
-Vbn2
+
-
a) Assume that Q1 is OFF and Q2 is ON at t = 0-. Calculate the node voltages (the
voltages with respect to ground at each collector base and emitter). Using your
own calculated values verify that Q1 is indeed OFF and Q2 is in saturation.
b) Calculate the node voltages at t = T-
c) Calculate the node voltages at t = T+
203
APPENDIX L MID SEMESTER TESTS FOR PDSC
_____________________________________________________________
MID SEMESTER EXAMINATION - I
Max. Time Allowed: 90 min. Max. Marks: 24 ______________________________________________________________________
SECTION A
1. Except a sinusoidal signal, no other signal can preserve its form when transmitted
through a linear network. Why?
2. Define lower 3dB and upper 3dB frequencies for high pass and low pass circuits
respectively.
3. The rise time of the output signal of low pass circuit is directly proportional to the time
constant τ and inversely proportional to the bandwidth. Prove.
4. A 20 V peak to peak sinusoidal input having 0V dc is to be sliced above 6V. Draw the
circuit, which would do the needful.
SECTION B
5. Following input is applied to a high pass circuit, having time constant RC = T/5.
Calculate and sketch the output waveform to scale.
6. Deduce the relationship between gb’e and gm of a CE amplifier.
7. What is an uncompensated attenuator? How will you compensate it?
T
V
V’
204
SECTION C
8. Discuss the behavior of the given circuit for an exponential input
Also deduce the expression for output voltage.
9. The square waveform having upper and lower voltage levels as 0V and -5V and
having duty cycle 40%, with On time as 50µs is fed to an RC coupling network. What
are the voltage waveforms across R and C if (a) RC is very large, say RC = 10T and
(b) RC is very small, say RC = T/10?
C
R
------>I(t)
Vi(t)+
-
Vo(t)+
-
205
MID SEMESTER EXAMINATION - II
Max. Time Allowed: 90 min. Max. Marks: 24
______________________________________________________________________
SECTION A
1. Comment on: “By connecting an inductor in the collector circuit in series with the
collector resistor a wideband common emitter amplifier can be compensated for high
frequency response.”
2. What is the difference between comparator and clipper? Give two example and two
applications of each circuit.
3. State and prove clamping circuit theorem.
4. In a binary why is applying a negative voltage at the input of a transistor, which is ON,
a better method of triggering than applying a positive voltage at the transistor, which is
OFF?
SECTION B
5. (a) Sketch the transfer characteristics of following circuit, assuming ideal diodes.
(b) It is desired to have clipping of a sinusoidal waveform at two independent levels 2V
and –2V. Draw the circuit diagram. Assume ideal diodes.
6. (a) A sinusoidal wave is applied to following circuit. Assuming ideal diode draw the
steady state output waveform.
200Kohm
25 V
Vi
+
-
Vo
+
-
D D
100Kohm
100 V
D
R
C
Vr
Vi
+
-
Vo
+
-
206
(b) A square waveform of peak-to-peak amplitude V is applied to RC differentiator
circuit. Sketch steady state output waveform
7. While compensating wideband common emitter amplifier by the method of pole zero
cancellation, prove that the compensated rise time tr’ is given by
tr’ = 2.2 Rcrb’eC/(Rc+hie), where RC, rb’e and hie have their usual meanings.
SECTION C
8. Explain how a common emitter transistor configuration as given here works as a
clipper.
9. In the self biased binary, find out the voltages: VEN, VCN2, VBE2 and currents IB2 and
IC2. Take hFE(min) = 20. Assume following values for circuit elements: RC = 4.7K, R1=
30K, R2 = 15K, RE = 0.39K, hFE = 25, VCC = 20V, VCE(sat) = 0.4V, VBE(sat) = 0.8V,
VBE(cut off) = 0V
Q1------> ib
Rc
Vi
+
-
Vbe
+
-
VCC
Vo
+
-
Q2
ON
Q1
OFF
R1
R2R2
R1
RcRc
VCC
Re
207
APPENDIX M END SEMESTER KNOWLEDGE TESTS
_____________________________________________________________
END SEMESTER KNOWLEDGE TEST
(USED BY FACLITATOR 1)
Note: 1. Section A is compulsory. Attempt any four questions from Section B and any two from Section C 2. Each question in Section A carries two marks each. Each question in Section B carries 4 marks and each one in Section C carries 8 marks.
SECTION A 1. Under what condition does the pulse shape is preserved in a
(a) Low Pass Circuit
(b) High Pass Circuit
2. A 1KHz square wave output from an amplifier has rise time tr= 350ns and tilt = 5%
Determine the upper and lower 3 dB frequencies.
3. Draw a circuit to transmit that part of a sine wave, which is below +6V.
4. For the circuit given, draw the output waveform, for a sinusoidal input of 10Vp-p
centered at Vr.
5. State necessary and sufficient conditions for the transistor to act as a switch.
6. Define (a) rise time (b) storage time and (c) fall time
7. Can an astable multivibrator act as voltage to frequency converter? How?
8. What is the most efficient method of applying trigger to a multivibrator?
9. “The response of a wide band amplifier rolls off at both the frequency ends”. Justify.
10. What type of compensation is used in a wideband amplifier to limit the overshoot?
D
R
C
Vr
Vi
+
-
Vo
+
-
208
Why?
SECTION B
11. A step generator of 50Ω impedance applies a 10V pulse of 2.2ns rise time to a series
combination of a capacitance C and a resistance R = 50Ω. There appears across R, a
pulse of amplitude 1V. Find the value of the capacitance C.
12. The clipper shown in the figure, is used with the input waveform as shown. Draw the
output waveform assuming that the reverse resistance of the diode is infinite.
13. Prove that the for the CE shunt compensated stage the two values of critical
inductances are equal (L’=L’’) if Rc = rbb’hie/rb’e
14. Draw and explain the unsymmetrical triggering technique for a monostable
multivibrator.
15. For a CE transistor circuit with VCC = 15V. RC = 1.5 kΩ, calculate the transistor power
dissipation (a) at cut off and at (b) saturation
SECTION C
16. Calculate the stable voltages and currents for the self biased binary using pnp-Ge-
transistors as given in the figure. Find the minimum value of hFE which will keep the
ON transistor in saturation. If the commutating capacitor C1 = 100 pf, determine the
maximum frequency of operation.
tp
t 0V
-10V
+10V
Q1
----->Ib
Rc1.5Kohm
Vo
V115 V
Vi
+
-
209
17. An unsymmetrical square wave with T1 = 1ms and T2 = 1µs has an amplitude of 20V.
This signal is applied to the clamping circuit, in which Rf = 100Ω, R = 100kΩ and Rs
= 0. Assume that capacitor C is arbitrarily large, so that the output is a square wave
without a tilt. (a) Find where the zero level is located on the output waveform. (b) If
the waveform is inverted so that T1 = 1µs and T2 = 1ms, find the location of zero level.
17. An exponential input as given below, is applied to a (a) Low Pass Circuit and (b) High
Pass Circuit. Derive the expression and draw the waveform for output voltages.
Rc5Kohm
Q1Q2
Rc=5 Kohm
R2
R=25 Kohm
C1
C1 C1R3
R1=25 K ohm
R2=15 Kohm R2=15 Kohm
Re1Kohm
-20V-Vcc
Vs
RsC
R D
Vi
+
-
Vo
+
-
1us
20-V1
1000us
0V
1000us
1us
20-V1
t0V
Vi Af
Ar
t
Af
V1
Ar
f1
I
0.707
|A|
210
END SEMESTER THEORY PAPER AS KNOWLEDGE TEST
(USED BY FACLITATOR 2)
Note:
1. Section A is compulsory. Attempt any four questions from Section B and any two from
Section C
2. Each question in Section A carries two marks each. Each question in Section B carries
4 marks and each one in Section C carries 8 marks.
SECTION A
1. What do you mean by blocked condition in an astable multi?
2. When is the loop gain 1 and when is it less than 1 for a bistable multi?
3. A Common emitter amplifier circuit as shown in PDSC-KT II-Fig (a) has VCC = 20V
and a collector resistor which can be either 20kΩ or 2kΩ. Calculate the minimum
values of base current to achieve saturation in each case.
4. Why is the clamper circuit also known as dc restorer?
5. In a clipper circuit, the diode can be used either as a series element or as a shunt
element. What are the advantages and disadvantages of using diode as a series or as a
shunt element?
6. The Schmitt trigger is made up of regenerative comparators. Justify.
7. Does the rise time of a passive attenuator related to the factor of attenuation? How?
8. Draw the circuit diagram of a double differentiator and write the equation relating
output and input.
9. Why the study of wideband amplifiers is called so?
10. How does the input impedance of the second stage of a cascaded amplifier affect the
Q1
Rc20 Kohm OR 2 Kohm
VceVCC
<-----Ic
Vi
----->Ib
211
output impedance of the first stage?
SECTION B
11. The equivalent circuit of a wideband amplifier taking source impedance into account
is shown in the figure
Derive an expression for high frequency cut off for this wideband amplifier.
12. A 10Hz square wave is fed to an amplifier. Calculate and plot the output waveform
under following conditions: the lower 3db frequency is (a) 0.3Hz, (b) 3.0Hz, (c) 30Hz
13. The periodic waveform as shown in PDSC-KT II-Fig(c) is applied to an RC
integrating network, whose time constant is 10µs. Sketch the output. Calculate the
maximum and minimum values of output voltage with respect to ground.
14. An input voltage Vi, varies from 0V to 150 V. It is applied to two clipper circuits as
given in the figure. Sketch the output voltages Vo of both the clipper circuits on the
same time scale as the input voltage.
10µs 1µs
100 V
0V
gb'eCe
gb'c(k-1/k)
Cc(k-1/k)
gce
gb'c(1-k)
CcRL
gmVb'e
B
Ii----->
E
C
E
212
15. The fixed biased binary of given circuit uses npn 2N706A Si transistors with hFE = 20.
The circuit parameters are VCC = 12V, VBB = 3V, RC = 1K and R1 = 5K and R2 = 10K.
Verify that one transistor is cut off and the other is in saturation and find the stable
state currents and voltages. As the ambient temperature increases, what maximum
value ICBO can attain, before the condition is reached where neither transistor is cut off
for VCE(sat) = 0 and VBE(sat) = 0?
SECTION C
16. It is required to generate a 100kHz square wave of voltage levels ±5V. Design a
circuit, to do the needful. Use transistors as active devices.
17. A step input of 20V is applied to the network shown. Draw the output waveform Vo.
Make reasonable approximations and estimate the rise time of the waveforms, the
magnitude of the overshoot and the time constant of the decay to the final value.
18. It is required to amplitude filter all the spurious voltage on the zero line being received
at a receiver. The useful signal is only beyond +V1 level in the positive side and below
–V2 level in the negative side. Design a circuit, which serves the purpose.
Rc2.2 Kohm
Q1Q2
Rc=5 Kohm
R1=15 Kohm R1
R2=100 Kohm R2
VCC
-12V-Vcc
VBB
-12V
VC1+
Vb1
+
VC2+
VB2
+
213
APPENDIX N
END SEMESTER SKILL TEST FOR PDSC ___________________________________________________________
The circuit of emitter-coupled monostable multi as given as following figure was hard
wired on a bread board. The students were not given any schematic but they were just told
the name of the circuit. Three faults were introduced in the hard wired circuit – one, a
missing signal connection; second, a wrong connection and third a missing ground
connection. The teams were required to find out what the circuit does, draw its circuit
diagram and rectify the faults and make it working. They were also required to measure all
the voltages at various nodes and draw the response of the given circuit.The students were
free to choose their team mates and then perform the task within three hours. The
evaluation was done by a panel of three senior teachers.
Q1B1
Q2B2
Ci
positive
trigger
R1
R2 C2
Rb
V(5V)
-Re(4 K)
C
C1
Rc1(6 K)
R4(100 K) Rc2
(5 K)
VCC
(18 V)
Vcn2+
-
Ven+
-Vbn2
+
-
