APB4 GPIO Datasheet - Roa Logic · APB4 GPIO Datasheet ... The IO are accessible via an AMBA APB...

APB4GPIO

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APB4GPIODatasheet

APB4GPIO


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IntroductionThe APB4 GPIO Core is fully parameterised core designed to provide a user-definednumberofgeneralpurpose,bidirectionalIOtoadesign.

The IO are accessible via anAMBAAPB v2.0 Specification interface – typicallyreferredtoasAPB4–andthecoreoperatessynchronouslywiththerisingedgeoftheAPB4BusClock..

Inputs to the core may operate asynchronously to the core and will beautomatically synchronised to the bus clock. Outputs may be configured tooperateinpush-pullmodeoropen-drain.

Figure1:APB4GPIOSignalling

Features

• CompliantwithAMBAAPBv2.0Specification• User-definednumberofBi-directionalGeneralPurposeIO• AutomaticsynchronisationofGeneralInputstoBusClock• EachGeneralOutputconfigurableaspush-pulloropen-drain

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TableofContentsIntroduction...........................................................................................................2Features..................................................................................................................................................................21 GettingStarted.................................................................................................41.1 Deliverables..............................................................................................................................................41.2 Runningthetestbench.........................................................................................................................51.2.1 Self-checkingtestbench...................................................................................................................51.2.2 Makefilesetup......................................................................................................................................51.2.3 Makefilebackup..................................................................................................................................51.2.4 NoMakefile...........................................................................................................................................5

2 Specifications....................................................................................................62.1 FunctionalDescription.........................................................................................................................62.2 OperatingModes.....................................................................................................................................62.2.1 Push-PullMode....................................................................................................................................62.2.2 Open-DrainMode...............................................................................................................................72.2.3 PadInference.......................................................................................................................................7

3 Configurations..................................................................................................83.1 Introduction..............................................................................................................................................83.1 CoreParameters.....................................................................................................................................83.1.1 PDATA_SIZE..........................................................................................................................................83.1.2 INPUT_STAGES....................................................................................................................................8

3.2 Registers.....................................................................................................................................................83.2.1 INPUT......................................................................................................................................................93.2.2 OUTPUT..................................................................................................................................................93.2.3 DIRECTION............................................................................................................................................93.2.4 MODE.......................................................................................................................................................9

4 Interfaces........................................................................................................104.1 GlobalSignals........................................................................................................................................104.1.1 PRESETn...............................................................................................................................................104.1.2 PCLK.......................................................................................................................................................10

4.2 APB4(Peripheral)Interface...........................................................................................................114.2.1 PSEL.......................................................................................................................................................114.2.2 PENABLE..............................................................................................................................................114.2.3 PWRITE.................................................................................................................................................114.2.4 PSTRB....................................................................................................................................................114.2.5 PADDR...................................................................................................................................................114.2.6 PWDATA...............................................................................................................................................124.2.7 PRDATA................................................................................................................................................124.2.8 PREADY.................................................................................................................................................124.2.9 PSLVERR...............................................................................................................................................12

4.3 GPIOInterface.......................................................................................................................................124.3.1 GPIO_I....................................................................................................................................................124.3.2 GPIO_O...................................................................................................................................................124.3.3 GPIO_OE................................................................................................................................................12

5 Resources.......................................................................................................14

6 RevisionHistory..............................................................................................15

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1 GettingStarted1.1 DeliverablesAll IP isdeliveredasazipped tarball,whichcanbeunzippedwithall commoncompressiontools(likeunzip,winrar,tar,…).

Thetarballcontainsadirectorystructureasoutlinedbelow.

Figure2:IPDirectoryStructure

The doc directory contains relevant documents like user guides, applicationnotes,anddatasheets.

The rtl directory contains the actual IP design files. Depending on the licenseagreement the APB4 GPIO is delivered as either encrypted Verilog-HDL or asplain SystemVerilog source files. Encrypted files have the extension “.enc.sv”,plainsourcefileshavetheextension“.sv”.Thefilesareencryptionaccordingtothe IEEE-P1735 encryption standard. Encryption keys for Mentor Graphics(Modelsim,Questasim,Precision), Synplicity (Synplify, Synplify-Pro), andAldec(Active-HDL, Riviera-Pro) are provided. As such there should be no issuetargetinganyexistingFPGAtechnology.

Ifanyothersynthesisoranalysis tool isused thenaplainsourceRTLdeliverymay be needed. A separate license agreement andNDA is required for such adelivery.

Thebenchdirectorycontainsthe(encrypted)sourcefilesforthetestbench.

doc

rtl

verilog

sim

rtlsim

bin

run

bench

verilog

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Thesimdirectorycontainsthefiles/structuretorunthesimulations.Section1.2‘Runningthetestbench’providesforinstructionsonhowtousethemakefile.

1.2 Runningthetestbench

TheAPB4GPIOIPcomeswithadedicatedtestbenchthattestsallfeaturesofthedesign and finally runs a full random test. The testbench is started from aMakefilethatisprovidedwiththeIP.

The Makefile is located in the <install_dir>/sim/rtlsim/run directory. TheMakefile supports most commonly used simulators; Modelsim/Questasim,Cadencencsim,AldecRiviera,andSynopsysVCS.

To start the simulation, enter the <install_dir>/sim/rtlsim/run directory andtype: make <simulator>. Where simulator is any of: msim (formodelsim/questasim), ncsim (for Cadence ncsim), riviera (for Aldec Riviera-Pro), or vcs (for Synopsys VCS). For example typemake msim to start thetestbenchinModelsim/Questasim.

1.2.1 Self-checkingtestbench

The testbenches is a self-checking testbench intended tobe executed from thecommand line. There is no need for a GUI or a waveform viewer. Once thetestbenchcompletesitdisplaysasummaryandclosesthesimulator.

1.2.2 Makefilesetup

The simulator is executed in its associated directory. Inside this directory isanotherMakefilethatcontainssimulatorspecificcommandstostartandexecutethe simulation. The <install_dir>/sim/rtlsim/run/Makefile enters the correctdirectoryandcallsthesimulatorspecificMakefile.

For example modelsim is executed in the <install_dir>/sim/rtlsim/run/msimdirectory. Typingmakemsim loads themainMakefile,which then enters themsimsub-directoryandcallsitsMakefile. ThisMakefilecontainscommandstocompile the RTL and testbench sources with Modelsim, start the Modelsimsimulator,andrunthesimulation.

1.2.3 Makefilebackup

The <install_dir>/sim/rtlsim/bin directory contains backups of the originalMakefiles.ItmaybedesirabletomodifyorextendtheMakefilesortocompletelycleantherundirectory.Usethebackupstorestoretheoriginalsetup.

1.2.4 NoMakefile

For users unfamiliar with Makefiles or those on systems that do not nativelysupport make (e.g. Windows) a run.do file is provided that can be used withModelsim/QuestasimandRiviera-Pro.

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2 Specifications2.1 FunctionalDescriptionTheRoaLogicAPB4GPIOisaconfigurable,fullyparameterizedsoftIPtoenablegeneralconnectivitytoaAPB4basedMaster(Host)ItisfullycompliantwiththeAMBAAPBv2.0busprotocols.

TheIPcontainsasingleMasterInterfacetoconnecttotheAPB4Hostandauserdefined number of General Purpose IO, configurable as a bi-directional bus asshownbelow:

Figure3:BidirectionalIOPad

The core operates synchronously with the APB4 Bus Clock. Inputs may beasynchronoustothisbusclockandthereforetheimplementsconfigurablelengthsynchronisation

2.2 OperatingModes

ThecoresupportsbidirectionalIOpadsasshowninFigure3,whereeachIOmayoperate inapush-pulloropen-drainmode.Themodeofeach IO isdefinedviatheMODEregister–seesectionError!Referencesourcenotfound.

Note: IO Pads are not implemented within the APB4 GPIO core – thistechnologyspecificcapabilityistheresponsibilityofthedesigner.

2.2.1 Push-PullMode

Inpush-pullmode,theGPIO_ObusisdrivenfromaninternalOUTPUTregister(Seesection3.2.2)andGPIO_OEiscontrolledviatheDIRECTIONregister(SeesectionError!Referencesourcenotfound.).

Logicallythepush-pullmodeisconfiguredasfollows:

GPIO_OE

GPIO_O

GPIO_I

APB4

APB4 GPIO

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Figure4

2.2.2 Open-DrainMode

Inopen-drainmode,GPIO_Oisalwaysdrivenlow(‘0’)andindividualGPIO_OEsignals set to enable (i.e. Logic ‘0’) or high-Z (Logic ‘1’) at the output buffercorrespondingtothevalueoftheOUTPUTregister.

Figure5

2.2.3 PadInference

The inclusionof technology specific IOPads isnotpartof theAPB4GPIOcoreandinsteadlefttothedesigner.Padsmaybebehaviourallyinferredhoweverasfollows:

PAD[n] <= GPIO_OE[n] ? GPIO_O[n] : 1’bz;

GPIO_OE

GPIO_OIO Pad

INPU

TO

UTPU

TDI

RECT

ION

GPIO_I

GPIO_OE

GPIO_OIO Pad

INPU

T

‘0’

DIRE

CTIO

N

GPIO_I

OUT

PUT

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3 Configurations3.1 IntroductionThe Roa Logic AHB-Lite APB4 GPIO is a fully configurable General PurposeInput/Outputcore.Thecoreparametersandconfigurationoptionsaredescribedinthissection.

3.1 CoreParameters

Parameter Type Default DescriptionPDATA_SIZE Integer 8 APB4DataBus&GPIOSizeINPUT_STAGES Integer 3 NumberofGPIO_Iinput

synchronizationstagesTable3-1:CoreParameters

3.1.1 PDATA_SIZE

The PDATA_SIZE parameter specifies the width of the APB4 data bus andcorresponding GPIO interface width. This parameter must equal an integermultipleofbytes.

3.1.2 INPUT_STAGES

The APB4 GPIO inputs are sampled on the rising edge of the APB4 bus clock(PCLK). As these inputs may be asynchronous to the bus clock, the coreautomatically synchronises these signals and the INPUT_STAGES parameterdeterminesthenumberofsynchronisationstages.

Increasing this parameter reduces the possibility ofmetastability due to inputsignalschangingstatewhilebeingsampled,butatthecostofincreasedlatency.

TheminimumanddefaultvalueoftheINPUT_STAGESparameteris3

3.2 Registers

TheAPB4GPIOcoreimplements4useraccessibleregisters.Thesearedescribedbelow:

Register Address Access FunctionINPUT Base+0x3 ReadOnly InputDataStoreOUTPUT Base+0x2 Read/Write OutputDataStoreDIRECTION Base+0x1 Read/Write OutputEnablecontrolMODE Base+0x0 Read/Write Push-PullorOpen-DrainMode

Table3-2:UserRegisters

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3.2.1 INPUT

INPUT isaPDATA_SIZEbitswideread-onlyregisteraccessibleattheaddress0x3.

OntherisingedgeoftheAPB4BusClock(PCLK)inputdataonpinsGPIO_I issampled, synchronisedandstored in theINPUT registerwhere itmaybereadviatheAPB4BusInterface.

3.2.2 OUTPUT

OUTPUT is a PDATA_SIZE bits wide read/write register accessible at theaddress0x2.

DatatobetransmittedfromtheAPB4GPIOcoreviatheGPIO_O&GPIO_OEbusesiswrittenfromtheAPB4InterfacetotheOUTPUTregister.

3.2.3 DIRECTION

DIRECTIONisaPDATA_SIZEbitswideactive-highread/writeregister,accessibleattheaddress0x1,andcontrolstheoutputenablebusGPIO_OE.

DIRECTION[n] Direction0 Input1 Output

Table3-3:DIRECTIONRegister

3.2.4 MODE

MODEisaPDATA_SIZEbitswideRead/Writeregisteraccessibleattheaddress0x0. It individuallysets theoperatingmode foreachsignalof theGPIO_O andGPIO_OEbusesaseitherpush-pulloropendrain,asfollows:

MODE[n] OperatingMode0 Push-Pull1 OpenDrainTable3-4:MODERegister

In push-pull mode, data written to the OUTPUT register directly drives theoutput bus GPIO_O. TheDIRECTION register is then used to enable GPIO_O todrivetheIOpadwhensetto‘Output’mode(‘1’).

Inopen-drainmode,GPIO_Oispermanentlydrivenlow(‘0’)andtheOUTPUTregistersetsGPIO_OEto‘Output’toassertalogic‘0’onthebus,or‘Input’(i.e.High-Z)toassertalogic‘1’.

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4 InterfacesTheAPB4GPIOCore featuresa singleAPB4Slave interfaceandauser-definedGeneral Bidirectional Interface thet is typically connect to device IO Pads. Theindividualsignalsfortheseinterfacesareshownanddescribedbelow:

4.1 GlobalSignalsThefollowingsignalsarecommontoallsynchronouselementswithintheAPB4GPIOIP:

Port Size Direction DescriptionPRESETn 1 Input AsynchronousactivelowresetPCLK 1 Input ClockInput

Table4-1:GlobalSignals

4.1.1 PRESETn

When the active low asynchronousPRESETn input is asserted (‘0’), the APB4andGPIOinterfacesareputintotheinitialresetstate.

4.1.2 PCLK

PCLK is the APB4 interface system clock. All internal logic for the APB4GPIOoperatesattherisingedgeofthissystemclockandalltimingsarerelatedtotherisingedgeofPCLK.

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Figure4-1:APB4GPIOSignalInterfaces

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4.2 APB4(Peripheral)InterfaceTheAPB4InterfaceisaregularAPB4SlaveInterface.SeetheAMBAAPBProtocolv2.0Specificationsforacompletedescriptionofthesignals.

Port Size Direction DescriptionPSEL 1 Output PeripheralSelectPENABLE 1 Output PeripheralEnableControlPWRITE 1 Output WriteSelectPSTRB PDATA_SIZE/8 Output ByteLaneIndicatorPADDR 3 Output AddressBusPWDATA PDATA_SIZE Output WriteDataBusPRDATA PDATA_SIZE Input ReadDataBusPREADY 1 Input TransferReadyInputPSLVERR 1 Input TransferErrorIndicator

Table4-2:APB4PeripheralInterfacePorts

Note: The APB4 GPIO IP does not require data transfer protectionsupport, therefore the APB4 protocol signal PPROT is notimplemented.

4.2.1 PSEL

TheAPB4MastergeneratesPSEL,signallingtoAPB4GPIOperipheral that it isselectedandadatatransferispending.

4.2.2 PENABLE

TheAPB4MasterassertsPENABLEduring the2ndandsubsequentcyclesofanAPB4datatransfer.

4.2.3 PWRITE

PWRITEindicatesadatawriteaccesstotheAPB4GPIOwhenassertedhigh(‘1’)andareaddataaccesswhennegated(‘0’).

4.2.4 PSTRB

TheAPB4MasterdrivesonePSTRBsignalperbytelaneoftheAPB4writedatabus(PWDATA).Thesesignals indicatewhichbyte lanetoupdateduringawritetransfersuchthatPSTRB[n]correspondstoPWDATA[(8n+7):8n].

4.2.5 PADDR

PADDRistheAPB4addressbus.Onlythe3leastsignificantbits(PADDR[2:0])areconnectedtotheAPB4GPIOIP.

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4.2.6 PWDATA

PWDATA is the APB4write data bus and is driven by the APB4Master duringwrite cycles, indicatedwhenPWRITE is asserted (‘1’). The buswidthmust bebyte-alignedandisdefinedbythePDATA_SIZEparameter.

4.2.7 PRDATA

PRDATA istheAPB4readdatabus.TheAPB4GPIOdrivesthisbusduringreadcycles, indicated whenPWRITE is negated (‘0’). The bus widthmust be byte-alignedandisdefinedbythePDATA_SIZEparameter.

4.2.8 PREADY

PREADYistypicallyusedtoextendanAPB4transfer,howeverastheAPB4GPIOisalwaysreadythissignalisalwaysasserted.

4.2.9 PSLVERR

PSLVERR is used to indicate a failed data transfer. This functionality isunnecessary for the APB4 GPIO and an optional feature the AMBA APB v2.0Protocol. Therefore as requiredby theAMBAAPBv2.0 Specification theAPB4GPIOalwaysnegatesthissignal

4.3 GPIOInterface

Port Size Direction DescriptionGPIO_I PDATA_SIZE Input InputSignalsGPIO_O PDATA_SIZE Output OutputSignalsGPIO_OE PDATA_SIZE Output OutputEnableSignal

4.3.1 GPIO_I

GPIO_I is the input bus. The bus is PDATA_SIZE bits wide and each bit issampledon the risingedgeof theAPB4bus clockPCLK.As the inputsmaybeasynchronoustothebusclock,synchronisationisimplementedwithinthecore.Seesection3.1.2.

4.3.2 GPIO_O

GPIO_OistheoutputbusandisPDATA_SIZEbitswide.DataisdrivenontotheoutputbusontherisingedgeoftheAPB4busclockPCLK.

4.3.3 GPIO_OE

GPIO_OEisanactive-highOutputEnablebusandisPDATA_SIZEbitswide.

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ThespecificfunctionalityoftheGPIO_OEbusisdefinedbytheMODEregister.Inpush-pullmodeitisusedtoenableabidirectionaloutputbufferwhoseinputisdriventheGPIO_Obus

In open-drainmode theGPIO_OEbus is used to enable a logic ‘0’ tobedrivenfromtheGPIO_Obus,andalogic’1’bydisabling(‘High-Z’)theoutputbuffer.

Seesection2.2forfurtherinformation

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5 ResourcesBelowaresomeexampleimplementationsforvariousplatforms.

All implementations arepushbutton, no efforthasbeenundertaken to reduceareaorimproveperformance.

Platform DFF LogicCells

Memory Performance(MHz)

Table5-1:ResourceUtilizationExamples

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6 RevisionHistoryDate Rev. Comments 1.0

Table6-1:RevisionHistory

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