“I hereby declare that I have read this thesis and in my...

“I hereby declare that I have read this thesis and in my opinion this thesis is sufficient in

terms of scope and quality for the award of the degree of

Master of Engineering (Electrical - Electronics and Telecommunications)”

Signature :…………………………………………………

Name of Supervisor : Associate Professor Dr. Norsheila Binti Fisal

Date :…………………………………………………

TITLE PAGE

DESIGN OF AN OFDM TRANSMITTER AND RECEIVER USING FPGA

LOO KAH CHENG

A project report submitted in partial fulfillment of the

requirements for the award of the degree of

Master of Engineering (Electrical - Electronics and Telecommunications)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

NOVEMBER 2004

ii

DECLARATION

I declared that this thesis entitled “Design of an OFDM Transmitter and Receiver Using

FPGA” is the result of my own research except as cited in references. The thesis has not

been accepted for any degree and is not concurrently submitted in candidature of any

other degree.

Signature :…………………………………………………….

Name : Loo Kah Cheng

Date :…………………………………………………….

iii

DEDICATION

To my parent for their love.

iv

ACKNOWLEGEMENT

I wish to express my sincere appreciation to my thesis supervisor, Associate Professor

Dr. Norsheila Binti Fisal, for the guidance, encouragement, critics and care.

I wish to say thank you to Mr. Sharifuddin Sapoan for sharing his experience with me.

I would like to express my appreciation to my family for their support and

encouragement.

Thank you for all who have involved in helping me to complete this project.

v

ABSTRACT

Orthogonal Frequency Division Multiplexing (OFDM) is a multi carrier

modulation technique. OFDM provides high bandwidth efficiency because the carriers

are orthogonal to each others and multiple carriers share the data among themselves.

The main advantage of this transmission technique is their robustness to channel fading

in wireless communication environment. The main objective of this project is to design

and implement a base band OFDM transmitter and receiver using FPGA. This project

focuses on the core processing block of an OFDM system, which are the Fast Fourier

Transform (FFT) block and the Inverse Fast Fourier Transform (IFFT). The 8 points

IFFT / FFT decimation-in-frequency (DIF) with radix-2 algorithm is analyzed in detail

to produce a solution that is suitable for FPGA implementation. The FPGA

implementation of the project is performed using Very High Speed Integrated Circuit

(VHSIC) Hardware Descriptive Language (VHDL). This performance of the coding is

analyzed from the result of timing simulation using Altera Max Plus II.

vi

ABSTRAK

Orthogonal Frequency Division Multiplexing (OFDM) atau Pemultipleksan

Pembahagian Frekuensi Orthogonal adalah sejenis pemodulation pelbagai pembawa.

OFDM menyediakan kecekapan lebar jalur yang lebih tinggi kerana pemodulatan

pelbagai pembawa mempunyai ciri-ciri dimana setiap pembawa aalah ortoganal sesama

sendiri dan data di kongsi bersama setiap pembawa. Kebaikan utama jenis pemodulatan

pelbagai pembawa ini adalah ia tidak terjejas kepada channel fading dalam komunikasi

tanpa wayar. Tujuan utama projek ini adalah merekebentuk dan melaksanakan satu

penghantar (transmitter) and penerima (receiver) OFDM. menggunakan FPGA. Projek

ini tertumpu kepada struktur pemprosesan utama dalam satu OFDM system, iaitu, blok

Jelmaan Fourier Pantas atau Fast Fourier Transform (FFT) dan block Songsangan

Jelmaan Fourier Pantas atau Inverse Fast Fourier Transform (IFFT). 8 sampel blok

Jelmaan Fourier Pantas dan Blok Songsangan Jelmaan Fourier Pantas (IFFT)

menggunakan pembahagian dalam frekuensi (DIF) dengan pembahagian 2 atau radix-2

dikaji dengan teliti untuk menghasilkan satu kaedah yang sesuai untuk pelaksanaan

rekebentuk menggunakan FPGA. Komputer program ditulis menggunakan Very-High-

Speed-Integrated-Circuit (VHSIC) Hardware Descriptive Language (VHDL). Kod ini

diuji dan dianalisis dengan menggunakan keputusan daripada simulasi masa yang

dilaksanakan dengan menggunakan Altera Max Plus II.

vii

TABLE OF CONTENTS

TITLE PAGE i

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLE xi

LIST OF FIGURE xii

CHAPTER

1

TITLE

INTRODUCTION

PAGE

1

1.1 Digital Communication System Structure 1

1.2 Project Background 2

1.3 Project Objective 5

1.4 Project Scope 6

1.5 Project Outline 6

CHAPTER

2 LITERATURE REVIEW 8

2.1 Orthogonal Frequency Division Multiplexing 8

2.2 History of OFDM 8

2.3 Basic Mathematical Principle of OFDM System 10

2.4 Basic OFDM Implementation 12

viii

2.5 OFDM Advantages and Disadvantages 14

2.6 OFDM Applications 15

2.7 VHSIC Hardware Description Language

2.7.1 Synthesis Process in VHDL

16

17

2.8 Field Programmable Gate Arrays (FPGA) 18

2.9 Fast Fourier Transform (FFT) / Inverse Fast Fourier

Transform

20

2.10 Decimation-in-frequency (DIF) FFT algorithm 22

CHAPTER

3 IMPLEMENTATION OF AN OFDM TRANSMITTER

AND RECEIVER BASED ON 8-POINTS INVERSE FAST

FOURIER TRANSFORM (IFFT) AND FAST FOURIER

TRANSFORM (FFT) 26

3.1 Introduction 26

3.2 Algorithm of an 8-point Inverse Fast Fourier Transform

(IFFT)

3.2.1 Structural method of an 8-point IFFT

3.2.2 Direct Method of an 8-point IFFT

26

27

28

3.3 Implementation of an 8-point IFFT processor

3.3.1 Pass module of 8 point IFFT processor

3.3.2 Path 0 and Path 4 module of an 8 point IFFT

processor

3.3.3 Path 1, Path 3, Path 5, Path 7 modules of an 8 point

IFFT processor

33

34

35

36

3.4 Algorithm of an 8-point Fast Fourier Transform (FFT) 38

CHAPTER

4 RESUL OF VHDL SIMULATION 44

4.1 Introduction 44

4.2 FFT Processor Result 44

ix

4.2.1 Pass Module Simulation Result for FFT Processor

4.2.2 Path 0 and Path 4 Module Simulation Result for FFT

Processor

4.2.3 Path 2 and Path 6 Module Simulation Result for FFT

Processor

4.2.4 Path 1, Path 3, Path 5 and Path 7 Module Simulation

Result for FFT Processor

4.2.5 8-points FFT Simulation Result

45

47

50

53

58

4.3 IFFT Processor Result

4.3.1 Pass Module Simulation Result for IFFT Processor

4.3.2 Path 0 and Path 4 Module Simulation Result for IFFT

Processor

4.3.3 Path 2 and Path 6 Module Simulation Result for IFFT

Processor

4.3.4 Path 1, Path 3, Path 5 and Path 7 Module Simulation

Result for IFFT Processor

4.3.5 8-points IFFT Simulation Result

60

60

62

65

68

73

4.4 8-points FFT Simulation Result 75

CHAPTER

5 CONCLUSTION 78

5.1Conclustion 78

5.2 Challenges and Issues 79

5.3 Suggestion for Improvement 80

REFERENCE 81

APPENDIX A FFT VHDL IMPLEMENTATION FLOW

CHART

83

APPENDIX B IFFT VHDL IMPLEMENTATION FLOW

CHART

92

APPENDIX C VHDL SYNTHESIS CODE FOR FFT AND 101

x

IFFT PROCESSOR

xi

LIST OF TABLE

TABLE

NO.

TITLE PAGE

2.1 Symmetry properties of mW822

2.2 Computation of DFT in direct method and

decimation-in-frequency algorithm

25

3.1 Final equations for an 8-point IFFT processor 32

3.2 Symmetry properties of mW839

3.3 Final equations for an 8-point IFFT processor 43

4.1 Matlab FFT Simulation Output 76

4.2 Matlab IFFT Simulation Output 77

xii

LIST OF FIGURES

FIGURE

NO.

TITLE PAGE

1.1 Digital Communication Systems 1

1.2 OFDM Transmitter 2

1.3 OFDM Receiver 4

2.1 OFDM Structure 10

2.2 OFDM Transmission System 12

2.3 Synthesis Process in VHDL Environment 18

2.4 8-point DIF FFT flow chart 24

3.1 Single Butterfly Flow Chart in IFFT 27

3.2 Structural Implementation of IFFT 28

3.3 Stage 1 Computation Flow Chart of an 8-point IFFT

Computation

29


Computation

30


Computation

31

3.6 Block diagram of an 8 point IFFT processor 33

3.7 8-point FFT flow chart 39

3.8 Stage 1 Computation Flow Chart of an 8-point FFT

Computation

40

3.9 Stage 2 Computation Flow Chart of an 8-point FFT

Computation

41

3.10 Stage 3 computation flow chart of an 8-point IFFT 42

xiii

Computation

4.1 Pass Module Simulation Output for FFT Processor 46

4.2 Path 0 Module Simulation Output for FFT Processor 48








4.10 FFT Processor Output 59

4.11 Pass Module Simulation Output for IFFT Processor 61

4.12 Path 0 Module Simulation Output for IFFT Processor 63








4.20 IFFT Processor Output 74

CHAPTER 1

INTRODUCTION

1.1 Digital Communication System Structure

A digital communication system involves the transmission of information in

digital form from one point to another point as shown in Figure 1.1

1. 1Figure 1.1 Digital Communication Systems

2

Regardless of the form of communication method, the three basic elements in a

communication system consist of transmitter, channel and receiver.

The source of information is the messages that are to be transmitted to the other

end in the receiver. A transmitter can consist of source encoder, channel encoder and

modulation. Source encoder employed an efficient representation of the information

such that resources can be conserved. A channel encoder may include error detection

and correction code. The aim is to increase the redundancy in the data to improve the

reliability of transmission. A modulation process convert the base band signal into band

pass signal before transmission.

During transmission, the signal experiences impairment which attenuates the

signals amplitude and distort signals phase. Also, the signals transmitting through a

channel also impaired by noise, which is assumed to be Gaussian distributed component.

In the receiver end, the reversed order of the steps in the transmitter is

performed. Ideally, the same information must be decoded in the receiving end.

1.2 Project Background

Figure 1.2 and 1.3 show a detailed OFDM transmitter and receiver

communications system. In this project, the main focus is in the FFT and IFFT part of

the OFDM system.

Figure 1.2 OFDM Transmitter

3

The input symbols are input into the transmitter in series at R symbols/second.

These symbols pass through a serial to parallel converter and output data on M lines in

parallel. The data rate on every M line is R/M symbols/second.

A symbol in this parallel stream of data is denoted as Xi,k. The index i refer to

which sub channel the symbol belongs to, and i ranges from 1 to M. The k denotes the

k-th collection of M symbols. The sub symbol collection from X1,k to XM,k makes up an

OFDM symbol.

The M symbols are sent to an Inverse Fast Fourier Transform (IFFT) block that

performs N-point IFFT operation. The IFFT transform a spectrum (amplitude and phase

of each component) into a time domain signal. An IFFT converts a number of complex

data points, of length that is power of 2, into the same number of points in time domain.

Each data point in frequency spectrum used for an FFT or IFFT operation is called a bin.

The output is N time-domain samples.

In order to preserve the sub-carrier orthogonality and the independence of

subsequent OFDM symbols, a cyclic guard interval is introduced. Time and frequency

synchronization can be established by means of cyclic extension in the prefix and the

postfix period.

In this case, assumed a cyclic prefix of length Lp samples is pre-pended to the N

samples to form a cyclically extended OFDM symbol. The cyclic prefix is simply the

last Lp samples of the N inverse Fast Fourier Transform output samples.

For example, assumed N=4 and Lp=2. If the outputs of a 4 point inverse Fourier

transform is [1 2 3 4]. The cyclic prefix will be [3 4]. The cyclically extended symbol

would be [3 4 1 2 3 4]. Therefore, the length of the transmitted OFDM symbol is N+

Lp.

4

Pre-pending the cyclic prefix aids in removing the effects of the channel at the

receiver. ISI can occur when multi path channel cause delayed version of previous

OFDM symbol to corrupt the current received symbol. If the value of Lp is greater than

or equal to the size of the transmission channel, the ISI will only affect the cyclic prefix.

The actual OFDM symbol will arrive unchanged.

The cyclic prefix makes the OFDM symbol appear periodic over the band of

interest. The cyclically extended symbols are passed through a parallel-to-serial

converter. They are transmitted in series across the channel response of the OFDM

symbol with the frequency response of the channel.

Figure 1.3 OFDM Receiver

The received symbol is in time domain and it is distorted due to the effect of the

channel. The received signal goes through a serial to parallel converter and cyclic prefix

removal.

After the cyclic prefix removal, the signals are passed through an N-point fast

Fourier transform to convert the signal to frequency domain. The output of the FFT is

formed from the first M samples of the output.

5

1.3 Project Objective

The project aim is to design an OFDM transmitter and receiver using FPGA.

The OFDM signal is generated by implementing the Inverse Fast Fourier Transform

(IFFT) function at the transmitter. At the receiver end, the Fast Fourier Transform

(FFT) is implemented.

The objective of this project is to use High-Speed-Integrated-Circuit (VHSIC)

Hardware Description Language (VHDL) to produce VHDL code that carry out FFT

and IFFT function.

The synthesis tool utilized is Altera Max Plus II to map the design to targeted

device. Validation of the result and timing simulation are also using Altera Max Plus II.

The main challenge in this project is to derive the algorithm that is to be used in

this project, for example, the algorithm for Fast Fourier Transform (FFT) and Inverse

Fast Fourier Transform (IFFT). There are many algorithms available that can

implement FFT / IFFT.

Second, the author finds it is very challenging on how software algorithm may

be mapped to hardware logic. After the simulation result is verified, the process of

converting the software statement into VHDL code is a major task. A variable may

correspond to a wire or a register depending on its application and sometimes an

operator can be mapped to hardware like adder, latches, multiplexers etc.

6

1.4 Project Scope

The scope of the project is focuses on the design and implementation of OFDM

base band transmitter and receiver. This project focuses on the core processing block of

the transmitter and receiver, which is the IFFT and FFT block. This design computes 8-

points IFFT and implements 8 inputs of real binary bits. The design will discuss on

optimization of computational time by using the direct mathematical derivation method.

The implementation of the IFFT and FFT block is using VHDL code. The

computation is done in separate sub modules for each output. Each sub module

computes a single output path. The combination of eight sub modules produces the

complete design of 8 points IFFT and FFT.

1.5 Project Outline

The project is organized into five chapters, namely introduction, literature

review, implementation of an OFDM transmitter and receiver based on 8- points inverse

Fast Fourier Transform and Fast Fourier Transform, result of VHDL simulation and

Conclusion.

Chapter 1 discusses the general idea of the project which cover the overview,

project objective, project background and scope of the project.

Chapter 2 shows the literature review of the OFDM system. The history and

principle of the OFDM system, Fast Fourier Transform introduction and VHDL

programming basic introduction is elaborate in this chapter.

7

Chapter 3 derives the Fast Fourier Transform and Inverse Fourier Transform

algorithm using direct mathematical method. The equations are optimized for digital

implementation.

Chapter 4 shows the VHDL simulation output. The results are presented in their

sub-modules and then all the modules are combined to give the final output. Then, the

VHDL output are compared with Matlab simulation output.

Chapter 5 consists of conclusion, problems encountered in completing this

project and suggestion to further improve this project.

CHAPTER 2

LITERATURE REVIEW

2.1 Orthogonal Frequency Division Multiplexing

OFDM system has inherent advantage over single carrier system in frequency-

selective fading channel. It has been adopted by various standards in recent years

including DSL and 802.11a wireless LAN standards. The principle of operation of

OFDM system is described in the chapter. The advantages of OFDM transmission are

discussed. Programmable logic devices (PLDs) playing a major role in implementing

OFDM system because making it easier for engineers to integrate complex intellectual

property (IP) blocks and utilize the benefits of high performance PLD architecture.

2.2 History of OFDM

OFDM can be viewed as a collection of transmission techniques. When this

technique is applied in wireless environment, it is referred as OFDM. In the wired

environment, such as asymmetric digital subscriber lines (ADSL), it is referred as

discrete multi tone (DMT). In OFDM, each carrier is orthogonal to all other carriers.

However, this condition is not always maintained in DMT [1]. OFDM is an optimal

version of multi carrier transmission schemes.

9

OFDM started in the mid 60’s, Chang [2] proposed a method to synthesis band

limited signals for multi channel transmission. The idea is to transmit signals

simultaneously through a linear band limited channel without inter channel (ICI) an inter

symbol interference (ISI).

After that, Saltzberg [3] performed an analysis based on Chang’s work and he

conclude that the focus to design a multi channel transmission must concentrate on

reducing crosstalk between adjacent channels rather than on perfecting the individual

signals.

In 1971, Weinstein and Ebert [4] made an important contribution to OFDM.

Discrete Fourier transform (DFT) method was proposed to perform the base band

modulation and demodulation. DFT is an efficient signal processing algorithm. It

eliminates the banks of sub carrier oscillators. They used guard space between symbols

to combat ICI and ISI problem. This system did not obtain perfect orthogonality

between sub carriers over a dispersive channel.

It was Peled and Ruiz [5] in 1980 who introduced cyclic prefix (CP) that solves

the orthogonality issue. They filled the guard space with a cyclic extension of the

OFDM symbol. It is assume the CP is longer than impulse response of the channel.

10

2.3 Basic Mathematical Principle of OFDM System

2. 2

Figure 2.1 OFDM Structure

In the analog version of OFDM system, the base band transmits an OFDM signal

through i-th sub carrier in t=ts is

otherwisets

TtttttTi

jts ss

N

Ni

sNid

0)(

}2exp[{)(1

2

2

2 (Equation 1)

where,

di = Symbol-mapped symbol of the i-th sub-channel at time interval [ Tttt ss ]

N = Number of sub channel

T = OFDM symbol duration

When the k-th sub carrier is demodulated by down converting the signal with a

frequency k/T and then integrating the signal over T seconds, the result can be written as

11

Td

dtttT

kijd

dtttT

ijtt

T

kj

Ni

s

Tt

t

N

Ni

Ni

N

Ni

sNi

Tt

t

s

s

s

s

s

d

2

2

22

12

2

2

)(2exp(

]2exp[)[(2exp(

(Equation 2)

A complex carrier is integrated over T seconds. When i is equal to k, the

integration give the desired output Td Ni

2

. For all other sub carriers, the integration is

zero.

The discrete version of OFDM system model using IDFT (IFFT) and DFT (FFT)

is shown below.

The IDFT output sequence of an OFDM symbol

1

0

)/2exp(1 N

iin NnijX

Nx (Equation 3)

The IDFT sequence of infinite OFDM symbol is

1

0,, )/2exp(

1 N

ili

nln NnijX

Nx (Equation 4)

where,

Xi = data mapped

12

The DFT output sequence of a received OFDM symbol is

)/)(2exp(]1

[

)/2exp(]/2exp(1

[

)/2exp(

1

0

1

0

1

0

1

0

1

0

'

NkinjXN

NnkjNnijXN

NnijxY

N

n

N

ii

N

n

N

ii

N

ink

(Equation 5)

if i=k,

kk

N

n

N

ii

XXN

N

NnjXN

Yk

1

)/)0(2exp(]1

[1

0

1

0 (Equation 6)

if i is not equal to k, 0k

Y

2.4 Basic OFDM Implementation

Figure 2.2 OFDM Transmission System

13

Figure 2.2 shows the block diagram of a OFDM transmission system. This is a

digital implementation of OFDM sub carrier modulator / demodulators based on discrete

Fourier transform (DFT). The number of sub carrier can be changed. This model is

suggested by [6].

The serial data stream is mapped to symbols with a symbol rate of 1/Ts using

modulation scheme like M-PSK, QAM. The resulting symbol stream is de-multiplexed

into N data symbols So to SN-1 (in this example). The parallel data symbol rate is 1/NTs.

This means the parallel symbol duration is N times longer than the serial symbol

duration Ts. The inverse FFT (IFFT) of the data symbol is computed and the output s0 to

sN-1 constitute an OFDM symbol. This symbol period is transmitted serially over the

channel with symbol rate of 1/Ts.

At the receiver, the received time domain symbols are decomposed by

employing FFT operation, the recovered data symbols are restored in serial order.

Assume the OFDM spectrum is finite, the corresponding time domain signal has

an infinite duration. Recall, the DFT operation assume the signal is periodic for infinite

duration. However, in practice, it is sufficient to repeat the time domain signal

periodically for the duration of channel delay spread [6]. Hence, for transmission over

dispersive channels, each time domain OFDM symbol is extended by cyclic extension

or guard interval of Ng samples duration in order to overcome ISI due to channel delay

spread. The disadvantage of cyclic extension is it’s reducing the OFDM transmission

rate by N/(N+Ng) assuming the transmission rate is N.

14

2.5 OFDM Advantages and Disadvantages

The major advantage of OFDM is its robustness against multi path propagation.

Thus, it is suitable to be implemented in wireless environments. The introduction of

cyclic prefix made OFDM system resistance to time dispersion. OFDM symbol rate is

low since a data stream is divided into several parallel streams before transmission.

This make the fading is slow enough for the channel to be considered as constant during

one OFDM symbol interval.

Cyclic prefix is a crucial feature of OFDM used to combat the inter-symbol-

interference (ISI) and inter-channel-interference (ICI) introduced by the multi-path

channel through which the signal is propagated. The basic idea is to replicate part of the

OFDM time-domain waveform from the back to the front to create a guard period. The

duration of the guard period Tg should be longer than the worst-case delay spread of the

target multi-path environment. The use of a cyclic prefix instead of a plain guard

interval, simplifies the channel equalization in the demodulator.

In wire system, OFDM system can offer an efficient bit loading technique. It

enables a system to allocate different number of bits to different sub channels based on

their individual SNR. Hence, an efficient transmission can be achieved.

One of the major disadvantages of OFDM is its requirement for high peak-to-

average-power ratio. This put high demand on linearity in amplifiers.

Second, the synchronization error can destroy the orthogonality and cause

interference. Phase noise error and Doppler shift can cause degradation to OFDM

system. A lot of effort is required to design accurate frequency synchronizers for

OFDM.

15

2.6 OFDM Applications

Initially, OFDM applications are scarce because of their implementation

complexity. Now, OFDM has been adopted as the new European digital audio

broadcasting (DAB) standard and for terrestrial digital video broadcasting (DVB) [6].

In fixed-wire applications, OFDM is employed in asynchronous digital

subscriber line (ADSL) and high bit-rate digital subscriber line (HDSL) systems. It has

been proposed for power line communications systems as well due to its resilience to

dispersive channel and narrow band interference.

Here is a brief discussion on 4 applications that has incorporated OFDM

technique [7]:

Digital Audio Broadcasting (DAB)

DAB is the first standard to use OFDM. DAB network is efficient in handling

multipath delay spread. As a result, improved CD quality sound, new data services and

higher spectrum efficiency can be achieved.

Terrestrial Digital Video Broadcasting (DVB)

DVB was created by a pan-broadcasting-industry group in 1993. DVB defined a

set of specifications for delivery of digital television over cable, DSL, and satellite. In

1997, Digital Terrestrial Television Broadcasting (DTTB) was standardized. It utilizes

OFDM system in the 2000 and 8000 sub carrier modes.

16

Magic WAND

Magic WAND (Wireless ATM Network Demonstrator) is a wireless OFDM-

based ATM network. This system operates in 5 GHz band is gaining acceptance for

OFDM in high-rate wireless communications. It also acts as basis for HiperLAN2.

IEEE802.11a/HiperLAN2 and MMAC Wireless LAN

All the above system operates in 5GHz band. 802.11a is selected by IEEE to be

used in US targeting a range of data rates up to 54 Mbps.

ETSI BRAN in Europe is working on 3 extensions for OFDM in HiperLAN

standard: (i) HiperLAN2, a wireless indoor LAN with a QoS provision; (ii) HiperLink, a

wireless indoor backbone; and (iii) HiperAccess, an outdoor fixed wireless network

providing access to a wired infrastructure.

MMAC is developed by Japan. It is a standard similar to IEEE and ETSI BRAN.

2.7 VHSIC Hardware Description Language

VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit)

Hardware Description Language. It is intended for documenting and modeling digital

systems ranging from a small chip to a large system. It can be used to model a digital

system at any level of abstraction ranging from the architectural level down to the gate

level.

17

VHDL language can be regarded as an integration of the following languages

[10],

Sequential Language

Concurrent Language

Net list Language

Timing Specifications

Waveform Generation

It allows user to model the system as an interconnection of components. Test

waveforms can be generated using the same constructs. All the above constructs may be

combined to provide a comprehensive description of the system in a single model.

The models written in VHDL can be verified using a VHDL simulator [11]. It

inherits extensive range of modeling capabilities that are difficult to understand.

Fortunately, it is possible to quickly assimilate a core subset of the language that is easy

and simple to understand without learning the complex features. This subset is

sufficient to model most applications. The complete language has sufficient power to

capture the description of the most complex chips to a complete electronics system.

2.7.1 Synthesis Process in VHDL

VHDL is a hardware description language that allows designers to model a

circuit at different level of abstraction, ranging from the gate level, RTL level,

behavioral level to the algorithmic level.

Synthesis process is to construct a gate-level net list from a model of a circuit

described in VHDL. The synthesis process is described in diagram below.

18

Figure 2.3 Synthesis Process in VHDL Environment

A synthesis program may alternately generate a RTL net list, which is consists of

register-transfer level blocks such as flip-flops, arithmetic-logic-units, an multiplexers

interconnected by wires. All these are performed by RTL module builder. This builder

is to build or acquire from a library predefined components, each of the required RTL

blocks in the user-specified target technology.

The above synthesis process produced an unoptimized gate level net list. A logic

optimizer can used the produced net list and the constraint specified to produce an

optimized gate level net list. This net list can be programmed directly into a FPGA chip.

2.8 Field Programmable Gate Arrays (FPGA)

By modern standards, a logic circuit with 20000 gates is common. In order to

implement large circuit, it is convenient to use a type of chip that has a large logic

capacity. A field-programmable gate arrays (FPGA) is a programmable logic device that

19

support implementation of relatively large logic circuits. FPGA is different from other

logic technologies like CPLD and SPLD because FPGA do not contain AND or OR

planes. Instead, FPGA consists of logic blocks for implementing required functions.

A FPGA contain 3 main types of resources: logic blocks, I/O blocks for

connecting to the pins of the package, and interconnection wires and switches. The logic

blocks are arranged in a two-dimensional array, and the interconnection wires are

organized as horizontal and vertical routing channels between rows and columns of

logic blocks. The routing channels contain wires and programmable switches that allows

the logic blocks to be interconnected in many ways. FPGA can be used to implement

logic circuits of more than a few hundred thousands equivalent gates in size. Equivalent

gates is a way to quantify a circuit’s size by assume the circuit is to be built using only

simple logic gates and then estimate how many of these gates are needed.

Each logic block in a FPGA typically has a small number of inputs and one

output. The FPGA products on the market feature different types of logic blocks. The

most commonly used logic block is a lookup table (LUT), which contains storage cells

that are used to implement a small logic function. Each cell is capable of holding a

single logic value, either 0 or 1. The stored value is produced as the output of the storage

cell. LUT of various sizes may be created, where the size is defined by the number of

inputs.

For a logic circuit to be realized in a FPGA, each logic function in the circuit

must be small enough to fit within a single logic block. In practice, a user’s circuit is

automatically translated into the required form by using CAD tools. When a circuit is

implemented in an FPGA, the logic blocks are programmed to realize the necessary

functions and the routing channels are programmed to make the required

interconnections between logic blocks.

20

FPGA is configured by using the in-system programming (ISP) method, the

FPGA can be programmed while the chip is still attached to its circuit board. The

storage cells in the LUTs in an FPGA are volatile, which means that they lose their

stored contents whenever the power supply for the chip is turned off. Hence the FPGA

has to be programmed every time power is applied. Of this, a small memory chip that

holds its data permanently, called a programmable read-only memory (PROM) is

included on the circuit board that houses the FPGA. The storage cells in the FPGA are

loaded automatically from the PROM when power is applied to the chips.

2.9 Fast Fourier Transform (FFT) / Inverse Fast Fourier Transform

The FFT/IFFT operates on finite sequences. Waveforms which are analog in

nature must be sampled at discrete points before the FFT/IFFT algorithm can be applied.

The Discrete Fourier Transform (DFT) operates on sample time domain signal

which is periodic. The equation for DFT is:

NkjN

n

enxkX /21

0

)()( (Equation 7)

X(k) represent the DFT frequency output at the k-the spectral point where k

ranges from 0 to N-1. The quantity N represents the number of sample points in the

DFT data frame. The quantity x(n) represents the n-th time sample, where n also ranges

from 0 to N-1. In general equation, x(n) can be real or complex.

The corresponding inverse discrete Fourier transform (IDFT) of the sequence

X(k) gives a sequence x(n) defined only on the interval from 0 to N-1 as follows:

21

NkjN

k

ekXN

nx /21

0

)(1

)( (Equation 8)

The DFT equation can be re-written into:

1

0

)()(N

n

nkNWnxkX (Equation 9)

The quantity is defined as: nkNW

NnkjnkN eW /2

This quantity is called twiddle factor. It is the sine and cosine basis functions

written in polar form [13].

Examination of the first equation reveals that the computation of each point of

DFT requires the following computation. (N-1) complex multiplication, (N-1) complex

addition (first term in sum involves ej0=1). Thus, to compute N points in DFT require

N(N-1) complex multiplication and N(N-1) complex addition.

As the N increases, the number of multiplications and additions required is

significant because the multiplication function requires a relatively large amount of

processing time even using computer. Thus, many methods for reducing the number of

multiplications have been investigated over the last 50 years [12]. The next section

discussed in detail one of the method made popular by Cooley and Tukey.

The twiddle factor is the sine and cosine basis functions. By taking the

advantage of the symmetry and periodicity of the twiddle factors as shown:

22

rN

NrN

rN

Nr

N

WW

WW 2

The twiddle factor for N= 8 is calculated as shown in Table 2.1

Table 2.1 Symmetry properties of mW8

m mW8

0 +1

1 +0.7071 – j0.7071

2 -j

3 -0.7071 +j 0.7071

4 -1

5 -0.7071 + j0.7071

6 +j

7 0.7071-j0.7071

2.10 Decimation-in-frequency (DIF) FFT algorithm

In the decimation-in-frequency algorithm, the output or frequency points are

regrouped or subdivided. Consider the DFT equation

1

0

)()(N

n

nkNWnxkX (Equation 9)

The DFT equation 9 can be divided into first half and last half in the following

manner.

23

1

2

12

0

)()()(N

Nn

knN

N

n

knN WnxWnxkX (Equation 10)

12

0

)2

(1

2

0

)2

()()(

N

n

Nnk

N

N

n

knN W

NnxWnxkX

12

0

2/

12

0

)2

()()(

N

n

knN

NkN

N

n

knN W

NnxWWnxkX (Equation 11)

12

0

)]2

()1()([)(

N

n

nkN

k WN

nxnxkX (Equation 12)

Now, consider k as even and odd separately. Let k=2r (even) and k=(2r+1)

(odd).

12

0

2)]2

()([)2(

N

n

nrNW

NnxnxrX (Equation 13)

12

0

)12()]2

()([)12(

N

n

nrNW

NnxnxrX (Equation 14)

Given

nN

nrN

nrN

nrN

nrN

WWW

WW

2/)12(

2/2

Equation 13 and Equation 14 can be simplified into:

12

02/)]

2()([)2(

N

n

nrNW

NnxnxrX

12

02/)]

2()([)12(

N

n

nN

nrN WW

NnxnxrX

The above 2 equations are recognized as (N/2)-point DFT. The (N/2)-point DFT

can be subdivided until only two points are left in each DFT. The resulting flow graph

24

for this method for 8-point data is shown in Figure 2.4. Since the outputs were

subdivided to obtain this algorithm, it is referred to as decimation-in-frequency (DIF)

FFT algorithm.

x(0)

x(1)

x(2)

x(4)

x(5)

x6)

x(7)

x(8)

X(0)

X(4)

X(2)

X(6)

X(1)

X(5)

X(3)

X(7)

-1

-1

-1

-1

-1

-1

-1

-1 -1

-1

-1

-1

0NW

0NW

0NW

0NW

0NW

0NW

0NW

2NW

2NW

2NW

1NW

3NW

Figure 2.4 8-point DIF FFT flow chart

It is clear from Figure 2.4 that computation is carried out in three stages for N=8

and each stage requires 4 multiplication and hence a total of 12 complex multiplications

are required. In general, for N point sequence there is log2 N stages and each stage

requires N/2 complex multiplication hence a total of N/2 log2 N complex multiplications

are required. Number of additions required is N log2 N. Comparison on the computation

basis between the direct method and decimation-in-frequency is given in Table 2.1.

25

Table 2.2 Computation of DFT in direct method and decimation-in-frequency algorithm

Direct Method Decimation-in-frequency FFT N Complex

multiplications N(N-1)

Complex additionsN(N-1)

Complex multiplications

N/2 log2 N

Complex additionsN log2 N

4 12 12 4 88 56 56 12 24

16 240 240 32 6432 992 992 80 160

As can be seen from Table 2.2, it is obvious that DIF FFT algorithm achieves

considerable reduction in the computation of DFT.

CHAPTER 3

IMPLEMENTATION OF AN OFDM TRANSMITTER AND RECEIVER BASED

ON 8-POINTS INVERSE FAST FOURIER TRANSFORM (IFFT) AND FAST

FOURIER TRANSFORM (FFT)

3.1 Introduction

This section discusses the approach and method that is chosen to design the core

processing block in an OFDM transmitter. The computational time between DFT and

FFT is faster using FFT method because the number of multiplications and additions

operation in FFT is less compared to DFT method as shown in Table 2.2. The FFT and

IFFT operation are almost identical except for scaling and conjugation of the twiddle

factor. Thus, it is assumed the computational time between FFT and IFFT is same.

There are two methods to implement the OFDM transmitter, namely structural method

and direct computation method. Both methods will be discussed in the following

section.

3.2 Algorithm of an 8-point Inverse Fast Fourier Transform (IFFT)

The core processing block in an OFDM transmitter is the Inverse Fast Fourier

Transform. The IFFT can be implemented using 2 methods, structural method or direct

mathematical method.

27

3.2.1 Structural Method of an 8-point IFFT

Structural method implements a single butterfly computation.

3. 3

Figure 3.1 Single Butterfly Flow Chart in IFFT

In the digital implementation of an IFFT operation, the single butterfly

computation is implemented in the data path unit. A control unit controlling the data

path and determine the stage of operations. The control unit coordinates the appropriate

pairs of inputs into the butterfly computation and the output pairs is store in the memory.

Each pair of random input bits will undergo multiples of butterfly computation in stage

1. Assume the input string bits are x0, x1, x2, x3, x4, x5, x6, and x7 respectively, Stage

1 computation will store its result in certain memory location, assume memory A.

At stage 2, the result in memory A is feed into butterfly computation in paris.

The control unit acts as a selector to select the correct input for the butterfly

computation in every stage. The output from Stage 2 is stored in the same memory

location

For 8-point IFFT, the process ends at Stage 3. The output of the Stage 2 is

divided by 8 and the final output is the computed Inverse Fast Fourier Transform.

28

x(0)

x(1)

x(2)

x(4)

x(5)

x6)

x(7)

x(8)

X(0)

X(4)

X(2)

X(6)

X(1)

X(5)

X(3)

X(7)

-1

-1

-1

-1

-1

-1

-1

-1 -1

-1

-1

-1

0NW

0NW

0NW

0NW

0NW

0NW

0NW

-2NW

-2NW

-2NW

-1NW

-3NW

Stage 1 Stage 2 Stage3

Memory location A Memory location A

÷8

÷8

÷8

÷8

÷8

÷8

÷8

÷8

Figure 3.2 Structural Implementation of IFFT

3.2.2 Direct Method of an 8-point IFFT

In the direct method, the final output is derived from the input directly. In a

structural method, the single butterfly and summation has to be carried out 12 times for

an 8-point IFFT. The multiplication and summation has to be carried out, although the

twiddle factor has value of 0 or 1. This introduces redundancy in the implementation.

29

For example, the implementation of structural approach is X=(0)a+(1)b, where

in the direct mathematical approach, the implementation is simply X=b. Multiplication

of the twiddle factor is skipped to avoid redundancy in and reduce computation time.

Thus, this method is optimized.

In the Figure 3.2, it is shown that there are 3 stages in an 8-point IFFT. Stage 1

accepts the input data directly. The Figure 3.3 shows the computation in Stage 1.

Figure 3.3 Stage 1 Computation Flow Chart of an 8-point IFFT Computation

It is shown the even samples and odd samples are processed separately. The

outputs of Stage 1 are feed as the inputs of the Stage 2. Stage 2 computation take place

and this process repeats at the final stage, Stage 3.

30

The output of Stage 1 is connected to the input of Stage 2. The complexity of

the output equations increases as the Stage number increases because twiddle factor

computations are involved. The twiddle factor includes multiplication and additions

operations.

The Figure 3.4 shows the Stage 2 computation. The even inputs are grouped

together and summed up in pairs. The other inputs are multiplied with their respective

twiddle factor. Each of these inputs will undergo butterfly operation. Some of the

outputs will have to multiply again with the twiddle factor. The outputs of the Stage 2

are fed into Stage 3. At Stage 3, the butterfly computations are repeated. The

computations complexity is increased.


31


The final output equations derived from Figure 3.5 is shown as below (before

divide 8):

32

The final equations that are implemented using VHDL to produce an 8-point

IFFT processor is shown Table 3.1. The equations have been optimized for an efficient

implementation. The twiddle factors are represented b 8 bit binary number. There will

be slight error percentage in this design due to the approximation of the twiddle factor

values.

Table 3.1 Final equations for an 8-point IFFT processor

X(0)=x(0)+ x(4)+ x(2)+ x(6)+ x(1)+ x(5)+ x(3)+ x(7)

X(4)=x(0)+ x(4)+ x(2)+ x(6)- x(1)- x(5)- x(3)- x(7)

X(2)=x(0)+ x(4)- x(2)- x(6)+ jx(1)+ jx(5)- jx(3)- jx(7)

X(6)=x(0)+ x(4)- x(2)- x(6)- jx(1)- jx(5)+ jx(3)+ jx(7)

X(1)=x(0)- x(4)+ jx(2)- jx(6)+ 0.7071x(1)+ j0.7071x(1)- 0.7071x(5)- j0.7071x(5)- 0.7071x(3)- j0.7071x(3)

+ 0.7071x(7)+ j0.7071x(7)

X(5)=x(0)- x(4)+ jx(2)- jx(6)- 0.7071x(1)- j0.7071x(1) + 0.7071x(5)+ j0.7071x(5)

+ 0.7071x(3)+ j0.7071x(3)- 0.7071x(7)- j0.7071x(7)

X(3)=x(0)- x(4)- jx(2)- jx(6)- 0.7071x(1)+ j0.7071x(1) + 0.7071x(5)- j0.7071x(5)

+ 0.7071x(3)- j0.7071x(3)- 0.7071x(7)+ j0.7071x(7)

X(7)=x(0)- x(4)- jx(2)- jx(6)+ 0.7071x(1)- j0.7071x(1)- 0.7071x(5)+ j0.7071x(5)- 0.7071x(3)+ j0.7071x(3)

+ 0.7071x(7)- j0.7071x(7)

33

3.3 Implementation of an 8-point IFFT processor

The implementation of an 8 point IFFT processor involved few modules. All

this modules are combined together to produce an 8 point IFFT processor. Figure 3.5

shows an 8 point IFFT block diagram and their interconnections.

Figure 3.6 Block diagram of an 8 point IFFT processor

This figure shows the complete functional block diagram where the inputs are

passed into the design synchronously at every positive egde triggered. Then, the path

module shows the arithmetic computation for each respective output.

In the IFFT algorithm (generally), the even and odd outputs are computed

separately in two main groups. The odd output blocks computation is more complex

compared to the even group computation. The odd output computations are represented

34

by Path 1, Path 3, Path 5 and Path 7. The even output computations are Path 0, Path 2,

Path 4 and Path 6.

In the even outputs, the twiddle factor at the output equations has been

simplified. The detailed block diagram of each sub-module is shown in the Appendix B.

In the sub-modules, few digital circuitries are implemented. The most important

components are adder, subtractor and unsigned divider. Multiplexers are used to

approximate the decimal values to the nearest integer. They are also used to convert the

summation to unsigned numbers which are connected to the divider. If the signed bit is

‘1’, then the quotient value will be converted into unsigned number. Conversion of

signed and unsigned numbers is not required for positive summation values.

The input range is from -15 to 15 to avoid overflow from occurring in Xout(0).

The maximum summation (before division) value which can be supported ranges from -

128 to +127. Any value which exceeds this range will contribute to overflow problem.

3.3.1 Pass module of 8 point IFFT processor

This module passes the inputs to the sub-modules that do the IFFT computations.

The Pass module consists of 8 D flip flop registers. The outputs of this block are 8 lines

of 8 bit output which are connected to Path 0, Path 1, Path 2, Path 3, Path 4, Path 5, Path

6 and Path 7.

The programming flowchart for this block is shown in Appendix B.

35

3.1.1 Path 0 and Path 4 module of 8 point IFFT processor

The function of Path 0 and Path 4 is to compute and display the result of these

computations. The outputs are Xout(0) and Xout(4) respectively. The arithmetic

operation for Xout(0) is summation. The Xout(4) arithmetic involves summation,

subtraction and division. The computation flowchart which implements equations

below is shown in Appendix B.

X(0)=x(0)+ x(4)+ x(2)+ x(6)+ x(1)+ x(5)+ x(3)+ x(7)

X(4)=x(0)+ x(4)+ x(2)+ x(6)- x(1)- x(5)- x(3)- x(7)

3.3.2 Path 2 and Path 6 module of 8 point IFFT processor

The function of Path 2 and Path 6 is to compute and display the result of these

computations. The outputs are Xout(2) and Xout(6) respectively. The arithmetic

operation for Xout(2) and Xout(6) involves real and imaginary operation. They are

performed separately. The arithmetic operation involves summation, subtraction and

division. The twiddle factor for this output is either j or –j which contributes to the

imaginary component for this path. The computation flowchart which implements

equations below is shown in Appendix B.

X(2)=x(0)+ x(4)- x(2)- x(6)+ jx(1)+ jx(5)- jx(3)- jx(7)

X(6)=x(0)+ x(4)- x(2)- x(6)- jx(1)- jx(5)+ jx(3)+ jx(7)

36

3.3.3 Path 1, Path 3, Path 5, Path 7 modules of an 8 point IFFT processor

The function of Path 1, Path 3, Path 5 and Path 7 is to compute and display the

result of these computations. The outputs are Xout(1), Xout(3), Xout(5) and Xout(7)

respectively. The arithmetic operations for all of these modules involve real and

imaginary operation. They are performed separately. The arithmetic operation involves

summation, subtraction and division. The computation flowchart which implements

equations below is shown in Appendix B.

The twiddle factor for all these modules consists of real an imaginary value of

sine 45 degree or cos 45 degree. The output of the twiddle factor is approximated to

0.7071. In this design, the value is approximated to 0.70703125 or in binary

0.110110101, including a most significant bit (MSB) to indicate the twiddle factor is a

positive number. Any decimal value after summation is approximate to integer ‘1’

when it is greater than 0.5.

The output equations implemented are as below:

37


+ 0.7071x(7)+ j0.7071x(7)

X(5)=x(0)- x(4)+ jx(2)- jx(6)- 0.7071x(1)- j0.7071x(1) + 0.7071x(5)+ j0.7071x(5)

+ 0.7071x(3)+ j0.7071x(3)- 0.7071x(7)- j0.7071x(7)

X(3)=x(0)- x(4)- jx(2)- jx(6)- 0.7071x(1)+ j0.7071x(1) + 0.7071x(5)- j0.7071x(5)

+ 0.7071x(3)- j0.7071x(3)- 0.7071x(7)+ j0.7071x(7)


+ 0.7071x(7)- j0.7071x(7)

38

3.4 Algorithm of an 8-point Fast Fourier Transform (FFT)

In this sub-section, the direct method algorithm of an 8 point FFT is developed.

The FFT equation is shown below.

1

0

)()(N

n

nkNWnxkX

With careful examination, the equation for FFT is similar to IFFT equation

except for the negative sign in the twiddle factor and the scaling factor. Thus, the

algorithm developed for the IFFT in the previous section can be used for FFT algorithm

development with minor modification.

3.4.1 Direct method of an 8 point FFT

In the Figure 3.6, it is shown that there are 3 stages in an 8-point FFT. Stage 1

accepts the input data directly. The Figure 3.7 shows the computation in Stage 1.

39

x(0)

x(1)

x(2)

x(4)

x(5)

x6)

x(7)

x(8)

X(0)

X(4)

X(2)

X(6)

X(1)

X(5)

X(3)

X(7)

-1

-1

-1

-1

-1

-1

-1

-1 -1

-1

-1

-1

0NW

0NW

0NW

0NW

0NW

0NW

0NW

2NW

2NW

2NW

1NW

3NW

Figure 3.7 8-point FFT flow chart

The twiddle factor for N= 8 is calculated as shown in Table 3.2

Table 3.2 Symmetry properties of mW8

m mW8

0 +1

1 +0.7071 + j0.7071

2 +j

3 -0.7071 -j 0.7071

4 +1

5 -0.7071 - j0.7071

6 -j

7 +0.7071 + j0.7071

40

Figure 3.8 Stage 1 Computation Flow Chart of an 8-point FFT Computation

It is shown the even samples and odd samples are processed separately. The

outputs of Stage 1 are feed as the inputs of the Stage 2. Stage 2 computation take place

and this process repeats at the final stage, Stage 3.

The output of Stage 1 is connected to the input of Stage 2. The complexity of

the output equations increases as the Stage number increases because twiddle factor

computations are involved. The twiddle factor includes multiplication and additions

operations.

The Figure 3.4 shows the Stage 2 computation. The even inputs are grouped

together and summed up in pairs. The other inputs are multiplied with their respective

41

twiddle factor. Each of these inputs will undergo butterfly operation. Some of the

output will have to multiply again with the twiddle factor. The outputs of the Stage 2

are fed into Stage 3. At Stage 3, the butterfly computations are repeated. The

computations complexity are increased.

Figure 3.9 Stage 2 Computation Flow Chart of an 8-point FFT Computation

42

Figure 3.10 Stage 3 computation flow chart of an 8-point IFFT Computation

The final output equations derived from Figure 3.10 is shown as below):

43

The final equations that are implemented using VHDL to produce an 8-point

IFFT processor are shown Table 3.1. The equations have been optimized for an

efficient implementation. The twiddle factors are represented b 8 bit binary number.

There will be slight error percentage in this design due to the approximation of the

twiddle factor values.

Table 3.3 Final equations for an 8-point IFFT processor

X(0)=x(0)+ x(4)+ x(2)+ x(6)+ x(1)+ x(5)+ x(3)+ x(7)

X(4)=x(0)+ x(4)+ x(2)+ x(6)- x(1)- x(5)- x(3)- x(7)

X(2)=x(0)+ x(4)- x(2)- x(6)+ jx(1)+ jx(5)- jx(3)- jx(7)

X(6)=x(0)+ x(4)- x(2)- x(6)- jx(1)- jx(5)+ jx(3)+ jx(7)


+ 0.7071x(7)+ j0.7071x(7)

X(5)=x(0)- x(4)+ jx(2)- jx(6)- 0.7071x(1)- j0.7071x(1) + 0.7071x(5)+ j0.7071x(5)

+ 0.7071x(3)+ j0.7071x(3)- 0.7071x(7)- j0.7071x(7)

X(3)=x(0)- x(4)- jx(2)- jx(6)- 0.7071x(1)+ j0.7071x(1) + 0.7071x(5)- j0.7071x(5)

+ 0.7071x(3)- j0.7071x(3)- 0.7071x(7)+ j0.7071x(7)


+ 0.7071x(7)- j0.7071x(7)

CHAPTER 4

RESULT OF VHDL SIMULATION

4.1 Introduction

This chapter discusses the results obtained from the Altera Max Plus II

simulation with random input samples. Each of the input samples contains 8-bits of

input. The accuracy of the output is compared to the output from Matlab simulation.

The result is divided into 2 different sections, for FFT processor and IFFT

processor. The output from each of the modules is shown and followed b the overall

output.

4.2 FFT Processor Result

In this sub section, the output of each of the modules of FFT processor is

presented.

45

4.2.1 Pass Module Simulation Result for FFT Processor

This modules it to pass the input data at each positive clock edge to the different

modules of FFT processor with the condition the load signal is active high. One clock

signal is required to pass the data in.

The result is shown in Figure 4.1. 4. 4

46

Figure 4.1 Pass Module Simulation Output for FFT Processor

47

4.2.2 Path 0 and Path 4 Module Simulation Result for FFT Processor

These modules implement almost the identical mathematical operation except

the mathematical operators are different. The equations are shown in Chapter 3. There

is no imaginary component present at the output.

The result is shown in Figure 4.2 and Figure 4.3.

48

Figure 4.2 Path 0 Module Simulation Output for FFT Processor

49


50

4.2.3 Path 2 and Path 6 Module Simulation Result for FFT Processor



is imaginary component present at the output. Thus, Path 2 and Path 6 have more

complex mathematical expressions.

The result is shown in Figure 4.4 and Figure 4.5

51


52


53

4.2.4 Path 1, Path 3, Path 5 and Path 7 Module Simulation Result for FFT Processor

These blocks are the most complicated among all the modules in the FFT

processors because it involves a number of mathematical operators, like, addition,

subtraction, and multiplication. The outputs contain real and imaginary components.

The imaginary components is resulted from the twiddle factor which involves sin 45

degree and cos 45 degree. This value is approximated to 0.70703125 which is

equivalent to 0.10110101 in binary form.

The result is shown in Figure 4.6, Figure 4.7, Figure 4.8 and Figure 4.9.

54


55


56


57


58


This sub section shows the overall simulation result obtained by combining all

the modules that has been presented earlier. The result is shown in Figure 4.10.

59

Figure 4.10 FFT Processor Output

60

4.3 IFFT Processor Result

The IFFT processor has more complex mathematical operations because it has a

scaling factor (1/N). In the digital domain, this translates a division operation.

The simulation result will be presented in a similar fashion as the previous

section.

4.3.1 Pass Module Simulation Result for IFFT Processor

This module performs the same function as the Pass module in the FFT

processor. This modules it to pass the input data at each positive clock edge to the

different modules of FFT processor with the condition the load signal is active high.

One clock signal is required to pass the data in.

The result is shown in Figure 4.11.

61

Figure 4.11 Pass Module Simulation Output for IFFT Processor

62

4.3.2 Path 0 and Path 4 Module Simulation Result for IFFT Processor



is no imaginary component present at the output.

The result is shown in Figure 4.12 and Figure 4.13.

63

Figure 4.12 Path 0 Module Simulation Output for IFFT Processor

64


65

4.3.3 Path 2 and Path 6 Module Simulation Result for IFFT Processor



is imaginary component present at the output. Thus, Path 2 and Path 6 have more

complex mathematical expressions.

The result is shown in Figure 4.14 and Figure 4.15

66


67


68

4.3.4 Path 1, Path 3, Path 5 and Path 7 Module Simulation Result for IFFT Processor

These blocks are the most complicated among all the modules in the IFFT

processors because it involves a number of mathematical operators, like, addition,

subtraction, and multiplication. The outputs contain real and imaginary components.

The imaginary component is resulted from the twiddle factor which involves sin 45

degree and cos 45 degree. This value is approximated to 0.70703125 which is

equivalent to 0.10110101 in binary form.

The result is shown in Figure 4.16, Figure 4.17, Figure 4.18 and Figure 4.19.

69


70


71


72


73


This sub section shows the overall simulation result obtained by combining all

the modules that has been presented earlier. The result is shown in Figure 4.20.

74

Figure 4.20 FFT Processor Output

75

4.4 Verification of VHDL Simulation Output

The result presented in this chapter has to be verified. The VHDL output and the

Matlab simulation output using same random input number are compared to gauge the

accuracy of the result.

As shown in Table 4.1 and Table 4.2, the accuracy of the VHDL simulation

output has been rounded to the nearest integer. It is cause by the only 8 bit is used to

represent the output value.

76

Table 4.1 Matlab FFT Simulation Output X

(7)

0 -9.7

1-j1

9.78

6.95

-j12

.19

-1.6

6-j4

.586

17.0

7+j7

.58

-5-j

6.24

3.29

+j1

0.95

5.29

-j8.

36

3.07

-j5.

9

-17.

54+

j13.

02

-5.0

5-j1

1.06

1

-7.2

4-j1

.59

-0.5

4+j4

.71

-6.0

7+j1

5

13.6

6+j5

.83

17.7

8+j5

.19

X(6

)

0 -3-j

15

-7-j

17

-2+

j2

1-j4

7+j8

2+j1

6-j3

-2-j

16

21+

j3

3-j3

8+j1

2

1+j3

-2-j

4

-13+

j8

6-j1

1

X(5

)

0 -8.2

9+j4

.22

-2.9

5-j6

.19

9.66

+j7

.41

2.93

-j10

.4

-5-j

2.24

4.71

-j1.

05

6.71

-j4.

36

-11-

j13.

9

-10.

46+

j11.

02

-14.

95-j

9.61

1.24

+j4

.42

6.54

-j3.

3

8.07

-j15

2.34

-j0.

17

2.22

+j1

3.2

X(4

)

0 -2 12 -6 7 -31

17 -23

18 2 18 18 -4 -2 13 -17

X(3

)

0 -8.2

9-j4

.22

-2.9

5+j6

.19

9.66

-j7.

41

2.93

+j1

0.4

-5+

j2.2

4

4.71

+j1

.05

6.71

+j4

.36

-11+

j13.

9

-10.

46-j

11.0

2

-14.

95+j

9.61

1.24

-j4.

42

6.54

+j3

.3

8.07

+j1

5

2.34

+j0

.17

2.22

-j13

.2

X(2

)

0 -3+

j15

-7+

j17

-2-j

2

1+j4

7-j8

2-j1

6+j3

-2+

j16

21-j

3

3+j3

8-j1

2

1-j3

-2+

j4

-13-

j8

6+j1

1

X(1

)

0 -9.7

1+j1

9.78

6.95

+j12

.19

-1.6

6+j4

.586

17.0

7-j7

.58

-5+

j6.2

4

3.29

-j10

.95

5.29

+j8

.36

3.07

+j5

.9

-17.

54-j

13.0

2

-5.0

5+j1

1.06

1

-7.2

4+j1

.59

-0.5

4-j4

.71

-6.0

7-j1

5

13.6

6-j5

.83

17.7

8-j5

.19

X(0

)

120

60 58 66 47 61 51 59 58 60 56 74 38 58 61 53

77

Table 4.2 Matlab IFFT Simulation Output X

(7)

0 -1.2

1+j2

.47

0.87

+j1

.52

-0.2

1+j0

.57

2.13

-j0.

95

-0.6

3+j0

.78

0.41

-j1.

37

0.66

+j1

.05

0.38

+j0

.74

-2.1

9-j1

.63

-0.6

3+j1

.45

-0.9

1+j0

.2

-0.0

7-j0

.59

-0.7

6-j1

.88

1.71

-j0.

73

2.22

-j0.

65

X(6

)

0 -0.3

8+j1

.88

-0.8

8+j2

.13

-0.2

5-j0

.25

0.13

+j0

.5

0.88

-j1

0.25

-j0.

13

0.75

+j0

.38

-0.2

5+j2

2.63

-j0.

38

0.38

+j0

.36

1-j1

.5

0.13

-j0.

38

-0.2

5+j0

.5

-1.6

3-j1

0.75

+j1

.38

X(5

)

0 -1.0

4-j0

.53

-0.3

7+j0

.77

1.21

-j0.

93

0.37

+j1

.3

-0.6

3+j0

.28

0.59

+j0

.13

0.84

+j0

.55

-1.3

8+j1

.74

-1.3

1-j1

.38

-1.8

7+j1

.2

0.16

-j0.

55

0.82

+j0

.41

1.01

+j1

.87

0.29

+j0

.02

0.28

-j1.

65

X(4

)

0 -0.2

5

1.5

-0.7

5

0.87

-3.8

8

2.13

-2.8

8

2.25

0.25

2.25

2.25

-0.5

-0.2

5

1.63

-2.1

3

X(3

)

0 -1.0

4+j0

.53

-0.3

7-j0

.77

1.21

+j0

.93

0.37

-j1.

3

-0.6

3-j0

.28

0.59

-j0.

13

0.84

-j0.

55

-1.3

8-j1

.74

-1.3

1+j1

.38

-1.8

7-j1

.2

0.16

+j0

.55

0.82

-j0.

41

1.01

-j1.

87

0.29

-j0.

02

0.28

+j1

.65

X(2

)

0 -0.3

8-j1

.88

-0.8

8-j2

.13

-0.2

5+j0

.25

0.13

-j0.

5

0.88

+j1

0.25

+j0

.13

0.75

-j0.

38

-0.2

5-j2

2.63

+j0

.38

0.38

-j0.

36

1+j1

.5

0.13

+j0

.38

-0.2

5-j0

.5

-1.6

3+j1

0.75

-j1.

38

X(1

)

0 -1.2

1-j2

.47

0.87

-j1.

52

-0.2

1-j0

.57

2.13

+j0

.95

-0.6

3-j0

.78

0.41

+j1

.37

0.66

-j1.

05

0.38

-j0.

74

-2.1

9+j1

.63

-0.6

3-j1

.45

-0.9

1-j0

.2

-0.0

7+j0

.59

-0.7

6+j1

.88

1.71

+j0

.73

2.22

+j0

.65

X(0

)

15 7.5

7.25

8.25

5.88

7.63

6.38

7.38

7.25

7.5

7 9.25

4.75

7.25

7.63

6.63

CHAPTER 5

CONCLUSION

5.1 Conclusion

This chapter discusses the overall contribution of the thesis. The objective of

this project is the implementing the core processing blocks of an Orthogonal Frequency

Division Multiplexing (OFDM) system, namely the Fast Fourier Transform (FFT) and

Inverse Fast Fourier Transform (IFFT).

The Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (FFT)

have been chosen to implement the design instead of the Discrete Fourier Transform and

Inverse Discrete Fourier Transform because they offer better speed with less

computational time. These methods requires the odd and even samples inputs are

process separately before they are combine to give the final output. The result of the

computation is in integer bits which might comprises of real and imaginary components.

The decimal value of the output if greater than 0.5 is approximated to 1 and vice versa.

The design implementation is done using VHDL coding. Direct mathematical

method is adopted because it is an efficient and optimized method instead of the

structural implementation which is based on butterfly operation. Altera Max Plus II is

use to generate the design netlist file (which has .edf format) and translate the design

into the target FPGA device. Then, the timing simulation is performed from Max Plus

79

II. The output of the timing simulation from the timing simulation matches the data

calculated from Matlab.

In conclusion, the main objective of this project has been successfully

accomplished and the result obtained from this project is valid.

5.2 Challenges and Issues

The main problem encountered in this design is the overflow issue. This is due

to the limited of bits allocated for the output bits. Overflow occurred when the output

bits are not sufficient to represent the correct value. In order to overcome this problem,

a dedicated circuitry can be design to detect overflow. When an overflow occurs, this

circuitry will output a signal to indicate the input are not valid.

Another issued is the signed bit problem that is encountered in the VHDL

coding. The unsigned dividers are implemented in this design resulted incorrect result

when dividing negative number. To overcome the issue, before division is performed,

the number is checked and converted to a positive number (if it is a negative number)

before division operation is performed.

The Altera Max Plus II is not able to compile a larger design with higher

computational points where the mathematical operation become complex.

80

5.3 Suggestion for Improvement

The design in this project can be upgraded to give better performance. To

increase the result accuracy, the number of bits in the output variables can be increased.

This will definitely give an accurate and precise samples representation compared to

current design.

This design can be modified to accept complex number. Additional digital

circuitry implementation can be performed such that this design can accept complex

number as inputs.

The design can be optimize for timing constraint and delay in signal. This can

be done by optimize the components used in the design and the place and route of the

logic cells. The interconnection between the logic cells which are situated far apart from

each other can contribute to a larger critical path, thus giving delay.

81

REFERENCE

1. Dusan Matiae, “OFDM as a possible modulation technique for multimedia

applications in the range of mm waves,” TUD-TVS, 30-10-1998.

2. R. W. Chang, “Synthesis of Bandlimited Orthogonal Signals for Multichannel Data

Transmission,” Bell System Tech. J., pp. 1775-1796, Dec, 1966.

3. B. R. Saltzberg, “Performance of an Efficient Parallel Data Transmission Sytem,”

IEEE Trans. Comm. , pp 805-811, Dec, 1967.

4. S. B. Weinstein and P.M. Ebert, “Data transmission by frequency division

multiplexing using the discrete fourier transform,” IEEE Transactions on

Communication Technology”, vol. COM-19, pp. 628-634, October 1971.

5. A. Peled and A. Ruiz, “Frequency Domain Data Transmission using Reduced

Computational Complexity Alogrithms,” In Proc. IEEE Int. Conf. Acoust., Speech,

Signal Processing, pp 964-967, Denver, CO, 1980.

6. L. Hanzo, M. Munster, B.J. Choi and T. Keller, “OFDM and MC-CDMA for

Broadband Multi-User Communications, WLANs and Broadcasting,” IEEE Press,

Wiley.

7. White paper, “Orthogonal Frequency Division Multiplexing (OFDM) Explained”,

Magis Networks, Inc. 2001

8. Eric Lawrey, "The suitability of OFDM as a modulation technique for wireless

telecommunications, with a CDMA comparison", 1997, BSEE thesis.

9. Erich Cosby, “Orthogonal Frequency Division Multiplexing (OFDM): Tutorial and

Analysis”, 11-12-2001, Virginia Tech. Northern Virginia Center.

10. J. Bhasker, “A VHDL Synthesis Primer”, 2nd Edition, Star Galaxy Publishing, 1998.

11. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu & Eric S. Lin, “VHDL Modeling for

Digital Design Synthesis.” Kluwer Academic Publishing, 1995.

82

12. Jeffrey H. Reed, “Software Radio A Modern Approach to Radio Engineering”,

Prentice Hall, 2002

13. Mark Zwolinski, “Digital System Design with VHDL”, Prentice Hall, 2000

APPENDIX A

FFT VHDL IMPLEMENTATION FLOW CHART

84

Flow chart for Pass module in FFT processor

START

Initialize input from Block Pass

Positive edgetriggered

Pass input value as output

END

Yes

No

85

Flow chart for Path 0 and Path 4 in FFT processor

86

Flow chart for Path 2 in FFT processor

87


START

Even Input Odd Input


X2Re=x0- x2+ x4- x6 X2Im=x1- x3+ x5 -x7

outre6

END

outre6

88


89


90


91


APPENDIX B

IFFT VHDL IMPLEMENTATION FLOW CHART

93

Flow chart for Pass module in FFT processor

START


Positive edgetriggered

Pass input value as output

END

Yes

No

94

Flow chart for Path 0 and Path 4 in IFFT processor

95

Flow chart for Path 2 in IFFT processor

Invert to +ve

START



X2Re=x0- x2+ x4- x6 X2Im=x1- x3+ x5 -x7

Concatenate bit ‘0’ Concatenate bit ‘0’

Invert to -ve

outre2

END

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

Invert to +ve

Invert to -ve

outre2

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

96


Invert to +ve

START



X6Re=x0- x2+ x4- x6 X6Im=-x1+ x3- x5+ x7

Concatenate bit ‘0’ Concatenate bit ‘0’

Invert to -ve

outre2

END

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

Invert to +ve

Invert to -ve

outre2

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

97


START



Re: X1Re= x0- x4Im: X1Re= x2- x6

X1dRe= x1- x3- x5+ x7X1dIm= x1-x3- x5+ x7

Adder

Multiply with 0.70703125

Real Imaginary

Invert to +ve

Invert to -ve

outre1

END

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

Invert to +ve

Invert to -ve

outim1

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

98


START



Re: X3Re= x0- x4Im: X3Re= -x2- x6

X3dRe= -x1+ x3+ x5- x7X3dIm= x1- x3- x5+ x7

Adder


Real Imaginary

Invert to +ve

Invert to -ve

outre1

END

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

Invert to +ve

Invert to -ve

outim1

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

99


START



Re: X5Re= x0- x4Im: X5Re= x2- x6

X5dRe= -x1+ x3+ x5- x7X5dIm= -x1+ x3+ x5- x7

Adder


Real Imaginary

Invert to +ve

Invert to -ve

outre1

END

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

Invert to +ve

Invert to -ve

outim1

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

100


START



Re: X7Re= x0- x4Im: X7Re= -x2- x6

X7dRe= x1- x3- x5+ x7X7dIm= -x1+ x3+ x5- x7

Adder


Real Imaginary

Invert to +ve

Invert to -ve

outre7

END

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

Invert to +ve

Invert to -ve

outim7

Yes

Yes

No

NoQuo

Sign bit -ve

Unsigned Divider

Sign bit +ve

APPENDIX C

VHDL SYNTHESIS CODE FOR FFT AND IFFT PROCESSOR

102

--FFT 8 pts library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;

entity FFT8pts is port ( reset : in std_logic; load: in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); outre0: out std_logic_vector(7 downto 0); outre1: out std_logic_vector(7 downto 0); outre2: out std_logic_vector(7 downto 0); outre3: out std_logic_vector(7 downto 0); outre4: out std_logic_vector(7 downto 0); outre5: out std_logic_vector(7 downto 0); outre6: out std_logic_vector(7 downto 0); outre7: out std_logic_vector(7 downto 0); outim1: out std_logic_vector(7 downto 0); outim2: out std_logic_vector(7 downto 0); outim3: out std_logic_vector(7 downto 0); outim5: out std_logic_vector(7 downto 0); outim6: out std_logic_vector(7 downto 0); outim7: out std_logic_vector(7 downto 0) );end FFT8pts;

architecture arch_FFT8pts of FFT8pts is

signal x0: std_logic_vector(7 downto 0); signal x1: std_logic_vector(7 downto 0); signal x2: std_logic_vector(7 downto 0); signal x3: std_logic_vector(7 downto 0); signal x4: std_logic_vector(7 downto 0); signal x5: std_logic_vector(7 downto 0); signal x6: std_logic_vector(7 downto 0); signal x7: std_logic_vector(7 downto 0);

103

component pass port ( reset : in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); x0: out std_logic_vector(7 downto 0); x1: out std_logic_vector(7 downto 0); x2: out std_logic_vector(7 downto 0); x3: out std_logic_vector(7 downto 0); x4: out std_logic_vector(7 downto 0); x5: out std_logic_vector(7 downto 0); x6: out std_logic_vector(7 downto 0); x7: out std_logic_vector(7 downto 0) );end component;

component fftpath0 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre0: out std_logic_vector(7 downto 0) );end component;

component fftpath1 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0);

104

x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre1: out std_logic_vector(7 downto 0); outim1: out std_logic_vector(7 downto 0) );end component;

component fftpath2 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre2: out std_logic_vector(7 downto 0); outim2: out std_logic_vector(7 downto 0) );end component;


component fftpath4 port (

105

reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre4: out std_logic_vector(7 downto 0) );end component;


component fftpath6 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre6: out std_logic_vector(7 downto 0); outim6: out std_logic_vector(7 downto 0) );

106

end component;


begin

U_pass:passport map(reset, CLOCK, in_x0, in_x1, in_x2, in_x3, in_x4, in_x5, in_x6, in_x7, x0, x1, x2, x3, x4, x5, x6, x7);

U_fftpath0:fftpath0port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, outre0);

U_fftpath1:fftpath1port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, outre1, outim1);



U_fftpath4:fftpath4port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, outre4);



107


end arch_FFT8pts; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;

entity pass isport ( reset : in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); x0: out std_logic_vector(7 downto 0); x1: out std_logic_vector(7 downto 0); x2: out std_logic_vector(7 downto 0); x3: out std_logic_vector(7 downto 0); x4: out std_logic_vector(7 downto 0); x5: out std_logic_vector(7 downto 0); x6: out std_logic_vector(7 downto 0); x7: out std_logic_vector(7 downto 0) );end pass;

architecture arch_pass of pass is component D_FF port (D: in std_logic_vector(7 downto 0); Q: out std_logic_vector (7 downto 0); reset, CLOCK: in std_logic); end component;

beginU1: D_FF port map (in_x0, x0, reset, CLOCK); U2: D_FF port map (in_x1, x1, reset, CLOCK); U3: D_FF port map (in_x2, x2, reset, CLOCK); U4: D_FF port map (in_x3, x3, reset, CLOCK); U5: D_FF port map (in_x4, x4, reset, CLOCK); U6: D_FF port map (in_x5, x5, reset, CLOCK); U7: D_FF port map (in_x6, x6, reset, CLOCK); U8: D_FF port map (in_x7, x7, reset, CLOCK);

108

end arch_pass;

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;

entity D_FF is port ( D: in std_logic_vector(7 downto 0); Q: out std_logic_vector (7 downto 0); reset, CLOCK: in std_logic );end D_FF;

architecture arch_D_FF of D_FF is

beginprocess (CLOCK) begin if reset='0' then Q<=(others=>'0'); elsif CLOCK'event and CLOCK='1' then Q<=D; end if; end process; end arch_D_FF;

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all;

entity fftpath0 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre0: out std_logic_vector(7 downto 0)

109

);end fftpath0;

architecture arch_path0 of fftpath0 is

signal Xout0_9, outre0a: std_logic_vector (8 downto 0); signal X0_QUO: std_logic_vector(7 downto 0);

begin

process (x0, x1, x2, x3, x4, x5, x6, x7) begin outre0 <= x0 + x1 + x2 + x3 + x4 + x5 +x6 + x7; end process; end arch_path0;


entity fftpath1 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre1: out std_logic_vector(7 downto 0); outim1: out std_logic_vector(7 downto 0) );end fftpath1;


signal X1Re, X1Im, X1dRe_jum, X1dIm_jum: std_logic_vector(7 downto 0); signal x1cd, x3cd, x5cd, x7cd, X1dRe, X1dIm: std_logic_vector(16 downto 0);

begin

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process (x0, x1, x2, x3, x4, x5, x6, x7, X1Re, X1Im, x1cd, x3cd, x5cd, x7cd, X1dRe, X1dIm) begin X1Re <= x0 - x4; X1Im <= x6 - x2;

x1cd <="010110101" * x1; x3cd <="010110101" * x3; x5cd <="010110101" * x5; x7cd <="010110101" * x7;

X1dRe <=x1cd - x5cd - x3cd + x7cd; X1dIm <=x5cd + x7cd - x1cd - x3cd;

if X1dRe(7)='1' then X1dRe_jum <= X1dRe(15 downto 8) +'1'; else X1dRe_jum <= X1dRe(15 downto 8); end if;

if X1dIm(7)='1' then X1dIm_jum <= X1dIm(15 downto 8) +'1'; else X1dIm_jum <= X1dIm(15 downto 8); end if;

outre1 <= X1Re + X1dRe_jum; outim1 <= X1Im + X1dIm_jum;

end process; end arch_path1;


entity fftpath2 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0);

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x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre2: out std_logic_vector(7 downto 0); outim2: out std_logic_vector(7 downto 0) );end fftpath2;


signal X2Re9, X2Im9, outre2a, outim2a : std_logic_vector (8 downto 0); signal X2Re, X2Im : std_logic_vector(7 downto 0);

begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X2Re, X2Im) begin outre2 <= x0 + x4 - x2 - x6; outim2 <= x3 + x7 - x1 - x5;





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begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X3Re, X3Im, x1cd, x3cd, x5cd, x7cd, X3dRe, X3dIm) begin

X3Re <= x0 - x4; X3Im <= x2 - x6;


X3dRe <=x3cd + x5cd - x1cd - x7cd; X3dIm <=x5cd + x7cd - x1cd - x3cd;






entity fftpath4 isport ( reset : in std_logic;

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CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre4: out std_logic_vector(7 downto 0) );end fftpath4;


begin

process (x0, x1, x2, x3, x4, x5, x6, x7) begin

outre4 <= x0 - x1 + x2 - x3 + x4 - x5 +x6 - x7;




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begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X5Re, X5Im, x1cd, x3cd, x5cd, x7cd, X5dRe, X5dIm) begin X5Re <= x0 - x4; X5Im <= x6 - x2;


X5dRe <=x5cd + x3cd - x1cd - x7cd; X5dIm <=x1cd + x3cd - x5cd-x7cd;






entity fftpath6 is

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port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); outre6: out std_logic_vector(7 downto 0); outim6: out std_logic_vector(7 downto 0) );end fftpath6;


begin

process (x0, x1, x2, x3, x4, x5, x6, x7) begin

outre6 <= x0 + x4 - x2 - x6; outim6 <= x1 + x5 - x3 - x7;



entity fftpath7 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0);

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outre7: out std_logic_vector(7 downto 0); outim7: out std_logic_vector(7 downto 0) );end fftpath7;



begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X7Re, X7Im, x1cd, x3cd, x5cd, x7cd) begin

X7Re <= x0 - x4; X7Im <= x2 - x6;


X7dRe <=x1cd + x7cd - x5cd - x3cd; X7dIm <=x1cd + x3cd - x5cd - x7cd;





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--IFFT 8 pts library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;

entity IFFT8pts is port ( reset : in std_logic; load: in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); outre0: out std_logic_vector(7 downto 0); outre1: out std_logic_vector(7 downto 0); outre2: out std_logic_vector(7 downto 0); outre3: out std_logic_vector(7 downto 0); outre4: out std_logic_vector(7 downto 0); outre5: out std_logic_vector(7 downto 0); outre6: out std_logic_vector(7 downto 0); outre7: out std_logic_vector(7 downto 0); outim1: out std_logic_vector(7 downto 0); outim2: out std_logic_vector(7 downto 0); outim3: out std_logic_vector(7 downto 0); outim5: out std_logic_vector(7 downto 0); outim6: out std_logic_vector(7 downto 0); outim7: out std_logic_vector(7 downto 0) );end IFFT8pts;

architecture arch_IFFT8pts of IFFT8pts is

signal x0: std_logic_vector(7 downto 0); signal x1: std_logic_vector(7 downto 0); signal x2: std_logic_vector(7 downto 0); signal x3: std_logic_vector(7 downto 0); signal x4: std_logic_vector(7 downto 0); signal x5: std_logic_vector(7 downto 0); signal x6: std_logic_vector(7 downto 0); signal x7: std_logic_vector(7 downto 0);

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signal X0_QUOa, Xout0: std_logic_vector(7 downto 0); signal X4_QUOa, Xout4: std_logic_vector(7 downto 0); signal real2, X2_Re_Quo2, imag2, X2_Im_Quo2: std_logic_vector(7 downto 0); signal real6, X6_Re_Quo6, imag6, X6_Im_Quo6: std_logic_vector(7 downto 0); signal real1, imag1, re_deci1, im_deci1, X1gt_Re, X1_Re_Quo1, X1gt_Im, X1_Im_Quo1: std_logic_vector(7 downto 0); signal real5, imag5, re_deci5, im_deci5, X5gt_Re, X5_Re_Quo5, X5gt_Im, X5_Im_Quo5: std_logic_vector(7 downto 0); signal real3, imag3, re_deci3, im_deci3, X3gt_Re, X3_Re_Quo3, X3gt_Im, X3_Im_Quo3: std_logic_vector(7 downto 0); signal real7, imag7, re_deci7, im_deci7, X7gt_Re, X7_Re_Quo7, X7gt_Im, X7_Im_Quo7: std_logic_vector(7 downto 0); signal X0_REM, X4_REM, X2_Re_Rem, X2_Im_Rem, X6_Re_Rem, X6_Im_Rem, X1_Re_Rem, X1_Im_Rem, X5_Re_Rem, X5_Im_Rem, X3_Re_Rem, X3_Im_Rem, X7_Re_Rem, X7_Im_Rem: std_logic_vector(3 downto 0);

component pass port ( reset : in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); x0: out std_logic_vector(7 downto 0); x1: out std_logic_vector(7 downto 0); x2: out std_logic_vector(7 downto 0); x3: out std_logic_vector(7 downto 0); x4: out std_logic_vector(7 downto 0); x5: out std_logic_vector(7 downto 0); x6: out std_logic_vector(7 downto 0); x7: out std_logic_vector(7 downto 0) );end component;

component path0 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0);

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x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); Xout0: buffer std_logic_vector(7 downto 0); X0_QUOa: out std_logic_vector(7 downto 0); X0_REM: out std_logic_vector(3 downto 0); outre0: out std_logic_vector(7 downto 0) );end component;

component path4 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); Xout4: buffer std_logic_vector(7 downto 0); X4_QUOa: out std_logic_vector(7 downto 0); X4_REM: out std_logic_vector(3 downto 0); outre4: out std_logic_vector(7 downto 0) );end component;

component path2 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real2: out std_logic_vector(7 downto 0); X2_Re_Quo2: out std_logic_vector(7 downto 0); X2_Re_Rem: out std_logic_vector(3 downto 0);

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imag2: out std_logic_vector(7 downto 0); X2_Im_Quo2: out std_logic_vector(7 downto 0); X2_Im_Rem: out std_logic_vector(3 downto 0); outre2: out std_logic_vector(7 downto 0); outim2: out std_logic_vector(7 downto 0) );end component;

component path6 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real6: out std_logic_vector(7 downto 0); X6_Re_Quo6: out std_logic_vector(7 downto 0); X6_Re_Rem: out std_logic_vector(3 downto 0); imag6: out std_logic_vector(7 downto 0); X6_Im_Quo6: out std_logic_vector(7 downto 0); X6_Im_Rem: out std_logic_vector(3 downto 0); outre6: out std_logic_vector(7 downto 0); outim6: out std_logic_vector(7 downto 0) );end component;

component path1 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real1: out std_logic_vector(7 downto 0); re_decil: out std_logic_vector(7 downto 0); im_decil: out std_logic_vector(7 downto 0);

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X1_Re_Quo1: out std_logic_vector(7 downto 0); X1_Re_Rem: out std_logic_vector(3 downto 0); X1gt_Re: buffer std_logic_vector(7 downto 0); X1gt_Im: buffer std_logic_vector(7 downto 0); imag1: out std_logic_vector(7 downto 0); X1_Im_Quo1: out std_logic_vector(7 downto 0); X1_Im_Rem: out std_logic_vector(3 downto 0); outre1: out std_logic_vector(7 downto 0); outim1: out std_logic_vector(7 downto 0) );end component;

component path5 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real5: out std_logic_vector(7 downto 0); re_deci5: out std_logic_vector(7 downto 0); im_deci5: out std_logic_vector(7 downto 0); X5_Re_Quo5: out std_logic_vector(7 downto 0); X5_Re_Rem: out std_logic_vector(3 downto 0); X5gt_Re: buffer std_logic_vector(7 downto 0); X5gt_Im: buffer std_logic_vector(7 downto 0); imag5: out std_logic_vector(7 downto 0); X5_Im_Quo5: out std_logic_vector(7 downto 0); X5_Im_Rem: out std_logic_vector(3 downto 0); outre5: out std_logic_vector(7 downto 0); outim5: out std_logic_vector(7 downto 0) );end component;

component path3 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0);

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x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real3: out std_logic_vector(7 downto 0); re_deci3: out std_logic_vector(7 downto 0); im_deci3: out std_logic_vector(7 downto 0); X3_Re_Quo3: out std_logic_vector(7 downto 0); X3_Re_Rem: out std_logic_vector(3 downto 0); X3gt_Re: buffer std_logic_vector(7 downto 0); X3gt_Im: buffer std_logic_vector(7 downto 0); imag3: out std_logic_vector(7 downto 0); X3_Im_Quo3: out std_logic_vector(7 downto 0); X3_Im_Rem: out std_logic_vector(3 downto 0); outre3: out std_logic_vector(7 downto 0); outim3: out std_logic_vector(7 downto 0) );end component;

component path7 port ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real7: out std_logic_vector(7 downto 0); re_deci7: out std_logic_vector(7 downto 0); im_deci7: out std_logic_vector(7 downto 0); X7_Re_Quo7: out std_logic_vector(7 downto 0); X7_Re_Rem: out std_logic_vector(3 downto 0); X7gt_Re: buffer std_logic_vector(7 downto 0); X7gt_Im: buffer std_logic_vector(7 downto 0); imag7: out std_logic_vector(7 downto 0); X7_Im_Quo7: out std_logic_vector(7 downto 0); X7_Im_Rem: out std_logic_vector(3 downto 0); outre7: out std_logic_vector(7 downto 0); outim7: out std_logic_vector(7 downto 0) );end component;

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begin

U_pass: pass port map(reset, CLOCK, in_x0, in_x1, in_x2, in_x3, in_x4, in_x5, in_x6, in_x7, x0, x1, x2, x3, x4, x5, x6, x7);

U_path0:path0port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, Xout0, X0_QUOa, X0_REM, outre0);

U_path4:path4port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, Xout4, X4_QUOa, X4_REM, outre4);

U_path2:path2port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, real2, X2_Re_Quo2, X2_Re_Rem, imag2, X2_Im_Quo2, X2_Im_Rem, outre2, outim2);

U_path6:path6port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, real6, X6_Re_Quo6, X6_Re_Rem, imag6, X6_Im_Quo6, X6_Im_Rem, outre6, outim6);

U_path1:path1port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, real1, re_deci1, im_deci1, X1_Re_Quo1, X1_Re_Rem, X1gt_Re, X1gt_Im, imag1, X1_Im_Quo1, X1_Im_Rem, outre1, outim1);


U_path:path3 port map(reset, CLOCK, x0, x1, x2, x3, x4, x5, x6, x7, real3, re_deci3, im_deci3, X3_Re_Quo3, X3_Re_Rem, X3gt_Re, X3gt_Im, imag3, X3_Im_Quo3, X3_Im_Rem, outre3, outim3);


end arch_IFFT8pts;

library IEEE; use IEEE.std_logic_1164.all;

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use IEEE.std_logic_arith.all;

entity pass isport ( reset : in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); x0: out std_logic_vector(7 downto 0); x1: out std_logic_vector(7 downto 0); x2: out std_logic_vector(7 downto 0); x3: out std_logic_vector(7 downto 0); x4: out std_logic_vector(7 downto 0); x5: out std_logic_vector(7 downto 0); x6: out std_logic_vector(7 downto 0); x7: out std_logic_vector(7 downto 0) );end pass;


entity pass isport ( reset : in std_logic; CLOCK: in std_logic; in_x0: in std_logic_vector(7 downto 0); in_x1: in std_logic_vector(7 downto 0); in_x2: in std_logic_vector(7 downto 0); in_x3: in std_logic_vector(7 downto 0); in_x4: in std_logic_vector(7 downto 0); in_x5: in std_logic_vector(7 downto 0); in_x6: in std_logic_vector(7 downto 0); in_x7: in std_logic_vector(7 downto 0); x0: out std_logic_vector(7 downto 0); x1: out std_logic_vector(7 downto 0); x2: out std_logic_vector(7 downto 0); x3: out std_logic_vector(7 downto 0); x4: out std_logic_vector(7 downto 0);

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x5: out std_logic_vector(7 downto 0); x6: out std_logic_vector(7 downto 0); x7: out std_logic_vector(7 downto 0) );end pass;

architecture arch_pass of pass is component d_ff port (D: in std_logic_vector(7 downto 0); Q: out std_logic_vector (7 downto 0); reset, CLOCK: in std_logic); end component;

beginU1: D_FF port map (in_x0, x0, reset, CLOCK); U2: D_FF port map (in_x1, x1, reset, CLOCK); U3: D_FF port map (in_x2, x2, reset, CLOCK); U4: D_FF port map (in_x3, x3, reset, CLOCK); U5: D_FF port map (in_x4, x4, reset, CLOCK); U6: D_FF port map (in_x5, x5, reset, CLOCK); U7: D_FF port map (in_x6, x6, reset, CLOCK); U8: D_FF port map (in_x7, x7, reset, CLOCK);

end architecture;


entity D_FF is port ( D: in std_logic_vector(7 downto 0); Q: out std_logic_vector (7 downto 0); reset, CLOCK: in std_logic );end D_FF;

architecture arch_D_FF of D_FF is

beginprocess (CLOCK) begin if reset='0' then Q<=(others=>'0'); elsif CLOCK'event and CLOCK='1' then

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Q<=D; end if; end process; end arch_D_FF;


entity path0 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); Xout0: buffer std_logic_vector(7 downto 0); X0_QUOa: out std_logic_vector(7 downto 0); X0_REM: out std_logic_vector(3 downto 0); outre0: out std_logic_vector(7 downto 0) );end path0;

architecture arch_path0 of path0 is

signal CLKEN : std_logic; signal ACLR: std_logic; signal DENOM: std_logic_vector(3 downto 0); signal Xout0_9, indiv, outre0a: std_logic_vector (8 downto 0); signal X0_QUO: std_logic_vector(7 downto 0);

component LPM_DIVIDE generic ( LPM_WIDTHN: integer :=8; LPM_WIDTHD: integer :=4; LPM_TYPE: string := "LPM_DIVIDE"; LPM_PIPELINE: integer :=0; LPM_HINT: string := "UNUSED" );

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port ( NUMER: in std_logic_vector (LPM_WIDTHN-1 downto 0); DENOM: in std_logic_vector (LPM_WIDTHD-1 downto 0); CLOCK: in std_logic; CLKEN: in std_logic; ACLR: in std_logic; QUOTIENT: out std_logic_vector (LPM_WIDTHN-1 downto 0); REMAIN: out std_logic_vector (LPM_WIDTHD-1 downto 0) );end component;

begin

process (x0, x1, x2, x3, x4, x5, x6, x7, Xout0_9, indiv, outre0a, X0_QUO, Xout0) begin Xout0 <= x0 + x1 + x2 + x3 + x4 + x5 +x6 + x7; Xout0_9 <= '0' & Xout0;

if Xout0(7)='1' then indiv <= "100000000" - Xout0_9; else indiv <= Xout0_9; end if;

X0_QUOa <= X0_QUO;

if Xout0(7)='1' then outre0a <="100000000" - X0_QUO; outre0 <= outre0a (7 downto 0); else outre0 <=X0_QUO (7 downto 0); end if; end process;

CLKEN <='1'; ACLR <='0'; DENOM <= "1000";

U_LPM_DIVIDE: LPM_DIVIDE port map (indiv (7 downto 0), DENOM, CLOCK, CLKEN, ACLR, X0_QUO, X0_REM);end arch_path0;


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use IEEE.std_logic_signed.all;

entity path1 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real1: out std_logic_vector(7 downto 0); re_decil: out std_logic_vector(7 downto 0); im_decil: out std_logic_vector(7 downto 0); X1_Re_Quo1: out std_logic_vector(7 downto 0); X1_Re_Rem: out std_logic_vector(3 downto 0); X1gt_Re: buffer std_logic_vector(7 downto 0); X1gt_Im: buffer std_logic_vector(7 downto 0); imag1: out std_logic_vector(7 downto 0); X1_Im_Quo1: out std_logic_vector(7 downto 0); X1_Im_Rem: out std_logic_vector(3 downto 0); outre1: out std_logic_vector(7 downto 0); outim1: out std_logic_vector(7 downto 0) );end path1;


signal CLKEN : std_logic; signal ACLR: std_logic; signal DENOM: std_logic_vector(3 downto 0); signal X1gt_Re9, X1gt_Im9, indivR, indivI, outre1a, outim1a: std_logic_vector (8 downto 0); signal X1Re, X1Im, X1_Re_Quo, X1_Im_Quo, X1dRe_jum, X1dIm_jum: std_logic_vector(7 downto 0); signal x1cd, x3cd, x5cd, x7cd, X1dRe, X1dIm: std_logic_vector(16 downto 0);

component LPM_DIVIDE generic ( LPM_WIDTHN: integer :=8; LPM_WIDTHD: integer :=4; LPM_TYPE: string := "LPM_DIVIDE"; LPM_PIPELINE: integer :=0;

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LPM_HINT: string := "UNUSED" );


begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X1Re, X1Im, x1cd, x3cd, x5cd, x7cd, X1dRe, X1dIm, X1dRe_jum, X1dIm_jum, CLKEN, ACLR, DENOM, outre1a, outim1a, X1gt_Re, X1gt_Im, X1_Re_Quo, X1_Im_Quo, X1gt_Re9, X1gt_Im9) begin X1Re <= x0 - x4; X1Im <= x2 - x6;


X1dRe <=x1cd - x5cd - x3cd + x7cd; X1dIm <=-x5cd + x1cd - x3cd + x7cd;



real1 <=X1Re; imag1 <=X1Im; re_decil <= X1dRe_jum;

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im_decil <= X1dIm_jum;

X1gt_Re <= X1Re + X1dRe_jum; X1gt_Im <= X1Im + X1dIm_jum;

X1gt_Re9 <='0' & X1gt_Re; X1gt_Im9 <='0' & X1gt_Im;

if X1gt_Re(7)='1' then indivR <= "100000000" - X1gt_Re9; else indivR <= X1gt_Re9; end if;

if X1gt_Im(7)='1' then indivI <= "100000000" - X1gt_Im9; else indivI <= X1gt_Im9; end if;

if X1gt_Re(7)='1' then outre1a <="100000000" - X1_Re_QUO; outre1 <= outre1a (7 downto 0); else outre1 <=X1_Re_QUO (7 downto 0); end if;

if X1Im(7)='1' then outim1a <="100000000" - X1_Im_QUO; outim1 <= outim1a (7 downto 0); else outim1 <=X1_Im_QUO (7 downto 0); end if;

X1_Re_Quo1 <= X1_Re_Quo; X1_Im_Quo1 <= X1_Im_Quo; end process;

CLKEN <='1'; ACLR <='0'; DENOM <= "1000";

U_LPM_DIVIDE: LPM_DIVIDE port map (indivR(7 downto 0), DENOM, CLOCK, CLKEN, ACLR, X1_Re_Quo, X1_Re_Rem);

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U_LPM_DIVIDE_1: LPM_DIVIDE port map (indivI(7 downto 0), DENOM, CLOCK, CLKEN, ACLR, X1_Im_Quo, X1_Im_Rem); end arch_path1;


entity path2 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real2: out std_logic_vector(7 downto 0); X2_Re_Quo2: out std_logic_vector(7 downto 0); X2_Re_Rem: out std_logic_vector(3 downto 0); imag2: out std_logic_vector(7 downto 0); X2_Im_Quo2: out std_logic_vector(7 downto 0); X2_Im_Rem: out std_logic_vector(3 downto 0); outre2: out std_logic_vector(7 downto 0); outim2: out std_logic_vector(7 downto 0) );end path2;


signal CLKEN : std_logic; signal ACLR: std_logic; signal DENOM: std_logic_vector(3 downto 0); signal X2Re9, X2Im9, indivR, indivI, outre2a, outim2a: std_logic_vector (8 downto 0); signal X2Re, X2Im, X2Re_jum, X2Im_jum, X2_Re_Quo, X2_Im_Quo: std_logic_vector(7 downto 0);

component LPM_DIVIDE generic ( LPM_WIDTHN: integer :=8; LPM_WIDTHD: integer :=4;

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LPM_TYPE: string := "LPM_DIVIDE"; LPM_PIPELINE: integer :=0; LPM_HINT: string := "UNUSED" );


begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X2Re, X2Im, CLKEN, ACLR, DENOM, outre2a, outim2a, X2_Re_Quo, X2_Im_Quo, X2_Im_Quo, X2Re9, X2Im9) begin X2Re <= x0 + x4 - x2 - x6; X2Im <= x1 + x5 - x3 - x7; real2 <=X2Re; imag2 <=X2Im; X2Re9 <='0' & X2Re; X2Im9 <='0' & X2Im;

if X2Re(7)='1' then indivR <= "100000000" - X2Re9; else indivR <= X2Re9; end if;

if X2Im(7)='1' then indivI <= "100000000" - X2Im9; else indivI <= X2Im9; end if;

if X2Re(7)='1' then outre2a <="100000000" - X2_Re_QUO; outre2 <= outre2a (7 downto 0); else outre2 <=X2_Re_QUO (7 downto 0); end if;

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CLKEN <='1'; ACLR <='0'; DENOM <= "1000";




entity path3 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real3: out std_logic_vector(7 downto 0); re_deci3: out std_logic_vector(7 downto 0); im_deci3: out std_logic_vector(7 downto 0);

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X3_Re_Quo3: out std_logic_vector(7 downto 0); X3_Re_Rem: out std_logic_vector(3 downto 0); X3gt_Re: buffer std_logic_vector(7 downto 0); X3gt_Im: buffer std_logic_vector(7 downto 0); imag3: out std_logic_vector(7 downto 0); X3_Im_Quo3: out std_logic_vector(7 downto 0); X3_Im_Rem: out std_logic_vector(3 downto 0); outre3: out std_logic_vector(7 downto 0); outim3: out std_logic_vector(7 downto 0) );end path3;





begin

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process (x0, x1, x2, x3, x4, x5, x6, x7, X3Re, X3Im, x1cd, x3cd, x5cd, x7cd, X3dRe, X3dIm, X3dRe_jum, X3dIm_jum, CLKEN, ACLR, DENOM, outre3a, outim3a, X3gt_Re, X3gt_Im, X3_Re_Quo, X3_Im_Quo, X3gt_Re9, X3gt_Im9) begin X3Re <= x0 - x4; X3Im <= -x2 -x6;


X3dRe <=x5cd + x3cd - x1cd - x7cd; X3dIm <=-x5cd + x7cd + x1cd - x3cd;



real3 <=X3Re; imag3 <=X3Im; re_deci3 <= X3dRe_jum; im_deci3 <= X3dIm_jum;




if X3gt_Im(7)='1' then

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indivI <= "100000000" - X3gt_Im9; else indivI <= X3gt_Im9; end if;




CLKEN <='1'; ACLR <='0'; DENOM <= "1000";




entity path4 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0);

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x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); Xout4: buffer std_logic_vector(7 downto 0); X4_QUOa: out std_logic_vector(7 downto 0); X4_REM: out std_logic_vector(3 downto 0); outre4: out std_logic_vector(7 downto 0) );end path4;


signal CLKEN : std_logic; signal ACLR: std_logic; signal DENOM: std_logic_vector(3 downto 0); signal Xout4_9, indiv, outre4a: std_logic_vector (8 downto 0); signal X4_QUO: std_logic_vector(7 downto 0);



begin

process (x0, x1, x2, x3, x4, x5, x6, x7, Xout4_9, indiv, outre4a, X4_QUO, Xout4) begin

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Xout4 <= x0 - x1 + x2 - x3 + x4 - x5 +x6 - x7; Xout4_9 <= '0' & Xout4;

if Xout4(7)='1' then indiv <= "100000000" - Xout4_9; else indiv <= Xout4_9; end if;

X4_QUOa <= X4_QUO;

if Xout4(7)='1' then outre4a <="100000000" - X4_QUO; outre4 <= outre4a (7 downto 0); else outre4 <=X4_QUO (7 downto 0); end if; end process;

CLKEN <='1'; ACLR <='0'; DENOM <= "1000";

U_LPM_DIVIDE: LPM_DIVIDE port map (indiv (7 downto 0), DENOM, CLOCK, CLKEN, ACLR, X4_QUO, X4_REM);end arch_path4;


entity path5 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real5: out std_logic_vector(7 downto 0);

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re_deci5: out std_logic_vector(7 downto 0); im_deci5: out std_logic_vector(7 downto 0); X5_Re_Quo5: out std_logic_vector(7 downto 0); X5_Re_Rem: out std_logic_vector(3 downto 0); X5gt_Re: buffer std_logic_vector(7 downto 0); X5gt_Im: buffer std_logic_vector(7 downto 0); imag5: out std_logic_vector(7 downto 0); X5_Im_Quo5: out std_logic_vector(7 downto 0); X5_Im_Rem: out std_logic_vector(3 downto 0); outre5: out std_logic_vector(7 downto 0); outim5: out std_logic_vector(7 downto 0) );end path5;





begin

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process (x0, x1, x2, x3, x4, x5, x6, x7, X5Re, X5Im, x1cd, x3cd, x5cd, x7cd, X5dRe, X5dIm, X5dRe_jum, X5dIm_jum, CLKEN, ACLR, DENOM, outre5a, outim5a, X5gt_Re, X5gt_Im, X5_Re_Quo, X5_Im_Quo, X5gt_Re9, X5gt_Im9) begin X5Re <= x0 - x4; X5Im <= x2 - x6;


X5dRe <=x5cd + x3cd - x1cd - x7cd; X5dIm <=-x1cd + x3cd + x5cd - x7cd;







if X5gt_Im(7)='1' then

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indivI <= "100000000" - X5gt_Im9; else indivI <= X5gt_Im9; end if;




CLKEN <='1'; ACLR <='0'; DENOM <= "1000";




entity path6 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0);

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x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real6: out std_logic_vector(7 downto 0); X6_Re_Quo6: out std_logic_vector(7 downto 0); X6_Re_Rem: out std_logic_vector(3 downto 0); imag6: out std_logic_vector(7 downto 0); X6_Im_Quo6: out std_logic_vector(7 downto 0); X6_Im_Rem: out std_logic_vector(3 downto 0); outre6: out std_logic_vector(7 downto 0); outim6: out std_logic_vector(7 downto 0) );end path6;


signal CLKEN : std_logic; signal ACLR: std_logic; signal DENOM: std_logic_vector(3 downto 0); signal X6Re9, X6Im9, indivR, indivI, outre6a, outim6a: std_logic_vector (8 downto 0); signal X6Re, X6Im, X6Re_jum, X6Im_jum, X6_Re_Quo, X6_Im_Quo: std_logic_vector(7 downto 0);



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begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X6Re, X6Im, CLKEN, ACLR, DENOM, outre6a, outim6a, X6_Re_Quo, X6_Im_Quo, X6_Im_Quo, X6Re9, X6Im9) begin X6Re <= x0 + x4 - x2 - x6; X6Im <= x3 + x7 - x1 - x5; real6 <=X6Re; imag6 <=X6Im; X6Re9 <='0' & X6Re; X6Im9 <='0' & X6Im;

if X6Re(7)='1' then indivR <= "100000000" - X6Re9; else indivR <= X6Re9; end if;

if X6Im(7)='1' then indivI <= "100000000" - X6Im9; else indivI <= X6Im9; end if;

if X6Re(7)='1' then outre6a <="100000000" - X6_Re_QUO; outre6 <= outre6a (7 downto 0); else outre6 <=X6_Re_QUO (7 downto 0); end if;



CLKEN <='1'; ACLR <='0'; DENOM <= "1000";

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entity path7 isport ( reset : in std_logic; CLOCK: in std_logic; x0: in std_logic_vector(7 downto 0); x1: in std_logic_vector(7 downto 0); x2: in std_logic_vector(7 downto 0); x3: in std_logic_vector(7 downto 0); x4: in std_logic_vector(7 downto 0); x5: in std_logic_vector(7 downto 0); x6: in std_logic_vector(7 downto 0); x7: in std_logic_vector(7 downto 0); real7: out std_logic_vector(7 downto 0); re_deci7: out std_logic_vector(7 downto 0); im_deci7: out std_logic_vector(7 downto 0); X7_Re_Quo7: out std_logic_vector(7 downto 0); X7_Re_Rem: out std_logic_vector(3 downto 0); X7gt_Re: buffer std_logic_vector(7 downto 0); X7gt_Im: buffer std_logic_vector(7 downto 0); imag7: out std_logic_vector(7 downto 0); X7_Im_Quo7: out std_logic_vector(7 downto 0); X7_Im_Rem: out std_logic_vector(3 downto 0); outre7: out std_logic_vector(7 downto 0); outim7: out std_logic_vector(7 downto 0) );end path7;


signal CLKEN : std_logic; signal ACLR: std_logic; signal DENOM: std_logic_vector(3 downto 0);

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signal X7gt_Re9, X7gt_Im9, indivR, indivI, outre7a, outim7a: std_logic_vector (8 downto 0); signal X7Re, X7Im, X7_Re_Quo, X7_Im_Quo, X7dRe_jum, X7dIm_jum: std_logic_vector(7 downto 0); signal x1cd, x3cd, x5cd, x7cd, X7dRe, X7dIm: std_logic_vector(16 downto 0);



begin

process (x0, x1, x2, x3, x4, x5, x6, x7, X7Re, X7Im, x1cd, x3cd, x5cd, x7cd, X7dRe, X7dIm, X7dRe_jum, X7dIm_jum, CLKEN, ACLR, DENOM, outre7a, outim7a, X7gt_Re, X7gt_Im, X7_Re_Quo, X7_Im_Quo, X7gt_Re9, X7gt_Im9) begin X7Re <= x0 - x4; X7Im <= -x2 - x6;


X7dRe <=x1cd + x7cd - x5cd - x3cd; X7dIm <=-x1cd + x3cd + x5cd -x7cd;

if X7dRe(7)='1' then X7dRe_jum <= X7dRe(15 downto 8) +'1'; else

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X7dRe_jum <= X7dRe(15 downto 8); end if;






if X7gt_Im(7)='1' then indivI <= "100000000" - X7gt_Im9; else indivI <= X7gt_Im9; end if;

if X7gt_Re(7)='1' then outre7a <="100000000" - X7_Re_QUO; outre7 <= outre7a (7 downto 0); else outre7 <= X7_Re_QUO (7 downto 0); end if;


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CLKEN <='1'; ACLR <='0'; DENOM <= "1000";



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