ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRIT · ANSYS Solution –Geometry Based Reliability...

1 © 2018 ANSYS, Inc. February 2, 2018 ANSYS

ANSYS CPS SOLUTIONFOR SIGNAL AND POWER INTEGRITY

Rémy FERNANDESLead Application EngineerANSYS


ANSYS - Engineering simulation software leaderOur industry reach and solution offerings

Automotive

Aerospace & Defense

Academic

Construction

Consumer Goods

High-Tech

Energy

Healthcare

Industrial Equip.& Rotating Machinery

Materials &Chemical Processing

Industry Presence

Fluids

Structures

Electromagnetics

Thermal

Power Integrity

Systems

Embedded Software

Leading Disciplines

45,000+CUSTOMERSGLOBALLY

Global Reach

1,375+ 650+ 800+PEOPLE2,000+

FROM CHANNEL PARTNERS


• Trends and Challenges of Electronics Industry

– ANSYS Chip-Package-System

• ANSYS SIwave : SI, PI simulation overview

• Demo

AGENDA


Key Trends In Electronics Industry

Miniaturization

Mobility and Wireless Connectivity

Faster Communication

Power Efficiency

Embedded Software


Challenges

Thermal reliability Structural reliability

• Electronics cooling

• Fast hotspots determination

• Board deformations

• Vibrations analysis

• Delamination

• Fatigue

Electrical reliability

• Signal integrity

• Power integrity

• Electrostatic discharge

• Electromagnetic emission


Electrical reliability

Electrostatic dischargeSignal & power integrity

0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00Time [ns]

-0.00020

-0.00015

-0.00010

-0.00005

0.00000

0.00005

0.00010

0.00015

0.00020

V_vlin

e

l_slot__160mmV_lineCurve Info

V_vlineSetup1 : Transient

0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00Time [ns]

-0.00020

-0.00015

-0.00010

-0.00005

0.00000

0.00005

0.00010

0.00015

0.00020

v_lin

e1

l_slot__160mmXY Plot 6Curve Info

v_line1Setup1 : Transient

0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00Time [ns]

-0.00020

-0.00015

-0.00010

-0.00005

0.00000

0.00005

0.00010

0.00015

0.00020

v_lin

e2



0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00Time [ns]

-0.00020

-0.00015

-0.00010

-0.00005

0.00000

0.00005

0.00010

0.00015

0.00020

v_lin

e3



0.00 2.50 5.00 7.50 10.00 12.50 15.00 17.50 20.00Time [ns]

-0.00020

-0.00015

-0.00010

-0.00005

0.00000

0.00005

0.00010

0.00015

0.00020

v_lin

e4

l_slot__160mmXY Plot 8_1Curve Info


Electromagnetic emission


Thermal reliability

Resistive heating of tracesHot spots Flow pattern


Structural reliabilityTrace mapping

Exact deformations and stresses

ECAD

Optimal vibrational behavior Successful passing of the drop test


Power and Signal Integrity Analysis

ECAD Design

ANSYS Solution – Geometry Based Reliability Design

• Multiphysics simulation of printed circuit boards Electro-Thermal Stress Analysis

Joule heating LossesTemperature Field

Temperature Field

Electrical Reliability

Thermal Reliability

Mechanical Reliability

Thermal Analysis

Stress Analysis

ANSYS Mechanical

ANSYS SIwave

ANSYS Icepak


ANSYS Electronic Business UnitDriving CPS : Chip-Package-System Convergence

PACKAGE

Siwave™, HFSS™,Q3D, Icepak®, Mechanical

BOARD

Siwave™, HFSS™,Q3D, Icepak®, Mechanical

CONNECTORHFSS, Q3D,Mechanical

Analog IPsTotem

DDR

HDMI

RF

FLASH

End-to-End Chip-Package-SystemPower, Noise, Thermal, EMI, Timing Platform

Digital RTLPowerArtist

CHIPRedHawk


ANSYS Technologies for Electronic Systems


ANSYS SIWAVE FOR SIGNAL AND POWER INTEGRITY


ANSYS Typical SI/PI Design Flow

Electronic Design Environment(Cadence, Mentor, Zuken, Altium ...)

EM Simulation & Extract Parasitics

Database ImportGeometry, Stack up, Components

SpiceS Parameter

Verilog-AIBIS 5

IBIS AMI

Circuit Simulation

EM Model


Application Example

DC Power Design

• Objective: DC Power Solution

– All ICs require DC power to operate. It is common for layout engineers to inadvertently cause DC shorts and use too few vias when designing PDNs.

• ANSYS Solution

– Use SIwave to predict DC power distribution problems that result in respinning PCBs. This solution finds current bottlenecks, predicts high power losses, and large voltage drops

– Use bidirectional link with Icepak to determine thermal effects

• Value of Simulation

– The simulation of DC power using ANSYS starts with design concepts, includes the influences of manufacturing, and allows detailed evaluation of the power delivery network, signal net routing, connector and via breakouts.


Current Vectors Showing Electron DirectionDC Path Resistance

SIwave Thermal Solves using IcepakPower & Ground Plane Voltage Drop

0.99mΩ0.96mΩ

DC Results & Analysis


Application Example

Timing Analysis

• Objective: High Density & High Speed

– Develop modern electronic devices with greater density of SDRAM (larger RAM) using even-faster speed devices.

• ANSYS Solution

– Performs timing analysis that includes signals & PDN

– Performs fast flight time analysis

– Performs virtual compliance for memory busses


– The simulation of memory, high speed serial links using ANSYS starts with design concepts, includes the influences of manufacturing, and allows detailed evaluation of the power delivery network, signal net routing, connector and via breakouts.


Receiver IC

Driver IC

A digital signal

U7.(pin)60

U1.(pin)25

SNA provides: Zo@ void A Zo@ void B

Void Aon return current path

Void Bon return current path

1. Zo Profile & Delayfor all paths of a signal.

2. Reflection Noisethrough transient analysis.

Signal Net Analyzer Impedance & Flight Time Calculations

Characteristic ImpedanceVoltage waveform at receiver IC


Building the Channel

• Single environment allows extraction of component models such as vias, connectors, and transmission lines as well as concatenating these and other models into a channel schematic

• S-parameters, eye diagrams, and bit error rate of channel can be simulated

• Individual components can be optimized and channel results updated quickly

TX RX


Frequency Domain Channel Analysis

• Simultaneous component- and system-level accuracy allows rapid evaluation of tradeoffs

• In this example a change from stripline to microstrip improves loss at the expense of crosstalk


Time Domain Channel Analysis

• Closed eye at receiver with the stripline topology

• Open eye at receiver with re-designed microstrip topology.

Eye at reference receiver on Stripline topology

Eye at reference receiver on improved Microstrip topology

EH: 62mV


Application Example

AC PDN analysis

• Objective: High Density & High Speed

– Develop modern electronic devices with greater density of SDRAM (larger RAM) using even-faster speed devices.

• ANSYS Solution

– Model power delivery networks and noise propagation on PCBs

– Automates decoupling capacitor selection, placement and optimization

– Predicts capacitor placement effectiveness by analyzing loop return currents

– Use CPM models to predict chip performance to complete system-level simulation


– Simulation of memory using ANSYS starts with design concepts, includes influences of manufacturing, and allows detailed evaluation of power delivery network, signal net routing, connector and via breakouts.


• Designs of today operate in conjuction with a number of clocks, oscillators, power supplies, and signaling standards. Supplying sufficient power means designing a Power Delivery Network capable of handling any perturbations or irregularities that these complex systems demand.

• The example below shows voltage for both the time and frequency domain simulation results of a memory interface. A good design will minimize the voltage ripple to ensure that all active devices have a stable and reliable voltage reference. Excessive perturbations in power could cause adverse affects to input and output margins or even couple to other power rails.

Power Integrity Analysis

873 mV pk-pk due to 200 MHz PRBS


VRM Transient Simulation Setup

Voltage Regulator Module (VRM) is modeled with a series source resistance of 5mΩ for this example.

Active Device is modeled as a Current Sink

• 1A Amplitude: 𝐼𝑝𝑘−𝑝𝑘 = 2𝐴

• Frequency = 5 MHz

• Time Delay = 1𝜇𝑠

Example 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = 𝐼 (5𝑀𝐻𝑧) ∗ 𝑍 (5𝑀𝐻𝑧)

𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = 5𝑚𝑉 = 10𝑚𝑉𝑝𝑘−𝑝𝑘

Supplying Power

VRMActiveDevice


VRM Frequency Domain Response

At DC, 𝑍11 = 5𝑚Ω which is the VRM series resistance.

At 𝑓 → ∞, 𝑍11 → ∞ due to the path loop inductance. In this case, a total of 11pH.

Example 𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = 𝐼 (5 𝑀𝐻𝑧) ∗ 𝑍 (5 𝑀𝐻𝑧)

𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = 1𝐴 ∗ 𝟓𝒎𝜴

𝑉𝑟𝑖𝑝𝑝𝑙𝑒 = 5𝑚𝑉 = 10𝑚𝑉𝑝𝑘−𝑝𝑘

Supplying Power

0

RZ=0.1ohm

0.005

1V

1p0.01n

𝒁𝟏𝟏


Early PI Investigations : Auto Select Capacitor• Define a VRM Model + PCB using ESR and ESL parameters : Red curves• Define an Impedance Mask as Target or Load it• Filter Capacitors Vendors, Series, EIA size and run the AUTO .


• Circuit Simulation vs. Electromagnetic Field Solvers Real, physical designs have many more inductive loops, capacitive planes, and resistive paths which were not

depicted in the previous example circuit. In order to account for all of the effects of physical layout and geometry complexities, a field solver such as Siwave or HFSS must be used.

In any of the methods shown, loop inductance plays a vital role in determining the frequency of effectiveness. The L-C combination dictates the resonant frequency of adding or changing a capacitor value at a specific location.

𝑓𝑟𝑒𝑠𝑜𝑛𝑎𝑛𝑐𝑒 =1

2𝜋 𝐿𝐶 Equivalent Series Resistance (ESR) and conductor path resistance affects the quality factor (Q) of the placed

component.

𝑄 =

12𝜋𝑓𝐶

𝐸𝑆𝑅

Simulation of Physical Structures

VRM

Active Device

Active DeviceVRM


Resonance Simulation

• Eigenmode analysis identifies location and frequency of natural cavity resonances that exist between planes

• Scans entire PCB/PKG on all layers

• If a resonance is excited, Signal Integrity can be compromised :

• High Z, null in S21, EMI etc.

• Resonances should be moved away from critical parts and outside operating frequency

• Reducing Resonance :

• Resonances always exist but you can reduce their impact by:

Changing the decoupling scheme

Changing the stackup

Changing plane dimensions

Adding via stitching

Moving discrete parts


SIwave – SYZ Analysis Setup to extract [S], Z vs Freq

Ports are similarto probes in lab measurements

To Perform a circuitextraction or SI analysis,

place ports in desired location


Power Delivery Network Impedance

• Full-wave extraction of entire PDN including:• Board geometry

• Passive components : Turn ON or OFF decaps

Bare PCB

With Capacitors

Z11


• SIwave AC Solver or PSI AC Solver

• SIwave AC Solve Time = 15 min 7 sec Frequency Setup

• 1KHz <= f < 1GHz

Genetic Algorithm Setup• Optimized for Impedance• Optimized for Total Number of Caps• Optimized for Capacitor Types• Optimized for Price

• Original solution Total # Caps: 74

• Optimized Solution Total # Caps: 18 Capacitor Types = 5

• AVX, Samsung, and Kemet

PI Advisor: Automated PI Analysis

Optimizes Decoupling Capacitors for Power Integrity

1.7nH

.25nH

1.0nH


• The final step is to run a transient simulation to look at the Switching Power Noise

• Load Voltage Swing within 50 mV Target!

PDN Transient Circuit Simulation

Time-domain noise specification met


Example : PCIe3.0 simulation

Controller Side (Driver)

Connector Side (Termination)

1.5V supply

• Transient stimulus is applied to critical nets and the Near- and Far-Field response is computed in SIwaveusing Push Excitation.

• IBIS model is used for the controller to excite the TX, RX and CLK diff pairs

– 100MHz clock source (with jitter) for CLK

– PRBS7 for TX and RX; UI = 1ns (1/1GHz for PCIe3.0), 8b/10b encoding

– Terminate the pins at the Connector side using Resistors

– 100ohm differential termination

– Supply an ideal 1.5V input at the VRM node

clk_out Spectral Waveform Power supply lines


EMI/EMC simulation : Near-Field Plots

E –Field @ 100MHz

• SIwave Near Field analysis is using the results from the transient simulation as current sources to excite the PCB with the true excitations (Push Excitation process)


Thank youMerci

ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRIT · ANSYS Solution –Geometry Based Reliability...

Documents

Transcript of ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRIT · ANSYS Solution –Geometry Based Reliability...