Annealing of Heavy-Ion Induced Floating Gate Errors: LET and Feature Size Dependence

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 4, AUGUST 2010 1835

Annealing of Heavy-Ion Induced Floating GateErrors: LET and Feature Size Dependence

Marta Bagatin, Simone Gerardin, Giorgio Cellere, Alessandro Paccagnella, Angelo Visconti, Silvia Beltrami,Mauro Bonanomi, and Reno Harboe-Sørensen

Abstract—We discuss the room temperature annealing ofFloating Gate errors in Flash memories with NAND and NOR ar-chitecture after heavy-ion irradiation. We present the evolution ofraw bit errors as a function of time after the exposure, examiningthe annealing dependence on the particle LET, cell feature size,and, for Multi Level Cells, on the program level. The results areexplained based on the statistical properties of the cell thresholdvoltage distributions before and after heavy-ion strikes.

Index Terms—Annealing, flash memories, heavy ions, radiationeffects.

I. INTRODUCTION

I T IS hard to underestimate the importance of Flash tech-nologies in the current memory market for ground-level ap-

plications, from MP3 players to digital cameras. In addition,Flash memories are used in areas where high reliability is offundamental importance (automotive, biomedical, security con-trols, etc.). Thanks to their low power requirements and extremedensity, they are increasingly attractive for use in harsh environ-ments as well, where the sensitivity to ionizing radiation is animportant issue. For this reason, a careful evaluation of SingleEvent Effect (SEE) and Total Ionizing Dose (TID) susceptibilityis necessary to predict the device behavior when exposed to radi-ation in harsh environments, such as space, high-energy physics,nuclear power plants, etc.

Many contributions in the literature deal with SEE and TIDeffects on both the Floating Gate (FG) array and the peripheralcircuitry [1]–[7]. Until 10 years ago it was unlikely that a singleion hit could affect the information stored in the FG [1], [2],due to the large dimension of the memory cells. As a conse-quence, at that time the attention during radiation experimentswas mainly focused on the study of the control circuitry sensi-tivity (especially charge pumps). This scenario changed in thefirst half of this decade, when errors in the FG array started to be

Manuscript received September 11, 2009; revised January 14, 2010; acceptedFebruary 17, 2010. Date of current version August 18, 2010.

M. Bagatin, S. Gerardin, and A. Paccagnella are with the RREACT group,Dipartimento di Ingegneria dell’Informazione, Università di Padova, Italy, andwith Istituto Nazionale di Fisica Nucleare (INFN), Padova, Italy (e-mail: marta.bagatin, [email protected], [email protected]).

G. Cellere was with the RREACT group, Dipartimento di Ingegneria dell’In-formazione, Università di Padova, Italy, and is now with Applied Materials Bac-cini, Treviso, Italy (e-mail: [email protected]).

A. Visconti, M. Bonanomi, and S. Beltrami are with Numonyx, R&DTechnology Development, Agrate Brianza (MI), Italy (e-mail: [email protected], [email protected], [email protected]).

R. Harboe-Sørensen is with ESA/ESTEC, The Netherlands (e-mail: [email protected]).

Digital Object Identifier 10.1109/TNS.2010.2045131

detected as well [3]. Finally, in the second half of this decade theFG matrix cross section became comparable or even exceededthat of the control circuitry [4], [6], [10] . This was the resultof technology scaling, which drastically reduced the amount ofcharge needed in the FG to store the required logic level, causingthe read margins to become smaller and smaller, increasing thecell sensitivity. In addition, the introduction of Multi Level Celldevices is causing the radiation response to become even morecomplex.

The mechanisms proposed to explain errors in the FG are con-nected with two distinct phenomena: charge loss from the FG,due to a transient conductive path across the tunnel oxide; andcharge trapping in the tunnel oxide [3], [5], [8]. Annealing ofFG errors has been recently addressed in a number of contri-butions [8]–[11] in connection with charge detrapping/neutral-ization, leaving some questions to be answered. Neglecting thepost radiation annealing may cause, depending on the programlevel and other factors, not only an overestimation, but in somecases also an underestimation of the ion-induced number of er-rors [11]. For this reason, annealing should be carefully takeninto account during testing and properly modeled.

The purpose of this work is to gain a deeper understandingof the FG error annealing, by analyzing the dependence of thepost-radiation error reduction on the cell feature size and onthe LET of the incident particle. As we shall see, these factorsstrongly affect both the percentage of annealed errors and theannealing rate. Accurate modeling can be made only throughproper statistical information on the threshold voltage dis-tributions, available only to the manufacturer.

The paper is organized as follows: after a description of theexperimental details, we will first present the results on SingleLevel Cell NAND memories of two different technology nodes,irradiated with ions having different LET; and then on MultiLevel Cell NOR memories. After that we will investigate the an-nealing dependence on the ion LET, technology, program level,and discuss how the shape of the threshold voltage distributionaffects the annealing dynamics.

II. EXPERIMENTAL APPROACH AND DEVICE DESCRIPTION

In this paper we study commercial Flash devices manufac-tured by Numonyx: 1-Gbit 90-nm and 4-Gbit 70-nm SingleLevel Cell (SLC) NAND (part number NAND0XG-B2B);90-nm Multi Level Cell (MLC), 2-bit-per-cell NOR Flash (partnumber M58PR256J). Table I summarizes the features of thestudied devices. Information is stored in a Floating Gate cellby introducing excess charge in the FG, either electrons orholes, thus changing its . The cell is then compared toa reference voltage , through a sensing circuit, in order

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1836 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 4, AUGUST 2010

Fig. 1. Sketch for the � distributions in SLC NAND memories. Erased andprogrammed levels correspond to holes and electrons in the FG, respectively,while neutral cells have no charge stored in the FG.

Fig. 2. Sketch for the � distributions in MLC NOR memories. The erasedlevel stores holes in the FG. For the program levels, increasing cell � ’s areobtained storing an increasing number of electrons in the FG. Neutral cells haveno charge in the FG.

TABLE IUSED DEVICES

to generate a digital output, which is the only informationavailable in User Mode (UM). Figs. 1–2 depict the diagram ofthe cell distributions for the SLC NAND and MLC NORdevices used in this work, respectively. Neutral cells are thecells with neither holes nor electrons stored in the FG, whileerased and programmed ones feature different amounts of holesand electrons, respectively.

The memories were irradiated at the SIRAD beam line ofthe TANDEM accelerator at the INFN Laboratori Nazionali diLegnaro (LNL) (Padova, Italy), with ions having different LET.All the details about the ion species we used are reported inTable II.

Some NAND blocks and NOR sectors of the devices wereprogrammed prior to irradiation with different patterns (eitherall zeroes ’00’ or checkerboard ’55’, for SLC NAND; all fourprogram levels, for MLC NOR). To exclude the onset of errorsother than FG cell errors, we protected the memory peripheralcircuitry (charge pumps, row decoder, page buffer, etc.) with

TABLE IIION SPECIES

4-mm-thick Aluminum shields during heavy-ion exposure. Allirradiations were performed with the device unbiased, at normalincidence, and at room temperature. An ion fluence between

– ions/cm was chosen (and adjusted for every ion de-pending on its LET) so that a statistically significant numberof errors (several hundreds or thousands) could be gathered foreach experimental point. Note that all irradiations lasted just fewtens of seconds, so it is possible that some errors annealed duringexposure itself.

After irradiation, we kept the devices unbiased at roomtemperature, and periodically monitored their functionalityup to 120 hours after exposure (3000 hours for NOR MLCdevices), measuring the number of errors in the irradiatedblocks/sectors. For both NAND and NOR memories, manda-tory Error Correction Codes (ECC) algorithms were disabledduring the experiments, allowing us to simplify the analysisand have the maximum visibility on ion-induced errors. ECCis managed in different ways in NAND and NOR devices. InNAND, it is user’s responsibility to correctly implement ECC(to this purpose, the manufacturer dedicates some extra bits inevery page—the so-called “spare area”). Hence, “ignoring” theECC simply means not implementing it. Conversely, in NORdevices the reliability of each single bit is guaranteed by themanufacturer by the implementation of error correction insidethe device itself. For this reason, a special Test Mode routinein our NOR testing board enables the deactivation of ECCduring read operations. In the following, we will call the errorsobserved without the application of ECC “raw bit errors”.

III. RESULTS

Immediately after heavy-ion irradiation of SLC NANDblocks and MLC NOR sectors programmed with differentpatterns, we detected several single-bit errors on NAND cellsprogrammed at ’0’ (i.e., with electrons stored in the FG) and onNOR cells programmed at ’00’ and ’01’. On the other hand, noerrors were detected in the lowest levels (’1’ for SLC NAND,’10’ and ’11’ for MLC NOR; see Figs. 1–2). Error correction,when embedded, was disabled during the experiments.

After irradiation, the devices were kept unbiased at room tem-perature and the errors were periodically monitored. We foundthat, for all the tested devices, the number of errors decreases asa function of the time after exposure. This phenomenon was al-ready observed in [10] and earlier works [8], [9]. More recently,a similar behavior was reported after x-ray and proton expo-sure as well [11]. FG error annealing is observed, although withdifferent characteristics, in NAND and NOR architectures, indevices belonging to different technology nodes and producedby different vendors, and in memories irradiated with ions of

BAGATIN et al.: ANNEALING OF HEAVY-ION INDUCED FLOATING GATE ERRORS: LET AND FEATURE SIZE DEPENDENCE 1837

Fig. 3. Room temperature annealing (lin-log scale) of FG cell errors in a 70-nmNAND Flash after Nickel irradiation. Some blocks were programmed with all’0’, some others with checkerboard pattern. The reported time is the time elapsedfrom the end of the irradiation. The number of FG cell errors has been normal-ized by its value a few minutes after the exposure.

Fig. 4. Room temperature annealing of FG cell errors in a 70-nm NAND Flashafter Bromine irradiation. Some blocks were programmed with all ’0’, someothers with checkerboard pattern. The number of FG cell errors has been nor-malized by its value a few minutes after the exposure.

Fig. 5. Room temperature annealing of FG cell errors in a 70-nm NAND Flashafter Iodine irradiation. Some blocks were programmed with all ’0’, some otherswith checkerboard pattern. The number of FG cell errors has been normalizedby its value a few minutes after the exposure.

different LETs. It is therefore a general and fundamental phe-nomenon, that is not associated with a particular set of devicesor experimental conditions.

Fig. 6. Percentage of annealed errors for 70-nm and 90-nm SLC NAND de-tected 120 hours after irradiation, as a function of ion LET, with respect tothe number of errors one hour after irradiation. The errors refer to blocks pro-grammed with all zeros pattern.

Figs. 3–5 show the temporal evolution (in lin-log scale) of FGerrors in three 70-nm SLC NAND Flash memories irradiatedwith different ions (Nickel, Bromine, and Iodine). In order tocompare the behavior with the three ions, the number of FGerrors has been normalized at the same time after the exposure(a few minutes after the irradiation).

In all cases, a monotonic decreasing trend is observed, eventhough different rates of annealing are observed depending onthe ion LET. In fact, despite the similar qualitative trends, thedecrease of the errors in Fig. 3 is slower at the beginning than atthe end (two slopes are clearly observable in the figure), whereasthe opposite occurs in Figs. 4 and 5 represents an intermediatecase. In other words, the reduction of the errors after higherLET ion exposure is stronger at short times, and weaker at longtimes. Irradiations were performed with the NAND blocks pro-grammed with both all zeroes and checkerboard pattern, andvery similar results were obtained in the two cases, as shownin Figs. 3–5, if one considers only the FG programmed to ’0’(again, no errors were detected in FGs set to ’1’). This meansthat no proximity effects occur (i.e., the error probability of agiven cell is not affected by errors in the neighbor cells).

The scatter in the annealing data reported in Figs. 3–5 is dueto intermittent errors. In fact, when the ion-induced shiftbrings the cell close to the reference voltage, that bit issometimes read as 1 or as 0, depending on the noise on the celland read-out circuits. By the way, this effect is exacerbated invery scaled technologies where the random telegraph noise ofthe FG cells is more severe. For a deeper discussion about in-termittent errors see [10]. To quantitatively assess these varia-tions (and error bars), we processed the data by removing themain trend (due to the annealing) and calculating the fluctua-tions in the number of read errors. Fluctuations are 1% at mostin Figs. 3–5.

An analogous behavior was observed in the 90-nm parts, butwith different annealing rates (not shown). Fig. 6 summarizesall the data we gathered on NAND memories. In particular, thegraph depicts the percentage of annealed errors 120 hours afterthe heavy-ion exposure, as a function of the ion LET and tech-nology node, for memories programmed with all zeros pattern


Fig. 7. Room temperature annealing of User Mode errors (no ECC) in a 90-nmNOR MLC Flash after Nickel irradiation. The errors are monitored in sectorsprogrammed with the two highest� program levels (’00’ and ’01’, see Fig. 2).Both experimental data and logarithmic fits are reported.

before exposure. The percentage of annealed errors is calculatedwith respect to the errors detected 1 hour after irradiation: in thisway, we neglect the initial part of the annealing process, wherethe fluctuations in the number of errors may be significant andalter our analysis. The most striking feature we observe in Fig. 6is the more pronounced annealing for errors in 90-nm devicescompared to 70-nm ones. In fact the annealed error percentageranges from 4% to 10% in the smaller feature size devices, whilefor the larger technology node it reaches 34% to 74% in the con-sidered LET range. In addition, as seen in the figure, for both70-nm and 90-nm parts, the lower the particle LET the higherthe percentage of errors that anneal after 120 hours.

Flash memories with Multi Level Cell NOR architecture alsoexhibit an annealing of the observed FG errors. Fig. 7 illus-trates the post-radiation error evolution for a 90-nm MLC NORmemory irradiated with Nickel. Again, the number of raw biterrors (i.e., measured without ECC) is maximum immediatelyafter the exposure and then monotonically decreases as timegoes by. As the experimental data are quite scattered (due tointermittent errors, as explained in the previous section), Fig. 7also provides logarithmic fits of the number of FG errors thatare useful as a guide to the eye.

Interestingly enough, the evolution of the errors in the cellsprogrammed with ’01’ (corresponding to the distribution athigher , see Fig. 2) features a different behavior comparedto the cells with pattern ’00’. In fact, both the annealing speedand the number of annealed errors for cells programmed in the’01’ state are lower with respect to the ’00’ state. In other words,the higher the of the FG cell, the smaller the percentageof annealed errors for that program level. Concerning the othertwo patterns, we did not observe any error both in the erasedcells (’11’) and in the cells programmed with the lowerlevel (’10’), due to the lower electric field.

We just briefly mention that, for both NAND and NOR mem-ories, errors must be measured at a constant temperature. In fact,the number of detected errors depends on the device tempera-ture during read operation (for a more detailed discussion ontemperature effects please refer to [11]).

IV. DISCUSSION

It is worthwhile to remark that the single-bit errors describedup to now are not due to radiation damage in the memory controlcircuitry. In fact, all the peripheral circuitry was shielded duringour experiments. Therefore, the errors can be traced back toshifts in the FG cells, which can be explained by thecombination of two phenomena:

i. Charge loss from the FG;ii. Charge trapping in the oxides surrounding the FG.The discharge of the FG cell through a transient ion-in-

duced conductive path across the tunnel oxide has been deeplyinvestigated in the last decade [3]. The result of charge lossis a permanent shift (which can be recovered only afterreprogramming the cell), that in the following will be called

. In addition to charge loss, charge trapping mayalso occur in the oxides surrounding the FG [5], especially inthe tunnel oxide. Contrary to charge loss, charge trapping isrecoverable through neutralization. In the following, we willcall the threshold voltage shift induced by chargetrapping. This term is a function of time after irradiation dueto neutralization and detrapping of the charge in the oxide.Note that all the above mentioned threshold voltage shifts areaverage values.

Our results can be explained based on the relative contribu-tions of these terms and on the shape of the distributions,before and after the heavy-ion irradiation [12].

A. NAND SLC: Technology and LET Effects

Fig. 8 depicts a sketch of the cell distributions for SLCNAND memories. In these memories the watershed betweenprogrammed (’0’) and erased (’1’) status is the read voltage

, which is 0 V in our SLC NAND devices (verticaldashed line in Fig. 8). The ion-induced shift causessome memory cells to move away from the distribution ofthe programmed cells, giving rise to a secondary peak, shownwith solid line in Fig. 8, at an average distance (givenby ) which corresponds to the distancebetween the peak of the primary and secondary distributions. Abit error occurs if the overall shift is largeenough to bring the cell beyond , so that the cell is incor-rectly read. Depending on the amount of the two contributions

and , a given error may anneal or not afterexposure. If alone is able to bring the cell beyond

, the error will not anneal, not even after neutralization oftrapped charge. Conversely, if both contributions are necessaryto cause the wrong read of the cell, the error may anneal aftercharge neutralization/detrapping. In fact, due to neutralization,the cell may cross again, as we discussed in previouswork [10].

These considerations deal with average values, but to deter-mine the amount of annealed errors and the rate and shape ofthe annealing curves, statistical distributions of the initialand of the shifts induced by heavy ions are of great impor-tance. If all the distributions of cell threshold voltages wereDirac delta functions, errors would disappear all at once, with astep-like function. Conversely, different shapes of the secondary


Fig. 8. Sketch of � cell distributions (in log-lin scale) for SLC NANDafter irradiation. Secondary peaks induced by heavy ions are shown with solidlines, while primary distributions with dotted lines. Note that “maximum” and“slower” refer to the number of the annealed errors (not to the percentage).

distributions lead to different error annealing curves. If we as-sume that changes at a fixed rate (in a log scale), awide secondary distribution determines a slower annealing thana narrow one, because in a fixed interval of time during the re-covery process, the number of cells crossing will be lowercompared to a narrow distribution. On the contrary, a narrowdistribution will cause a faster reduction in the FG errors, asschematically shown in Fig. 8. Wider secondary distributionsare expected with smaller floating gate cells, because of the in-trinsic higher variability associated with smaller feature size.This is certainly a reason for the technological trend observedin Fig. 6, where 70-nm memories exhibit a smaller percentageof annealed errors than 90-nm parts (at least up to 120 hours).

An important parameter we should examine when comparingdifferent technologies is the tunnel oxide thickness. In fact, theerror recovery process is due to electrons tunneling into theoxide and either recombining with the holes, or forming com-pensating sites, as described by Lelis et al. in [13] . It is wellknown that this tunneling process is faster in thinner oxides. Ashighlighted in Table I, both the 90-nm and 70-nm samples usedin this study have the same tunnel oxide thickness (8.5 nm). Asa consequence, this parameter is not considered in the analysis.

Since secondary distributions move over time, because ofcharge detrapping/neutralization, the annealing rate for a singledevice may change as time elapses, depending on the pointwhere crosses the secondary distribution as a function oftime, which is in turn determined by the amount of heavy-ioninduced . This is in agreement with the experimentalobservations of Figs. 3–5, where variable annealing rates arepresent as a function of time.

As depicted in Fig. 8, the maximum annealing (in terms ofthe absolute number of annealed errors) takes place when thesecondary distribution is centered on the read voltage. The rel-ative position of the secondary distribution with respect to theread voltage is a function of the ion LET. To a first order ap-proximation, this is determined by the charge loss contribution.In fact, has been shown to dominate overin these devices [11], due to the small thickness of the tunneloxide layer 8.5 nm , which has minimal charge trapping. In

Fig. 9. Measured charge loss induced threshold voltage shift �� as afunction of ion LET for the 70-nm and 90-nm SLC NAND samples used in thiswork.

addition, the trapped charge is neutralized quite fast by the tun-neling electrons, leaving charge loss (which is irreversible) asthe dominant factor.

As reported in previous works, is a function ofthe ion LET [3]. The higher the LET, the larger theproduced by the ion. In particular, Fig. 9 shows the measured

generated in the NAND FG by the ions we used inthis work, for both the 70-nm and 90-nm technology nodes. Asseen in the figure, the trend is practically linear and very similarfor both technologies, even though the charge loss impact onthe is higher for the 70-nm parts, as expected, due to thelower number of carriers used to store information.

Even though there is a simple enough relationship betweencharge loss and LET, the dependence of the annealing rate onthe ion ionizing power is not straightforward at all. In fact, de-pending on the actual values, the read voltage may intersect therising or the falling part of the secondary distribution, causingthe absolute number of annealed errors to increase or decreasewith LET. When considering the relative number of annealederrors (as in Figs. 3–5), one must also consider that the totalnumber of errors (some of which will never anneal because theyare too far from [10]) observed immediately after irradia-tion increases with LET for a given ion fluence. This obviouslygoes in the direction of lowering the percentage of annealed er-rors for increasing LET.

The dependence of charge trapping [14], [15] on the par-ticle LET should be taken into account as well, to estimate thenumber of errors that may potentially anneal after exposure. Itis clear that the larger the amount of trapped charge, the largerthe amount of cells that may recover, crossing back . Theamount of trapped charge is proportional to the charge gener-ated in the oxide by the impinging ion (i.e., the LET), multipliedby the fractional yield, which gives the amount of charge thatsurvives recombination, and by the trapping coefficient of thestudied oxide. Charge yield is, in turn, a function of LET. Therelationship between fractional yield and LET has been theoret-ically and experimentally analyzed by Stapor et al. [15]. Usingthe data in [15], we can calculate the ratio between and

. It turns out that the ratio is reasonably constant with


the LET (less than 10% in the range of interest). We can con-clude that goes in the direction of increasing the an-nealing rate for increasing LET. This term should be accountedfor, together with the other factors we have discussed in this sec-tion, to determine the annealing behavior of the device.

B. Modeling of the Annealing Curves

To further analyze the aspects we have considered in the pre-vious section and schematically summarized in Fig. 8, we mod-eled the error annealing curves, studying the impact of the tech-nology. The main starting hypotheses for the model are:

a. Gaussian distribution for the cell before irradiation(see [16]);

b. Gaussian distribution for the LET of the incoming ions,which is valid for particles with low energy over mass [17](which is the case for our experimental conditions);

c. Larger variance for the post-rad distribution insmaller feature size devices (due to the intrinsic highervariability associated to smaller cells);

d. Larger for the more scaled devices[18];e. The read voltage intersects the secondary peak.

Combining i. and ii., it follows that the ion-induced sec-ondary distributions can be modeled as a Gaussian function aswell.

Based on this, we can model the shape of the annealing curve,calculating the number of cells in the secondary distribution thatcross the reference voltage due to positive charge detrapping.

As shown in Fig. 10, where realistic values are used for ,, etc., the annealing rate strongly depends on the varianceof the secondary distributions and on the position of the

read voltage relative to the secondary peak (i.e., on ), asqualitatively discussed in the previous section. The x axis of thefigure represents the ion-inducedwhich is directly related to the particle LET. Fig. 10 thereforeanalytically confirms that the higher the LET (larger ), thefaster the annealing process, in agreement with the experimentalresults shown in Figs. 3–5. In addition to that, narrow secondarydistributions (indicated in Fig. 10 with ’smaller ’) cause a morepronounced percentage of annealed errors than wider distribu-tions (’larger ’), at least if we consider small enough(see Fig. 10, for high values of the trend is reversed). Wealso find qualitative agreement between Fig. 10 and the exper-imental data shown in Fig. 6, keeping in mind that for smallerfeature size cells the ion-induced is larger with respect tolarger cells.

It is important to remark that our discussion assumes that thecrosses the ion-induced secondary peak (hypothesis v.).

In fact, as shown in [19], in addition to the secondary peak, atail in the distributions is created after irradiation, betweenthe primary and the secondary peaks. This tail includes all thosecells that experienced a non-negligible Ä , even though theyhave not been hit directly by impinging particles. In the case theread voltage intersect the distribution exactly in this tail, theanalysis we have made up to now should be properly adapted.

C. NOR MLC: Effect of Different Patterns

For MLC memories the situation is more complex becausefour primary distributions are present, being two bits stored in

Fig. 10. Percentage of annealed errors as a function of �� , obtained modeling the secondary distributions with Gaussian func-tions having different variance ��.

Fig. 11. Sketch of � cell distributions (in log-lin scale) for Multi Level CellNOR memories after heavy-ion irradiation. Secondary peaks induced by heavyions are shown with solid lines, while primary distributions with dotted lines.Reference voltages are represented with vertical dashed lines.

every FG cell. Fig. 11 schematically depicts the cell distri-butions for our MLC NOR devices after heavy-ion irradiation;the three reference voltages are shown with dashed lines. Ascharge loss and charge trapping take place, the hit cells shift to-wards the neutral distribution (i.e., that with neither electronsnor holes stored in the FG) which, for these samples, lies be-tween the ’11’ and ’10’ peaks (see Fig. 2). Due to the differentvalues of the electric field in the various program levels, thelarger the distance from the neutral distribution, the larger the

of the hit cell. As mentioned before, domi-nates over . That is why increases for increasingcell .

What is left to clarify is the different annealing rate and per-centage of annealed errors observed in Fig. 7 for the two pro-gram patterns. One possibility is to assume that the ’01’ sec-ondary peak is more spread than ’00’ one (Fig. 11), becauseof the shape of the primary distributions those cells come from(the ’01’ distribution is usually more spread than the ’00’ onein MLC devices). A narrow distribution, as reported in the pre-vious Section, means a slower annealing of the raw bit errors,thus explaining the behavior observed in Fig. 7.


V. CONCLUSIONS

We have shown that heavy-ion induced Floating Gate errorsanneal at room temperature after irradiation. This phenomenonoccurs in both NAND and NOR architectures, with differentrates depending on the memory cell size and the impinging ionLET. Several factors can influence the annealing dynamics. Theshape and position of the secondary distribution, which con-tains the cells hit by the ions, relative to the read voltage arethe most important ones. These two factors are mainly deter-mined by the ion LET, cell parameters, and their statistical vari-ations. Concerning the shape of the secondary peak, the morespread the secondary distribution, the slower the annealing. Asfor the position of the peak with respect of the read voltage, thenumber of errors that anneal is maximum when the secondarydistribution is centered on the read voltage. These findings aresupported by an analytical model through which we model theannealing curves, representing secondary peaks with Gaussiandistributions. For Multi Level Cell memories, errors in cells pro-grammed with different patterns anneal with different rates, de-pending on the amount of the threshold voltage shift and on theshape of the pre-irradiation distribution.

ACKNOWLEDGMENT

The authors would like to thank A. Vigilante and S. Schippers(WBG—Wireless Business Group, Numonyx) for their tech-nical support, and S. Mattiazzo, D. Pantano, and M. Tessaro(INFN, Padova) for their invaluable help with the SIRADirradiation facility.

REFERENCES

[1] H. R. Schwartz, D. K. Nichols, and A. H. Johnston, “Single-eventupset in flash memories,” IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp.2315–2324, Dec. 1997.

[2] D. N. Nguyen, S. M. Guertin, G. M. Swift, and A. H. Johnston, “Radi-ation effects on advanced flash memories,” IEEE Trans. Nucl. Sci., vol.46, no. 6, pp. 1744–1750, Dec. 1999.

[3] G. Cellere, P. Pellati, A. Chimenton, A. Modelli, L. Larcher, J. Wyss,and A. Paccagnella, “Radiation effects on floating-gate memory cells,”IEEE Trans. Nucl. Sci., vol. 48, no. 6, pp. 2222–2228, Dec. 2001.

[4] T. Langley and P. Murray, “SEE and TID test results of 1 Gb flashmemory,” in Proc. IEEE Radiation Effects Data Workshop Rec., 2005,pp. 58–61.

[5] T. Oldham, R. Ladbury, M. Friendlich, H. Kim, M. Berg, T. Irwin,C. Seidleck, and K. LaBel, “SEE and TID characterization of an ad-vanced commercial 2 Gbit NAND flash nonvolatile memory,” IEEETrans. Nucl. Sci., vol. 53, no. 6, pp. 3217–3222, Dec. 2006.

[6] F. Irom and D. N. Nguyen, “Single event effect characterization of highdensity commercial NAND and NOR non volatile flash memories,”IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2547–2553, Dec. 2007.

[7] M. V. O’Bryan, K. A. LaBel, S. P. Buchner, R. L. Ladbury, C. F.Poivey, T. R. Oldham, M. J. Campola, M. A. Carts, M. D. Berg, A.B. Sanders, and S. R. Mackey, “Compendium of recent single eventeffects results for candidate spacecraft electronics for NASA,” in Proc.IEEE Radiation Effects Data Workshop Rec., 2008, pp. 11–20.

[8] S. Guertin, D. Nguyen, and J. Patterson, “Microdose induced data losson floating gate memories,” IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp.3518–3524, Dec. 2006.

[9] H. Schmidt, D. Walter, M. Brüggerman, F. Gliem, R. Harboe-Sørensen,and P. Roos, “Annealing of static data errors in NAND-flash memo-ries,” RADECS 2007, 5 pp.

[10] M. Bagatin, S. Gerardin, G. Cellere, A. Paccagnella, A. Visconti, S.Beltrami, R. Harboe-Sørensen, and A. Virtanen, “Key contributions tothe cross section of NAND flash memories irradiated with heavy ions,”IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3302–3308, Dec. 2008.

[11] M. Bagatin, S. Gerardin, G. Cellere, A. Paccagnella, A. Visconti, M.Bonanomi, and S. Beltrami, “Error instability in floating gate flashmemories exposed to TID,” IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp.3267–3273, Dec. 2009.

[12] G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi, S. Beltrami,R. Harboe-Sorensen, and A. Virtanen, “Effect of ion energy on chargeloss from floating gate memories,” IEEE Trans. Nucl. Sci., vol. 55, no.4, pp. 2042–2047, Aug. 2008.

[13] A. J. Lelis, H. E. Boesch, Jr, T. R. Oldham, and F. B. McLean, “Re-versibility of trapped hole annealing,” IEEE Trans. Nucl. Sci., vol. 35,no. 6, pp. 1186–1191, Dec. 1988.

[14] T. R. Oldham, K. W. Bennett, J. Beaucour, T. Carriere, C. Polvey, andP. Garnier, “Total dose failures in advanced electronics from singleions,” IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1820–1830, Dec. 1993.

[15] W. J. Stapor, L. S. August, D. H. Wilson, T. R. Oldham, and K. M.Murray, “Proton and heavy-ion radiation damage studies in MOS tran-sistors,” IEEE Trans. Nucl. Sci., vol. NS-32, no. 6, pp. 4399–4404, Dec.1985.

[16] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories.Boston, MA: Kluwer Academic, 2000.

[17] M. Murat, A. Akkerman, and J. Barak, “Ion track structure and dy-namics in SiO ,” IEEE Trans. Nucl. Sci., vol. 55, no. 4, pp. 2113–2120,Aug. 2008.

[18] G. Cellere, S. Gerardin, M. Bagatin, A. Paccagnella, A. Visconti, M.Bonanomi, S. Beltrami, P. Roche, G. Gasiot, R. H. Sorensen, A. Vir-tanen, C. D. Frost, P. Fuochi, C. Andreani, G. Gorini, A. Pietropaolo,and S. Platt, “Neutron-induced soft errors in advanced flash memories,”in IEEE IEDM Tech. Dig., 2008, pp. 357–360.

[19] G. Cellere, A. Paccagnella, A. Visconti, and M. Bonanomi, “Secondaryeffects of single ions on floating gate memory cells,” IEEE Trans. Nucl.Sci., vol. 53, no. 6, pp. 3291–3297, Dec. 2006.

Annealing of Heavy-Ion Induced Floating Gate Errors: LET and Feature Size Dependence

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