ANNA UNIVERSITY OF TECHNOLOGY,...

ANNA UNIVERSITY OF TECHNOLOGY, COIMBATORE

B.E/B.Tech DEGREE EXAMINATIONS NOV/DEC 2011

REGULATIONS: 2008

V SEM ECE

MICROPROCESSORS AND APPLICATIONS

PART A

1. What is the role of stack in microprocessor?

2. Specify the two 8085 signals that are used to latch data in an output port

3. List the segment registers and their corresponding default offset registers in 8086

4. What happen in 8086 when DEN =0 and DIR=1?

5. What is the operation carried out when 8086 executes the instruction MOVSW?

6. List the interrupts of 8086.

7. What is the difference between two key lockout and N-key rollover modes in 8279?

8. If a 10 bit ADC has the reference voltage of 10V.What is the resolution of ADC?

9. How many address lines are required to interface 8KB memory?

10. What is memory mapped I/O?

Solutions:

1. Stack

The stack is a group of memory locations in the R/W memory that is used for the temporary storage

of binary information during the execution of the program. The stack related instructions are PUSH

& POP

2. 8085 signal

ALE, IO/M and WR

3. Segment registers in 8086?

There are 4 segment registers present in 8086. They are

1. Code Segment (CS ) register - The code segment register gives the address of the current code

segment. ie. It will points out where the instructions, to be executed, are stored in the memory.

2. Data Segment (DS ) register - The data segment register points out where the operands are stored

in the memory.

3. Stack Segment (SS ) register - The stack segment registers points out the address of the current

stack, which is used to store the temporary results.

4. Extra Segment (ES ) register - If the amount of data used is more the Extra segment register points

out where the large amount of data is stored in the memory.

4. DEN, DIR

This signal indicates the availability of valid data over the address/data lines. It is used to enable the

transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It

is active from the middle of T2 until the middle of T4. This is tristated during ‘hold acknowledge’

cycle.

5. MOVSW

Copy word at DS:[SI] to ES:[DI]. Update SI and DI.

Algorithm:

� ES:[DI] = DS:[SI]

� if DF = 0 then

o SI = SI + 2

o DI = DI + 2

else

o SI = SI - 2

o DI = DI - 2

6. Classifications of 8086 interrupts?

• Predefined interrupts

• User defined Hardware interrupts

• User defined software interrupts.

7. Difference between 2-key lockout and N-key rollover modes in 8279.

The two operating modes of keyboard section are 2-key lockout and N-key rollover.

In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.

In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO.

8. ADC

Resolution=10V/210

=9.76 mV

9. 8KB memory

2N=8KB, N=13

10. Memory Mapped I/O i. Reading and writing an I/O device similar to memory read/write

ii. Uses same memory read and write signals

iii. Most processors use this I/O mapping

PART B

11. (a).(i) Explain the instruction set of 8085 with example.

Instruction set of 8085

Data Transfer Instructions

Arithmetic Instructions

Logical Instructions

Branch Instructions

Machine Control Instructions

(ii) Write a program to add a series of 10 numbers stored from location 3000H onwards. Add a series of 10 numbers

MVI D, 00

MVI C, 05

LXI H, 8030

MOV A, M

DCR C

AHEAD INX H

ADD M

JNC LOOP-1

INR D

LOOP-1 DCR C

JNZ AHEAD

STA 8056

MOV A, D

STA 8051

HLT

OR

(b)Draw the functional block diagram of 8085 and explain its architecture in detail. BLOCK DIAGRAM OF 8085

Block Diagram explanation of

Registers Available, General purpose registers, special purpose registers

Function Of Accumulator,Flags,Program Counter

Explanation about all blocks in the block diagram

Explanation of control signals

12.(a)(i) Indicate the signals which are different when 8086 is in minimum mode and maximum mode. Draw the timing diagram for Minimum mode in Read and Write Operation

Explanation of the signals involved.

Draw the timing diagram for Maximum mode in Read and Write Operation

Explanation of the signals involved

compare both the modes of operation

(ii) Explain the memory segmentation of 8086.

explain how effective address and physical address are calculated

Explain about the different segments and segment registers present,their functions and examples

OR

(b)Explain the architecture of 8086 with neat diagram.

BLOCK DIAGRAM OF 8086






13(a)(i) Write a program to find the largest number in the series of signed numbers using 8086.

Program

Result Verification

(ii)Explain the arithmetic and logical instructions used in 8086. explain about addition,subtraction ,division multiplication,increment and decrement instructions

Explain the different logical instruction to perform AND,OR,XOR,NOT operation

OR

(b)(i) Write a program to transfer a block of 20 data from one memory location to another location. Program

Result Verification

(ii) Explain the addressing modes of 8086 with neat diagram. Types of addressing modes with examples

14 (a)(i) Explain the architecture and working of 8253 timer. Block Diagram


(ii) Write a program to generate triangular waveform using DAC 0800

Block Diagram of interfacing DAC with 8085

Program to generate the waveform.

OR

(b) Explain with neat diagram, how 8259 can be used for interrupt generation and control.

Block Diagram


15 (a)Design an 8086 based system with the following specifications:

(i) 64Kb EPROM with starting address F0000H and

(ii) 64Kb RAM with starting address 30000H

Draw the schematic of the design indicating address map.

• The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4 numbers of 8Kb RAM.

• Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the processor are

connected to 13address pins of all the memory lCs.

The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate eight chip select signals.

These eight chip select signals can be used to select one of the eight memories at any one time.

OR

(b) Explain DMA interface in detail. Block Diagram

Types of DMA


ANNA UNIVERSITY OF TECHNOLOGY,COIMBATORE

B.E/B.Tech DEGREE EXAMINATIONS APRIL/MAY 2011

REGULATIONS:2008

V SEM ECE


PART A 1. List the operations performed by IO/M in 8085.

2. What is a tristate device?

3. Define wordlength.

4. Differentiate between STA and STAX.

5. What is the function of ALE signal in 8085 µP?

6. State the function of HOLD pin in 8085 µP.

7. What are the interrupt available in 8085 µP and mention its vector address.

8. Give the function of pins B̅H̅E̅ and QS0-QS1.

9. Define an assembler directive. Give examples.

10. What are the contents of flag registers in 8086?

11. What is the function performed by the instruction AAD in 8086?

12. How does the port C differ from port A and port B in 8255?

13. What are the functions of bus Interface unit in 8086?

14. Write down the function performed by the instructions

DAD H DAA

15. List the various modes of 8253 timer/counter.

16. State the difference between Opcode and Operand.

17. What is an interrupt?

18. Write an ALP to multiply a number by 4 using rotate instruction.

19. Differentiate DRAM and SRAM

20. What is the need for programmable interface device?

Solutions:

1. IO/M

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes

2.Tristate Device

The three states of the device is ‘0’,’1’ and ‘Z’,where ‘Z’ is high impedence state.

3.The word length of 8085 is 8 bit.

4. STA :The contents of the accumulator are copied into the memory location specified by the operand. This

is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-

order address.

Example: STA 4350H

STAX:The contents of the accumulator are copied into the memory location specified by the contents of the

operand (register pair). The contents of the accumulator are not altered.

Example: STAX B

5. ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get

latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold

times for the address information. ALE can also be used to strobe the status information. ALE is never

3stated.

6. HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and Data Buses.

The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the

completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is

acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

7. INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the

last clock cycle of the instruction.

RESTART INTERRUPTS; These three inputs have the same timing as I NTR except

they cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of

any interrupt

8. BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order (D15-D8) data

bus. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory

bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a

byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and

T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt

acknowledges cycle.

QS1 QS0 Indication

0

0

1

1

0

1

0

1

No Operation

First Byte of the opcode from the queue

Empty Queue

Subsequent Byte from the Queue

9. The pseudo operations which are instructions to the assembler are called assembler directives

10.

11. ASCII Adjust before Division.

Prepares two BCD values for division.

Algorithm:

� AL = (AH * 10) + AL

� AH = 0

Example:

MOV AX, 0105h ; AH = 01, AL = 05

AAD ; AH = 00, AL = 0Fh (15)

RET

12. PORT C is used as handshake signals while port A and port B is used for I/O .

13. The BIU performs all bus operations such as instruction fetching, reading and writing operands for

memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the

instruction queue.

14. DAA Decimal adjust accumulator

The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD)

digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and

the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the

operation.

If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction

adds 6 to the low-order four bits.

If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the

instruction adds 6 to the high-order four bits.

Example: DAA

DAD Add register pair to H and L registers

The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is

stored in the HL register. The contents of the source register pair are not altered. If the result is larger than

16 bits, the CY flag is set. No other flags are affected.

Example: DAD H

15. 1. Mode 0 (Interrupt on terminal count)

2. Mode 1 (Programmable monoshot)

3. Mode 2 (Rate generator)

4. Mode 3 (Square wave generator)

5. Mode 4 (Software triggered strobe)

6. Mode 5 (Hardware triggered strobe)

16. The data on which the operation is to be performed is called as an Operand.The assembly code which

indicates the operation is opcode.

17. Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.

18.MVI A,20

RLC

RLC

HLT

19. Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in

order to keep their data. This is in contrast to DRAM,

The problem with the use of flip-flops for storage cells is that each cell requires at least 6 transistors

to build, and the cell holds only 1 bit of data. In recent years, the cells have been made of 4 transistors,

which still is too many. The use of 4-transistor cells plus the use of CMOS technology has given birth to

a high-capacity SRAM, but the capacity of SRAM is far below DRAM.

20. An interface is a shared boundary between the devices which involves sharing information. Interfacing

is the process of making two different systems communicate with each other

PART B

21. With neat diagram explain the architecture of 8085 microprocessor.

Block Diagram explanation


Function Of Accumulator, Flags, Program Counter



22. (a) What are the Various machine cycles available in 8085 µP? (4)

Explain the various machine cycles like opcode fetch, memory read, memory write, I/O read and

I/O write.

(b) Draw and explain the timing diagram for LDA 2500 (8) Draw the timing diagram for LDA 2500

explain about the machine cycles of LDA 2500 wwhich are Opcode fetch,memory read,memory

read and memory read.

Explain about the the signals like CLK,AD0-AD7,AD8-AD15,ALE,RD and WR and their

functions .

23 Discuss the operation performed by the following 8085 instructions. Specify The addressing modes

used by the instructions and also mention its instruction length.(i)ADC B (ii)CMP M (iii)RAR

(iv)LDA 1234 (v)IN 80 (vi) MOV A,M

(i)ADC B Add register B to accumulator with carry

1 Byte length

(ii)CMP M

compare memory with accumulator

1 Byte length

(iii)RAR

Rotate A register right with carry

1 Byte length

(iv)LDA 1234

-The contents of a memory location, specified by a 16-bit address in the operand, are

copied to the accumulator. The contents of the source are not altered.

3 Bytes length

(v)IN 80 _ Input data to accumulator from a port with 8-bit address

2 Bytes length

(vi) MOV A,M- Copy from source(Memory) to destination(Accumulator)

1 Byte length

24. With a neat sketch explain the architecture of 8086 up






25. What are the various addressing modes in 8086 instruction set?

Explain the addressing modes with examples

Immediate addressing

Register addressing

Memory addressing

There are different forms of memory addressing modes

1. Direct Addressing

2. Register indirect addressing

3. Based addressing

4. Indexed addressing

5. Based indexed addressing

6. Based indexed with displacement

I/O port addressing

26. Explain the block diagram of 8255 PPI and explain its various modes of Operations

Block Diagram

Explanation about all the ports available.

Explanation about the modes of transfer with diagrams

Explain the control Word Register and signals involved in each mode

27. With the help of function block diagram, explain the operation of 8279 Programmable keyboard

display interface

Block Diagram

Types of Display Available

Types of keys available


Explain the various modes of operation and how to initialize the control words for each mode

28 a. What is meant by interrupt driven data transfer ? _Briefly Explain

draw the block diagram

explain about the signals involved

b. Explain the operation of optical motor shaft encoders .

Diagram

Types of optical motor shaft encoders

Incremental Shaft Encoders

Absolute Shaft Encoders

explain the operation and its application

ANNA UNIVERSITY OF TECHNOLOGY, COIMBATORE

B.E/B.Tech DEGREE EXAMINATIONS: MAY/JUNE 2010

REGULATIONS: 2007

V SEM ECE


PART A

1. Define bit and byte?

2. What are PUSH and POP instructions?

3. List out the interrupts in 8085 processor. Which interrupt has the highest priority?

4. Mention the operation carried out by the following instructions.

STA 2003 LXI H, 3002

5. Define machine cycle and T state.

6. What are BIU and EU in 8086?

7. How many address lines and data lines in 8086?

8. What are the segment register in 8086?

9. What is USART?

10. What is 8259A and mention the different priority modes?

11. Mention the Programmable Peripheral interface IC. What is the function of it?

12. What are the operational modes of programmable timer IC?

13. Give examples for single operand instruction and double operand instruction in 8086.

14. List out the operating modes of 8086 which pin decides this operating mode?

15. What are the functions of the pointers SP and BP in 8086?

16. Give some examples of string instructions of 8086.

17. What is addressing mode? How many addressing modes are there in 8086?

18. What is an assembler?

19. What are the drawbacks in SRAM?

20. What is meant by refreshing DRAM?

Solutions:

1. BIT-Bit is an abbreviation for the term binary digit

Byte-8 bit forms a byte

2. PUSH: The contents of the register pair designated in the operand are copied onto the stack in the

following sequence. The stack pointer register is decremented and the contents of the highorder register (B,

D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of

the low-order register (C, E, L, flags) are copied to that location.

Example: PUSH B or PUSH A

POP: The contents of the memory location pointed out by the stack pointer register are copied to the low-

order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents

of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer

register is again incremented by 1.

Example: POP H or POP A

3. TRAP, RST 5.5

RST 6.5 - (Inputs)

RST 7.5

INTR

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected

by any mask or Interrupt Enable. It has the highest priority of any interrupt.

4. STA 2003: The contents of the accumulator are copied into the memory location 2003. This is a 3-byte

instruction, the second byte specifies the low-order address and the third byte specifies the high-order

address.

LXI H,3002: The instruction loads 16-bit data in the register pair HL

5. Machine cycle is defined as the time required to complete one operation of accessing memory,I/O or

acknowledging an external request.

T-state is defined as one subdivision of the operation performed in one clock period

6. The BIU performs all bus operations such as instruction fetching, reading and writing operands for

memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the

instruction queue.

EU executes instructions from the instruction system byte queue.

7. 8086 address lines -20

Data bus 16

8.

9. The 8251A is a programmable serial communication interface chip designed for synchronous and

asynchronous serial data communication.

It supports the serial transmission of data.

10. 1. It is programmed to work with either 8085 or 8086 processor.

2. It manage 8-interrupts according to the instructions written into its control registers.

3. In 8086 processor, it supplies the type number of the interrupt and the type number is

programmable. In 8085 processor, the interrupt vector address is programmable. The priorities of the

interrupts are programmable.

11. 8255. The INTEL 8255 is a device used to parallel data transfer between processor and slow peripheral

devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.

12. Six programmable counter modes

A. Interrupt on terminal count

B. Hardware retriggerable one-shot

C. Rate generator

D. Square wave mode

E. Software-triggered strobe

F. Hardware-triggered strobe (retriggerable)

13. Single operand: INC AL

Double operand: CMP AL, BL

14. In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In a minimum

mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to

logic 1.

15. Stack Pointer (SP) is a 16-bit register pointing to program stack, ie it is used to hold the address of the

top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack segment (specified by

the SS segment register).Unlike the SP register, the BP can be used to specify the offset of other program

segments.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used by

subroutines to locate variables that were passed on the stack by a calling program. BP register is usually

used for based, based indexed or register indirect addressing.

16. String Instructions

MOVS - Move byte or word string

SCAS - Scan byte or word string

LODS,STOS- Load, store byte or word string

17. Definition: An instruction acts on any number of operands. The way an instruction accesses its operands

is called its Addressing modes

We can classify the addressing modes of 8086 into four groups:

• Immediate addressing

• Register addressing

• Memory addressing

• I/O port addressing

18. The assembler translates the assembly language program text which is given as input to the assembler

to their binary equivalents known as object code. The time required to translate the assembly code to

object code is called access time. The assembler checks for syntax errors & displays them before giving

the object code.

19. SRAM uses bistable latching circuitry made of Transistors/MOSFETS to store each bit. Compared to

Dynamic RAM (DRAM), SRAM does't have a capacitor to store the data, hence SRAM works without

refreshing. In SRAM the data is lost when the memory is not electrically powered.

20. Each cell must be refreshed every few milliseconds to avoid losing data. Whenever a row is read, the

sense amps automatically write back entire row, so we only need to access every row once during the

refresh interval.

PART B

21. With the neat block diagram, explain the architecture of 8085 Block Diagram explanation





22. (a) Discuss in detail about timing diagram.

(b) Draw the timing diagram for the execution of the instruction MOV A,B in 8085 processor and

explain. Explain the machine cycles needed for every Instructions and draw the timing diagram

23. Discuss in detail about different types of interrupts in 8086 with necessary examples

Examples.

External signal

Special instruction in the program

Condition produced by instruction

24. List out different types of addressing modes in 8086 and explain each mode with necessary

examples.

Explain the addressing modes with examples

Immediate addressing

Register addressing

Memory addressing

There are different forms of memory addressing modes

1. Direct Addressing

2. Register indirect addressing

3. Based addressing

4. Indexed addressing

5. Based indexed addressing

6. Based indexed with displacement

I/O port addressing

25. With a neat block diagram explain about DMA controller and its operation in master and slave

mode. Block Diagram


26. With neat logic schematic of Intel 8279, explain its interfacing with the microprocessor. Block Diagram

Types of Display Available

Types of keys available


Explain the various modes of operation and how to initialize the control words for each mode

27. Write an assembly language program to find the largest number in a data array. Program

Result Verification

28. Explain the concept of SRAM interfacing and DRAM interfacing. Draw the block diagram of the interfacing circuit

Explanation of the basic signals involved

Explanation of the addressing scheme, decoding logic and signals involved

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