Anjali Supekar *, Mohita Batra *, Rakesh Gulati *, Shahabuddin Qureshi °, Hina Mushir#, Prashant Pandey#, Samant Paul °, Seema Jaiswal °

* Automation Team ° IP Team # Silicon Test and Debug Team

ST MICROELECTRONICS

Due to reduced margins in the SOC design, number of critical path are increasing. Digital timing analysis methods are shaking hands with spice validation methodologies resulting in mixed signal analysis modes.

CURRENT METHODS:Highly time consumingUse complete spice (large size)

OUR INTEND: Simulating any path of any hierarchy of a designQuick & flexible analysis of true behavior of the path over wide range of operating conditionsUse output of the tool to optimize the design .

However…However…....

Mixed Mode

Multiple corner butTime Taking

Huge pattern set

STA

Limited corner

Unable to characterize small portion of hard IP

With change in technologies, there was a need to reduce the “extra margin” under consideration in order to get characterization for a small area leading to more optimistic approach. With the existing options (Sign Off /Mixed Mode) , analysis was possible only at full block level and hierarchical analysis was not supported. For such huge hierarchies we have developed a solution which lies between HDL and mixed mode analysis . The solution provides extraction at multiple corners and increased accuracy

Less Accurate

Large coverage(Not specific,

unsuitable for flat design)

MemoryMemoryMemoryMemory

Pulse GeneratorPulse Generator SensorSensor

Q1LSB

LoadLoad

ClockClock

Q2MSB

Source Clock

Pulse Clock

Pulse Propagation

Clock Clock SlopeSlope

Q Q SlopeSlope

• Expected Access Time on Silicon: TA

• Actual Access Time obtained from CAD: TAA

• CAD Correction Factor (CCF) Δ = TA - TAA

• TTA A == ΔΔ + T + TAAAA

CK & Q

PULSE FROMMEM

CCF

•Total Contribution (4-1)

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APPLICATION UNDER STUDY: CAD CORRECTION FACTOR

•Balancing Contribution (2-1) •Path Contribution ( 4-3)•PulseGen Contribution (3-2)

22 33 44

Memory

Q

CK

PULSEGEN(Sensor lib)

CUT1Test chip logic for pulse propagationAnd mixing to a central location

Sensor

Digital Output

CentralLocation(PulseTo digitalConversion)

Memory

Q

CK

PULSEGEN(Sensor lib)

CUTn

Error sources inTTAAAA measurement

TERROR-TC : Rise (Edge) Delay – Fall (Edge) Delay Pulse variation Error depends on input Slopes.

Error of the order of medium size inverter delay

This value (extracted from STA) is provided in testdoc on signoff conditions for each cut

-Balanced structure (Controlled placement and routing etc)

PROBLEM STATEMENT: The TTAAAA measured on chip measurement (Sensor) is going below CAD fast limits. CAD analysis on TTAAAA pulse propagation from memory to Sensor shows reduction in pulse width

Clock Slopes

XLS

SimulationEnvironmen

t

Spice Simulato

r

LoadSlopes

XLS

Detailed CCF Detailed CCF

CCF TOOL FLOW

The PVT Generator is an automation tool written in VB which facilitates the generation of PVT sheet from the standard input sources from the Front End and Sensor data

INPUTS

•Memory Test Specification

•Clock SlopeDelivered along with SPICE files

•PVT Mapping Information• Simulation and Spice Extraction Temperature• Process and RC Extraction

PVT GENERATOR FLOW

• CCF Flow involves parsing of PVT Topsheet which contains CUT details and PVT information for CCF

calculations. • For Spice simulation, it processes Spice to be

directly used, write simulation stubs for each cut, to calculate Clock slopes and CCF.

• Simulation Environment : Automation supports, Writing simulation files and invoking Simulation Environment for launching of clock slope simulations and CCF simulations.

• Flow supports Compilation of the Clock slopes and CCF for all the CUTs in tool internal format

Manual (Before Automation)Thorough knowledge about Spice files, its extraction, modification, Eldo simulation and other tools for calculating CCF

Set-up Time was approximately 1-2 days (includes spice extraction, correction, run files, stimuli and other data files)

Simulation was initially sequential. Even if it was parallel, there was no tracking mechanism. Simulation time was approximately 4-5 days

Result compilation was tedious as there were many excel sheets having huge data which was unmanageable. It took approximately 8-10 hours

No debug options

After AutomationUser need not be aware of any simulation tools. Tool is user friendly and no prior knowledge required.

Set-up Time reduced to half an hour

Parallel simulation along with tracking mechanism. At any point user can check simulation status of any CUT. Simulation time reduced to 4-5 hours

Result compilation made easy with proper monitoring of all sheets for each cut. Time reduced to 5-6 minutes

Easy Debug options90% of user

time is saved 90% of user

time is saved

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PURE MEMORY CAD

NEW MEMORY CAD

V1 V2 V3 V4 V5

V5 > V1 T5<T1

T1

T2

T3

T4

T5

CAD v/s Silicon Analysis of a TestchipCAD v/s Silicon Analysis of a Testchip

CAD v/s SI Aligned with Increased Accuracy of

new CCF

CAD v/s SI Aligned with Increased Accuracy of

new CCF

CAD CORRECTION FACTOR

SYSTEM ACCURACY

Testchip Process Sensor

Memory

Ring Oscillators

Process Sensor Block (for Sensor Data Analysis)

•Temperature sensitivity•voltage sensitivity•RC Impact •Impact of device sensitivity

Standard Cell RO Block CAD Data•Generation for any type of architecture (flops, mux, etc) •easy analysis (currents, timing , frequency)

CAD Correction Factor (CCF) + MCF (Memory)

A TAA error value calculation for test chips is an important step to calculate path contribution to extract the deviation of CAD from Silicon.

PotentialApplications Proposed solution addresses different components of SOC.

AUTOMATIC CAD CORRECTION FACTOR GENERATION THROUGH MCF

EXISTING FLOW NEW OPTIMIZED FLOW

13

Clock Slope and Q load @ multiple corners

Extract slope @ multiple corners

Extract Load slopes @ multiple corners

Extracts CCF @ multiple corners

Extract memory CAD

manual adjustment for CCF

Memory team do delivery of CAD Data to Test team

Clock Slope / load @ multiple corners

simulations for Unified CAD Data {CCF included}

CAD Data Delivery

Cycle time + Cycle time + No. of simulationsNo. of simulations

" Faster & Accurate" CAD data generation for Improving Accuracy for CAD vs Si analysis.

3X 3X GainGain

TESTCHIP TEAM

MEMORY TEAM

TESTCHIP TEAM

MEMORY TEAM

Tool fully automates the Sensor Design Analysis and CAD Data Generation for Silicon validation.

Sensor Data

Analysis

Temperature Sensitivity

RC Impact

Process Sensor Block

Voltage Sensitivity

Enable this tool for SoC designers at physical implementation stage.

Option for generating GDS and CDL of a specific portion of targeted block of SOC taking DEF as input and then extracting Spice from GDS and CDL.

Analyzing Critical paths using Actual Spice Simulations