Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

69
PART 3 Field-Effect Transistors U p to now, we have discussed semiconductor materials and two-terminal devices. By far the most important semiconductor devices, however, are transistors, which are three-terminal devices. Transistors have two very useful modes of operation: they can be amplifiers and they can be switches. When a transistor is used as an amplifier, as in analog circuits, the current or voltage at one terminal controls the current or voltage between the other two ter- minals. A small change in the control signal (the electrical equivalent of turning a knob) can produce large changes in the output signal; thus, the small signal is amplified. In the digital mode, the signal at the control terminal of the transistor con- trols the state of the switch. A change in the input is the electrical equivalent of throwing a lever—the input controls whether or not current can pass through the transistor. Any transistor can operate as either an amplifier or a switch; it depends only on the surrounding circuitry. We leave the discussion of circuit design to another course, but in this book, we focus on the physics of operation of the transistors themselves. There are two major classes of transistors, based on the physics of their operation. These are the field-effect-transistors (FETs), which are discussed in this part of the book, and the bipolar junction transistors (BJTs), which are covered in Part 4. The origin of the names will become clear as we develop an understanding of how these devices work. Interestingly, the field-effect transistor was invented first, but the bipolar junction transistor was the first be developed into a practical device. For many years, bipolar transistors predominated. More recently, however, FETs have surpassed BJTs in ease of fabrication and low cost, and currently most electronic circuits use FETs as the fundamental circuit elements. There are many types of field-effect transistors, but they all have in common the element that an electric field across a gate structure controls the flow of cur- rent between the other two terminals, the source and the drain. The differences 373 and69779_ch07.qxd 2/10/04 10:50 AM Page 373

Transcript of Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

Page 1: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

P A R T 3Field-Effect Transistors

Up to now, we have discussed semiconductor materials and two-terminaldevices. By far the most important semiconductor devices, however, aretransistors, which are three-terminal devices. Transistors have two very

useful modes of operation: they can be amplifiers and they can be switches.When a transistor is used as an amplifier, as in analog circuits, the current or

voltage at one terminal controls the current or voltage between the other two ter-minals. A small change in the control signal (the electrical equivalent of turninga knob) can produce large changes in the output signal; thus, the small signal isamplified.

In the digital mode, the signal at the control terminal of the transistor con-trols the state of the switch. A change in the input is the electrical equivalent ofthrowing a lever—the input controls whether or not current can pass through thetransistor.

Any transistor can operate as either an amplifier or a switch; it depends onlyon the surrounding circuitry. We leave the discussion of circuit design to anothercourse, but in this book, we focus on the physics of operation of the transistorsthemselves.

There are two major classes of transistors, based on the physics of theiroperation. These are the field-effect-transistors (FETs), which are discussed inthis part of the book, and the bipolar junction transistors (BJTs), which arecovered in Part 4. The origin of the names will become clear as we develop anunderstanding of how these devices work.

Interestingly, the field-effect transistor was invented first, but the bipolarjunction transistor was the first be developed into a practical device. For manyyears, bipolar transistors predominated. More recently, however, FETs havesurpassed BJTs in ease of fabrication and low cost, and currently most electroniccircuits use FETs as the fundamental circuit elements.

There are many types of field-effect transistors, but they all have in commonthe element that an electric field across a gate structure controls the flow of cur-rent between the other two terminals, the source and the drain. The differences

373

and69779_ch07.qxd 2/10/04 10:50 AM Page 373

Page 2: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

374 PART 3 Field-Effect Transistors

between the various types of FETs are primarily in the structure of the gate andmechanism used to apply the field.

The Generic FET

Before we begin to analyze specific types of field effect transistors, we examinea generic device to understand the basic principles of operation. A simplified per-spective view of a field effect transistor is shown in Figure III.1. There are threeterminals, called the source (S), drain (D), and gate (G). There is an electricallyconducting channel extending from the source to the drain. The gate is above butelectrically isolated from the channel. As we will see, the voltage on the gateterminal with respect to the source, VDS , is used to control the passage of carri-ers through the channel by varying the field in the insulating region. The mecha-nism of this control depends on the particular type of FET, so for now we justshow the gate electrode symbolically.

In Figure III.1a the source, channel, and drain are n type and are fabricatedin a p-type semiconductor (substrate). This device is referred to as an n-channelfield-effect transistor, or NFET. In the p-channel device (PFET) in Figure III.1bthe source, channel and drain are p type, and the substrate is n type.

Note that in both cases a pn junction exists between the FET and the sub-strate. In practice, this junction must never be forward biased (often the substrateis connected to the source). This is because the current should flow between thedrain and the source, not into the substrate. In addition, if multiple FETs are put

Figure III.1 A generic field-effect transistor contains a source S, a drain D, and a channel controlled by a gate electrode G. Since this is a generic device, the gate is shown only symbolically. Specific gatestructures will be discussed later. (a) An n-channel device; (b) p-channel FET. Direction of conventionalcurrent flow is in the direction of the dashed arrows. Here W is the channel width and L is the channellength.

W

SG

n

p

Gate

Channel

Drain

Source

Substrate

L

p-channel device

(b)

n-channel device

(a)

SG

D

Insulatingregion

Electricalcontacts

Flow of ID

D

p

n

Channel

Drain

Source

Substrate

L

Gate

W

and69779_ch07.qxd 2/10/04 10:50 AM Page 374

Page 3: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

PART 3 Field-Effect Transistors 375

onto the same substrate, as long as the junctions are not forward biased, then ineffect the FETs are all electrically isolated from each other.

We will see later that virtually no dc current flows into or out of the gate. Theapplication of a voltage on the gate produces an electric field that affects the con-ductance of the channel, but the gate itself does not conduct.

Since the carriers (electrons or holes) cannot flow into the substrate andcannot flow through the gate, they are confined to the channel, and underappropriate bias conditions, these carriers can flow between the source andthe drain, producing a current in the channel. We refer to this current as ID , thecurrent at the drain, but it is also the channel current and the source current.1

The dashed arrows in Figure III.1 indicate the path of the current flow. In ann-channel FET the channel carriers are electrons and the drain voltage withrespect to the source, VDS , is positive. Electrons flow from source to drain, sothe direction of current is from drain to source, as shown in the figure.

In a p-channel FET, the carriers are holes and the drain-to-source voltage isnegative. Therefore, the holes flow from the source to the drain. The current ID

by convention is defined as positive going from drain to source and is thereforenegative.

An example of a FET used in a simple circuit is shown in Figure III.2. TheFET, M1, is an n-channel metal-oxide-semiconductor field-effect transistor(MOSFET) discussed in more detail in Chapter 7. The drain supply voltage VDD

1Of course, some leakage current does flow between channel and gate and between channel andsubstrate, but this leakage current is normally small compared with the channel current between drain and source.

Figure III.2 Simple (inverter) circuit for anNFET. The input voltage VG controls thechannel current ID and the output voltage VD.

G D

S

VDD

ID RL

Vin � VG

VD � Vout

M1

and69779_ch07.qxd 2/10/04 10:50 AM Page 375

Page 4: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

376 PART 3 Field-Effect Transistors

Figure III.3 The ID-VDS characteristics for a typical NFET (a) and PFET (b) for five values of VGS. Thedashed line separates the sublinear and saturation regions at VDS = VDSsat. In the NFET, the drainvoltage and drain current are positive, and the gate voltage must be higher than the threshold voltage VT

for appreciable current to flow. In the PFET, the drain voltage and drain current are negative, and thegate voltage must be lower than the threshold for current to flow.

IDsat4

IDsat3

IDsat2

IDsat1

Sublinearregion

Saturationregion

(a)

VDS � VDSsat

VGS � VT(subthreshold region)

ID

VGS1

VGS2

VGS3

VGS4

VDS

is in series with the load resistor RL and the channel connects the drain D andsource S. Recall that the conductivity of a semiconductor is controlled by theconcentration of carriers. Since in this illustration, the source is at ground (zero)potential, the source voltage VS = 0, the gate to source voltage VGS = VG , andthe drain-to-source voltage VDS = VD . The electron concentration in the channelis controlled by the gate (input) voltage Vin = VG . The output voltage of thecircuit is Vout = VD . From Kirchhoff’s voltage law,

Vout = VDS = VD = VDD − ID RL

For VG such that ID = 0, Vout = VDD . For VG such that ID is very large, Vout ≈ 0.(We will see later that when the drain current ID is very large, the voltage be-tween the drain and the source is small.) For intermediate values of VG,

0 < Vout < VDD .Figure III.3a shows the typical electrical characteristics of an NFET. Here

the current through the channel, ID , is plotted as a function of the voltage acrossthe channel VDS , for various values of the controlling gate voltage VGS . There arethree regions of operation: the sublinear region, the saturation region, and thesubthreshold region. The subthreshold region is the horizontal line markedVGS ≤ VT . We define the threshold voltage VT as the value of VGS required toinitiate a given current flow through the channel, often taken (in the currentsaturation region) as IDsat = 40W/L nA. For all gate voltages below this

IDsat1

IDsat2

IDsat3

IDsat4

(b)

VDS � VDSsat ID

VGS4

VGS3

VGS2

VGS1

VDS

Sublinearregion

Saturationregion

VGS � VT(subthreshold region)

and69779_ch07.qxd 2/10/04 10:50 AM Page 376

Page 5: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

PART 3 Field-Effect Transistors 377

threshold, ID is small and often considered to be zero, regardless of the value ofthe drain-source voltage VDS . That means all the ID-VDS curves for VGS < VT lieclose to the horizontal axis.

When the gate voltage VGS is above threshold, current can flow. In an NFET,for VGS > VT and VDS positive, electrons flow from source to drain, or currentflow is from drain to source.

Next, look at one of the curves on the plot. Notice that for a given VGS abovethreshold (VGS > VT ), as VDS increases, the ID-VDS relation is sublinear andeventually ID saturates. The value of saturated ID is called IDsat, while the valueof VDS at which the current saturates is VDSsat. These are both functions of thegate voltage VGS and the properties of the FET.

The region for VDS > VDSsat is referred to as the current-saturation region, orsimply the saturation region. The region for VDS < VDSsat is variously called thelinear region (although it is sublinear), the triode region, or simply the sublinearregion. The dashed line in Figure III.3a indicates the division between these tworegions. For higher gate voltages, the value of IDsat and VDSsat are both larger.

Typical characteristics for a PFET are shown in Figure III.3b. Here holesflow (and thus current flows) from the source to the drain for negative values ofVDS . For the PFET, the gate voltage is less than (more negative than) the thresh-old voltage for a finite ID .

In Part 3 of this book, we examine the I-V characteristics in some detail. Asan introduction here, however, let us consider a geographical analogy to helpunderstand why the curves are shaped as they are. Suppose we have two deeplakes, connected to each other by a shallow canal as illustrated schematically inFigure III.4a. The bottom of the lake system is somewhat analogous to potentialenergy for electrons as a function of position while the depth of the water repre-sents the electron concentration. The lake on the left (S, representing source) isconsidered to be at constant depth. Four cases for the lake on the right (D, drain)

Figure III.4 Lake analogy to FET operation. (a) Two lakes are connected by a canal. The water levelof lake S is constant. Four values of water level (and depth) of lake D are shown. (b) The correspondingrates of water flow.

1234

1234

Canal

(a)

Lake S Lake D

Rat

e of

wat

er f

low

Surface of S minus surface of D

1

2

3 4

(b)

and69779_ch07.qxd 2/10/04 10:50 AM Page 377

Page 6: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

378 PART 3 Field-Effect Transistors

are shown. In case 1, the surface of D is the same height as the surface of S andno water flows between the lakes. This is indicated by position 1 in Figure III.4b,which shows a plot of water flow versus the difference in surface levels of thetwo lakes. When the surfaces are equal, the flow is zero. In case 2, the surface ofD is slightly below that of S and so some water flows from S to D. Case 3 repre-sents the situation in which the surface of D is at the same height as the bottomof the canal. The slope of the water surface in the canal is increased and so is therate of flow. For the surface of D below the bottom of the canal (case 4), the slopeof the surface in the canal is not affected. Since the rate of water flow is deter-mined by the slope of the water surface in the canal, the rate of flow saturated atits value at 3. As the level of surface D continues to drop, the rate of water flowthrough the canal stays the same.

Transistors in Circuits

Most of Part 3 of this book will be devoted to understanding and deriving theshapes of the ID-VDS characteristics of FETs. First, though, we will brieflyinvestigate how these transistors can be used as amplifiers and as switches.

We said earlier that in a digital circuit, changing the gate voltage would belike throwing a switch. Figure III.5a shows an NFET inverter circuit with aresistive load. This is the circuit of Figure III.2 repeated. Suppose that a positivevoltage supply VDD is applied to the drain through a load resistor RL . If the inputgate voltage VGS is below threshold (logic low), little current can flow through thechannel—the switch is open circuited. Since ID ≈ 0, the voltage drop across theresistor ID RL is also zero and the output voltage is VDS ≈ VDD (logic high) asindicated at the “switch open” position in Figure III.5b. If the gate voltage ischanged to a value above threshold (for the NFET), then current flows across thechannel—the switch is closed. The amount of current that can flow is nowdetermined by the external circuit as well as by the transistor. The circuit deter-mines the load line (dashed in the figure). The resistance in the external circuitcauses some voltage drop in VDS as ID increases. The output voltage is thenVDS = VDD − ID RL .

For the analog case, the gate voltage is kept above threshold, but is variedby a small amount within some range, Figure III.5c. As the gate voltagevaries, the current ID and the voltage VDS also vary proportionally. Usuallythe variation in the gate voltage is quite small (the difference in gate voltagefrom one curve to the next in the figure may be a fraction of a volt), while thevariation in VDS is considerably larger—perhaps about a volt. Hence, the tran-sistor acts as an amplifier, magnifying the small change in VGS to a large changein VDS .

To optimize the transistor design, then, the engineer will want to have athorough understanding of the ID-VDS characteristics and how to shape them.Here in this introduction, we will outline the basic approach for analyzing thedrain current as a function of the gate and drain voltages. Then, in Chapter 7 weexecute and refine that approach.

and69779_ch07.qxd 2/10/04 10:50 AM Page 378

Page 7: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

PART 3 Field-Effect Transistors 379

The Basis for Deriving the ID-VDSCharacteristics of a FET

To begin our understanding of the drain current, we recall from elementaryphysics that current is defined as the amount of charge passing through a givenarea per unit time. We consider the case of an n-channel FET, Figure III.6. In anNFET, electrons carry the current by moving in the positive y direction. We takethe x coordinate to be downward, across the channel.

Figure III.5 The ID-VDS characteristics determine the transistor operation in a circuit. Forexample, (a) shows a digital circuit, an inverter. In digital operation, (b) the gate voltage isswitched between two values, one above threshold and one below. Current is either near zero,or some value determined by both the transistor (solid lines) and the circuit (dashed line). In ananalog circuit (c), the gate voltage remains above threshold, but varies. As VGS changes, thecurrent through the transistor also changes, as well as the voltage VDS.

G D

S

VDD

RL

VGS

VDS

(a)

Switch closed

(b)

ID

Resistive load line(determined by external circuit)

Some VGS � VT

Switch open

VDS � VDD

VGS � VT

VDS

ID

Load line (determinedby external circuit)

VGS varies

VDS � VDD

VDS

(c)

and69779_ch07.qxd 2/10/04 10:50 AM Page 379

Page 8: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

380 PART 3 Field-Effect Transistors

Figure III.6 The geometry of the NFET used for deriving the current. (a) The big picture; (b) the channelcharge is the charge per unit area under the strip.

Substrate

p

n

S

D

L y

xW

Gate

n-channel device

(a)

Electronflowdy

0

x

xC(y)

dy

(b)

W

Qch is the total charge undera unit area of the strip

Total area ofstrip is W dy

Area chargescross

Total charge understrip is Qch W dy

Let us consider the current flowing across the shaded region. Suppose thereare n charges per unit volume in the channel where n = n(x, y). The charge perunit area in the channel at position y is

Qch(y) = −q

xC (y)∫0

n(x, y) dx (III.1)

and the integral is taken across the channel depth, xC as indicated in Fig-ure III.6a. In an incremental length dy at position y in the channel, the total chan-nel charge is

(Channel charge in dy) = Qch(y)W dy (III.2)

Since the current is equal to the charge passing a given area per unit time, thechannel current ID at a given y is

ID = −WQch(y)v(y) (III.3)

where v(y) is the average channel electron velocity at position y. Note that inEquation (III.3), the velocity v is positive, the charge Qch is negative, and the

and69779_ch07.qxd 2/10/04 10:50 AM Page 380

Page 9: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

PART 3 Field-Effect Transistors 381

Figure III.7 (a) The longitudinal field �L for an NFET. (b) The incrementalchannel voltage dVch.

Substrate

(a)

p

S G D

VGS �VDS

n� n�

y

�L

negative sign ensures that ID (from drain to source) is a positive quantity. Notealso that ID is independent of y, so Qch(y) and v(y) are inversely proportional.

Equation (III.3) is the fundamental equation for current flow in all FETsand is the starting point for deriving the electrical characteristics for any givenstructure. What is needed, then, are analytical expressions for Qch(y) and v(y)

as functions of applied voltages for a particular FET structure. Once these para-meters are modeled, the mathematical analysis is similar for all classes ofFETs.

Note that the charge per unit area in the channel, Qch, Figure III.6b, is anal-ogous to the quantity of water per unit area in the canal of Figure III.4a; i.e., theamount of water per unit volume times the depth of the water. The term v is theaverage velocity of the water flow at position y. From the water analogy, it isclear that the depth of the water varies along the canal, and similarly the amountof charge available for conduction varies with position in a FET.

In general, current in the channel flows by a combination of drift and diffu-sion. In practice, however, we are primarily concerned with the operation ofFETs in which drift current predominates. That occurs when the density ofcharge in the channel is so great that the drift current is large compared with thediffusion current.

The drift current is driven by the electric field along the channel. We callthis the longitudinal field �L shown in Figure III.7a. In an n-channel device, thedrain is more positive than the source. The longitudinal electric field then, is inthe negative y direction. The electrons are accelerated toward the positive ter-minal, so their velocity is in the opposite direction to the field. Thus for elec-trons we have

v(y) = −µ(y)�L(y) (III.4)

where µ(y) is the average channel mobility (a positive quantity) at position y.Substituting into Equation (III.3), we find the channel current is

ID = WQch(y)µ(y)�L(y) (III.5)

(b)

S G D

VGS �VDS

n� n�

y

�L

�dVch�

dy

and69779_ch07.qxd 2/10/04 10:50 AM Page 381

Page 10: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

382 PART 3 Field-Effect Transistors

Electric field is, by definition, � = −dV/dy . The incremental voltageacross the channel increment dy is dVch, as shown in Figure III.7b. Then

�L = −dVch

dy(III.6)

Equation (III.5) can then be expressed in the form

(III.7)

We will use this equation as the starting point for deriving the electrical charac-teristics of all FETs.

The organization of Part 3 is as follows. Chapter 7 is limited to the dc char-acteristics of MOSFETs. As we study the static characteristics, we will also cometo understand the principles of operation of field-effect transistors. Chapter 8presents additional material on MOSFET devices, including transient effects andsmall-signal equivalent circuits. Further, modern devices have very shortchannels—appreciably less than 1 µm. This makes the devices operate faster, butit affects the physics, too. The models that we develop in Chapter 7 will have tobe modified to describe these “short-channel effects.” Therefore, a part ofChapter 8 is devoted to examining short-channel effects and their effects on theID-VDS characteristics of modern field-effect devices. Three other classes ofFETs are also discussed briefly in Chapter 8: the heterojunction field-effect tran-sistor (HFET), the metal-semiconductor field-effect transistor (MESFET), andthe junction field-effect transistor (JFET). This material is largely qualitative.

In Chapter 7, the operation of MOSFETS is discussed for an n-channelMOSFET as a model. The results are readily adapted for p-channel MOSFETs.However, most circuits use a combination of NMOS and PMOS devices fabri-cated in a single substrate. A circuit containing both NMOS and PMOS devices isreferred to as a CMOS (complementary MOS) circuit. Figure III.8 illustrates aCMOS inverter, a common structure used in digital circuits. It consists of a p-typesubstrate in which an NMOS is fabricated, while the PMOS resides in an n-typeregion within the p substrate.2 Note that the gates of the two FETs are connectedelectrically, as are the two drains. The circuit diagram of this inverter is shown inFigure III.9a, while input and output voltages are indicated in Figure III.9b. Theinput voltage applied to the gates varies between zero volts and VDD (the supplyvoltage) while the inverted output varies between VDD and zero. Note that in thiscircuit the source of the NMOS is at ground (zero) potential and the sourcevoltage of the PMOS is VDD. The operation of this switch is discussed further inChapter 8.

ID = −WQch(y)µ(y)dVch(y)

dyor ID dy = −WQch(y)µ(y) dVch(y)

2This arrangement is called n-well technology.

and69779_ch07.qxd 2/10/04 10:50 AM Page 382

Page 11: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

PART 3 Field-Effect Transistors 383

Figure III.8 The CMOS inverter. (a) Physical structure, adapted fromC. G. Fonstad, Microelectronic Devices and Circuits, McGraw-Hill,1994;(b) cross-sectional diagram, adapted from R. C. Jaeger, MicroelectronicCircuit Design, McGraw-Hill, 1997.

p�

p�n well

Isolationoxide

P�

Heavily dopedpolysilicon

Gate electrodes

n�n�

n�

p

Oxide

p p p

p� n� n� p� p� n�

n well

VDD

SourceBodycontact

Drain Drain Source Bodycontact

Vin

Vout

NMOS FET PMOS FET

(b)

Gateelectrode

Gateelectrode

Figure III.9 (a) CMOS logic inverter circuit diagram; (b) input and output waveforms.

Vin

VSS � 0

Vout

S

DPMOS

D

SNMOS

(a)

�VDD

VDD

VDD

0

0

Vin

Vout

(b)

t

t

(a)

and69779_ch07.qxd 2/10/04 10:50 AM Page 383

Page 12: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

384 PART 3 Field-Effect Transistors

Supplemental information on FETs is presented in the Supplement to Part 3.The gate-substrate capacitance is discussed to indicate how it can be used asa fabrication diagnostic tool. Some degradation mechanisms of MOSFETsare briefly discussed. Variations of the MOSFET structures—dynamic random-access memories (DRAMS) and charge-coupled devices (CCDs)—arequalitatively described. Applications of SPICE to MOSFETs are also brieflydiscussed. ■

and69779_ch07.qxd 2/10/04 10:50 AM Page 384

Page 13: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

C H A P T E R 7

385

The MOSFET

7.1 INTRODUCTIONIn this chapter, we discuss the basic operation of the most important class ofFETs: The Si-based insulated-gate field-effect transistor (IGFET). The gatematerial in these devices was originally a metal (aluminum) and the insulatorwas silicon dioxide (SiO2). That is the origin of the term metal-oxide-semiconductor field-effect transistor, or MOSFET. For ease of fabrication andreproducibility, however, the current practice is to use degenerately doped poly-crystalline Si (poly Si), which is highly conductive, instead of metal for thegate. In n-channel devices, n+ poly-Si is used for the gates, and p+ poly-Si isused for p-channel devices. Silicon dioxide is still usually used for the insulator,although nitrogen is sometimes incorporated into the SiO2 to increase its dielec-tric constant (and thus device performance). While the term IGFET is a moreaccurate description, in this book we adopt the practice common in the industry,which is to use the more common term MOSFET to describe this class ofdevices.

In this chapter, we discuss the MOSFET fundamentals involved in the staticelectrical characteristics. In Chapter 8, we will cover the short-channel effectsimportant in modern MOSFET devices, the time-dependent characteristics, andin addition, we discuss the other types of field-effect transistors, including theCMOS, HFET, JFET, and MESFET.

7.2 MOSFETs (QUALITATIVE)In this section, we explore, qualitatively, the basic principles of operation of theMOSFET. To illustrate how the MOSFET channel is formed, a brief qualitativedescription of MOS capacitors is presented. A more detailed description of MOScapacitors appears in the supplement to FETs.

and69779_ch07.qxd 2/10/04 10:50 AM Page 385

Page 14: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

386 PART 3 Field-Effect Transistors

7.2.1 INTRODUCTION TO MOS CAPACITORS

In this section we consider an ideal MOS capacitor (MOSC) with the structure ofFigure 7.1a. This capacitor consists of a degenerate n+ Si gate, a thin layer of(insulating) SiO2 separating a gate from a p-type substrate.

Figure 7.1b shows the cross section of the MOSC. The energy band diagramalong the cut A-A′ slicing through the gate in the x direction is shown in (c) and(d). We determine the energy band diagrams by following the procedure used inChapter 6 for heterojunctions. In this case, however, we have two heterojunctions,

Figure 7.1 The MOS capacitor. (a) Physical structure of an n+-Si/SiO2/p-Si MOS capacitor;(b) cross section; (c) the energy band diagram under charge neutrality; (d) the energy banddiagram at equilibrium (note that the surface of the p-type substrate near the oxide interfacehas become weakly inverted).

n� poly Sicontact VG

SiO2

p-type Si

(a)

p-type substrate

(b)

n� poly SiSiO2

Draw energy banddiagram along this line

A�

tox

A

χox

�S

�G � �S

�G � χG

ECEiEf

EVEVG

ECG � EfG

tox

Oxide

(c)

A A�

Bulkn� Si gate

x

E

qφf

ECG � EfG

EVG

Evac

Evac

EC

EiEfEV

qVbi � �G � �S

x

E

qφS

qφox

(d )

qφf

and69779_ch07.qxd 2/10/04 10:50 AM Page 386

Page 15: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 387

one between the polysilicon gate and the insulator, and another between theinsulator and the semiconductor substrate.

We assume electrical neutrality in every macroscopic region to start, inwhich case Evac is constant. The result is shown in Figure 7.1c. Here �G and �S

are the work functions1 (in eV) of the gate and the semiconductor respectively.2

Note that �G is approximated as being equal to χG because the gate material isdegenerately doped and its Fermi level in the gate is thus near the conductionband edge. The quantity φ f is the potential difference (in volts) between theFermi level and the intrinsic level. The uppercase �’s and the χ ’s are energies,expressed in eV, and the lowercase φ’s are potentials, expressed in volts. On theenergy band diagrams, the φ’s will always be expressed as qφ, in energy units.

To achieve equilibrium, electrons flow (through an external circuit) from thegate to the semiconductor substrate, causing the Fermi levels to line up. Theresulting (equilibrium) energy band diagram is shown in Figure 7.1d.3 We seethat the bands bend, and a built-in voltage results. Some of the voltage is droppedacross the oxide and some across the semiconductor. Furthermore, the semicon-ductor now has a depletion region near its surface—it is depleted of majoritycarriers, which are holes in this case, since the material is p type.

The total built-in voltage is

Vbi = −1

q|�G − �S| = φox + φs (7.1)

The voltage drop across the oxide is φox. The voltage across the Si depletion re-gion, often referred to as the surface potential (i.e., the voltage at the Si surfacerelative to that in the neutral bulk), is designated as φs . Notice that the electricfield (� = (1/q)(d Evac/dx)) is discontinuous at both interfaces of the insulator.This is caused by the difference in the permittivities of the materials (Gauss’slaw, �1ε1 = �2ε2). The fraction of the built-in voltage appearing across the oxideincreases with increasing oxide thickness and with increasing doping level inthe Si.

Notice that for this example, at equilibrium (Figure 7.1d), the Fermi level ac-tually crosses the intrinsic level. This means that, while the substrate is dopedp type, near its surface it is effectively n type. The Fermi level near the surface iscloser to the conduction band edge than to the valence band edge. At the inter-face, there is a higher concentration of electrons than holes because of the band

1Since the original gate material in a MOSFET was a metal, the term �M is also often used for the workfunction of the gate.2Note that the gate material is degenerately doped to a degree such that band-gap narrowing (Chapter 4)occurs. This causes the conduction band edge of the gate material, ECG, to be at a slightly lower energythan that of the substrate, ECsub. The gate material band gap is slightly smaller than the substrate bandgap. This band-gap shrinkage is, however, normally less than 0.1 eV and we ignore it. For simplicity,we also ignore any charge trapped in the oxide or at the SiO2/Si interface. These considerations arediscussed in Supplement 3.3Here the band lineup at the interface is obtained by the electron affinity model.

and69779_ch07.qxd 2/10/04 10:50 AM Page 387

Page 16: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

388 PART 3 Field-Effect Transistors

bending. The Si surface region is not only depleted, it is inverted. We note herethat the region consisting of the conductive gate, the insulating oxide, the deple-tion region and the substrate can be considered to be a capacitor with twodifferent dielectric layers between the electrodes (those of the oxide and of thedepletion region), with two different dielectric constants. Note that the built-involtage is divided between oxide and substrate. If a voltage is applied betweengate and substrate, it too will be divided between oxide and substrate and theresultant energy band diagram and charges will be altered.

Figure 7.2 shows the energy band diagrams and charge distributions for var-ious values of gate-substrate voltage VG for a n+ Si/SiO2/p-type semiconductor.In (a), the case for equilibrium is indicated. Because electrons from the gatetransfer to the substrate, with the resultant creation of a depletion region in the Siat the Si/SiO2 interface, the gate charge is positive and the Si depletion regioncharge is negative as indicated.

If a negative voltage is applied to the gate, this voltage is divided betweenoxide and semiconductor. The bands in the semiconductor bend up, causing anaccumulation of holes in the semiconductor at the oxide interface (b).

If a step voltage (e.g., 2 V) is applied to the gate, a depletion region will beestablished in the Si within about 3 dielectric relaxation times (∼10−12 s) result-ing in the energy band and charge distribution indicated in (c). However, withtime, electrons will be thermally excited into the conduction band where theywill be trapped in the potential energy well at the interface. This negative trappedcharge (Qi) raises the energy band in this region until the steady-state conditionis reached as indicated in (d), a process that requires on the order of 10 to 100 msin Si. In steady state, electron generation and recombination rates are equal. Notethat in the steady state, the depletion region width is independent of the dc volt-age, or QB is constant. The charge dependent on voltage resides in the interfacecharge Qi .

The capacitance-voltage characteristic of a MOS capacitor (MOSC) is animportant diagnostic tool for monitoring the fabrication of MOSFETs. Here wepresent a brief description of the MOSC C-V characteristics. A more detaileddescription is presented in Supplement 3.

A simple circuit for measuring the C-V characteristics of a MOSC is shownin Figure 7.3a. A dc voltage Vdc and a small-signal ac voltage vac are appliedbetween gate and substrate, and the ac current iac is measured. The ratio iac/vac =2π f C , and C can be calculated.

A typical C-V plot is indicated in (b). Recall that the (differential) capaci-tance is

C = d Q

dV= εA

W

where d Q is the variation of charge on either side of the oxide with a change dVand W is the spacing between the regions of changing charge. For a reverse dcbias (Figure 7.3b) a small change in dV causes a small change in dQ on either

and69779_ch07.qxd 2/10/04 10:50 AM Page 388

Page 17: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 389

Figure 7.2 Energy band diagrams for the n+-Si/SiO2/p-Si capacitorof Figure 7.1 along with the charge distributions for three biasconditions. In (a) the case for equilibrium is indicated. Electrons fromthe n+ gate transfer to the p-Si substrate, resulting in a positive gateand a negative depletion region in the substrate. The accumulationcondition is indicated in (b). Here a negative voltage is applied to thegate with respect to the substrate such that holes accumulate at thesilicon–to–silicon dioxide interface. The situation for a positive 2-Vstep voltage is shown in (c) immediately after the application of thevoltage. With time, electrons generated in the transition region aretrapped in the potential well at the interface until steady state isreach as indicated in (d).

���� Ef

QBQG

(a) Equilibrium (b) Accumulation

Ef

Qi

QG

��

���������� Ef

Ef

QBQG

(c) Immediately after positivevoltage applied on gate

QBQG

Qi

��

���

��

(d) Steady state with positivevoltage applied to gate

and69779_ch07.qxd 2/10/04 10:50 AM Page 389

Page 18: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

390 PART 3 Field-Effect Transistors

side of the oxide and C = Cox = εA/tox. Thus for this condition, with the area ofthe gate known, the oxide thickness can be determined.

At intermediate voltages, a voltage-dependent depletion region exists in thesemiconductor and the MOSC capacitance consists of two capacitors in series.

C = CoxCs

Cox + Cs

where Cs is the semiconductor depletion region capacitance and C < Cox.At sufficient positive voltage, an inversion layer exists in the semiconductor

and for steady-state dc, the depletion layer width is independent of Vdc.An ac voltage creates charge at the edge of the depletion region. If the fre-

quency is low enough (on the order of 1 to 10 Hz), those created electrons havetime to enter the inversion region and the ac influence on the depletion regionwidth is negligible.4 Thus on the semiconductor side d Q is at the interfaced Q = d Qi and again C = εA/tox.

At a high-frequency ac voltage (∼100 MHz), the generated electrons haveinsufficient time to enter the inversion region before the polarity changes, dQis at the edge of the depletion region, the capacitance is constant, and C =CoxCs/(Cox + Cs). Here Cs = εA/w, where w is the depletion region width andis a measure of the doping level in the substrate.

The MOS capacitance is treated in more detail in Supplement 3.

7.2.2 MOSFETs AT EQUILIBRIUM (QUALITATIVE)

A schematic of an n-channel MOSFET is shown in Figure 7.4. It resembles theMOS capacitor just discussed except that there are source and drain regions ofn+ Si at opposite sides of the gate region. Since electrical connections are made

Figure 7.3 (a) Circuit for measuring the capacitance of a MOS capacitor. (b) Capacitance-voltagecharacteristic for a MOS capacitor at low and high frequencies.

Vdc

vac

i

GateOxide

(a)

Substrate

Cox

C

0Vdc

DepletionAccumulation Strong inversion

Weak inversion

Low frequency

High frequency

(b)

4The low frequency voltage can be thought of as a slowly varying dc voltage which has no effect on thedepletion region width.

and69779_ch07.qxd 2/10/04 10:50 AM Page 390

Page 19: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 391

to gate, source, drain, and substrate, a MOSFET is a four-terminal device. Often,however, the substrate is connected to the source, and the MOSFET is thenconsidered to be a three-terminal device. The symbols W and L represent thewidth and length of the channel.

Figure 7.5a shows the cross section of the MOSFET of Figure 7.4. The equi-librium energy band diagram along the cut A-A′ normal to the gate is shownin (b). From the figure, it appears as though there is no n-type channel fromsource to drain in this device. From the energy band diagram for this structure,

Figure 7.4 Schematic diagram of the structure of ann-channel silicon-based MOSFET. The channel width W,length L, and oxide thickness tox are shown. The symbols S,G, D, and B represent the source, gate, drain, and substrate(body) respectively.

SiO2

n� poly Si

p-type Si

By � 0

y � L

x

z

yG

S

Dn�

n�

Wtox

L

y

Figure 7.5 (a) Cross section of an n-channel FET; (b) the energy band diagram at equilibrium.

n�

sourcen�

drain

n� poly Sitox

p-type substrate

(a)

SiO2

Draw energy banddiagram along this line

A�

A

qVbi � �G � �S

Evac

x

EEC

EiEf

EVqφs

qφox

qφf

ECG � EfG

EVG

(b)

and69779_ch07.qxd 2/10/04 10:50 AM Page 391

Page 20: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

392 PART 3 Field-Effect Transistors

we can determine whether a channel in fact exists. For the specific exampleshown, the band bending in the substrate (qφs) is about a half of an electron volt.The equilibrium energy band diagram of (b) is repeated in Figure 7.6, which alsoindicates the charge in the Si. It can be seen from the figure that the Fermi levelis still close to the intrinsic level near the semiconductor-oxide interface. In otherwords, while a channel does exist, it has a low conductance, since it contains fewelectrons. Because the electron concentration in the channel is so low, for an ap-plied drain-to-source voltage, only a miniscule current can flow between sourceand drain. This device is said to be in the subthreshold region.

The source and drain are doped n+, but the induced channel is only weaklyn type. The resulting difference in the electron concentration creates a modest(n+n) potential energy barrier at either end of the channel. Figure 7.7 shows theequilibrium energy band diagram along the channel instead of across it. Sincethe electron density function n(E) decreases exponentially with increasingenergy, the barrier EB is still large enough that only a small electron concentra-tion exists in the channel. Thus, the induced channel is n type but the channelconductivity is negligible. In the next section, we will see how changing the gatevoltage affects the barrier height and thus the channel conductance.

7.2.3 MOSFETs NOT AT EQUILIBRIUM (QUALITATIVE)

So far, we have considered the device to be at equilibrium. Now let us examinethe physics of MOSFET operation. We will take the substrate to be connected tothe source (a common arrangement). There are still two voltages that can be var-ied, the gate-source voltage VGS and the drain-source voltage VDS.

Figure 7.6 The channel charge accumulatesin the bulk near the oxide interface. In thiscase the channel charge consists of electrons.

ChannelchargeQch

Ionizedacceptors

p silicon

Holes

n� poly Si

EC

Ei

Ef

EV���������������

EV

EC

Oxide

Figure 7.7 The energy band diagram alongthe channel of the device of Figure 7.4.

ChannelSource

EB

EC

DrainEV

and69779_ch07.qxd 2/10/04 10:50 AM Page 392

Page 21: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 393

The Case for VDS = 0 We begin by connecting the source to the drain electri-cally, such that those two terminals are at the same potential, as shown in Fig-ure 7.8a. Let us then apply a voltage to the gate with respect to the source. Thisapplied voltage is also divided between oxide and substrate, just as the built-inpotential was in Figure 7.5. The effect of applying a positive gate voltage is tolower the channel energy (the conduction band edge), as shown in Figure 7.8b.Here we have drawn the energy band diagram along the line A-A′, perpendicularto the gate. The equilibrium diagram is in black, and the energy band diagramunder bias is in color. Under bias, the conduction band edge bends down towardthe Fermi level. The surface is now more strongly n type than before, and thusmore strongly inverted. There are now more electrons in the channel, increasingits conductance. We say that the channel has been “enhanced.”

Figure 7.8 A particular MOSFET example, (a) with source, substrate, and drain connected; (b) the energyband diagram along cross section A-A′ at equilibrium (black) and under bias (colored); (c) the energy banddiagram along the channel for three values of VGS.

�VGS

n� poly SiSiO2

n� source

p substrate

n� drain

A

A�

VS

Channel

(a)

(b)

Equilibrium

Bias

A A�

Ef (eq)

Channel

(c)

ChannelSEV

D

EC

VGS below threshold

Larger VGS

Even larger VGS

and69779_ch07.qxd 2/10/04 10:50 AM Page 393

Page 22: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

394 PART 3 Field-Effect Transistors

Another way to look at it is via Figure 7.8c, which shows the energy banddiagram along the channel for three different gate voltages. For VGS near thresh-old, the energy barrier between source and channel at the Si surface, EB, is fairlyhigh. Few electrons appear in the channel and its conductance is low. As VGS

increases above threshold, the barrier decreases. More electrons are able to enterthe channel, and thus its conductivity increases.

The channel charge Qch in the MOSFET channel is analogous to the inter-face charge Qi in a capacitor. However, for the capacitor, Qi is a result of ther-mal generation and recombination, a relatively slow process. For a MOSFET, thecharge is determined by the barriers between source and channel and betweendrain and channel. The electrons enter and exit the channel by a combination ofconduction and diffusion, typically on the order of 10−12 to 10−11 s, and isnormally considered to be instantaneous.

Definition of Threshold We have indicated that, when the gate voltage isbelow some threshold—i.e., in the subthreshold region—the channel conduc-tance is small. We look at the carrier distributions, and remember that the elec-tron concentration in the semiconductor varies as

n = NCe−(EC −E f )/kT (7.2)

The electron concentration and thus the conductance of the channel variesexponentially with EC − E f . This quantity is dependent on the gate-source volt-age VGS . An exponential is a smoothly (albeit rapidly) varying function, so it isnot clear what value of gate-source voltage should be called threshold. A com-monly used criterion is that the threshold voltage is the gate-source voltage re-quired to induce an electron concentration at the Si surface that is equal to thehole concentration in the neutral substrate (N ′

A).5 This is equivalent to sayingthat a channel exists if the Fermi level in the n channel is as far above the intrin-sic level as the Fermi level in the bulk is below the intrinsic level. This conditionis shown Figure 7.9. Then

φs = 2φ f (7.3)

where φs is called the surface potential, i.e., the voltage at the Si surface relativeto that in the bulk.

Enhancement- and Depletion-Type FETs In our earlier example (Figure 7.5),the band bending caused the surface to be n type even with no bias applied. De-pending on the doping in the substrate, the surface of the semiconductor may ormay not be inverted at equilibrium. If a channel does exist, it may or may not bestrong enough to be considered conductive. In the earlier example, the surface wasinverted at equilibrium but not enough to be considered a proper channel. Withpositive gate-source voltage, the channel conductance increased. As mentioned

5As indicated earlier, another often-used criterion is that VT is the value of VGS required to produce asaturation current IDsat = 40 W/L nA.

and69779_ch07.qxd 2/10/04 10:50 AM Page 394

Page 23: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 395

before, the conductance of the channel is enhanced by the application of a positivegate voltage. An enhancement-type FET is normally off. It does not conduct ap-preciably until a channel is created by the application of a gate voltage.

Figure 7.10a and b shows an enhancement-type NFET and an enhancement-type PFET (i.e., n-channel FET and p-channel FET respectively). In the NFET, apositive gate-source voltage must be applied for the transistor to conduct appre-ciably. For the PFET, the conduction band edge must be bent upward to morefully invert the surface such that more holes can enter the channel. This requiresa negative voltage on the gate with respect to the source. Thus, for enhancementdevices, the threshold voltage of an NFET is positive and the threshold voltageof a PFET is negative. Increasingly negative gate voltage in the PFET causesincreasing channel conductance.

It is possible, however, for the device to be fabricated such that a good chan-nel does exist even with no gate-source voltage applied, as shown in Figure 7.10cand d. In other words, a conducting channel exists even at equilibrium. Thesetransistors are normally on. In these devices, one has to apply a gate-source volt-age to decrease the band bending, deplete the channel, remove the carriers, andthus turn off the conduction. These are called depletion devices.

Figure 7.9 The band bending at the surface of thesemiconductor. At threshold, the Fermi level is asfar above the intrinsic level at the surface (left-handedge) as it is below the intrinsic level in the bulk.

ECEi

EVEC, Ef

EV

Inversionlayer

EC

Eiqφf

qφS

Ef

EVqφf

E

x

and69779_ch07.qxd 2/10/04 10:50 AM Page 395

Page 24: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

396 PART 3 Field-Effect Transistors

Figure 7.10 The energy bands in the semiconductor for (a) theenhancement NFET; (b) the enhancement PFET; (c) the depletionNFET; (d) the depletion PFET.

No gate-source voltage,poorly conducting

channel

Positive gate-sourcevoltage applied,

channel enhanced

EnhancementNFET

p

n� n�

EnhancementPFET

n

p� p�

Negative gatevoltage applied,

channel enhanced

No gate-source voltage,poorly conducting

channel

(a)

(b)

EC

EiEfEV

EC

Ei

Ef

EV

DepletionPFET

n

(c)

(d)

DepletionNFET

p

n� n�

No gate-source voltage,channel exists

Negative gate-sourcevoltage applied,channel depleted

No gate-source voltage,channel exists

Positive gate-sourcevoltage applied,channel depleted

p� p�

EC

EiEfEV

EC

Ei

Ef

EV

6It is common practice to designate MOSFETs by the letter M.

Various symbols are used to represent MOSFETs in circuit schematics.Figure 7.11 illustrates some common symbols; M1, M2, and M3 represent n-channel MOSFETs,6 while M4, M5, and M6 represent p-channel MOSFETs.

The devices M1 and M4 represent NMOS and PMOS enhancement devicesrespectively. The broken line representing the channel between source and drain

and69779_ch07.qxd 2/10/04 10:50 AM Page 396

Page 25: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 397

indicate that no conducting channel exists for VGS = 0. The arrow between sub-strate (also called the body, B) and channel points in the direction from p to n asfor a diode. Depletion NMOS and PMOS devices are indicated by M2 and M5respectively. The solid (nonbroken) channel indicates that a conducting channelexists for VGS = 0.

Devices M3 and M6 represent NMOS and PMOS devices respectively.These symbols are often used where the substrate (body) is connected to thesource. The arrow in the source indicates the direction of current flow. Thesesymbols are used for both enhancement and depletion MOSFETs.

More About Threshold Let us look at the threshold conditions more closely.The concentration of electrons at the surface of the semiconductor is

ns = NCe−(ECch−E f )/kT (7.4)

where ECch is the energy of the conduction band edge in the channel at the Si sur-face, Figure 7.12. We see also that the barrier height is equal to EB = Ech − E f ,since in the heavily doped source E f ≈ EC (see Figure 7.12b). The concentra-tion of electrons in the channel at the surface can be expressed as

ns = NCe−EB/kT (7.5)

From this, we can solve for the barrier height:

EB = kT lnNC

ns(7.6)

Figure 7.11 Schematic representations (circuit symbols)for MOSFETs. M1 is an enhancement-mode NFET, M2 isa depletion-mode NFET, and M3 can be used for eithertype. P-channel MOSFETs are represented by M4(enhancement), M5 (depletion), and M6 (either mode).

G

D

S B

M4

Enhancement PFET

G

D

S B

M5

Depletion PFET

G

D

S

M6

Generic PFET

G

D

S B

M1

Enhancement NFET

G

D

S B

M2

Depletion NFET

G

D

S

M3

Generic NFET

and69779_ch07.qxd 2/10/04 10:50 AM Page 397

Page 26: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

398 PART 3 Field-Effect Transistors

From Figure 7.12a, the surface potential φs can be written

φs = 1

q[Eg − EB − δp] (7.7)

where δp is the energy difference between the Fermi level and the valence bandedge in the bulk (neutral) Si.

According to Equation (7.6), EB varies slowly (logarithmically) with ns;therefore, from Equation (7.7), φs also varies slowly. Since φs is varying slowly,the approximation is often used that above threshold, the band bending φs

remains equal to its threshold value. The gate voltage is dropped partly across theoxide and partly through the band-bending region in the semiconductor (thedepletion region). Because the amount of band bending φs is (roughly) constant,any change in gate voltage above threshold is assumed to be dropped across theoxide. We write this as

VGS − VT = φox − φthox VGS > VT (7.8)

where φthox is the oxide voltage at threshold.

Figure 7.12 The energy band diagram of the NFET across the channel(a) and along the channel (b), with zero voltage between the drain and thesource.

(a)

(b)

DS

G

Cha

nnel

x

ECch

EB � ECch � Ef Ef � EV bulk

EC

Channel

qφS

Ef

EV

Ei

Surface(interface with oxide)

Across channel

x

EC

Eg

Ef

EV

Ei

DSG

Channel y

EB � ECch � Ef

Channel

Source Drain

Along channel at interface

y

EC

ECch

EfEi

EV

E

and69779_ch07.qxd 2/10/04 10:50 AM Page 398

Page 27: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 399

Show that the approximation in Equation (7.8) is valid. That is, how realistic is it thatany additional gate voltage above threshold is dropped across the oxide and not thesemiconductor?

■ SolutionConsider the n-channel MOSFET of Figure 7.4. Let the net substrate doping beN ′

A = 1016 cm−3. We know that threshold occurs when the electron concentration atthe surface of the channel, ns , is equal to N ′

A , because that is when the surface has thesame number of electrons as the bulk has holes.

From Equation (7.6), we have

EB(threshold) = kT lnNC

ns(threshold)

= (0.026 eV) ln

(2.86 × 1019 cm−3

1016 cm−3

)

= 7.96kT = 0.207 eV

The maximum value that ns can realistically attain in silicon MOSFETs is about2 × 1018 cm−3, at which point

EB(way above threshold) = kT lnNC

ns(way above threshold)

= (0.026 eV) ln

(2.86 × 1019 cm−3

2 × 1018 cm−3

)

= 2.66kT = 0.069 eV

In other words, between threshold and way above threshold, the barrier height EB

and thus qφs vary by only about 5.3kT, or 138 meV, at room temperature. From Equa-tion (7.7), over this same range the surface potential φs varies by the value �EB/q =0.138 V.

From Equation (7.3), at threshold, φs(threshold) = 2φ f . Since φ f = (Ei − E f )/qand Ei − E f = kT ln(N ′

A/ni ), we have

φ f = kT

qln

N ′A

ni= 0.026 ln

1016

1.08 × 1010= 0.357 V

Therefore the band bending at threshold is

φs(threshold) = 2φ f = 2(0.357) = 0.714 V

Now we find the band bending at a surface concentration of 2 × 1018 cm−3, which is

φs(way above threshold) = 0.714 + 0.138 = 0.852 V

or about 20 percent above its value at threshold. The voltage drop across the semicon-ductor, then, is not exactly constant above threshold but it is changing slowly.Therefore, the approximation that the surface potential φs is constant above thresholdnormally is adequate.

The Case for VDS > 0 In the previous section, we looked at the effect of thegate-source voltage on the energy band diagram, barrier heights, and carrier con-centrations in the channel. The carrier concentration in the channel relates

EXAMPLE 7.1

and69779_ch07.qxd 2/10/04 10:50 AM Page 399

Page 28: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

400 PART 3 Field-Effect Transistors

directly to the conductance in the channel. We assumed there that both ends ofthe channel were at the same voltage.

In this section, we will allow the drain voltage to be different from the sourcevoltage, thus producing a longitudinal electric field in the channel. This field willinduce current to flow along the channel. Just as the current that flows through aresistor depends on the voltage across it, the current from the drain to the sourcedepends on the drain-to-source voltage. In a MOSFET, however, the conduc-tance (and thus resistance) of the channel depends on the gate-source voltage.In fact, this is the origin of the name transistor. The resistance across (trans)the device is controlled by the gate-source voltage. It is a voltage-controlledresistor.

Figure 7.13a shows an n-channel MOSFET. The drain is at a positive volt-age VDS with respect to the source. The gate has some applied voltage above

Figure 7.13 (a) With a voltage on the drain with respect to the source, the depletionregion width varies along the channel. So does the voltage across the channel at anygiven point. (b) The energy band diagrams normal to the gate at source and at drain.Here the drain voltage is higher than the source voltage, so the “depth” of the channelvaries along its length. (c) The energy band diagram along the channel with no voltageon the drain with respect to the source, and with positive bias applied drain to source.

��

VG � VD

��

VG � VS

VGVDVS

(a)

�L

ID

EB

qVDS

VDS � 0

E

y

Electronflow

Large VDS

(c)

EV

EV

EC, Ef

EC

G

(b)

Substrate

At source

At drain

Oxide

and69779_ch07.qxd 2/10/04 10:50 AM Page 400

Page 29: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 401

Figure 7.14 The ID-VDS characteristics of a typicalMOSFET. The threshold voltage for this MOSFET is 0.5 V.

VGS � 2.5 V

VGS � 2.0 V

VGS � 1.5 V

VGS � 1.0 V

VGS � 0.5 VVDS

ID

threshold, so the channel is conducting. If we could take an imaginary voltmeterand somehow measure the voltage across the oxide at the source end of the chan-nel, it would be VG − VS′ = VGS . At the drain end, the voltage across the oxideis VG − VD . Since the channel voltage varies along the channel and the substratevoltage is constant, this varying channel voltage means also that the depletionregion width varies from one end to the other. Thus, the channel is wider at thedrain end than at the source end.

Since VDS is positive, electrons entering the potential well from the sourceend will drift down the channel to the lower electron energy at the drain end.Figure 7.13b shows the energy band diagrams normal to the gate at source and atdrain for a positive drain voltage. The channel potential energy (EC) decreasesalong the channel from source to drain.

Figure 7.13c shows the energy band diagram along the channel. When nodrain-source voltage is applied (solid line), electrons in the channel do not drift,since the longitudinal field �L = 0. When VDS > 0 is applied, the electron en-ergy at the drain end is lowered and electrons are moved toward the drain. Sinceelectrons are negatively charged, the actual current ID flows from drain to source.

Let us examine the current-voltage characteristics of a typical NFET inFigure 7.14. We expect that when the gate voltage is below threshold(VGS ≤ VT ), the channel will be weakly conductive and the current ID will benegligible regardless of the value of VDS. The threshold voltage for the transistorin this example is taken to be VT = 0.5 V, so for any gate-source voltage below0.5 V the transistor does not conduct appreciably.

As VGS increases above the threshold voltage, the barrier height EB for elec-trons entering the channel decreases (recall Figure 7.8c), which results in moreelectrons entering the channel. The channel conductance increases and thus thecurrent also increases and becomes appreciable for VGS > VT .

There is an interesting feature of Figure 7.14 that bears investigation. Wemight expect that for a given gate voltage, and thus a given channel conductivity

and69779_ch07.qxd 2/10/04 10:50 AM Page 401

Page 30: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

402 PART 3 Field-Effect Transistors

(fixed resistor), we would see the current vary linearly with the voltage VDS

across the “resistor” (channel). We see this linear behavior in Figure 7.14 forvery small values of VDS, but then the current levels off and saturates. We canexplain the saturation effect as follows.

Figure 7.15 shows a plot of the energy band diagram along the channel fromsource to drain for a given value of VGS above threshold. There are three valuesshown—for VDS = 0, for small VDS, and for a larger value of VDS . When the drainvoltage is the same as the source voltage (VDS = 0), the longitudinal field in thechannel is also zero, so there is no slope to the conduction band edge along thechannel (�L = (1/q)(d EC/dy)). Thus ID = 0 [Equation (III.5) in the Introduc-tion to Part 3]. For small VDS , the energy band diagram tilts slightly. The electronsthat enter the channel from the source are accelerated toward the drain by thechannel field. At first, as the drain voltage increases, the longitudinal field in-creases and thus ID increases (look again at the low VDS end of the ID-VDS char-acteristics, Figure 7.14). We will show in the next section that, with increasingVDS, the longitudinal field �L increases faster near the drain end than the sourceend (this is shown in the figure—remember that field is proportional to the slopeof the conduction band edge), and most of the incremental drain voltage isdropped near the drain. In other words, with increasing VDS there are increasinglysmaller changes in the longitudinal field at the source end, as shown in the figure.Eventually, at some value of VDS, the field at the source reaches a limiting value.Since the current at one end of the channel must be the same as the current atthe other end, the current ID is limited to what can be supported by this field at thesource end. The drain current ID ∝ ns�L(source), and ns (the carrier concentration inthe channel at the source) is controlled by the barrier height EB and thus by VGS.

Figure 7.15 The energy band along the channel for threedifferent values of VDS. The current saturates because, asthe drain voltage increases, the slope (and thus the electricfield) increases faster at the drain end, but at the sourceend, there is little change. Thus the current is limited by thefield at the source end.

VDS � 0Small VDS

Large VDS

Slope changesfaster at drain end

Little furtherchange in slope

ns controlled by EB(which is controlled by VG)

EB

Slight change in slope

and69779_ch07.qxd 2/10/04 10:50 AM Page 402

Page 31: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 403

When the field �L(y = 0) saturates, so does ID. (Compare with the analogy withthe two lakes and the canal discussed in the Introduction to Part 3.)

Note also that EB , the barrier from source to channel depends on the gate-source voltage VGS . Therefore, the number of electrons in the channel ns , whichdepends on the barrier height, also depends on VGS but not on VDS .7

To summarize our qualitative discussion of MOSFET behavior, a MOSFETis a voltage-controlled resistor. The resistor is between the source and the drain.We can control the conductance of the channel between source and drain bycontrolling the number of channel carriers available for conduction. In theMOSFET, that control results from adjusting the gate voltage, which in turn con-trols the band bending in the semiconductor. The gate voltage forces theconduction band edge to bend closer to or farther away from the Fermi level.

Current does not flow into the gate terminal, because there is an insulatingoxide layer between the gate and the source, channel and drain. The gate voltageinduces an electric field in the oxide, which in turn influences the energy bandsin the semiconductor. The electric field from which the FET gets its name is thefield induced by the gate voltage. For a MOSFET, it is the field across the oxide.

In the next section, we will apply our physical understanding of theseprocesses to derive expressions for the ID-VDS characteristics of the transistors.

7.3 MOSFETs (QUANTITATIVE)Now that we have a physical understanding of how MOSFETs work, we can bemore quantitative. We will derive expressions for the ID-VDS characteristics ofan NFET. These derivations of the electrical characteristics of MOSFETs arepresented in three steps. First, we consider a formulation, in which the carriermobility is assumed constant along the channel. [1] This is the simplest model,called the long-channel model, and it predicts the general form of the ID-VDS

characteristics. It is useful for obtaining insight into the general behavior ofMOSFETs but does not closely reproduce the results for modern devices.Therefore, we will then modify the simple model to account for variation inmobility. The mobility is affected by two things: the transverse and the longitu-dinal electric fields in the channel. Accounting for these are the second and thirdsteps in our development.

We consider the enhancement-type NFET device of Figure 7.4, which isrepeated as Figure 7.16. The figure indicates channel width W, the channellength, L, and the oxide thickness tox. The direction of the longitudinal field �L

is shown, along with the field component perpendicular to the channel, called thetransverse field, �T . Recall from Figure III.7 that the channel voltage Vch is thevoltage at a given point along the channel with respect to the source, and is afunction of position along the channel. At the drain end of the channel the chan-nel voltage Vch is equal to the drain-source voltage VDS .

7As we will discuss in Chapter 8, for very short (submicrometer) channel lengths, VDS does, in fact,affect the value of EB . In this chapter, however, this effect is ignored.

and69779_ch07.qxd 2/10/04 10:50 AM Page 403

Page 32: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

404 PART 3 Field-Effect Transistors

Our starting point will be Equations (III.3) to (III.7), which we repeat herefor convenience:

ID = −W Qch(y)v(y) (III.3)

v(y) = −µ(y)�L(y) (III.4)

ID = W Qch(y)µ(y)�L(y) (III.5)

�L = −dVch

dy(III.6)

ID dy = −W Qch(y)µ(y) dVch(y) (III.7)

Since our goal is to obtain an expression for ID , we see from Equation (III.7)that we need the following: an analytical expression for µ, the carrier mobilityin the channel; an expression for Qch, the charge per unit area in the channel (thisis the mobile charge, in this case electrons in the conduction band); and an ex-pression for Vch as a function of position y. We will derive these first for the sim-ple long-channel model, to illustrate the physics. Later we will add more realism(and complication) to the equations.

7.3.1 LONG-CHANNEL MOSFET MODEL WITH CONSTANT MOBILITY

There are several models used to describe µ and Qch. We will start with an over-simplified model for these quantities. While this model gives realistic resultsonly for the ID-VDS characteristics for MOSFETs with very long channels(L > 5 to 10 µm), it is mathematically simple and does illustrate the general prin-ciples of operation. This formulation is employed in the SPICE Level 1 model.

Channel Charge Density Since the channel current depends on the channelcharge density, our first task will be to analyze the charge in the channel. The

Figure 7.16 The NFET. Longitudinal and transverse electricfield directions are indicated.

SiO2

n� poly Si

p type

y � 0y � L

x

z

y

n�

n�

tox

L�L

�T

W

and69779_ch07.qxd 2/10/04 10:50 AM Page 404

Page 33: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 405

charge will depend on the bias conditions. When the gate voltage is belowthreshold, the conductance is small because the number of electrons available forconduction is small. For simplicity we approximate:

Qch ≈ 0 and ID ≈ 0 VGS ≤ VT (7.9)

For VGS > VT , of course, Qch is nonzero. We can find how much charge ispresent by recognizing that the region under the gate acts as a capacitor. Twoconductive plates (the heavily doped polysilicon gate electrode and the conduc-tive channel) are separated by an insulator (the oxide). The capacitance of aparallel plate capacitor is given by

C = εA

t(7.10)

where ε is the permittivity of the insulator, A is the area of the plate, and t is thethickness of the dielectric layer. In our device, we use the oxide thickness tox. Thearea of the gate electrode is W × L .

On a given integrated circuit, different transistors may have different widthsand lengths. The oxide thickness, on the other hand, is usually a constant for agiven process and therefore common to all devices on the chip. It is thereforeuseful to define an oxide capacitance per unit area C ′

ox:

C ′ox = εox

tox(7.11)

where εox is the permittivity of the oxide εox = εrε0, and εr is the relative per-mittivity (dielectric constant) of the dielectric. The dielectric constant is εr = 3.9for SiO2.

We will need to know the voltage across the capacitor, which is the voltageacross the oxide. We don’t know what the voltage across the oxide is, exactly, butwe do recall from Example 7.1 that to reasonable approximation, for VGS > VT

any change in gate voltage appears across the oxide. Since capacitance isC = |d Q/dV |, then

C ′ox = −d Qch

dVGS= −�Qch

�VGS= − Qch(VGS) − Qch(VT )

VGS − VT= − Qch(VGS) − 0

VGS − VT

(7.12)

where we have used the information that Qch is negative and for VGS = VT ,,Qch = 0 [Equation (7.9)]. Letting Qch = Qch(VGS), we have

Qch = −C ′ox(VGS − VT ) VDS = 0 (7.13)

When VDS is no longer zero but is positive, the voltage on the lower plate ofthe capacitor between the channel and ground, Vch, is a function of position yalong the channel. The voltage dropped across the oxide will thus vary along yand affect Qch:

Qch(y) = −C ′ox(VGS − VT − Vch(y)) VGS − VT > Vch(y) (7.14)

and69779_ch07.qxd 2/10/04 10:50 AM Page 405

Page 34: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

406 PART 3 Field-Effect Transistors

At the source end of the channel, where Vch = 0 since Vch is the channelvoltage with respect to the source, this reduces to Equation (7.13).

We now have expressions for the channel charge—but there is a problem.Equation (7.14) is valid only for (VGS − VT ) > Vch(y). This will always be trueat the source end of the channel, provided the gate voltage is above threshold,since Vch = 0. At the drain end, however, Vch(y = L) = VDS . Thus, if VDS >

(VGS − VT ), then at some position y in the channel, the channel voltage must beequal to Vch = (VGS − VT ). At that point along the channel, Equation (7.14) im-plies that Qch = 0. However, since VGS is above threshold and VDS is not zero,we know that a current ID is flowing through the channel. Then from Equa-tion (III.3), since ID > 0, this implies that the electron velocity is infinite. Fur-thermore, at y greater than this value, Vch > (VGS − VT ), implying that thechannel charge is positive. That would mean that the channel current is carried byholes. From physical arguments, however, we reject both of these scenarios. Weknow that the maximum possible velocity is the saturation velocity vsat, and fromFigure 7.12a holes clearly cannot enter the channel. Thus, since ID must be a con-stant at every position in the channel, from Equation (III.3) when the velocity hasa maximum the charge has a minimum. The minimum value of Qch is

Qch min = − IDsat

Wvsat(7.15)

where IDsat is the saturation current, which is indicated in Figure 7.17 for severalvalues of VGS. According to this model, the current cannot exceed this amount fora given value of gate voltage VGS. The saturation current is reached when there isa position in the channel for which Vch = VGS − VT . This happens first at the drainend, when VDS = VGS − VT . We call this the drain saturation voltage VDSsat.

Above this saturation point, Equation (7.14) no longer applies. We will takethis point up again later. In the region where it does apply, though, we now havea model for the channel charge.

Figure 7.17 The saturation current andsaturation voltage are defined.

VGS4IDsat4

IDsat3

IDsat2

IDsat1

VD

Ssat

1

VD

Ssat

2V

DSs

at3

VD

Ssat

4

VGS3

VGS2

VGS1

VDS

ID

VGS � VT

and69779_ch07.qxd 2/10/04 10:50 AM Page 406

Page 35: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 407

Channel Mobility Next, we examine the channel mobility µ. In this long-channel simple model, we will take the mobility to be constant. In reality, themobility depends on the longitudinal electric field �L (and thus on Vch). Forexample, we saw in Chapter 3 that, under high fields, the velocity saturates.Further, the transverse field �T will have an effect. We will handle these depen-dencies of mobility on the fields explicitly later, however. Here we will considerthe simplest model, the low-field case, in which the mobility is constant.

Long-Channel Model, Constant Mobility In this model, for mathematicalsimplicity we assume µ to be constant, and of value somewhere in the neighbor-hood of one-half to one-third of its bulk value. We use the term bulk to distin-guish the mobility in a large crystal from the mobility experienced by a carrier ina thin layer such as the channel of a MOSFET. The reason for assuming one-halfto one-third of the bulk value is that the small thickness of the channel will tendto slow the carriers down from the bulk value, as we will see later.

To obtain the ID-VDS characteristics for this model, we integrate both sidesof Equation (III.7):

L∫0

ID dy =VDS∫0

−WQch(y)µ(y) dVch (7.16)

Note the limits of integration. Over the length of the channel, the channel voltagevaries from the source voltage Vch = 0 to the drain-source voltage VDS .

As long as the drain voltage is less than (VGS − VT ), the channel voltage Vch

will also satisfy Vch < (VGS − VT ), so we can use Equation (7.14) for the chan-nel charge. Since the mobility µ is constant in this model, it comes out of theintegral. The current ID cannot vary with position along the channel, so it is alsoa constant and it also comes out of its integral. Thus Equation (7.16) becomes

ID

L∫0

dy = −Wµ

VDS∫0

Qch dVch

= −Wµ

VDS∫0

[−C ′ox(VGS − VT − Vch)] dVch (7.17)

Integrating, the result is, for VDS ≤ (VGS − VT ),

ID = WC ′oxµ

L

VDS∫0

(VGS − VT − Vch) dVch VDS ≤ (VGS − VT ) (7.18)

or

ID = WC ′oxµ

L

[(VGS − VT )VDS − V 2

DS

2

]VDS ≤ (VGS − VT ) (7.19)

and69779_ch07.qxd 2/10/04 10:50 AM Page 407

Page 36: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

408 PART 3 Field-Effect Transistors

There are two independent variables in this equation, the drain voltage andthe gate voltage. Figure 7.18 shows the drain current calculated from Equa-tion (7.19) versus the drain voltage for two different values of gate-source volt-age VGS . We chose the parameters of the NFET to be tox = 4 nm, W/L = 5, andµ = 500 cm2/V · s.

We see from the plot that the current reaches a maximum (d ID/dVDS = 0)

for VDS = (VGS − VT ). This is also the limit of validity of Equation (7.19). ForVDS > (VGS − VT ), from Equation (7.19), ID would be expected to decrease asindicated by the colored dashed line of Figure 7.18. We will show later that thesimple model predicts that once the curve in Figure 7.18 reaches its peak, thecurrent remains (essentially) constant for larger VDS. Thus, the current saturatesat some value of IDsat as indicated.

The value of VDSsat at which ID saturates is found from taking ∂ ID/∂VDS inEquation (7.19) and setting it to zero:

∂ ID

∂VDS= 0 = WC ′

oxµ

L(VGS − VT − VDSsat) (7.20)

orVDSsat = (VG − VT ) (7.21)

Above this value, ID remains constant.We can use this result in Equation (7.17). By setting the limit of integration

to VDSsat, we obtain an expression for the saturation current:

ID = IDsat = WC ′oxµ

L

[(VGS − VT − VDSsat

2

)VDSsat

](7.22)

Figure 7.18 The current predicted using Equation (7.19) (solidlines) is only valid up to the point where VDS = VGS − VT. After thatthe current saturates (black dashed lines), whereas Equation (7.19)would predict a decrease and eventually a sign reversal in thecurrent (colored dashed lines).

�2

0

0 1 2 3 4

2

4

Limit of validityof Equation (7.19)

IDsat2

IDsat1

VDS (volts)

I D (

mA

)Equation (7.19)

predicts

Expectedresults

VGS � VT � 2 V

VGS � VT � 1 V

VDSsat1 VDSsat2

and69779_ch07.qxd 2/10/04 10:50 AM Page 408

Page 37: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 409

But, since in this model VDSsat = VGS − VT , we can write:

IDsat = WC ′oxµ

2L(VGS − VT )2 = WC ′

oxµ

2LV 2

DSsat (7.23)

Since IDsat is proportional to V 2DSsat, this model is sometimes referred to as the

square law model. It results from the simple long-channel model, assuming con-stant mobility, and uses Equation (7.14) to represent the channel charge in theregion below threshold.

Thus, we can describe the ID-VDS characteristics for this model with the fol-lowing three equations:

ID = WC ′oxµ

L

[(VGS − VT )VDS − V 2

DS

2

]VDS ≤ VDSsat, VGS ≥ VT (7.24)

IDsat = WC ′oxµ

L

[(VGS − VT − VDSsat

2

)VDSsat

]= WC ′

oxµ

2L(VGS − VT )2

VDS ≥ VDSsat, VGS ≥ VT (7.25)

VDSsat = (VGS − VT ) (7.26)

Using the simple long-channel model, assuming constant mobility, plot the ID-VDS

characteristics for an NFET with W/L = 5 and tox = 4 nm. Take the constant mobil-ity for electrons in the channel to be 500 cm2/V · s. Plot for VGS − VT = 1, 2, 3, and4 V, and VDS from 0 to 5 V.

■ SolutionFrom Equation (7.11), we have

C ′ox = εox

tox= εr(ox)ε0

tox= 3.9(8.85 × 10−14 F/cm)

4 × 10−7 cm= 8.6 × 10−7 F/cm2

For each value of VGS − VT , we must find the saturation point to know whether touse Equation (7.24) or (7.25). For example, from Equation (7.26), we have forVGS − VT = 1 V, VDSsat = VGS − VT = 1 V. For VDS between 0 and 1 V, then, we useEquation (7.24)

ID = W

LC ′

oxµ

[(VGS − VT )VDS − V 2

DS

2

]

= (5)(8.6 × 10−7 F/cm2)(500 cm2/V · s)

[(1) · VDS − V 2

DS

2

]

= 2.15 × 10−3

[VDS −

(VDS

2

)2]

EXAMPLE 7.2

and69779_ch07.qxd 2/10/04 10:50 AM Page 409

Page 38: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

410 PART 3 Field-Effect Transistors

At VDS = VDSsat = 1 V, ID reaches its saturation value of [Equation (7.25)]

IDsat = WC ′oxµ

2L(VGS − VT )2 = (5)

(8.6 × 10−7)(500)

2(1)2 = 1.07 mA

A similar procedure is used for the other values of VGS − VT . The results are plottedin Figure 7.19. The dashed line indicates the boundary between the sublinear and thesaturation region, i.e., for VDS = VDSsat = (VGS − VT ).

Figure 7.19 The ID-VDS characteristics of the NFET ofExample 7.2: results from the simple model. For thisdevice W/L = 5, tox = 4 nm, C′

ox = 8.63 × 10−3 F/m2, and µn = 500 cm2/V · s.

I D (m

A)

VDS (V)

00 1 2 3 4

5

10

15

20

Boundary ofsaturation VGS � VT � 1 V

VGS � VT � 2 V

VGS � VT � 3 V

VGS � VT � 4 V

Current Saturation Revisited Earlier we claimed that the simple long-channel model (constant µ) predicts that once the drain voltage reachesVDSsat = VGS − VT , the current saturates and remains constant for all higherdrain voltages. This saturation was discussed qualitatively by analogy with waterflow between two lakes via a canal as discussed in Part 3, Field-Effect Transis-tors. Here we discuss current saturation more quantitatively.

When we discussed Figure 7.14, we indicated that for low values of VDS , thelongitudinal field �L is constant along the channel. At larger drain voltages, thefield increases appreciably at the drain end, but not much at the source end, aswas shown in Figure 7.15. Let us consider the effect of this point analytically.

For a given VGS and VDS with constant µ, Equation (III.5) becomes

ID = WµQch(y)�L(y)

The current is constant and proportional to the Qch�L product at any value of y.It is convenient to determine this product and thus the ID-VDS relation near thesource end of the channel (y = 0). We can find �L from Equation (III.6)(�L = −dVch/dy) if we have an expression for Vch as a function of y. We can

and69779_ch07.qxd 2/10/04 10:50 AM Page 410

Page 39: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 411

find Vch(y) by integrating Equation (III.7) from 0 to y. From Equations (III.7)and (7.14), then

ID

y∫0

dy = WC ′oxµ

Vch(y)∫0

(VGS − VT − Vch) dVch (7.27)

or

ID = WC ′oxµ

y

(VGS − VT − Vch(y)

2

)Vch(y) (7.28)

Solving for Vch(y)

Vch(y) = (VGS − VT ) −√

(VGS − VT )2 − 2ID y

WC ′oxµ

(7.29)

where the negative sign associated with the square root is used, since for y = 0,Vch(0) = 0.

This gives us an expression for the channel voltage as a function of distancealong the channel. The potential energy (EC ) has the same shape as the potential,but inverted (dEC/dy = −qdVch/dy), which means the conduction band edgehas the shape

EC(y) = EC(0) − qVch(y) (7.30)

Therefore, we can substitute Equation (7.29) into Equation (7.30) to obtain

EC(y) = EC(0) − q

[(VGS − VT ) −

√(VGS − VT )2 − 2ID y

WC ′oxµ

](7.31)

The conduction band edge along the channel is plotted in Figure 7.20a forseveral values of VDS , with W/L = 10, µ = 500 cm2/V · s, (VGS − VT ) = 2 Vand C ′

ox = 6.9 × 10−7 F/cm2 (tox = 5 nm), and with ID obtained from Equa-tion (7.19). For VDS = 0, ID = 0, and there is no voltage drop along the channeland EC is flat. As VDS increases, the band bends increasingly as seen in thefigure. We note that the magnitude of the slope of the EC -y plot at the source(y = 0) increases with increasing VDS and tends toward saturation as VDS

approaches VGS − VT (2 V).The electric field is proportional to the slope of EC . The longitudinal field at

some point y is

�L(y) = −dVch

dy= 1

q

d EC

dy= −

ID

WC ′oxµ√

(VGS − VT )2 − 2ID y

WC ′oxµ

(7.32)

The field �L(y) is plotted in Figure 7.20b for the same device, for variousvalues of drain voltage. Notice that near the source end, the magnitude of the

and69779_ch07.qxd 2/10/04 10:50 AM Page 411

Page 40: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

Figure 7.20 Illustration for current saturation. (a) The conduction band edgealong the channel bends more at the drain end than at the source end for largedrain voltage VDS. (b) Since the longitudinal field is proportional to the slope ofEC, the field changes rapidly at the drain end for increasing values of VDS butnot at the source end. (c) The field at the source end is constant as VDS

increases beyond a certain point; thus the current is constant as well.

0Source Distance along channel, y

(a)

DrainL

0.0

�0.5

�1.0

�1.5EC

(y)

� E

C(0

) (e

V)

Conduction band edgeVDS � 0

0.5 V

1.0 V

1.5 V

1.7 V1.8 V1.9 V

L

S D

0Source Distance along channel, y

(b)

DrainL

0

�1

�2

�3

�4

�5

VDS � 0

0.5 V

1.0 V

1.5 V

1.7 V

1.8 V

1.9 V

Longitudinal field �L

Lon

gitu

dina

l fie

ld �

L(y

) (V

/µm

)

Saturation:no change in fieldmeans no change in current

Field varies rapidly for small VDS

0.0

�0.2

�0.4

�0.6

�0.8

�1.0

0.0 0.5 1.0 1.5

(c)

2.0 2.5 3.0

Drain voltage VDS (V)

Fiel

d at

sou

rce

end

�L(0

) (V

/µm

)

�L(0)

VDSsat

412 PART 3 Field-Effect Transistors

and69779_ch07.qxd 2/10/04 10:50 AM Page 412

Page 41: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 413

EXAMPLE 7.3

field �L(0) varies rapidly with VDS for small values of VDS , but approaches aconstant (saturates) as VDS approaches VDSsat = VGS − VT .

Combining Equations (III.5) and (7.13) at y = 0, we have as our final result

ID = −WC ′ox(VGS − VT )µ�L(0) (7.33)

Again, the current is proportional to the electric field at the source end. Since thefield is saturating, the current also saturates.

Finally, let us examine the rate at which the last term, the field at the sourceend �L(0), varies with VDS . We use Equation (7.32) with y = 0:

�L(0) = −ID

WC ′oxµ

(VGS − VT )= − ID

WC ′oxµ(VGS − VT )

(7.34)

Substituting for ID from Equation (7.19) yields

�L(0) = −

(VGS − VT − VDS

2

)VDS

L(VGS − VT )= − 1

L

[1 − VDS

2(VGS − VT )

]VDS (7.35)

For VGS − VT = 2 V, we have

�L(0) = −

(1 − VDS

4

)VDS

L(7.36)

For a channel length of L = 1 µm, that produces a field of

�L(0) = −(

1 − VDS

4

)VDS

V

µm(7.37)

This is plotted in Figure 7.20c. We observe that the magnitude of the fieldincreases with VDS and then levels off. For saturation, we know that the slope iszero, or

d�L(0)

dVDS= 0 = −

(1 − VDS

2

)(7.38)

which occurs for VDS = (VGS − VT ) = 2 V, as seen in the figure.

Show that for constant µ, evaluating Equation (III.5) at y = 0 gives Equation (7.19)for ID .

■ SolutionEquation (III.5) is repeated here:

ID = W Qch(y)µ(y)�L(y)

and69779_ch07.qxd 2/10/04 10:50 AM Page 413

Page 42: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

414 PART 3 Field-Effect Transistors

At y = 0, we have Vch = 0. From Equation (7.14), then, Qch(0) = C ′ox(VGS −

VT ). Combining these with the expression for �L(0) from Equation (7.35) into Equa-tion (III.5), we obtain

ID = WµQch(0)�L(0) = Wµ[−C ′ox(VGS − VT )]

(VGS − VT − VDS

2

)VDS

L(VGS − VT )

Canceling (VGS − VT ) gives

ID = WµC ′ox

L

(VGS − VT − VDS

2

)VDS

which is Equation (7.19).

Channel Length Modulation In the above long-channel MOSFET model, inthe sublinear region the drain current is given by Equation (7.19):

ID = WC ′oxµ

L

[(VGS − VT )VDS − V 2

DS

2

]VDS ≤ VDSsat (7.19)

and in saturation combining Equations (7.25) and (7.26) gives

ID = IDsat = WC ′oxµ

2L(VGS − VT )2 = WC ′

oxµ

2LV 2

DSsat VDS ≥ VDSsat (7.39)

which is constant. In real devices, however, as the drain voltage increases abovethe saturation point VDS > VGS − VT = VDSsat, ID continues to increase slowlywith increasing VDS , as indicated in Figure 7.21. This figure represents theexperimental results for an n-channel MOSFET with tox = 4.7 nm, L = 0.27 µm,

Figure 7.21 Experimental ID-VDS characteristics for an n-channelMOSFET for three values of gate voltage. The current actuallyincreases with increasing VD in the “current saturation” regionbecause of channel-length modulation. For this device, tox = 4.7 nm,L = 0.27 µm, W = 8.6 µm, and VT = 0.3 V.

6.0

0.0

5.0

4.0

3.0

2.0

1.0

I D (

mA

)

0.0 0.5 1.0 1.5 2.0 2.5VDS (V)

Slope � 0 (because ofchannel-length modulation)

VGS � 2.1 V

VGS � 0.9 V

VGS � 1.5 V

and69779_ch07.qxd 2/10/04 10:50 AM Page 414

Page 43: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 415

and VT = 0.3 V. There are two physical reasons for this increase in drain currentthat were not taken into account in the simple model: (1) increasing drain voltageVDS reduces the effective channel length L, which we will discuss next, and(2) increasing VDS reduces the value of the threshold voltage. The second ofthese effects is important for very short channels and is discussed in Chapter 8,where short-channel effects are handled.

Let us examine qualitatively why the channel length is effectively shortenedas VDS increases above saturation. Figure 7.22a to d indicates the channel energyas a function of y for a given value of VGS > VT and for four values of VDS .Figure 7.22e shows the corresponding currents. In (a), where VDS = 0, thechannel charge Qch is constant in y and no current flows. In (b), for small VDS ,Qch decreases with increasing y and current flows as indicated. For VDS ≥(VGS − VT )= VDSsat , (c) the current saturates as discussed earlier. For VDS >

VDSsat, the channel voltage Vch reaches VDSsat somewhere before the end of thechannel [part (d) of the figure]. The effective channel length then is shorter than

Figure 7.22 Qualitative explanation for channel-length modulation. Parts (a)to (c) repeat the explanation of the simple long-channel model. In (d), as thedrain voltage continues to increase, the point at which the channel chargeapproaches 0 (shaded region), or the point at which Vch = VGS − VT, movesalong the channel toward the source. The channel becomes effectivelyshorter. (e) The corresponding points on the ID-VDS characteristics. Frompoint (c) on, the simple model predicts constant current (dashed line).

(a)

(b)

(c)

(d)

(d)(c)

(b)

VDS

IDsat

ID

(a)

Channel chargeS D

y

LLeff

�L

(e)

Predicted whenchannel-length

modulation is neglected

Actualcharacteristic

and69779_ch07.qxd 2/10/04 10:50 AM Page 415

Page 44: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

416 PART 3 Field-Effect Transistors

EXAMPLE 7.4

the physical channel by some amount �L :

Leff = L − �L (7.40)

Here we will treat �L as an empirical quantity (established from measurements). Now, substituting Equation (7.40) into Equation (7.39), we get for the drain

current

ID = WC ′oxµ

2(L − �L)V 2

DSsat = WC ′oxµ

2L

(1 − �L

L

)V 2DSsat = IDsat(

1 − �L

L

) (7.41)

where �L is a function of VDS . For small �L/L ,

1(1 − �L

L

) ≈(

1 + �L

L

)

and to first approximation, for VDS > VDsat the fractional change in channellength is proportional to VDS − VDSsat:

�L

L= λ(VDS − VDSsat) (7.42)

The quantity λ is known as the channel length modulation parameter (a SPICEparameter).8 For VDS > VDSsat then

ID ≈ IDsat[1 + λ(VDS − VDSsat)] (7.43)

The slope ∂ ID/∂VDS in the ID-VDS characteristic in saturation is the differ-ential output conductance. The output conductance is thus proportional to λ.From Equation (7.42) it is seen that λ increases with decreasing L.

Extrapolation of the ID-VDS plots to ID = 0 occurs at a voltage VA, oftenreferred to as the “Early voltage” analogous to a similar effect in the electricalcharacteristics in bipolar transistors discussed in Part 4.

Find the SPICE parameter λ for the device of Figure 7.21.

■ SolutionFrom Equation (7.43), for VDS > VDSsat ,

ID = IDsat[1 + λ(VDS − VDSsat)]

Then

λ = 1

IDsat

∂ ID

∂VDS= 1

IDsat

�ID

�VDS

8In SPICE Level 1, the expression used is ID = IDsat(1 + λVDS).

and69779_ch07.qxd 2/10/04 10:50 AM Page 416

Page 45: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 417

For this device, we find

C ′ox = εox

tox= 3.9(8.85 × 10−14 F/cm)

4.7 × 10−7 cm= 7.3 × 10−7 F/cm2

For VGS = 2.1 V, from Figure 7.21 the saturation voltage is VDSsat ≈ 1.2 V andIDsat ≈ 5.1 mA. To find the slope, we extrapolate the straight-line portion of theID-VDS curve from 2.5 V to 0 V, as shown in Figure 7.23. We obtain

�ID

�VDS= 5.36 − 4.9

2.5 − 0= 0.46 mA

2.5 V

Then

λ =(

1

5.1 mA

)(0.46 mA

2.5 V

)= 0.036 V−1

corresponding to an early voltage (VA) of 28 V.

Figure 7.23 Finding the channel-length modulation parameterrequires finding the slope of the ID-VDS characteristic in the “saturation”region (Example 7.4.). This is the same device as in Figure 7.21.

6.0

0.0

5.0

4.0

3.0

2.0

1.0

I D (

mA

)

0.0 0.5 1.0 1.5 2.0 2.5VDS (V)

ID � 4.9 mA ID � 5.36 mA

VGS � 0.9 V

VGS � 1.5 V

VGS � 2.1 V

7.3.2 MORE REALISTIC LONG-CHANNEL MODELS:EFFECT OF FIELDS ON THE MOBILITY

In the above long-channel model for finding the I -VDS characteristics of aMOSFET, we assumed that the mobility was a constant. In reality, the carriermobility is dependent on the transverse and longitudinal fields �T and �L . Thus,

and69779_ch07.qxd 2/10/04 10:50 AM Page 417

Page 46: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

418 PART 3 Field-Effect Transistors

the electrical characteristics of FETs will depend on the strengths of thesechannel fields. For example, for large longitudinal field �L , the carrier velocitiessaturate, which limits the current actually obtainable to something lower thanpredicted by the simple model. At low longitudinal fields, the mobility is inde-pendent of �L but it does depend on �T . We will consider the effects of these twofields separately.

When the longitudinal field (along the channel) is small enough that thevelocity is proportional to �L , the carriers have what is called their low-fieldmobility, µlf. The value of this low-field mobility, however, is influenced by thetransverse field (across the channel) �T .

We first consider the effects of �T on the low-field mobility, and then exam-ine how that affects the electrical characteristics of an FET. In the next section,we repeat this to account for the effects of �L .

Effect of the Transverse Field �T on the Low-Field Mobility In this section,we assume that the longitudinal field is low enough that the carrier velocity issmall compared with the saturation velocity for electrons moving along the chan-nel. Thus, the electrons have their low-field mobility µlf. The transverse field �T ,however, influences the value of the low-field mobility, [2] which earlier we tookto be constant (µ = µlf). Let us examine the origin of this effect.

In addition to the scattering mechanisms in bulk semiconductors, e.g., latticeand impurity scattering, the electron in the channel of a FET is additionally scat-tered by collisions with the walls of the channel, as shown in Figure 7.24a. Thisreduces the mean free time between collisions t̄ , and thus µ, from the bulk val-ues. As electrons travel from source to drain, they are restricted to the channelregion by the potential barrier at the Si/SiO2 interface and the barrier in EC inthe Si, Figure 7.24b. Note that most of the electrons in the channel are near thebottom of the potential well formed by these barriers, where the channel isextremely narrow. In practical MOSFETs, this additional scattering mechanismreduces the low-field mobility µlf by a factor of about 2 to 3 from the bulk value.

Let us examine this effect more analytically. We showed in Chapter 3 that inbulk Si the mean free time between collisions for electrons was on the order of2 × 10−13 s. The mean free path then is approximately

l̄ ≈ v̄t̄

where v̄ is the average thermal speed. At room temperature, this speed is on theorder of 107 cm/s = 105 m/s. Thus for bulk Si, the mean free path is aboutl̄ ≈ 2 × 10−13 × 105 = 2 × 10−8 m = 20 nm, and is independent of direction.

In a MOSFET, the mean free path l̄ and the mean free time between colli-sions t̄ for electrons traveling along the channel (in the y and z directions with nox-directed or transverse velocity) should be about the same as for bulk Si. Forelectrons with a vx component, however, there is the additional scattering fromcollisions with the channel walls just discussed. This additional scattering re-duces t̄ and the mobility µ, as seen in the following example.

and69779_ch07.qxd 2/10/04 10:50 AM Page 418

Page 47: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 419

Figure 7.24 The effect of the transverse electric field on the mobility. (a) Theelectrons in the channel collide with the “walls” of the channel. (b) The energyband diagram shows that the walls are potential barriers at the oxide interface andthe barrier of the depletion region in the semiconductor is sloped.

n�n�

p type

(a)

�T �L

(b)

�TEC

Ei

EV

EfElectron scattersoff these barriers

E

x

EXAMPLE 7.5

Estimate the time t̄x between collisions for a channel electron traveling in the x direc-tion, perpendicular to the gate. Compare this with the mean free time t̄ of an electronin bulk silicon.

■ SolutionConsider an electron with energy 3

2 kT above the channel floor, and suppose the trans-verse field is 105 V/cm = 107 V/m and assumed constant with x . Consider the electronto have just made a collision at the Si/SiO2 interface at t = 0, where its kinetic energyis 3

2 kT = m∗v2max/2. This is its maximum velocity because, as the electron goes across

the channel in Figure 7.25, its total energy is constant but the potential energy isincreasing so the kinetic energy (and thus the electron velocity) is decreasing. Theforce on the electron is F = −q�T = m∗dv/dt and tends to decelerate it.

We can write

−q�T

t̄x∫0

dt = m∗0∫

vmax

dv

and69779_ch07.qxd 2/10/04 10:50 AM Page 419

Page 48: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

420 PART 3 Field-Effect Transistors

and

t̄x = m∗vmax

q�T

But since

m∗v2max

2= 3

2kT

we have for vmax:

vmax =√

3kT

m∗

Thus,

t̄x = m∗

q�T

√3kT

m∗ =√

3m∗kT

q�T

Expressing kT in eV gives

t̄x = 1

�T

√3m∗kT (eV)

q

Figure 7.25 Geometry for Example 7.5. We consider only the transversecomponent of the electron’s motion.

�T

x

E

�T

xDS

yz

Poly Si gate

Gate oxide

Channel

Substrate

and69779_ch07.qxd 2/10/04 10:50 AM Page 420

Page 49: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 421

EXAMPLE 7.6

Letting m∗ be the conductivity effective mass, m∗ = 0.26m0, we have

t̄x = 1

107

√3 × 0.26 × 9.11 × 10−31× 0.026

1.6 × 10−19 = 0.34 × 10−13 s

which is approximately a factor of 6 smaller than the value of t̄ in bulk Si. As a re-sult, sidewall scattering is the predominant scattering mechanism for the x-directedelectrons.

For Example 7.5, find the distance l̄x between electron collisions.

■ SolutionFor constant �T , EK (eV) = �T l̄x

l̄x = EK (eV)

�T=

32 × 0.26

107 = 3.9 nm

This is appreciably less than the 20 nm for the mean free path l̄ in bulk silicon.

Note that electrons near the bottom of the channel have smaller kineticenergies and that the transverse field is higher there, reducing their time betweencollisions even further. Since electrons in the channel have a range of vx compo-nents, however, some average t̄x must be used, and it must also be averaged withthe mean free times in the y and z directions to obtain an overall t̄ . The point is,t̄ and µ are reduced from their bulk values.

The electron mean free path and thus t̄ are therefore dependent on �T , whichcan be seen another way in Figure 7.26. There we have plotted part of the energy

Figure 7.26 With increasedband bending, the transversefield �T increases. This inturn reduces l̄, t̄, and µlf.

E

x

EC2

EC1

dEC�T � dxq

1

and69779_ch07.qxd 2/10/04 10:50 AM Page 421

Page 50: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

band diagram in the region of the channel. The oxide interface is on the left, andtwo possible conduction band edges are shown on the right. The steeper theslope, the higher the transverse electric field and thus the smaller the mean freetime and the mobility.

The value of �T in the channel depends on the slope of the conduction bandedge. This is a function of two things. First, there is the charge per unit area, QB ,in the Si depletion region adjacent to the channel. In an n-channel device, theseare the fixed, negatively charged ionized acceptors in the p-type substrate, as dis-cussed in the Supplement to Part 3. Second, there is the mobile charge in thechannel, Qch. In an NFET the channel charges are electrons, which tend to raisethe potential energy of the channel, affecting the slope. Therefore, the transversefield strength varies with doping, bias conditions, and depth in the channel.

The effect of the transverse field on the low-field mobility is discussedfurther in the Supplement to Part 3. However, experimentally the low-fieldmobility can be expressed as

µlf = µ0

1 + θ(VGS − VT − Vch)(7.44)

where µ0 is the channel mobility at the source (Vch = 0) at threshold (VGS = VT ).Here the quantity θ is a measured empirical parameter, on the order of 0.03 to0.2 V−1, and depends on the processing parameters, including the substrate dop-ing, substrate bias, and oxide thickness.

An experimental plot [3] of µlf versus (VGS − VT − Vch) is shown in Fig-ure 7.27. We see there that µlf varies about 30 percent over about a 2-V variationin gate voltage.

422 PART 3 Field-Effect Transistors

Figure 7.27 Variation of the low-field mobilityas a function of VGS − VT − Vch for an n-channelMOSFET. The low-field mobility can beexpressed as µlf = µ0[1 − θ (VGS − VT − Vch)].

µ0

300

350

400

450

500

0.0 1.0 2.0 3.0VGS � VT � Vch (V)

Low

-fie

ld m

obili

ty µ

lf (

cm2 /V

• s)

and69779_ch07.qxd 2/10/04 10:50 AM Page 422

Page 51: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 423

EXAMPLE 7.7

We saw earlier that the low-field mobility in the channel, µlf, increases fromsource to drain. It can be seen in the figure that µlf decreases approximatelylinearly with (VGS − VT − Vch):

µlf = µ0[1 − θ(VGS − VT − Vch)]

where µ0 is the zero-voltage extrapolation and θ the negative of the slope. Notethat the maximum mobility is less than 500 cm2/V · s, considerably less than thebulk value of about 1000 (Figure 3.4).

Since θ(VG − VT − Vch) is small compared with unity, and since for x 1,,1 − x ≈ 1/(1 + x), µlf can be expressed in the more customary form of Equa-tion (7.44).

Find the value for θ for the device of Figure 7.27.

■ SolutionSince µlf = µ0[1 − θ(VGS − VT − Vch)], we can find a formula for θ by taking thederivative of this expression. Using points on the graph gives

θ =−d

µlf

µ0

d(VGS − VT − Vch)=− 1

µ0

dµlf

d(VGS − VT − Vch)=− 1

480

(355 − 480)

(2 − 0)= 0.13 V−1

Effect of �T on the ID-VDS Characteristics Now that we have considered theeffect of �T on µlf, the next step is to see how that affects the ID-VDS character-istics compared with the constant-mobility model. We correct Equation (7.17) toinclude the variation of the mobility with Vch [Equation (7.44)]. The expressionbecomes

ID

L∫0

dy = WC ′oxµ0

VDS∫0

VGS − VT − Vch

1 + θ(VGS − VT − Vch)dVch (7.45)

which yields

ID = WC ′oxµ0

θ2L

{θVDS + ln

[1 + θ(VGS − VT − VDS)

1 + θ(VGS − VT )

]}(7.46)

Equation (7.46) is, however, somewhat unwieldy and is not amenable tophysical interpretation. Consequently, Equation (7.44) is normally approxi-mated as

µlf = µ0

1 + θ(VGS − VT )(7.47)

In this case the dependence on Vch has been conveniently removed, sothat µ = µlf can be moved back outside the integral of Equation (7.16) with

and69779_ch07.qxd 2/10/04 10:50 AM Page 423

Page 52: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

424 PART 3 Field-Effect Transistors

EXAMPLE 7.8

the result

ID = WC ′oxµ0

L[1 + θ(VGS − VT )]

(VGS − VT − VDS

2

)VDS

= WC ′oxµlf

L

(VGS − VT − VDS

2

)VDS VDS ≤ VDSsat (7.48)

IDsat = WC ′oxµlf

L

(VGS − VT − VDSsat

2

)VDSsat VDS ≥ VDSsat (7.49)

These equations are similar to Equations (7.24) and (7.25) with constant µreplaced by µlf. The difference is that here the mobility is a function of VGS .

Compare the ID-VDS characteristics for a MOSFET using the constant mobilitymodel, and then taking the transverse field into account. Let W/L = 5, θ = 0.13 V−1,tox = 5 nm, VT = 1 V and µ0 = 480 cm2/V · s.

■ SolutionWe use Equations (7.48) and (7.49) where µlf = µ0 in the constant mobility modeland µlf = µ0/[1 + θ(VGS − VT )] to include the effect of �T on µlf.

The oxide capacitance per unit area is

C ′ox = εox

tox= 3.9(8.85 × 10−12)

5 × 10−9= 6.9 × 10−3 F/m2 = 6.9 × 10−7 F/cm2

The low-field mobility depends on VGS − VT . For VGS − VT = 0 V,

µlf = µ0

1 + 0= µ0 = 480 cm2/V · s

For VGS − VT = 1 V,

µlf = µ0

1 + θ(VGS − VT )= 480

1 + (0.13)(1)= 425 cm2/V · s

For VGS − VT = 2 V,

µlf = µ0

1 + θ(VGS − VT )= 480

1 + (0.13)(2)= 380 cm2/V · s

For VGS − VT = 3 V,

µlf = µ0

1 + θ(VGS − VT )= 480

1 + (0.13)(3)= 345 cm2/V · s

For VGS − VT = 4 V,

µlf = µ0

1 + (0.13)(4)= 316 cm2/V · s

Figure 7.28 compares the constant mobility curves with the curves obtainedby considering the effect of the transverse field. Notice that the drain currents are

and69779_ch07.qxd 2/10/04 10:50 AM Page 424

Page 53: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

noticeably smaller when the transverse field is accounted for. Note, however, thatneglecting the effect of Vch, i.e., using Equation (7.47) instead of (7.44), overes-timates the effect of VGS on the low-field mobility.

Effect of the Longitudinal Field �L on Channel Mobility We have seen thatthe transverse field has an effect on the mobility and thus affects the values of thesaturation current for a given gate voltage. In this section we examine the effectof the longitudinal field �L on the mobility and thus on the ID-VDS curves.

We saw in Chapter 3 that in semiconductors, carrier velocities increase withincreasing electric field and eventually saturate. This velocity saturation effectcan be significant for carriers in the channel of a FET. In modern devices, thegate lengths are very small (a fraction of a micrometer), resulting in very highfields over a significant fraction of the channel length.

For many semiconductors, including Si, the carrier velocity in the channel ofa FET can be empirically expressed as

|v| = µlf|�L |1 + µlf|�L |

vsat

(7.50)

CHAPTER 7 The MOSFET 425

Figure 7.28 Comparison of ID-VDS characteristics com-puted by using the constant mobility model (θ = 0, dashedlines) and taking into account the effect of the transversefield (solid line) for θ = 0.13 V−1. The transverse field tendsto reduce the currents.

14

I D (

mA

)

12

10

8

6

4

2

00 1 2 3 4 5

Accounting fortransverse fieldeffect on µ

Constant µ

VGS � VT � 2 V

VDS (V)

VGS � VT � 4 V

VGS � VT � 1 V

VGS � VT � 3 V

and69779_ch07.qxd 2/10/04 10:50 AM Page 425

Page 54: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

where µlf is the low-field mobility (channel carrier mobility at low �L ) and vsat

is the carrier saturation velocity in the channel. Equation (7.50) is used for bothelectrons in Si n-channel FETs and for holes in p-channel devices.

Since we know that

|v| = µ|�L | (7.51)

the mobility can be expressed as

µ = µlf

1 + µlf|�L |vsat

(7.52)

From Equation (7.52) we see that with increasing field |�L | along the chan-nel, µ decreases. As we saw in Chapter 3, this is a result of the reduction in themean free time between collisions due to optical phonon scattering. Figure 7.29shows experimental data of electron mobility as a function of �L in an n-channelMOSFET. The data are matched to Equations (7.51) and (7.52) (solid lines).From the figure, we see that the saturation velocity is vsat ≈ 4 × 106 cm/s for thisdevice. Although vsat depends somewhat on µlf—which depends on temperature,transverse field, and substrate doping concentration—for carriers in the channelof a Si MOSFET, we will use vsat = 4 × 106 cm/s for both electrons and holes,

426 PART 3 Field-Effect Transistors

Figure 7.29 Channel electron mobility and velocity (v = µ�) as afunction of lateral field for VGS = 1.42 V.

10

100

1000 107

106

105

104

101 102 103 104 105 106

Vel

ocity

(cm

/s)

Mob

ility

(cm

2 /V •

s)

Longitudinal field (V/cm)

and69779_ch07.qxd 2/10/04 10:50 AM Page 426

Page 55: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 427

unless otherwise indicated. [3] These values are somewhat smaller than the107 cm/s found for bulk Si.

Effect of �L on the ID-VDS Characteristics of MOSFETs We have seen thatµ varies with longitudinal electric field, so now we will revise the simple long-channel model to account for this influence of the carrier mobility on the ID ver-sus VDS characteristics. If we substitute Equation (7.52) into Equation (III.7), wecan write

ID dy = −WQchµlf dVch

1 + µlf|�L |vsat

(7.53)

The electric field can be expressed as |�L | = dVch/dy , so, substituting into thedenominator, we have

ID dy = −WQchµlf dVch

1 + µlf

vsat

dVch

dy

(7.54)

Multiplying both sides of Equation (7.54) by the denominator and rearranginggives

ID dy + IDµlf

vsatdVch = −WQchµlf dVch (7.55)

Now we can integrate both sides. For the sublinear region, we write

ID

L∫0

dy + ID

VDS∫0

µlf

vsatdVch = −W

VDS∫0

Qchµlf dVch VDS ≤ VDSsat (7.56)

and for the saturation region we have

IDsat

L∫0

dy + ID

VDSsat∫0

µlf

vsatdVch = −W

VDSsat∫0

Qchµlf dVch VDS ≥ VDSsat (7.57)

Integrating, the results are

ID = −Wµlf

∫ VDS

0Qch dVch

L + µlfVDS

vsat

0 ≤ VDS ≤ VDSsat (7.58)

IDsat = −Wµlf

∫ VDSsat

0Qch dVch

L + µlfVDSsat

vsat

VDS ≥ VDSsat (7.59)

and69779_ch07.qxd 2/10/04 10:50 AM Page 427

Page 56: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

428 PART 3 Field-Effect Transistors

Using the same model for the channel charge Qch as in the long-channel model[Equation (7.14 )], we obtain [4]

ID = WC ′oxµlf

L + µlfVDS

vsat

[(VGS − VT )VDS − V 2

DS

2

]VDS ≤ VDSsat (7.60)

IDsat = WC ′oxµlf

L + µlfVDSsat

vsat

[(VGS − VT )VDSsat − V 2

DSsat

2

]VDS ≥ VDSsat (7.61)

These are similar to the expressions from the previous model of Equations (7.48)and (7.49), except that L is replaced by L + µlfVDS/vsat for VDS ≤ VDSsat and byL + µlfVDSsat/vsat for VDS ≥ VDSsat . In effect, the inclusion of the longitudinalfield �L on the mobility causes the channel length to appear longer by theamount µlfVDS/vsat (or µlfVDSsat/vsat) than for the simpler model. To reflect thiseffect, Equations (7.58) and (7.59) are normally written

ID =−Wµlf

∫ VDS

0Qch dVch

L

(1 + µlfVDS

Lvsat

) VDS ≤ VDSsat (7.62)

IDsat =−Wµlf

∫ VDSsat

0Qch dVch

L

(1 + µlfVDSsat

Lvsat

) VDS ≥ VDSsat (7.63)

As we shall see shortly, VDSsat = (VGS − VT ), unlike the case for the simplelong-channel model.9

The quantity in the parentheses in the denominator of Equation (7.63), then,represents the influence of the velocity saturation effect on the ID-VDS charac-teristics, [4] and

ID = ID(no velocity saturation model)

1 + µlfVDS

Lvsat

VDS ≤ VDSsat (7.64)

IDsat = IDsat(no velocity saturation model)

1 + µlfVDSsat

Lvsat

VDS ≥ VDSsat (7.65)

9The effect of vsat is often considered to be a short-channel effect since its influence on ID increaseswith decreasing L. Here, however, since it is important for L in the low-micrometer range, we will notconsider it to be a short-(submicrometer) channel effect. The true short-channel effects are discussed inChapter 8.

and69779_ch07.qxd 2/10/04 10:50 AM Page 428

Page 57: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 429

where IDsat, without accounting for velocity saturation, is given by Equa-tion (7.49), but VDSsat = (VGS − VT ).

From the above equation, it is seen that the reduction of current from thatgiven by the long-channel model is greater as the channel lengths get shorter.This results from �L being large, causing the saturation velocity effects to beimportant over a larger fraction of the channel.

Since we will present some numerical illustrations of n-channel and p-channel MOSFETs, we present in Table 7.1 values for some parameters for roomtemperature operation of typical MOSFETs. We will also use these values in thefollowing example.

Find the value of L for an n-channel Si MOSFET for which the velocity saturationeffect reduces the subsaturation current by a factor of 2 for a drain-source voltageVDS = 2 V.

■ SolutionWe recognize from Equation (7.64) that we want to set(

1 + µlfVDS

Lvsat

)= 2

From Table 7.1, for µlf = 500 cm2/V · s and vsat = 4 × 106 cm/s, solving for L , wefind a channel length of

L = µlfVDS

vsat= (500 cm2/V · s) × (2 V)

4 × 106 cm/s= 250 × 10−6 cm = 2.5 µm

This channel length would be typical of the technology in the mid-1980s. Now, let ussuppose the (physical) channel length is made even smaller than this value. TakingL = 0.18 µm, a typical value in the late 1990s, we find that the current obtained usingthe long-channel model is off by a factor of

ID (long-channel model)

ID= 1 + µlfVDS

Lvsat= 1 + (500 cm2/V · s)× (2 V)

(18 × 10−6 cm)× (4 × 106 cm/s)= 13.9

Similarly, for the more recent 0.13 µm technology, the ratio is 19. Clearly, the effectof velocity saturation must be taken into account in realistic FETs.

Table 7.1 Some parameters for typical Si MOSFETs

Parameter n-channel MOSFET p-channel MOSFET

µlf (low-field mobility) 500 cm2/V · s 200 cm2/V · svsat (carrier saturation velocity) 4 × 106 cm/s 4 × 106 cm/stox (gate oxide thickness) 4 nm 4 nm

C ′ox = εox

tox(oxide 8.6 × 10−7 F/cm2 8.6 × 10−7 F/cm2

capacitance per unit area)

EXAMPLE 7.9

and69779_ch07.qxd 2/10/04 10:50 AM Page 429

Page 58: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

Continuing the derivation of the ID-VDS characteristics of the FET, werewrite Equations (7.64) and (7.65) in the standard form:

ID =WC ′

oxµlf

(VGS − VT − VDS

2

)VDS

L

(1 + µlfVDS

Lvsat

) VDS ≤ VDSsat (7.66)

IDsat =WC ′

oxµlf

(VGS − VT − VDSsat

2

)VDSsat

L

(1 + µlfVDSsat

Lvsat

) VDS ≥ VDSsat (7.67)

We need to find an expression for VDSsat. We can use the same approach wetook in Section 7.3.1. By setting ∂ ID/∂VDS = 0 in Equation (7.66):

VDSsat = vsat

µlfL

[(1 + 2µlf(VGS − VT )

vsatL

)1/2

− 1

](7.68)

Substituting (7.68) into (7.67) and solving for IDsat, we obtain

IDsat = WC ′oxvsat(VGS − VT − VDSsat) (7.69)

Let us compare the ID = VDS characteristics as obtained from the simplemodel and the model that includes velocity saturation. For this example wechoose the parameters of Table 7.1 with VGS − VT = 2.6 V and a channel lengthof L = 0.5 µm. First, we plot the results from the long-channel model usingconstant mobility in Figure 7.30 (dashed line).

Before we continue, we notice that both the PFET and the NFET have thesame result for the earlier model. Since the low-field mobilities for electrons andholes are different (µlfn ≈ 2.5µlfp), the currents in the two FETs would be signif-icantly different if the devices were otherwise identical. In many circuits usingboth NFETs and PFETs, it is desirable to have equal saturation currents of bothdevices. To achieve this for long-channel devices, the W/L ratios of PFETs aremade 2.5 times that of NFETs. This is what has been done here. We chooseW = 10 µm and 25 µm respectively for the NFET and the PFET. This willequate the characteristics for the two devices as predicted from the long-channelmodel, i.e., Equation (7.48).

The characteristics from the model that considers velocity saturation are alsoshown in the figure. From Equations (7.66) and (7.67), it is evident that even withthe width-to-length ratio corrected as above, the currents in the velocity saturationmodel are not the same for the NFET and PFET. We can see from Figure 7.30 thatat small VDS, both models predict the same slope. In this region, the longitudinal

430 PART 3 Field-Effect Transistors

and69779_ch07.qxd 2/10/04 10:50 AM Page 430

Page 59: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

field is not yet large enough for velocity saturation effects to be important. How-ever, the inclusion of velocity saturation effects causes the saturation current todecrease and the voltage at which current saturates (VDSsat) to decrease also.Since µlf is larger for the NFET than for the PFET, IDsat and VDSsat are smaller forthe NFET. As we will see in Chapter 8, this means that the velocity saturationeffect reduces the performance of the field-effect transistors.

We indicated earlier that, when velocity saturation is accounted for, the satu-ration voltage is no longer equal to VGS − VT . As the channel length gets shorter,from Equation (7.68) the saturation voltage VDSsat also decreases. For example,Figure 7.31 shows that for a channel length of L = 2 µm and (VGS − VT )=2.6 V, the saturation voltages are VDSsat = 1.7 and 2.1 V respectively for theNFET and the PFET. For a shorter channel device, e.g., L = 0.1 µm, these val-ues reduce to 0.57 and 0.84 V respectively. These values are appreciably smallerthan the VDSsat = (VGS − VT ) = 2.6 V we would get from the constant mobilitylong-channel model. Again, this is because the simple long-channel model doesnot consider velocity saturation.

While the saturation voltage VDSsat depends on the channel length L (but notthe channel width W), the saturation current IDsat depends on both W and L.Figure 7.32 shows IDsat as a function of L for a constant W/L ratio of 10. The fig-ure shows results for both n- and p-channel MOSFETs. As expected, for a givenW/L ratio, IDsat decreases with decreasing channel length, again because of ve-locity saturation.

CHAPTER 7 The MOSFET 431

Figure 7.30 The calculated I-VDS characteristics for the simple modeland for NMOS and PMOS with carrier velocity saturation accounted for.The case of VGS − VT = 2.6 V and L = 0.5 µm is considered. The W/Lratios of the NFET and PFET have been scaled to produce the sameI-VDS curve as predicted from the simple model. The differing mobilitiescause the scaled devices to be different.

00 1 2 3 4

0.5

1.0

1.5

2.0

2.5

3.0

PFET (considering velocity saturation)

NFET (considering velocity saturation)

Simple model (NFET and PFET)

|I D| (m

A)

|VDS | (V)

and69779_ch07.qxd 2/10/04 10:50 AM Page 431

Page 60: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

*7.3.3 SERIES RESISTANCE

Next, we look at the resistance of a FET, which is the resistance between thesource and the drain. This includes the resistance along the channel itself, plusthe resistances between the source and drain contacts and the channel, as shownin Figure 7.33 for an n-channel MOSFET. The total resistance Rtot in a FET is

Rtot = VDS

ID= RS + Rch + RD (7.70)

where RS is the resistance from the source contact to the source end of the

432 PART 3 Field-Effect Transistors

Figure 7.32 Saturation current |IDsat| as a function of L for n-and p-channel silicon MOSFETs. Here |(VGS − VT)| = 2.6 V, thewidth-to-length ratio is W/L = 10, and Wp = 2.5 Wn.

16

14

12

10

8

6

4

|I Dsa

t| (m

A)

2

00 1 2

L (µm)3 4

NFET

PFET

5

Figure 7.31 The saturation voltage as a function of channellength for |(VGS − VT)| = 2.6 V.

NFET

PFET

3.0

2.5

2.0

1.5

1.0

|VD

Ssat

| (V)

0.5

00 1 2

L (µm)3 4 5

and69779_ch07.qxd 2/10/04 10:50 AM Page 432

Page 61: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

channel, Rch is the resistance of the channel, and RD is the resistance from thedrain end of the channel to the drain contact.

The region 0 ≤ y ≤ L can be treated as an embedded transistor with exter-nal resistances RS and RD connected in series to the source and drain contactsrespectively. The voltage between the drain and source of the “intrinsic” transis-tor is then given by the drain-source voltage less the voltage drop in the“external” resistors, VDS − [ID(RS + RD)]. At the same time, the voltage be-tween the gate and source of the intrinsic transistor is given by VGS − ID RS .Then Equation (7.66) becomes, below saturation

ID =WC ′

oxµlf

[VGS − ID(RS)− VT − VDS − ID(RS + RD)

2

][VDS − ID(RS + RD)]

L

{1 + µlf[VDS − ID(RS + RD)]

Lvsat

}

VDS ≤ VDSsat (7.71)

Because of the symmetry of the MOSFET, the series resistances are nor-mally equal, so that RS ≈ RD and Equation (7.71) becomes

ID =WC ′

oxµlf

(VGS − VT − VDS

2

)(VDS − 2ID RS)

L

[1 + µlf(VDS − 2ID RS)

Lvsat

] VDS ≤ VDSsat (7.72)

In saturation, Equation (7.67) is adapted in a similar manner to obtain

IDsat =WC ′

oxµlf

(VGS − VT − VDSsat

2

)(VDSsat − 2IDsat RS)

L

[1 + µlf(VDSsat − 2IDsat RS)

Lvsat

] VDS ≥ VDSsat (7.73)

CHAPTER 7 The MOSFET 433

Figure 7.33 Schematic of an NMOS indicatingthe channel resistance Rch, the sourceresistance RS, and the drain resistance RD.

SG

D

RS RDRchn�

p

n�

0y

L

and69779_ch07.qxd 2/10/04 10:50 AM Page 433

Page 62: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

Equations (7.72) and (7.73) can be solved for the current, algebraically oriteratively.

We can neglect the series resistances for devices in which the channel resis-tance far exceeds the series resistances, or Rch � 2RS . The series resistancedepends on the processing details as well as on the channel width W. Typical val-ues for RS and RD are about 10 to 100 �.

7.4 COMPARISON OF MODELS WITH EXPERIMENT

We have examined several long-channel models for the ID-VDS characteristics ofMOSFETs. These are the constant-mobility model, the model in which trans-verse field is included, and the model in which velocity saturation is included.We also modified these to account for series resistance. We now wish to explorethe question: How good are these models?

Let us consider an actual n-channel MOSFET designed to operate with asupply voltage of 1.8 V. The measured parameters are:

L = 0.25 µm

W = 9.9 µm

tox = 4.7 nm

µlf = 400 cm2/V · s

RS = RS = 19.9 �

VT = 0.30 V

The gate-source voltage is taken equal to the supply voltage, 1.8 V.The top line in Figure 7.34 gives the results calculated from the simple long-

channel model [Equations (7.48) and (7.49)], that is, the model that assumesconstant mobility. Since we are considering only a single gate voltage, the ap-propriate value of low-field mobility has been selected and we do not need toconsider the effect of the transverse field variation with gate voltage. Also plottedare the results obtained by using the same device parameters but considering theeffects of the longitudinal field by accounting for velocity saturation [Equa-tions (7.66) and (7.67)]. Also indicated in Figure 7.34 are the results of the modeltaking into account the source and drain series resistances (Rs and RD) in addi-tion to velocity saturation. [5] The saturation velocity was not measured for thisdevice but was assumed to be vsat = 7 × 106 cm/s. Finally, the actual measureddata are plotted.

It can be seen from Figure 7.34 that the current predicted by the velocity sat-uration model is appreciably smaller than that predicted by the constant mobilitylong-channel model, and is in reasonable agreement with experiment. Taking

434 PART 3 Field-Effect Transistors

and69779_ch07.qxd 2/10/04 10:50 AM Page 434

Page 63: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

drain and source resistance into account results in quite good agreement betweentheory and experiment.

7.5 SUMMARYIn this chapter, we discussed the physical principles of operation of the Si-basedMOSFET. These transistors have three terminals. The voltage on the gate elec-trode is used to control the resistance along the channel, between the drain andthe source. These are called field-effect transistors because the gate controls thechannel conductance via an electric field. This field appears across the oxide.Note that only displacement current flows into the gate, because the oxide is aninsulator. The voltage applied to the gate creates the electric field that in turnbends the bands in the substrate, inverting the channel (enhancement MOSFETs)or uninverting it (depletion MOSFETs).

We began by considering a simple (long-channel) model for the current-voltage characteristics in a MOSFET, assuming constant channel mobility. Wesaw that when the gate voltage is greater than some threshold, current can flowin the channel. The greater the voltage across the channel (between the drain andthe source), the more current should flow. We found that this is true, but only upto a point. At some VDS , the longitudinal field �L is large enough that it sweepsthe carriers along the channel from source to drain as fast as they can be suppliedby the source, and the current saturates. The saturation voltage VDSsat and the sat-uration current IDsat both depend on the gate voltage.

CHAPTER 7 The MOSFET 435

Figure 7.34 Comparison of the simple long-channel model, themodel including velocity saturation, the model including bothvelocity saturation and the series resistances RS and RD, and theactual measured data. For this NFET device, L = 0.25 µm,W = 9.9 µm, and VT = 0.3 V. The gate-source voltage is 1.8 V.

Data

14

12

10

8

6

4

2

00.0 0.5 1.0

VDS (V)

I D (

mA

)

1.5

Including velocity saturationand series resistances

Including velocity saturation

Simple long channel

and69779_ch07.qxd 2/10/04 10:50 AM Page 435

Page 64: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

The equations for the simple long-channel model are:

The mobility is taken to be constant for all bias conditions, and is equal tothe low-field mobility in the channel. This mobility is considerably less than thebulk value.

Next, we considered the effects of channel length modulation, and saw thatunder large drain voltages the voltage in the channel reaches saturation some-where before the drain, producing a nonzero slope in the saturation characteris-tics. That slope was modeled empirically by

where the channel is effectively shortened by �L .Then we considered the effects of the transverse field. The channel is quite

thin, and carriers will reflect off the potential barriers at the interface with theoxide and the band bending in the substrate. As a result, carrier velocities are re-duced even more than accounted for earlier, with the result that the currentsare smaller as well. The carrier low-field mobility can be modeled in terms of thegate voltage:

where the parameters µ0 (the low-field mobility at the source end at threshold)and θ are determined experimentally. The influence on the ID-VDS characteristics

EFFECT OF TRANSVERSE FIELD (EMPIRICAL)

µlf = µ0

1 + θ(VGS − VT )(7.47)

CHANNEL MODULATION EFFECT (SATURATION ONLY)

ID ≈ IDsat(1 + λ(VDS − VDSsat)) (7.43)

with

�L

L= λ(VDS − VDSsat) (7.42)

SIMPLE LONG-CHANNEL MODEL

ID ≈ 0 VGS < VT (7.9)

ID = WC ′oxµ

L

[(VGS − VT )VDS − V 2

DS

2

]VDS ≤ VDSsat, VGS ≥ VT

(7.24)

IDsat = WC ′oxµ

L

[(VGS − VT − VDSsat

2

)VDSsat

]VDS ≥ VDSsat, VGS ≥ VT

(7.25))

VDSsat = VGS − VT (7.26)

436 PART 3 Field-Effect Transistors

and69779_ch07.qxd 2/10/04 10:50 AM Page 436

Page 65: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

is to replace constant mobility µ in the simple long-channel model by the low-field mobility µlf, which is dependent on gate voltage.

These simple long-channel models ignore velocity saturation (i.e., it is as-sumed that the carriers could attain an arbitrary high velocity such that theQchv product is constant). However, velocity saturation does occur in real de-vices. The mobility is reduced by the high longitudinal field that results from theshort channels. When we consider the reduced mobility, we saw that in a FET,the current could be expressed as

The drain-source voltage at which the current saturates is

VDSsat = vsat

µlfL

[(1 + 2µlf(VGS − VT )

vsatL

)1/2

− 1

](7.68)

The saturation current can be expressed in terms of VDSsat

IDsat = C ′oxWvsat(VGS − VT − VDSsat) (7.69)

It is found that the model involving velocity saturation effects agreesreasonably well with experiment.

Finally, we considered the effect of the source and drain series resistances onthe ID-VDS characteristics. The results are, including velocity saturation andassuming RS = RD ,

VELOCITY SATURATION AND SERIES RESISTANCE

ID =WC ′

oxµlf

(VGS − VT − VDS

2

)(VDS − 2ID RS)

L

[1 + µlf(VDS − 2ID RS)

Lvsat

] VDS ≤ VDSsat

(7.72)

IDsat =WC ′

oxµlf

(VGS − VT − VDSsat

2

)(VDSsat − 2IDsat RS)

L

[1 + µlf(VDSsat − 2IDsat RS)

Lvsat

] VDS ≥ VDSsat

(7.73)

LONG-CHANNEL MODEL WITH VELOCITY SATURATION

ID = ID (neglecting velocity saturation)(1 + µlfVDS

Lvsat

) VDS ≤ VDSsat (7.64)

IDsat = IDsat (neglecting velocity saturation)(1 + µlfVDSsat

Lvsat

) VDS ≥ VDSsat (7.65)

CHAPTER 7 The MOSFET 437

and69779_ch07.qxd 2/10/04 10:50 AM Page 437

Page 66: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

In all of these models, one can include transverse field effects if the value ofµlf is varied with VGS according to Equation (7.47), and one can account forchannel length modulation by allowing IDsat to increase with VDS according toEquation (7.41). In the next chapter, we will explore the MOSFET further. We’llsee that as devices become progressively smaller, there are more physical effectsthat come into play and change the ID-VDS characteristics. In addition, we haverestricted ourselves to static operation up to now; in Chapter 8, we will look atdynamic operation as well.

7.6 READING LISTItems 1, 2, 4, 8 to 12, 17 to 19, and 27 to 30 in Appendix G are recommended.

7.7 REFERENCES1. C. Y. Sah, “Evolution of the MOS transistor-from concept to VLSI,” Proc.

IEEE, 76, pp. 1280–1326, 1988.2. G. Baccarani and M. R. Wordman, “Transconductance degradation in thin-

oxide MOSFETs,” IEEE Trans. Electron Devices, ED-30, pp. 1295–1304,1983.

3. Dennis Hoyniak, Edward Nowak, and Richard L. Anderson, “Channelelectron mobility dependence on lateral electric field in field-effecttransistors,” J. Appl. Phys., 87, pp. 876–881, 2000.

4. B. T. Murphy, “Unified field-effect transistor theory including velocitysaturation,” IEEE J. Solid-State Circuits, SC-15, pp. 325–327, 1980.

5. Dac C. Pham, “Selective device-temperature scaling for optimum power-delay product in MOSFET circuit design,” dissertation, University ofVermont, 1998. Unpublished.

7.8 REVIEW QUESTIONS1. Explain why virtually no current flows into the gate of a MOSFET. If no

current flows into this electrode, how can a signal on the gate have aneffect on the operation of the rest of the transistor?

2. Explain in your own words why the current (rate of flow) between sourceand drain saturates as the potential difference between the drain and thesource increases.

3. Summarize in words the steps used to derive the ID-VDS characteristics ofa FET using the long-channel model as an example.

4. Explain in words how applying a voltage to the gate can, in effect, changethe material at the surface of the channel from p type to n type.

5. Is the device in Figure 7.5 an enhancement or a depletion FET?

438 PART 3 Field-Effect Transistors

and69779_ch07.qxd 2/10/04 10:50 AM Page 438

Page 67: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

7.9 PROBLEMS7.1 In any circuit, the transistor operation can be understood by examining

the superposition of the transistor characteristics and the conditionsimposed by the circuit (the load line). What differentiates, then, a digitaltransistor circuit from an analog one?

7.2 In modern FETs, the gate is usually degenerately doped silicon, whoseFermi level is essentially at the bottom of the conduction band (for anNFET) or at the top of the valence band (for a PFET).a. Draw an energy band diagram similar to Figure 7.2c, except making

the transistor a PFET.b. Suppose the device is an NFET, but the gate is made of metal (as was

done in the early days). Draw the energy band diagram. Take�M < �S .

7.3 For the transistor of Figure P7.1, by how much should the gate voltagebe changed to produce inversion? Threshold? Assume half the appliedvoltage appears across the oxide and half across the semiconductor. Ifthe device in the figure is at equilibrium, is this an enhancement or adepletion FET?

CHAPTER 7 The MOSFET 439

Figure P7.1

EVG

EC0.3 eV

EiEfEV

ECG � EfG

0.1 eV

7.4 For each of the transistors of Figure 7.10, a. What is the polarity of the threshold voltage VT ?b. What is the polarity of VDS that should be used?c. When VGS = 0 (equilibrium), is the transistor on or off?d. Is the current ID carried by electrons or holes?e. For VGS > VT , is the current ID carried primarily by drift or

diffusion?7.5 An NFET is fabricated with a degenerately doped n-type gate. What

doping concentration in the p-type substrate is needed for there to be achannel even with no voltage applied? Assume half the built-in voltage is

and69779_ch07.qxd 2/10/04 10:50 AM Page 439

Page 68: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

dropped across the oxide and half across the silicon. Let the definition of“a channel exists” be that the surface of the silicon is inverted such thatthe electron concentration at the Si/SiO2 interface is equal to the holeconcentration in the bulk is p type. Is the doping you found a minimumor a maximum required to create a depletion-type device?

7.6 Consider two silicon MOSFETs, one n channel and the other p channel,with substrate dopings of 1016 cm−3. The NMOS has an n+ gate and thePMOS has a p+ gate, both doped to 1019 cm−3. Find the built-in voltageVbi for each, and draw the energy band diagram. Neglect the band-gapnarrowing effects discussed in Chapter 2.

7.7 In the MOS process, structures like the gate of a transistor are used tomake capacitors as well. If the oxide thickness is 4 nm, what area isneeded to achieve a capacitance of 1 pF? The permittivity of silicondiode is 3.9ε0.

7.8 In MOS processing, the W/L ratio is often intentionally made differentfrom transistor to transistor. Plot the ID-VDS characteristics for the deviceof Figure 7.19 with the W/L ratio changed to 10 instead of 5. Comparethis with the results for W/L = 5.

7.9 Explain why the electron affinity model can be used to goodapproximation to determine the band lineup normal to the gate in aMOSFET. That is, why is the tunneling-induced dipole effect negligible?

7.10 Plot the ID-VDS characteristics for an NFET, using the long-channelmodel, for which W = 10 µm, L = 1 µm, tox = 4 nm, VT = 0.25 V,and the channel length modulation parameter is λ = 0.04 V−1. UseVGS = 1 V, 2 V, 3 V, and 4 V. Find the output conductance in saturationfor VGS = 3 V.

7.11 An enhancement NFET with the characteristics in Table 7.1 has athreshold voltage of VT = 1 V, a channel length of 1 µm, and a width of5 µm. Considering velocity saturation, with vsat = 5 × 106 cm/s, find thecurrent ID fora. VGS = 0 V, VDS = 1 Vb. VGS = 2 V, VDS = 1 Vc. VGS = 3 V, VDS = 1 V

7.12 An NFET is made with tox = 4 nm, L = 1 µm, W = 10 µm, VT = 1 V,and µlf = 500 cm2/V · s.

If the simple model is used, what should the width of the PFET be toget the same saturation current (apart from polarity). Let the low-fieldmobility for holes be 200 cm2/V · s.

7.13 An NFET and a PFET are made on the same chip, using the sameprocess. The NFET has C ′

ox = 8.6 × 10−7 F/cm2, tox = 4 nm,L = 0.2 µm, W = 15 µm, VT = 1.5 V, and µlf = 500 cm2/V · s. If thePFET is identical except for its mobility (200 cm2/V · s) and its width W,

440 PART 3 Field-Effect Transistors

and69779_ch07.qxd 2/10/04 10:50 AM Page 440

Page 69: Anderson - Fundamentals of Semiconductor Devices - And69779_ch07

CHAPTER 7 The MOSFET 441

a. What should W be for the PFET to make the characteristics the sameas for the NFET, as predicted by the simple model?

b. Find VDSsat and IDsat for VGS − VT = 1 V.c. If velocity saturation is considered, how different are VDSsat and IDsat

for the NFET and the PFET compared with the simple model results?Express your result as a ratio (e.g., IDsatNFET/IDsatPFET andVDSsatNFET/VDSsatPFET). Assume vsat = 4 × 106 cm/s.

7.14 A good way to check the validity of a derivation is to verify that itreduces to the expected result for a particular known case. For example,in the simple model, we neglected velocity saturation, and in the latermodel we considered it. Since the high field that causes velocitysaturation occurs in short-channel devices, we would expect that the latermodel would reduce to the simple model for long-channel devices.a. Show that in the limit of large L , VDSsat as given by Equation (7.68)

reduces to VDSsat = (VGS − VT ) as given by Equation (7.26) for thesimple (long-channel) model.

b. Show that in the limit of large L , IDsat as given by Equation (7.61)reduces to Equation (7.25) for the simple model.

You may find the following information useful:For x < 1

(1 ± x)n = 1 ± nx + n(n − 1)x2

2!± · · ·

(1 ± x)−n = 1 ∓ nx + n(n + 1)x2

2!∓ · · ·

7.15 Find an approximate closed-form expression for the drain current,accounting for series resistance and velocity saturation. That is, solvefor ID in Equation (7.72). Neglect the term in I 2

D .

and69779_ch07.qxd 2/10/04 10:50 AM Page 441