Analysis of Jitter for a Chain-of-Inverters including On ...
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Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects
M. S. Illikkal1, J N. Tripathi
2, H. Shrimali
1, R. Achar
3
1. Indian Institute of Technology Mandi, INDIA 2. STMicroelectronics, INDIA3. Carleton University, Canada
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Outline
Introduction
Power Supply Induced Jitter (PSIJ)
Semi-analytical Modeling: EMPSIJ
Chain-of-Inverters with interconnects
Results
Conclusion
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Introduction
Low power, smaller area, higher switching frequencies.
Leads to voltage fluctuations in PDNs.
IR-drop, Ldi/dt noise, LC resonance, Crosstalk, Electromagnetic
interference.
A typical Power Distribution Network (PDN)
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Jitter
Low power, smaller area, higher switching frequencies.
Can be categorized in Random Jitter (RJ) and
Deterministic Jitter (DJ).
DJ Inter-symbol Interference (ISI), Simultaneous
Switching Noise (SSN), Ground Bounce, EMI, etc.
Jitter budgets are defined to maintain timing margins.
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Power Supply Induced Jitter 5
Period Jitter: -16.1ps/6.3ps
Worst Case PVT SS-40 Worst Case PVT SS-40
Period Jitter: -91.6ps/110.9ps
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Recent Work
Slope based Approaches
J. Kim et al., IEEE EMC Symp., Aug. 2011.
J. N. Tripathi et al., EMPSIJ, T-CPMT, Oct. 2017.
Delay-based Approaches
X. J. Wang and T. Kwasniewski, TEMC, Apr.
2016.
J. N. Tripathi et al., TVLSI, Oct. 2017.
Statistical methods:
J. Kim et al., IEEE TCAS-1, Jul. 2014.
Via IBIS Models
X. Chu et al., TEMC, Nov. 2017.
Numerical Method
J. N. Tripathi and F. Canavero, IEEE MWCL,
Dec. 2017.
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EMPSIJ
Efficient Modeling of Power Supply Induced Jitter
(EMPSIJ). TCPMT, Oct. 2017.
Slope based Semi-analytical approach.
Requires only one-bit simulation to evaluate the slope
(β).
TIE for kth bit can be calculated as:
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Power Supply Noise in a CMOS Inverter
��, ��, and �� are the transfer functions
of respective paths.
���(t), �� t and ��� t are input noise
components.
�� � t and �� t are the input and
output data signals.
��� t is the total output noise.
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PSN Components and their paths in
CMOS inverter.
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PSN Components
The total output noise,
Where,
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Large Signal Analysis and Small-signal Model 10
Large signal modelInput and output waveforms
Small-signal model
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Noise Transfer Functions 11
Small-signal model in frequency domain.
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Noise Transfer Functions 12
Input noise
Output noise
Inverter with noise sources.
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Estimation of TIE and PSIJ 13
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PSN in Chain of Inverters 14
PSN Components and their paths in two cascaded inverters.
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Chain of Inverters with Interconnect 15
Chain of Inverters with On-Chip Interconnects
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Noise Transfer Functions 16
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Noise Transfer Functions 17
where,
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Results 18
Ex-1: Chain of inverters with 5 stages
Technology used BiCMOS 55nm (STMicroelectronics)
Supply voltage 1.8 V
Input data rate 2 Gbps
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Results 19
Ex-2: Delay Locked Loop
Ex-2: Tapered buffer with 5 stages
Technology used BiCMOS 55nm (STMicroelectronics)
Supply voltage 1.8 V
Input data rate 2 Gbps
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Results 20
Example Approach CPU Time Speed-up
Example-1
Conventional 8 min. 34 sec.
~123Proposed 4.17 sec.
Example-2
Conventional 12 min. 5 sec.
~133
Proposed 5.44 sec.
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Summary/Conclusion 21
Faster estimation for PSIJ is required to reduced design
cycle of SoCs.
Semi-analytical methods can be useful for the same.
Effects of off-chip and on-chip interconnects on jitter
should be studied thoroughly to avoid the
complications in meeting the specifications of overall
timing uncertainty!
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Thank You.