ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED CHARGE PUMPS … · 2017-10-27 · ABSTRACT...

ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED

CHARGE PUMPS WITH HIGH PERFORMANCE

A Thesis

Presented to

The Faculty of Graduate Studies

of

The University of Guelph

by

YOUNIS ALLASASMEH

In partial fulfilment of requirements

for the degree of

Master of Applied Science

Guelph, Ontario, Canada

c©Younis Allasasmeh, August, 2011

ABSTRACT

ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED

CHARGE PUMPS WITH HIGH PERFORMANCE

Younis Allasasmeh

University of Guelph, 2011

Advisor:

Professor Stefano Gregori

This thesis presents the design of new integrated charge pumps with high performance. An

analysis method is determined to evaluate the voltage gain,the output resistance and the conversion

efficiency parameters of integrated charge pumps. An optimization method is developed to improve

the performance through capacitor sizing based on area constraints. Several charge pumps structures

are optimized and compared including the losses due to devices parasitics. Results show that the

Dickson charge pump (voltage doubler) is the best structurefor integration. Therefore, techniques to

improve performance and conversion efficiency of integrated voltage doubler are proposed. Switch

bootstrapping technique prevents short-circuit losses, improves driving capability, and enhances the

overall efficiency. The application of charge reuse technique reduces the dynamic power losses of

integrated voltage doublers and double charge pumps. A prototype of the integrated voltage dou-

blers was fabricated in a 0.18-µm CMOS process with the proposed techniques. Measured results

have been presented, demonstrating the improvements in performance and conversion efficiency,

with a good correlation between measured and predicted results.

Acknowledgements

I would like to take this opportunity to express my sincere appreciation to my advisor

Dr. Stefano Gregori for his support and encouragement throughout my research. Without

his faith in my abilities and his consistent help, this work would not have been possible. I

would also like to thank Dr. Hussein Abdullah, who never let an opportunity pass without

lending me his sincere feedback, help, and advice.

I deeply appreciate the support from Kapik integration, andI would like to thank Kapik

team for the experience they have brought me throughout my internships. Also, I would

like to thank CMC for providing the semiconductor fabrication service that made the im-

plementation of my design possible.

Thanks to all my friends in the analog Nano-electronics group for their technical help

and feedback in the past three years. I am greatful to my relatives and friends in Jordan,

Morocco, and Guelph. Thanks for the great help and kindness.

Most of all, thanks are owed to my family for their countless care and sacrifice. To my

father, Dr. Abdelaziz Allasasmeh. To my mother, Dr. Wafa Alami. To my sisters, Alia,

Sarah, and Saja. To my love, Sara Altamimi. To them, I owe all.It was their motivation

and unconditional support that guides me throughout this long journey.

i

Contents

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2 Charge Pump Analysis 10

2.1 Method of Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Charge Pump Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Ideal Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.2 Gain with Parasitic Capacitances . . . . . . . . . . . . . . . . .. . 15

2.3 Charge Pump Output Resistance . . . . . . . . . . . . . . . . . . . . . .. 15

2.3.1 Analysis of Output Resistance with Parasitic Capacitances . . . . . 16

2.4 Power Losses in Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . .17

2.4.1 Load-Dependent Losses . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.2 Load-Independent Losses . . . . . . . . . . . . . . . . . . . . . . 18

2.5 Analysis of Single-Sided Charge Pumps . . . . . . . . . . . . . . .. . . . 19

2.5.1 Optimization of the Output Resistance . . . . . . . . . . . . .. . . 20

2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances . . . . . . 22

2.6 Analysis of Double Charge Pumps . . . . . . . . . . . . . . . . . . . . .. 25

ii

CONTENTS iii

2.6.1 Double Charge Pumps Performance with Parasitic Capacitances . . 26

2.7 Charge Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.8 Simulation Results with Charge Reuse . . . . . . . . . . . . . . . .. . . . 30

2.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3 Design 34

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 Losses and Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3.1 Load-Dependent Power Losses . . . . . . . . . . . . . . . . . . . . 37

3.3.2 Load-Independent Power Losses . . . . . . . . . . . . . . . . . . .38

3.3.3 Short-Circuit Power Losses . . . . . . . . . . . . . . . . . . . . . 39

3.4 Proposed Switch Bootstrapping Technique . . . . . . . . . . . .. . . . . . 41

3.5 Charge Reuse Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5.1 Charge Reuse Voltage Doubler Design . . . . . . . . . . . . . . .. 43

3.6 Design Constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.6.1 MOS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.6.2 Bootstrapping Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6.3 Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.7 Technology Constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

3.7.1 Integrated Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.7.2 Bulk Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.8 Design of CP’s Auxiliary Circuits . . . . . . . . . . . . . . . . . . .. . . 51

3.8.1 Clock Generation Circuit . . . . . . . . . . . . . . . . . . . . . . . 51

3.8.2 Inverter Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . 52

3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

CONTENTS iv

4 Results 54

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.1 Steady-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.2 Transient Analysis Results . . . . . . . . . . . . . . . . . . . . . .64

4.3 Prototype Implementation . . . . . . . . . . . . . . . . . . . . . . . . .. 67

4.3.1 Fabrication Technology . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3.2 Tools and Design Flow . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3.3 Test Setup Realization . . . . . . . . . . . . . . . . . . . . . . . . 69

4.3.4 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . 71

4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.5 Discussion of the Results and Design Considerations . . .. . . . . . . . . 81

5 Conclusion and Future Work 85

5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A Testing 89

A.1 View of the Full Chip and the Designed Circuits . . . . . . . . .. . . . . . 89

A.2 Circuits and Pads Arrangement for the Design . . . . . . . . . .. . . . . . 92

A.3 Bonding Diagram for the Design . . . . . . . . . . . . . . . . . . . . . .. 93

A.4 Test Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

A.4.1 Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

A.4.2 Adding Off-Chip Passive Components . . . . . . . . . . . . . . .. 95

A.4.3 Clamping the Package to the Fixture . . . . . . . . . . . . . . . .. 96

A.5 Schematic View of Circuits . . . . . . . . . . . . . . . . . . . . . . . . .. 97

B Published Papers 104

B.1 Refereed Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 104

CONTENTS v

Bibliography 105

List of Tables

2.1 Heap CP Design Parameters. . . . . . . . . . . . . . . . . . . . . . . . . .24

2.2 Fibonacci CP Design Parameters. . . . . . . . . . . . . . . . . . . . .. . . 25

2.3 Exponential CP Design Parameters. . . . . . . . . . . . . . . . . . .. . . 28

4.1 Devices available in the fabrication technology. . . . . .. . . . . . . . . . 67

5.1 Modular CP Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A.1 Signal types and description. . . . . . . . . . . . . . . . . . . . . . .. . . 90

vi

List of Figures

1.1 Four stage conventional Dickson CP [1]. . . . . . . . . . . . . . .. . . . . 3

1.2 Four stage bootstrapped Dickson CP [2]. . . . . . . . . . . . . . .. . . . . 4

1.3 Simplified schematic of the boosted voltage generator for DRAM word-

line driver [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Double charge pump [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 One stage voltage doubler CP [5]. . . . . . . . . . . . . . . . . . . . .. . 7

2.1 Block diagram of a generic charge pump. . . . . . . . . . . . . . . .. . . 11

2.2 Generic 2-phase CP building block. . . . . . . . . . . . . . . . . . .. . . 11

2.3 Procedure for evaluating CP gain. . . . . . . . . . . . . . . . . . . .. . . 14

2.4 Integrated capacitor model. . . . . . . . . . . . . . . . . . . . . . . .. . . 15

2.5 Procedure for evaluating CP output resistance. . . . . . . .. . . . . . . . . 16

2.6 Schematic diagrams of conventional charge pumps with parasitic capaci-

tances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7 Sketch of capacitors with optimal size of Dickson, heap,and Fibonacci CPs

of equal area and gain (i.e. leftA = 5, centreA = 8, rightA = 13). . . . . . 22

2.8 Normalized input conductanceg of Dickson, heap, and Fibonacci CPs as a

function ofA, whenα = 0.1 andβ = 0.05. . . . . . . . . . . . . . . . . . 23

2.9 Normalized output resistancer of Dickson, heap, and Fibonacci CPs as a

function ofA, whenα = 0.1 andβ = 0.05. . . . . . . . . . . . . . . . . . 24

vii

LIST OF FIGURES viii

2.10 Schematic diagrams of double charge pumps. . . . . . . . . . .. . . . . . 27

2.11 Sketch of capacitors with optimal size of double Dickson and double expo-

nential CPs of area and gain (i.e. leftA= 4, rightA = 8). . . . . . . . . . . 28

2.12 Charge reuse configuration of a generic double CP. . . . . .. . . . . . . . 29

2.13 Description of charge reuse concept in double charge pumps. . . . . . . . . 30

2.14 Schematic diagrams of double charge pumps with charge reuse (parasitic

capacitances are omitted for simplicity). . . . . . . . . . . . . . .. . . . . 31

2.15 Normalized input conductanceg versus voltage gainA for the three CP

types in standard configuration and with charge reuse, whenα = 0.1, and

β = 0.05. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.16 Conversion efficiency and output characteristics of the three CP types as a

function of the output currentIO, whenn = 4 for Dickson and heap CPs

andN = 3 for the Fibonacci CP,VDD = 1.8 V, CT = 200 pF,f = 10 MHz,

α = 0.1, andβ = 0.05. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1 Conventional 2-phases cross-coupled voltage doubler stage. . . . . . . . . . 36

3.2 2-phases cross-coupled voltage doubler stage. . . . . . . .. . . . . . . . . 39

3.3 Proposed bootstrapping technique applied to a voltage doubler stage. . . . . 41

3.4 Bootstrapped voltage doubler stage with charge reuse. .. . . . . . . . . . . 44

3.5 Maximum efficiency versus transistor width for a voltagedoubler when

N = 1, VDD = 1.8 V,f = 10 MHz,CT = 250 pF,α = 0.015, andβ = 0.01. . 46

3.6 Bootstrapping capacitor size versus the maximum efficiency. . . . . . . . . 47

3.7 CV curve of nMOS capacitor (Spectre simulation). . . . . . .. . . . . . . 49

3.8 Equivalent series resistance of MOS capacitor. . . . . . . .. . . . . . . . . 49

3.9 2-phases cross-coupled voltage doubler stage with dynamic bulk biasing

for pMOS switches [6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.10 Nonoverlapping clock generation scheme (detailed schematic is shown in

Appendix A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

LIST OF FIGURES ix

3.11 A CMOS inverter driver with tapering factor 4 (detailedschematic is shown

in appendix A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.1 Schematic diagrams of the conventional voltage doublers. . . . . . . . . . . 55

4.2 Schematic diagrams of the proposed voltage doublers. . .. . . . . . . . . . 56

4.3 Charge pump block diagram. . . . . . . . . . . . . . . . . . . . . . . . . .57

4.4 Output characteristics, conversion efficiencies, and input power improve-

ment of a one stage latched and bootstrapped voltage doublers as a function

of the output currentIO, whenN = 1,VDD = 1.8 V,f = 1 MHz,CT = 262.5

pF,α = 0.015, andβ = 0.01 (Spectre simulations). . . . . . . . . . . . . . 58

4.5 Output characteristics and conversion efficiencies of aone stage latched

and bootstrapped voltage doublers, and savings in input power due to switch

bootstrapping as a function of the output currentIO whenN = 1, VDD =

1.8 V, f = 10 MHz, CT = 262.5 pF,α = 0.015, andβ = 0.01 (Spectre

simulations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.6 Output characteristics and conversion efficiencies of atwo stage latched


bootstrapping as a function of the output currentIO whenN = 1,VDD = 1.8

V, f = 1 MHz,CT = 525 pF,α = 0.015, andβ = 0.01 (Spectre simulations). 61

4.7 Output characteristics and conversion efficiencies of atwo stage latched


bootstrapping as a function of the output currentIO whenN = 1,VDD = 1.8

V, f = 10 MHz,CT = 525 pF,α = 0.015, andβ = 0.01 (Spectre simulations). 62

4.8 Output characteristics and conversion efficiencies of atwo stage bootstrapped

voltage doubler and bootstrapped voltage doubler with charge reuse as a

function of the output currentIO, whenN = 2, VDD = 1.8 V,CT = 525 pF,

f = 1 MHz,α = 0.015, andβ = 0.01 (Spectre simulation). . . . . . . . . . 63

LIST OF FIGURES x

4.9 Output characteristics and conversion efficiencies of atwo bootstrapped

voltage doubler and bootstrapped voltage doubler with charge reuse as a

function of the output currentIO, whenN = 2, VDD = 1.8 V,CT = 525 pF,

f = 10 MHz,α = 0.015, andβ = 0.01 (Spectre simulation). . . . . . . . . 64

4.10 Start-up transient with 1 nF capacitive load (two-stage charge pump,VDD

= 1.8 V, andf = 10 MHz) (Spectre simulation). . . . . . . . . . . . . . . . 65

4.11 Energy consumption versus output current (IO) of a latched and bootstrapped

voltage doublers with 1nF capacitive load (two-stage charge pump,VDD =

1.8 V,f = 1 MHz) (Spectre simulation). . . . . . . . . . . . . . . . . . . . 65

4.12 Simulated waveforms of the current drawn from the powersupply of the

proposed charge reuse bootstrapped charge pump and the bootstrapped

charge pump (two-stage charge pump,VDD = 1.8 V,f = 10 MHz) (Spectre

simulation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.13 Diagram of the analog design flow used in the design (adapted from CMC). 68

4.14 Photograph of the 24-pin CFP package containing the fabricated chip. . . . 69

4.15 Layout of the designed test board. . . . . . . . . . . . . . . . . . .. . . . 70

4.16 Block diagram of the experimental setup. . . . . . . . . . . . .. . . . . . 71

4.17 Chip design layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

4.18 Microphotograph of the design; the chip size is 1 mm× 1.5 mm. . . . . . . 73

4.19 A microphotograph showing circuits designed in a one stage bootstrapped

voltage doubler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.20 Measured and simulated output characteristic and conversion efficiency of

a fully integrated two stage bootstrapped voltage doubler as a function of

the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . . . . . . . 75


a fully integrated two stage bootstrapped voltage doubler with charge reuse

as a function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . 76

LIST OF FIGURES xi

4.22 Measured and simulated improvement in input power consumption of the

two-stages bootstrapped voltage doubler with charge reusewith respect to

the two-stages bootstrapped voltage doubler as a function of the output

currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . . . . . . . . . . . . 77

4.23 Measured and simulated output characteristics and conversion efficiency

of a fully integrated two stage cross-coupled (latched) voltage doubler as a

function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . 78


a fully integrated one stage bootstrapped voltage doubler as a function of

the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . . . . . . . 79

4.25 Measured and simulated output characteristics and conversion efficiency

of a fully integrated one stage cross-coupled (latched) voltage doubler as a

function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . 80


one stage bootstrapped voltage doubler with respect to the one stage latched

voltage doubler as a function of the output currentIO, whenVDD = 1.8 V,

f = 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81


two stages bootstrapped voltage doubler with respect to thetwo stages

latched voltage doubler as a function of the output currentIO, whenVDD =

1.8 V,f = 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.28 Measured load independent power losses versus input supply voltage of

two-stage voltage doublers bootstrapped, latched, and bootstrapped with

charge reuse atf = 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.29 Measured maximum efficiencies versus frequency of two stage voltage

doublers latched, bootstrapped, and bootstrapped with charge reuse at a

supply voltageVDD = 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . 83

LIST OF FIGURES xii

4.30 Measured and calculated [7] output resistance of the two stage bootstrapped

voltage doublers at a supply voltageVDD = 1.8 V with parasitic resistance

of 120Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.1 Proposed bootstrapping technique in a modular CP stage used to build

generic double CPs (e.g. doubler-based CP, heap CP, Fibonacci CP, and

exponential CP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.2 Proposed bootstrapping technique in a modular CP stage used to build any

two-phase double CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

A.1 Top view of the designed chip schematic. . . . . . . . . . . . . . .. . . . 89

A.2 Block view of the six circuits. . . . . . . . . . . . . . . . . . . . . . .. . 91

A.3 Chip layout and pads arrangement. . . . . . . . . . . . . . . . . . . .. . . 92

A.4 Bonding diagram for the design. . . . . . . . . . . . . . . . . . . . . .. . 93

A.5 Photograph of the fabricated test board. . . . . . . . . . . . . .. . . . . . 94

A.6 Technical drawing of the 24-pin CFP package (Spectrum Semiconductor,

Inc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

A.7 Circuit 1 schematic (2stMVD). . . . . . . . . . . . . . . . . . . . . . .. . 97

A.8 Circuit 2 schematic (1stMVD). . . . . . . . . . . . . . . . . . . . . . .. . 98

A.9 Circuit 3 schematic (2stMVDDBB). . . . . . . . . . . . . . . . . . . .. . 99

A.10 Circuit 4 schematic (2stCSDBB). . . . . . . . . . . . . . . . . . . .. . . . 100

A.11 Circuit 5 schematic (1stCCVD). . . . . . . . . . . . . . . . . . . . .. . . 101

A.12 Circuit 6 schematic (2stCCVD). . . . . . . . . . . . . . . . . . . . .. . . 102

A.13 Clock generation circuit schematic. . . . . . . . . . . . . . . .. . . . . . . 103

Chapter 1.Introduction

Chapter 1

Introduction

1.1 Motivation

Charge pumps (CPs) are power converters that convert the power supply voltage to higher

or lower constant (DC) voltages. Charge pumps transfer charge packets from the power

supply to the output terminal using only capacitors and switches to generate the required

voltage level, thereby allowing integrated implementations.

In microsystems, charge pumps are usually fully built on-chip, rather than off-chip,

to simplify chip and board design and reduce costs. Integrated implementations of charge

pumps exploit integrated capacitors as storage elements and transistors as transfer switches,

where the drain and source terminals are the two switch terminals, and the gate terminal

is used to control the switch state. Many MOS-based systems such as Flash memories,

DRAMs, OTPs, RS-232 transceivers, and driver circuits require multiple supply voltage

levels for their functional blocks and therefore are equipped with charge pumps. Integrat-

ing the CP and other functional blocks on the same die is critical for footprint and cost

reduction, however, it presents unique design challenges in terms of power efficiency, de-

vice reliability, driving capability, and performance.

The first and most important challenge is power efficiency; charge pumps with low

1

Chapter 1.Introduction 2

power efficiency limit the benefit of power conversion on chip. It is desirable to increase

charge pumps efficiency not only in battery-powered systems, but also in many applications

with common supply voltages to reduce the integrated circuits packaging cost because of

heat dissipation.

A second challenge involves the driving capability; for some applications, a wide range

of load currents and output voltages are desirable. However, it is of particular impor-

tance that charge pumps are designed to function effectively for certain steady-state oper-

ating points with minimum silicon area. In addition, the down-scaling of oxide thickness

of MOS devices increases the oxide leakage currents and lessens the oxide breakdown

voltage, which in turn limits the maximum voltages that can be safely handled on chip.

The reliability of MOS structures is primarily determined by three threatening mechanisms

namely punchthrough, oxide breakdown, and well-diffusionjunction breakdown. In typ-

ical CMOS design, the first two factors happen at lower voltages than the well-substrate

junction breakdown.

The start-up time is an important factor in integrated charge pumps because start-up

time limits the functionality and the performance of other blocks, also a faster start-up time

can reduce the CP energy consumption during transients and improve the overall efficiency.

Finally, the output voltage ripple is a critical design specification; larger output ripple

degrades the performance of some functions. In particular,the ripple at the output of a

charge pump can have a negative impact on sensitive analog circuits such as reference

voltage generators, op-amps, and charge pump control circuitry.

1.2 Literature Review

The first widely used monolithic charge pump is the Dickson charge pump [1]. This circuit,

shown in Fig. 1.1, uses diode connected (N) MOS transistors and a chain of capacitors (C)

driven by two complementary phasesφ1 andφ2 to transfer charges from the power supply


Figure 1.1: Four stage conventional Dickson CP [1].

at a voltageVDD to the load capacitorCL at a higher voltage. The ratio between the output

voltage and the input voltage is the conversion ratio. The main drawback of this config-

uration is the threshold voltage drop associated with the diode connected transistors. At

higher conversion ratios, the performance is even worse because of the increased threshold

voltage due to the body effect. Moreover, conversion ratiosdecrease at low-supply voltages

since the threshold voltage shift cannot be scaled down.

In the bootstrapped Dickson CP [2], limitations of the switch on resistance, low con-

duction, and voltage drop associated with diode connected transistors are alleviated by

introducing an additional MOS switchNb and capacitorCb for boosting the gate voltage

of the main switchesN as shown in Fig. 1.2. This implementation needs devices ableto

withstand high voltages and the generation of four nonoverlapping clock phases (φ1, φ2, φ3,

andφ4), which also prevent short-circuit currents from nodes at higher voltages to nodes

at lower voltages. However, when the diode connected transistor of the output stage is for-

ward biased, it causes a voltage loss equal to the diode threshold voltage. This reduction is

particularly critical in the presence of low voltage power supplies.

A word-line driver with a boosted voltage generator is employed to improve DRAMs

performance [3]. The boosted voltage generator is conceived with cross-coupled nMOS

transistors driven by the nonoverlapping phasesφ1 andφ2. In this configuration, shown


Figure 1.2: Four stage bootstrapped Dickson CP [2].

in Fig. 1.3, a controlled serial switchNS is required at the output to obtain a constant DC

output voltage. The output switch is controlled with a feedback technique by utilizing two

additional charge pump circuits, an inverter, and two additional clock phasesφ3 andφ4.

To improve the performance of charge pumps, the double charge pump in Fig. 1.4 was

conceived to reduce the output ripple by feeding the load in each half period using the same

total capacitance [4]. The transfer capacitors of the last stage (C = C ′) are alternately

charged to the voltage of the previous stage (Vp) and then boosted by the same voltage

level to charge the load at a higher output voltage. The clocksignals ofφ1 andφ2 are

bootstrapped to the same level asVp to connect the two capacitors in series.

The voltage doubler of Fig. 1.5 usually consists two latchedCMOS pairs in each

stage [5]. The complementary voltage swings of the internalnodes are used to control

the switches of opposite branches. This circuit eliminatesthe voltage drop at the out-

put switches, reduces the output voltage ripple, and uses only two nonoverlapping phases.

Moreover, the voltage across each transistor is never higher than the power supply voltage

VDD. At high output currents, the overdrive voltage decreases causing the output resistance

to rise due to higher switch resistance, thus increasing resistive power losses and reducing

power efficiency and driving capability. Moreover, a short-circuit loss from higher voltage


Figure 1.3: Simplified schematic of the boosted voltage generator for DRAM word-linedriver [3].

Figure 1.4: Double charge pump [4].


nodes to lower voltage node exists during transitions. The resulting short-circuit current

reduces the charge pump efficiency and output voltage.

The two series pMOS transistors (P andP ′) in Fig. 1.5 act as charge-transfer devices to

provide a constant output voltage at the output. If the well potential is too low, the vertical

parasitic bipolar transistors create a leakage path to the substrate. As an effort to solve this

issue, the pMOS well potential is kept higher than the sourceand drain terminals by means

of a bulk biasing circuit [6]. The solution involves a switching circuit that connects the

well to the highest potential. Moreover, the pMOS transistors are driven independently by

an additional level shifter to improve their conductivity.However, the implementation is

constrained by an input supply voltage of one third the device voltage rating specified in

the process.

In the conventional voltage doubler [5], the complementaryvoltage transitions of inter-

nal nodes occur simultaneously during switching. The resulting short-circuit currents can

be reduced by exploiting two parallel stages to generate control signals of the main transfer

switches [8], or by using four nonoverlapping phases and bootstrapping the pMOS switches

[9]. In these implementations, at high output currents, thevoltage driving the switches de-

creases, therefore, reducing both the driving capability and the power efficiency.

To overcome the limitation of the charge pump driving capability, an unconventional

boosting technique to control switches is suitable for cascaded voltage doubler operating at

low supply voltages [10]. The auxiliary boosting circuit generates the proper control signals

from the main clock phases. The solution enhances the driving capability and allows the

use of low voltage devices, but does not eleminate short-circuit losses.

The maximum power efficiency is limited by dynamic power losses due to charging

and discharging the parasitic capacitances. Reusing some of the charges that are normally

wasted for charging and discharging parasitic capacitances at each cycle is a promising

approach for reducing power dissipation in charge pumps [11]. This technique improves

the power efficiency and reduces electromagnetic emission of conventional bootstrapped


C C'

P'

PN

N'V

DD

CL

f1 f

2

0

f1

f2

VDD

VDD

Figure 1.5: One stage voltage doubler CP [5].

Dickson charge pumps.

Several charge pump topologies with a voltage gain which increases at a higher rate

than the number of stages have been proposed in the literature. The Fibonacci charge pump

[12] achieves the highest voltage gain for a given number of capacitors [13]. Another CP

structure with a high voltage gain and based on double implementation is the exponential

charge pump [14] and [15], which has a voltage gain that increases exponentially with the

number of stages. However, it should be pointed out that, as aresult the high voltage rise

per stage, the output voltage is limited only by the fabrication process and the constraint on

the minimum oxide thickness of integrated devices forces the use of a high-voltage thick

oxide devices.

The heap charge pump represents a different topology that achieves the same ideal

gain as the Dickson charge pump for a given number of stages [16]. In this topology, the

transfer capacitors are alternately connected in parallelto the input supply voltage and then

connected in series to charge the output terminal to a highervoltage level. The maximum

voltage across any of the transfer capacitors is only equal to the input voltage, regardless


of the number of stages, which allow the structure to use low-voltage capacitors.

1.3 Contributions

The work presented here provides analysis, design, and implementation guidelines to en-

able successful on-chip integration of charge pumps. Six integrated charge pump circuits

were designed and fabricated in a TSMC 0.18-µm CMOS process. The aim of this research

is to develop approaches that reduce power losses with less area than existing conventional

CP circuits. Design trade-offs are discussed, including a test chip design and testing.

The main contributions of this thesis are summarized as:

• Determination of an analysis method for evaluating integrated charge pumps perfor-

mance and optimizing their design.

• Application of the charge reuse concept to effectively reduce the dynamic power

losses of integrated double charge pumps.

• Development of a switch bootstrapping technique for doublecharge pumps. The

technique prevents short-circuit losses, improves driving capability, and enables efficient

operation at low supply voltages.

• Implementation of six integrated circuits in a 0.18-µm digital process and comparison

of experimental results.

1.4 Thesis Organization

The rest of the thesis is organized as follows: Chapter 2 introduces an analysis method to

evaluate and optimize the performance of integrated single-sided charge pumps and double

charge pumps, and the application of charge reuse in integrated charge pumps. Chapter

3 examines the design limitations of integrated voltage doublers and provides an overview

on the design procedure of proposed integrated voltage doubler in standard CMOS process.

Chapter 4 presents the implementation of the designed circuits and shows simulation and


experimental results. The thesis concludes in chapter 5 with the discussion of the obtained

results and future developments.

Chapter 2.Charge Pump Analysis

Chapter 2

Charge Pump Analysis

2.1 Method of Analysis

In order to design efficient on-chip charge pumps, a careful analysis must be done. The

method described here is based on the pioneering work on switched-capacitor circuit anal-

ysis [17]. The method is suitable for networks containing switches, capacitors, and voltage

sources as illustrated in Fig. 2.1. The circuit is describedeffectively by means of switching

matrices, a capacitance matrix, and a voltage source matrix. The MOS switches are mod-

elled as ideal switches with zero on resistance, capacitorsas linear elements, and voltage

sources as ideal sources. The analysis is done under the following assumptions. First of

all, each switch changes its state (on, off) instantaneously at each switch eventtk, where

tk is an instant of time when at least one switch in the circuit changes state. Furthermore,

slow switching conditions are assumed, where the switchingperiod is much longer than

time constants due to capacitances and resistances of integrated components and intercon-

nects. Each switching period consists ofk consecutive non-overlapping fragments known

as phases, which define the state of the switches in every fragment (tk, tk+1) and, hence,

the charge transfer between capacitors. Finally, the circuit is analyzed in steady-state con-

ditions, where the capacitor voltages are periodic steady-state waveforms.

10

Chapter 2.Charge Pump Analysis 11

Figure 2.1: Block diagram of a generic charge pump.

C

f1

f21 2

5

f2

f1

3

4 6

1 2 3 4 5 6

1 2 3 4 5 6

f1

f2

Figure 2.2: Generic 2-phase CP building block.


In each phase, the nodes in the CP circuit are grouped intol separate parts, each part is

either a set of nodes connected by closed switches or an isolated node as shown in Fig. 2.2.

Therefore, ak-phase CP withn nodes is described byk switching matricesSk, with n rows

andn columns, to record the CP switching activity. By assigning appropriate numbers to

the nodes, the switching matrix elements are defined according to their connection in the

switching phasek as follows:

Sk(i, j) =

1 if i is the node with the lowest number in a separate part of

the closed switch network, and nodej belongs to that separate part

0 otherwise(2.1)

where 1≤ i ≤ j and 1≤ j ≤ n.

A n×n capacitance matrixC describes the CP capacitors in terms of their values, node

connections, and parasitics, and can be expressed as

C(i, j) =

total capacitance connected permanently to nodei if i = j

negative of the total capacitance betweeni andj if i 6= j(2.2)

The CP independent voltage source and ground (i.e. groundedswitches are connected

to a zero value voltage source) connections are described byan n × 2 matrix G, whose

elements are defined as

G(i, h) =

−1 if the h-th voltage source is connected to nodei

0 otherwise(2.3)

where 1≤ i ≤ n and 1≤ h ≤ 2.

The capacitance matrix and the voltage sources matrix do notchange as the switches

change states. The node voltages are represented by the (n×1) vectorv(tk), which defines


the voltage between thei-th node and ground at switch eventtk. The charges delivered by

the independent voltage sources are represented by the (2×1) vectorqI(tk), which denotes

the charge passed through theh-th voltage source from switch eventtk to switch eventtk+1.

In each phase, the closure of the switches imposes a set of(n − l + 2) KVL equations and

l charge conservation equations, from which we find the corresponding nodes voltage at

time tk and charges delivered by the sources during the interval (tk, tk+1). For a complete

solution, conservation equations can be compactly expressed as:

vI(tk)

SkCv(tk−1)

=

−GT 0

SkC + STk − I SkG

·

v(tk)

qI(tk)

, (2.4)

wherevI(tk) is a(2 × 1) vector which represents the independent voltage sources, and

I is then × n identity matrix. The (n + 2) × (n + 2) matrixΦk in (2.4) can be rearranged

to obtain a solution for the nodes voltagev(tk) and the delivered chargesqI(tk) as follows:

v(tk) = AkvI(tk) + BkSkCv(tk−1) (2.5)

and

qI(tk) = RkvI(tk) + OkSkCv(tk−1), (2.6)

whereAk andBk are the upper-leftn×2 submatrix and the upper-rightn×n submatrix

of Φ−1k , respectively.Rk andOk are the lower-left2×2 submatrix and the lower-right2×n

submatrix ofΦ−1k , respectively. In the case of a CP operating with two phases,in steady-

statev(tk−1) = v(tk+1) andv(tk) = v(tk+2), therefore the CP voltage nodes and delivered

charges can be calculated.


Figure 2.3: Procedure for evaluating CP gain.

2.2 Charge Pump Gain

CPs achieve capacitive voltage conversion by means of transfer capacitors and switches

driven by nonoverlapping clock phases. Each transfer capacitor is charged to a certain

voltage level and then it is boosted by another voltage levelresulting in a voltage increase

at the output terminal. Since CP circuits do not use inductors, they are well suited for

integrated implementations in planar conventional technologies.

2.2.1 Ideal Gain

The voltage gainA is defined as the ratio between the maximum open-circuit output voltage

VO and the input voltageVDD (assumed constant). Since no current is delivered to the load,

dependencies on the switching frequency and capacitances values are eliminated. When

ideal capacitors are assumed, the gain depends only on the number of capacitorsN , the

number of phases, and the topology, which, in turn, determines how the transfer capacitors

are interconnected in each phase. The procedure for evaluating the voltage gain includes

disconnecting any load at the output and finding the output voltage as shown in Fig. 2.3.


C

Substrate

bCaC

TopBottom

Figure 2.4: Integrated capacitor model.

2.2.2 Gain with Parasitic Capacitances

A key reason why the gain of a real integrated CP deviates fromthe ideal is the unavoidable

presence of parasitic capacitances, which share a portion of each charge packet transferred

between transfer capacitors resulting in reduced gain. Parasitic capacitances are expressed

by the technological parametersα andβ, which give the stray parasitic capacitancesα C

(between bottom plate and substrate) andβ C (between top plate and substrate) of any

integrated capacitorC as shown in Fig. 2.4. The value ofα andβ are determined by the

process and the type of the integrated capacitors used (integrated capacitors are discussed

in detail in Chapter 3). To assess the impact of parasitic capacitances on the voltage gain

A, their values are included in the capacitance matrixC by modelling the total capacitance

connected permanently to a node as (α + 1)C or (β + 1)C [18]. The gain with parasitic

elements is lower than the ideal gain, because a portion of each charge packet transferred

between stages is shared with the parasitic capacitors and wasted.

2.3 Charge Pump Output Resistance

In the case of ideal linear elements, the procedure for evaluating the output resistance in-

volves turning off the input voltageVDD, applying an ideal sourceVX to the output, and

calculating the ratio between the voltage and the average current of the applied source as

shown in Fig. 2.5. In a two-phase CP the output resistance [19] is given by


Vx

Ix= q

xfs

VIN

= 0Charge

pump

Figure 2.5: Procedure for evaluating CP output resistance.

RO =r

f · CT

, (2.7)

wheref is the switching frequency,CT is the value of the total capacitance defined as

the sum of the capacitances of all transfer capacitorsCT =∑N

i=1 Ci, andr is a constant

that depends on circuit topology which can be expressed as

r =N∑

i=1

a2ci, (2.8)

whereN is the number of capacitors andaci = qi/qX is the charge multiplier factor,

which is the ratio of the chargeqi, transferred by capacitorCi in a period, and the charge

qX delivered to the load. The charge multiplier factors are calculated by applying charge

conservation to the circuit in phase 1 and 2, and by considering that, in steady-state, each

capacitor receives and delivers the same charge in each of the two phases.

2.3.1 Analysis of Output Resistance with Parasitic Capacitances

To evaluate the effect of parasitic elements on the output resistance, we includeαCi and

βCi in the capacitance matrix, turn offVDD, connect a voltage source at the output, apply

the method above one more time, and find the chargeqX delivered by the voltage source

during the switching period, the corresponding current, and thus the output resistance. The

output resistance with parasitic elements is lower than theideal, because it is inversely


proportional to the node capacitances that increase with the parasitics.

2.4 Power Losses in Charge Pumps

Charge pumps transfer charge packets from the power supply at a voltageVDD to an out-

put terminal at a higher voltageVO. In this operation, CPs dissipate a portion of the input

power and may reduce the benefit of scaling the supply voltagedown. The energy effi-

ciency is defined as the average power delivered to the load divided by the average of input

power. Power losses arise mainly from capacitor charging and discharging losses, resis-

tive conduction losses, and losses due to parasitic capacitances and short-circuit currents.

The highest efficiency is achieved in slow switching conditions. In such conditions and in

steady-state, the main power losses are described by a simple model and can be divided

into load dependent losses and load independent losses [20].

2.4.1 Load-Dependent Losses

Load-dependent losses are revealed when the charge pump is connected to a load and the

output voltage decreases in the presence of a load currentIO > 0. These losses are mod-

elled through a non-zero equivalent output resistanceRO and the corresponding power

dissipation is

PLD = RO · I2O . (2.9)

This formula indicates that lower load dependent losses canbe achieved by reducing

the output resistanceRO given in (2.7) which is inversely proportional to the product of the

switching frequencyf and the total capacitanceCT .


2.4.2 Load-Independent Losses

Load independent losses are revealed when the CP is not connected to any load and it

still dissipates power. These losses mostly arise from charging and discharging parasitic

capacitances and are also called dynamic losses. They are modelled through a non-zero

equivalent input conductanceGI and the corresponding power dissipation is

PLI = GI · V2DD . (2.10)

The dynamic losses of switch drivers and other auxiliary functions could be incorpo-

rated in the model as well. However, for the present we focus our analysis only on the

charge pump core. In this case, the input conductance is proportional to the product of the

switching frequency and the total capacitance:

GI = fCT · g , (2.11)

whereg is a constant that depends on circuit topology and parasiticcapacitances. The

procedure for evaluating the input conductance involves disconnecting the output load and

calculating the charge delivered by the sourceVDD to the CP as shown in Fig. 2.3.

The output power of a charge pump (i.e. the power delivered tothe load) is

PO = VO IO = (A VDD − RO IO) IO , (2.12)

Assuming the gainA > 1, the charge pump has a conversion efficiency given by

η =PO

PO + PLD + PLI

=A VDD IO − RO I2

O

A VDD IO + GI V 2DD

, (2.13)


which is maximum when the output current is equal to

IO =GI VDD

A

(

√

A2

GI RO

+ 1 − 1

)

. (2.14)

In this condition, the ratio

PLI

PLD

=A2

GI RO

·1

(√

A2

GI RO

+ 1 − 1)2 , (2.15)

is larger than one for any acceptable value ofA, GI , andRO. In other words, at peak

efficiency, load-independent losses are larger than load-dependent losses (i.e.PLI > PLD

at IO = IO). In general, load-independent losses dominate at low currents such that

0 ≤ IO < VDD

√

GI/RO, (2.16)

while for higher currents load-dependent losses are larger. Therefore minimizing load

independent losses is a crucial design objective, especially for charge pumps meant to

operate at peak efficiency or at low currents.

2.5 Analysis of Single-Sided Charge Pumps

Several single-sided CP structures have been proposed in the literature, each suited to meet

specific application requirements and address process constrains. Single-sided CPs transfer

charge packets to the load once every switching period. Indeed, the differences between

CPs structures correspond to the configuration of their capacitors and switches in each

phase. Exploring different CPs structures is motivated by choosing the appropriate struc-

ture in order to maximize the efficiency.

In the Dickson CPs in Fig. 2.6(a) [2], MOS switches controlled by non-overlapping

control phases eliminate the voltage drops associated withthe diodes used in the classic


configuration [1]. Each transfer capacitor is charged to thevoltage of the preceding stage

and then boosted byVDD to charge the next stage at a higher voltage. Ideally, a circuit with

N stages has a voltage gainA = N + 1, an output resistanceRO = N2/(fCT ), and an

input conductanceGI = 0.

In the heap CP in Fig. 2.6(b) [16], the voltage across each capacitor never exceedsVDD

making this type of CPs attractive for implementations in low-voltage processes. A heap CP

with N stages has an ideal voltage gainA = N +1, an output resistanceRO = N2/(fCT ),

and an input conductanceGI = 0.

The Fibonacci CP with three capacitors shown in Fig. 2.6(c) [12] has the same ideal

gain as the Dickson and the heap CPs with four capacitors (Figs. 2.6(a) and 2.6(b)). This

two phase CP single-sided structure has the highest attainable gain for a given number of

capacitors [13]. The gain of an ideal Fibonacci CP withN stages isA = FN+1, whereFN

is theN-th Fibonacci number, withF0 = F1 = 1 andFi = Fi−1 + Fi−2 for i > 1. In the

case of equal transfer capacitorsCi = CT/N , the charge multiplier factors areaci = FN−i

for i = 1 to N , the output resistance of this topology isRO = Nf ·CT

∑N

i=1(FN−i)2, and the

input conductanceGI = 0.

2.5.1 Optimization of the Output Resistance

To minimize the output resistance of any CP for a constant total capacitanceCT , we sub-

stituteC1 = CT − C2 − ... − CN in (2.7) and we set the partials with respect to capacitors

Ci equal to zero, which means

∂RO

∂Ci

=1

f·

(

a2ci

CT − C2 − ... − CN

−a2

ci

C2i

)

= 0, (2.17)

for i = 2 to N [18].

Since the available silicon area is a critical constraint for a designer, the CPs capacitor

sizes, which are the largest portion of an integrated CP, areoptimized to improve CPs per-


0

VDD

12 21

1 12 2 1

C1

C2

C3

C4

0

bC2bC

1bC

3bC

4

a(C1+C

3) a(C

2+C

4)

VDD

VDD

VO

Load

0

IO

(a) Four-stage Dickson CP.

1

2

C1

C2

C3

C4

00

2 2 2

1

00

11

2

VDD

1 1 1 1 VO

Load

0

IO

bC3bC

2bC

1bC

4

aC1

aC2 aC

3aC

4

(b) Four-stage heap CP.

(c) Three-stage Fibonacci CP.

Figure 2.6: Schematic diagrams of conventional charge pumps with parasitic capacitances.

formance. Considering the three structures (i.e. the Dickson, the heap, and the Fibonacci)

and the calculated charge multiplier factors for each structure, the optimal capacitor sizes

are found. The optimal performance of anN-stage CP is not necessarily obtained when

capacitances are equal, but when they scale as a function of the charge multiplier factor.


C1 C

2C

3C

4

C1

C2

C3

C1

C2

C3

C4

Fib

onacci

Dic

kson

Heap

A = 5

C1

C2

C3

C4

C1

C2

C3

C4

C5

C6

C7

C1

C2

C3

C4

C5

C6

C7

A = 8

Fib

onacci

Dic

kson

Heap

C1

C2

C3

C4

C5

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C12

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

A = 13

Fib

onacci

Dic

kson

Heap

C11

Figure 2.7: Sketch of capacitors with optimal size of Dickson, heap, and Fibonacci CPs ofequal area and gain (i.e. leftA = 5, centreA = 8, rightA = 13).

For instance, the optimal performance of anN-stage Fibonacci CP is when capacitors are

scaled as the Fibonacci sequence with the largest capacitornext toVDD and the smallest

next to the load.

When the capacitors are optimized as shown in Fig. 2.7, the three CPs have a simi-

lar performance. In this case, the trade-off between gainA and output resistance can be

expressed as [18]:

RO =(A − 1)2

fCT

. (2.18)

2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances

The design parameters for the CPs shown in Fig. 2.6 are calculated as a function ofα and

β. For the Dickson CP the gain is

A =N

1 + β+ 1 , (2.19)

the output resistance is

RO =r

fCT

, (2.20)

with

r =N2

(1 + β), (2.21)


0

0.2

0.4

0.6

0.8

1 3 5 7 9 11

g

Voltage Gain A

Dickson

Fibonacci

Heap

Figure 2.8: Normalized input conductanceg of Dickson, heap, and Fibonacci CPs as afunction ofA, whenα = 0.1 andβ = 0.05.

and the input conductance is

GI = fCT ·α + β + αβ

1 + β, (2.22)

with

g =α + β + αβ

1 + β. (2.23)

The analytical expressions forA, r, andg in the case of the optimized heap and the

Fibonacci CPs are collected in Table 2.1 and 2.2. The performance comparison indicates

that the Dickson CP performs the best since bottom plate parasiticsα does not contribute

to the gain reduction as in other structures where a significant portion of charges delivered

to the output is shared with the parasitic capacitancesαCi associated with the bottom plate

of the transfer capacitors. Also, the input conductance of the Dickson CP is independent

of the number of stages. Accordingly, the load-independentlosses of Dickson CPs depend

only on α andβ, the total capacitance, the switching frequency, andV 2DD. On the other

hand, the heap CP has the worst performance, exhibiting a much lower gain than other

topologies at large number of stagesN .


0

4

8

12

16

1 2 3 4 5

r

Voltage Gain A

Dickson

Fibonacci

Heap

Figure 2.9: Normalized output resistancer of Dickson, heap, and Fibonacci CPs as afunction ofA, whenα = 0.1 andβ = 0.05.

Table 2.1: Heap CP Design Parameters.N Parameters

1 A = 1 +1

1+β

r =1

1+β

g =α+β+αβ

1+β

2 A = 1 +2+β

1+α+(3+α)β+β2

r =2(2+α+β)

(1+α+(3+α)β+β2)

g =(5+α+2β)(α+β+αβ)2(1+α+(3+α)β+β2

3 A =(2+α+β)(2+α+(4+α)β+β2)

1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β))

r =3(1+α+β)(3+α+β)

(1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β)))

g =((α+β+αβ)(14+α2+4α(2+β)+β(14+3β)))

(3(1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β))))

4 A =((1+α+(3+α)β+β2)(5+α2+β(5+β)+α(5+2β)))

(α3(1+β)+α(3+β)(2+3β(2+β))+α2(5+3β(3+β))+(1+β)(1+β(3+β)2))

r =4(2+α+β)(2+α2+2α(2+β)+β(4+β))

(α3(1+β)+α(3+β)(2+3β(2+β))+α2(5+3β(3+β))+(1+β)(1+β(3+β)2))

g =((α+β+αβ)(14+α2+4α(2+β)+β(14+3β)))

(3(1+α2(1+β)+β(2+β)(3+β)+α(3+2β(3+β))))


Table 2.2: Fibonacci CP Design Parameters.N Parameters

1 A = 1 + 11+β

r = 11+β

g = α+β+αβ

1+β

2 A = 1 + 21+β

r = 41+β

g = α+β+αβ

1+β

3 A = α(1+β)+(2+β)(5+2β(4+β))(1+β)(2+α+(5+α)β+2β2)

r = 4 2α(1+β)+((2+β)(4+5β)(1+β)(2+α+(5+α)β+β2

g = (α+β+αβ)(3α(1+β)+(2+β)(7+8β))4(1+β)(2+α+(5+α)β+2β2)

4 A = 48+α(1+β)(8+5β)+β(4+β)(35+6β(4+β))(3+2β)(2+3β)(1+β(3+β))+α2 (1+β)2+α(1+β)(7+β(16+7β))

r = 7 42+2α2(1+β)+α(19+3β(12+5β))+β(109+β(80+17β))(3+2β)(2+3β)(1+β(3+β))+α2 (1+β)2+α(1+β)(7+β(16+7β))

g = (α+β+αβ)(108+5α2(1+β)+α(49+92β+38β2)+β(277+200β+42β2))(7(1+α+(3+α)β+β2)(6+α+(13+α)β+6β2))

Examples of numerical values ofg andr for various values ofA are respectively shown

in Fig. 2.8 and Fig. 2.9, where they are plotted as function ofA for α = 0.1 andβ = 0.05. In

the Dickson CP, the normalized input conductanceg does not change with the number of

stages, while the voltage gainA and the output resistance does not depend on the value of

α, because the circuit can be built so that the bottom plates ofall capacitors are alternately

connected to ground andVDD without affecting the charge transfer through the CP. For the

Fibonacci and heap CPs, the normalized input conductanceg depends on the number of

stages because bottom plate parasitic capacitances share aportion of the charge transferred

to the output and therefore affect performance.

2.6 Analysis of Double Charge Pumps

The output voltage ripple can be reduced by splitting the CP in two parts, each part with half

the total capacitance and feeding the load in a different half period [4]. This configuration,

called double CP, is usually implemented as a parallel connection of stages operating with

opposite phases. Fig. 2.10 shows implementations of doubleCPs of the circuits seen in the


last section. The voltage gainA, the output resistanceRO, and the input conductanceGI

are the same as the single-sided CPs when the total capacitance is the same. On the other

hand, the voltage ripple defined as the peak to peak variations in the DC output voltage, is

halved with respect to the single-sided charge pump and can be expressed as [21]

Vripple =IO

2 · f · CL

, (2.24)

whereCL is the load capacitance.

Another CP structure used to achieve a high voltage gain is the exponential CP shown

in Fig. 2.10(d). The gain of an ideal exponential CP withN stages isA = 2N . In the case

of equal transfer capacitorsCi = CT /(2N), the charge multiplier factors areaci = 22(N−i)

for i = 1 to N , the output resistance isRO = Nf ·CT

∑N

i=1 22(N−i), and the input conductance

GI = 0. The optimal performance of an exponential CP withN stages is obtained using

(2.17), and the minimum output resistance is when capacitors are sized as

Ci =2N−i

2N − 1CT . (2.25)

A comparison between the optimal capacitors sizes of an ideal Dickson and an ideal

exponential CPs with the same performance is shown in Fig. 2.11

2.6.1 Double Charge Pumps Performance with Parasitic Capacitances

The analytical expressions forA, r, andg in the case of the optimized exponential CP are

collected in Table 2.3, whileA, r, andg for the double Dickson, double Fibonacci, and

double heap CPs are the same as those of the single-sided implementations. Comparing the

performance of the exponential CP to the double Dickson, again the Dickson CP performs

the better since bottom plate parasiticsα does not contribute to the gainA reduction as

in other structures where a significant portion of charges delivered to the output is shared

with transfer capacitances bottom plate parasitics and wasted every clock cycle. Also, the


1 1 2

C C C

2

VDD

1

C' C' C'

0

2

2

2 1

Load

0

IO

VO1

VDD

0VDD

2 1

VDD

0

0VDD

0VDD

2 1

VDD

0

2 121

21

1

C

C'

2

0VDD

2 1

VDD

21

0

(a) Four-stage double Dickson CP.

1

1 1 2

C C C

00

2

2

2

1

0

1

2

VDD

1

1

C' C' C'

00

2

2

0

1

2

2

1

2 1

Load

0

IO

VO

(b) Three-stage double Fibonacci CP.

2

C' C' C' C'

00

2

00

VDD

1

2

C C C C

00 00

2

1

2

2

1

2

2

1

2

2

1

1

2

1

1

2

1

1

2

1

1

1

Load

VO

0

IO

(c) Four-stage double heap CP. (d) Three-stage double exponential CP.

Figure 2.10: Schematic diagrams of double charge pumps.

input conductance of the exponential CP depends on the number of stages. Accordingly,

the load-independent losses of exponential CPs are higher,because of the voltage swings

across the parasitic capacitances larger thanVDD.

2.7 Charge Reuse

At low output current, the conversion efficiency is largely set by parasitic capacitances.

In order to reduce dynamic power losses, charge reusing [11]is investigated to mitigate

these losses. If we consider those internal nodes of a conventional charge pump (Fig. 2.6)

that are connected to ground through a switch at every cycle,the parasitic capacitances

associated with them are charged to a certain voltage and then discharged to 0, therefore

the related charge is wasted in every cycle. We can reuse partof that charge (and therefore


Figure 2.11: Sketch of capacitors with optimal size of double Dickson and double expo-nential CPs of area and gain (i.e. leftA= 4, rightA = 8).

Table 2.3: Exponential CP Design Parameters.N Parameters

1 A = 2+β

1+β

r = 11+β

g = α+β+αβ

1+β

2 A = 2.(2+β)2

(2+α+(5+α)β+2β2)

r = 3(6+α+3β)(2+α+(5+α)β+2β2)

g = 2(6+α+3β)(α+β+αβ)3(2+α+(5+α)β+2β2

3 A = 4.(2+β)3

α2(1+β)+(2+β)2(1+4β)+α(2+β)(4+5β)

r = 7(α2+6α(2+β)+7(2+β)2)(α2(1+β)+(2+β)2(1+4β)+α(8+14β+5β2))

g = 4(α+β+αβ)(α2+6α(2+β)+7(2+β)2)CT

7(α2(1+β)+(2+β)2(1+4β)+α(8+14β+5β2))


2

IO

1

0

VDD VO

Charge

pump 2

1

2

1 23

33 30

Charge

pump 1

0

OUTIN

OUTIN

0 0

Figure 2.12: Charge reuse configuration of a generic double CP.

save charges drawn from the power supply), if pairs of such nodes with complementary

voltage swings (i.e. 180 out of phase) are equalized before each switch event. DoubleCPs

clocked with opposite phases, have pairs of such nodes in each stage. Thus, charge reuse

can be applied to all stages of any double CP [20] as shown in Fig. 2.12.

Fig. 2.13 describes the charge reuse concept where an equalization switch driven by an

appropriate control signal is used to bring the nodes (X and X′) to an intermediate voltage

level. The time required by this operation is much smaller than the time needed for charging

the transfer capacitors, because only a small fraction (e.g. α) of the capacitance is involved.

Therefore, the time allocated for the equalization has a limited impact on the operating

frequency.

The principle of charge reuse is based on equalizing the voltages of the parasitic ca-

pacitances in each stage. The equalization switch controlled by phase 3 brings both ca-

pacitances to an intermediate voltage before each switch event, therefore the amount of

charges drawn from the power supply for charging parasitic capacitances is less than the

amount needed by conventional CPs. As a consequence, chargereusing reduces the load-

independent losses. As design examples, we consider doubleDickson CP, double Fibonacci

CP, and a double heap CP. Applying charge reusing requires splitting the circuits into two


(a) Circuit to describe the charge reuse.

(b) Clock phases and internalnodes voltage waveforms.

Figure 2.13: Description of charge reuse concept in double charge pumps.

symmetrical parts (double CP) driven by complementary control signals and operating in

parallel, as shown in Fig. 2.12. Examples of charge reuse application to the heap and Fi-

bonacci CPs are shown in Fig. 2.14(a) and 2.14(b), respectively. In these cases, charge

reusing not only reducesGI , it also increasesA andRO.

2.8 Simulation Results with Charge Reuse

Three CP types (i.e. the Dickson, the heap, and the Fibonaccicharge pumps) were designed

and simulated with Spectre using MOS switches and poly-diffusion capacitors in a standard

0.18-µm technology. Fig. 2.15 shows the normalized input conductanceg versus the gain

A. The reduction ofg (and consequently ofPLI) for the Dickson CP is 50%. On the other


(a) Three-stage double Fibonacci CP with charge reuse.

(b) Four-stage double heap CP with charge reuse.

Figure 2.14: Schematic diagrams of double charge pumps withcharge reuse (parasiticcapacitances are omitted for simplicity).

hand, the improvement for the Fibonacci and heap CPs is less than 50% for gains larger

than two and depends on the number of stages. Fig. 2.16 shows the output characteristics

and the conversion efficiencyη of the three CP types. The results are obtained whenN = 4

for Dickson and heap CPs and whenN = 3 for the Fibonacci CP. The output characteristics

of the Dickson CP is not changed, while the open-circuit gains of the Fibonacci and heap

CPs with charge reusing are improved (i.e. 1.9% and 8.7% increase, respectively), because

parasitic capacitances draw less charge from the primary charge transfer path. More signif-

icantly, charge reusing substantially improves the overall conversion efficiencyη in any CP

type: The maximum efficiency increases from 52.5% to 63% for the Dickson CP and from


0

0.2

0.4

0.6

0.8

1

1 3 5 7 9 11

g

Voltage Gain A

Dickson

Fibonacci

Heap

Dickson-reuse

Fibonacci-reuse

Heap-reuse

Figure 2.15: Normalized input conductanceg versus voltage gainA for the three CP typesin standard configuration and with charge reuse, whenα = 0.1, andβ = 0.05.

23% to 31% for the heap CP, and from 43% to 53% for the FibonacciCP. Reusing wasted

charges reduces the current drawn from the power supply and increases the conversion

efficiency.

2.9 Summary

In this chapter, a method of analysis for evaluating integrated charge pumps performance

and optimizing their capacitor sizes is determined. The analysis allows the calculation of

the voltage gainA, the output resistanceRO, and the input conductanceGI and conse-

quently the major power losses (resistive and dynamic powerlosses) of any integrated CP

can be evaluated. Moreover, charge reuse is applied to with the result of reducing the dy-

namic power losses and improving the overall conversion efficiency. The technique can

be applied to any double CP. The application of charge reuse results in reduced dynamic

power losses and a significant portion of wasted charges is recovered every clock cycle.

The Dickson CP has the best performance in terms of the voltage gain and power effi-

ciency. When charge reuse is considered the double Dickson (voltage doubler) CP has a


0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 100 200 300 400 500 600 700 800

Co

nv

ers

ion

Eff

icie

ncy

IO

Dickson

Fibonacci

Heap

Dickson-reuse

Fibonacci-reuse

Heap-reuse

( A)m

(a) Conversion efficiency.

0

1

2

3

4

5

6

7

8

9

10

0 100 200 300 400 500 600 700 800

VO

IO

Dickson

Fibonacci

Heap

Dickson-reuse

Fibonacci-reuse

Heap-reuse

( A)m

(b) Output characteristics.

Figure 2.16: Conversion efficiency and output characteristics of the three CP types as afunction of the output currentIO, whenn = 4 for Dickson and heap CPs andN = 3 forthe Fibonacci CP,VDD = 1.8 V, CT = 200 pF,f = 10 MHz, α = 0.1, andβ = 0.05.

better performance.

Chapter 3.Design

Chapter 3

Design

3.1 Introduction

The designer of integrated charge pumps has to face the constraints of the fabrication tech-

nology. Typically, integrated CMOS circuits share a singlesubstrate, thus the chip layout

geometry and the proximity of the process layers to the substrate produce parasitic capac-

itive couplings. The existence of such parasitics limits the charge pump performance and

efficiency. Moreover, the performance of a CP depends critically on how its MOS switches

are controlled. First of all, the overdrive voltage appliedto turn a switch on determines its

on resistance and drain-to-source voltage drop, which, in turn, affect the conversion effi-

ciency and voltage gain. In addition, the maximum and minimum voltages applied to the

switch gates affect the dynamic power losses and can be constrained by the device voltage

rating. Finally, precision and adjustability in controlling the switch affect the frequency

of operation (which trades off with the silicon area required for meeting design specifica-

tions) and can prevent short-circuit currents from nodes athigher voltages to nodes at lower

voltages during transitions (which affect efficiency).

Switch bootstrapping improves conduction during the on state by connecting a given

voltage between the gate and source terminals, typically byusing a capacitor pre-charged

34

Chapter 3.Design 35

during the off state [22]. Moreover, reusing some of the charges that are normally wasted

for charging and discharging parasitic capacitances at each cycle is a promising approach

for reducing power dissipation in charge pumps [11].

In this chapter, we analyze and discuss the design aspects ofintegrated voltage doubler.

First, the standard voltage doubler limitations are pointed out. Second, we propose a new

voltage doubler with a switch bootstrapping technique, where the voltages driving the gates

of nMOS and pMOS switches can be controlled both in terms of voltage swing and timing

such that limitations of standard voltage doubler are alleviated. The application of the

technique is demonstrated through the design of various voltage doublers. Also, dynamic

power losses due to parasitic capacitances are addressed and a method for reducing them

through charge reuse is described. Simulations of the various voltage doublers confirm the

effectiveness of the proposed techniques which result in animproved overall performance.

Technology and design constrains are addressed as well, anddesign trade-offs are discussed

in order to fine tune the circuit components.

3.2 Voltage Doubler

In the bootstrapped Dickson CP [2], switch voltage drop, varying on resistance, and low

conduction are alleviated by using four non-overlapping clock phases, which also prevent

short-circuit currents from nodes at higher voltages to nodes at lower voltages. This imple-

mentation needs the generation of four appropriate clock phases and MOS switches able to

withstand high voltages.

The output voltage ripple can be reduced by splitting the CP in two parts each with

half the total capacitance and feeding the load in a different half period [4] as depicted in

(2.24). This configuration, called double CP, is usually implemented as cascade connection

of voltage doublers [5], [6], which need only two clock phases instead of four. As shown

in Fig. 3.1, each modular stage is made of two latched CMOS pairs (N ′

i , P ′

i , Ni, Pi),

Chapter 3.Design 36

(

(

Figure 3.1: Conventional 2-phases cross-coupled voltage doubler stage.

two transfer capacitors (C ′

i, Ci), and two drivers (N ′

Di-P′

Di, NDi-PDi), and does not need

dedicated bootstrap drivers.Vi is the output voltage of thei-th stage andVi is the input

voltage. The transfer capacitors of each stage are alternately charged to the voltage of the

previous stage and then boosted byVDD to charge the next stage at a higher voltage. The

complementary voltage swings on the internal nodes are usedto control the switches of

opposite branches. Since the maximum voltage rise fromVi−1 to Vi is VDD, the voltage

across each device is never higher thanVDD and low voltage MOS switches can be used.

In steady state, the operation of the voltage doubler (Fig. 3.1) is as follows; during the

first half cycle,φ1 = VDD andφ2 = 0, transistorsNi, NDi, P′

i , andP ′

Di are on, and transistors

N ′

i , N′

Di, Pi, andPDi are off; transfer capacitorCi is charged toVi−1 throughNi andNDi,

while transfer capacitorC ′

i is boosted toVi−1+VDD throughP ′

i andP ′

Di. During the second

half cycle, and transistorsN ′

i , N′

Di, Pi, andPDi are turned on, and transistorsNi, NDi, P′

i ,

andP ′

Di are off; transfer capacitorC ′

i is charged toVi−1, while transfer capacitorCi is

boosted to charge next stage toVi−1 + VDD.

Chapter 3.Design 37

3.3 Losses and Efficiency

In slow-switching conditions, the main power losses of integrated charge pumps can be

simply classified into load-dependent losses, load-independent losses [23], and short-circuit

power losses of phase drivers and main pass transistors.

3.3.1 Load-Dependent Power Losses

When the load currentIO > 0, the output voltageVO of a voltage doubler withN stages

is reduced because of its non-zero equivalent output resistanceRO and can be expressed as

[1]

VO =

(

N

1 + β+ 1

)

· VDD −N · IO

(1 + β) · 2 · f · Ci

(3.1)

The voltage rise per stage∆V for a voltage doubler is

∆V =VDD

1 + β−

RO

N· IO . (3.2)

From (3.1), the maximum output current (i.e. whenVO = 0) IOmax is limited to

IOmax =N + 1 + β

N· 2 · f · Ci · VDD. (3.3)

In real implementations, the switches are designed with MOStransistors operating in

triode region. In particular, CMOS switches are turned on with an overdrive∆V − Vt (i.e.

for simplicity pMOS and nMOS switches are assumed to have thesame threshold voltage

Vt) and their on resistanceRON can be approximated as

RON =1

k · (∆V − Vt)(3.4)

wherek = µCoxW/L is the switch transconductance parameter. At high output cur-

rents, the overdrive voltage decreases according to (3.2) (i.e. ∆V becomes low). In these

Chapter 3.Design 38

conditions the on resistance of each switch increases and if∆V ≤ Vt the switches are off.

The CP output resistance given by

RO =N

(1 + β) · 2 · f · Ci

· coth

(

1

fCiRON

)

(3.5)

increases as well, thus making the load-dependent lossesPLD = ROI2O larger. Such losses

are particularly significant at high output currents and lowVDD, the maximum output cur-

rent IOmax in (3.3) is therefore reduced and a new maximum output current limit is ob-

tained. In other words, for the MOS switch to conduct in the triode region, it must satisfy

the relation

∆V ≥ Vt (3.6)

which imposes an upper bound onIO, and the maximum output current becomes

I ′

Omax = (VDD − (1 + β)Vt) 2fCi (3.7)

3.3.2 Load-Independent Power Losses

In integrated voltage doublers, load-independent power losses (also called dynamic or

switching losses) can be calculated through the non-zero equivalent input conductanceGI

as explained in Chapter 2, so that the corresponding power dissipation is approximated as:

PLI =α + β + αβ

1 + βfCT V 2

DD (3.8)

Accordingly, the load-independent power losses of a voltage doubler depend only onα

andβ, the switching frequency, the total capacitance, andV 2DD, and are independent from

the number of stages.

From the analysis in chapter 2, load-independent losses arethe major power losses at

Chapter 3.Design 39

Figure 3.2: 2-phases cross-coupled voltage doubler stage.

low currents. Therefore, based on the design specifications, minimizing load-independent

losses for voltage doublers meant to operate at maximum efficiency or at low currents is

a critical design consideration. From (2.21), (2.22), and (2.16), a limit condition when

load-independent losses in voltage doublers dominate is found and can be expressed as

IO ≤√

α + β + αβ ·fCTVDD

N. (3.9)

3.3.3 Short-Circuit Power Losses

In the conventional cross-coupled voltage doubler Fig. 3.2, each stage is seen as a CMOS

latch, the gates of switchesN ′

i ,−P ′

i andNi −Pi are driven by the voltage rise on nodesBi

andB′

i. At this point, three major cases of reversion and short-circuit losses are identified.

First, in the time slot during transitions when the voltage rise across the stage is higher

than the overdrive of pass transistorsNi or N ′

i (i.e. ∆V ≥ Vi−1 + Vt), a reversion current

flows fromCi or C ′

i back to nodeVi−1. Second, in the time slot during transitions when the

Chapter 3.Design 40

voltage rise across the stage is lower thanVi − Vt (i.e. ∆V ≤ Vi − Vt), pass transistorsPi

or P ′

i are partially on, causing a reversion current from nodeVi back toCi andC ′

i . Third,

the short time slot, when the CMOS pairsNi-Pi andN ′

i-P′

i are conducting simultaneously,

generates a short-circuit current from the higher-voltagenodeVi to the lower-voltage node

Vi−1. All these losses can degrade the CP efficiency and the outputvoltage [24]. The short-

circuit power consumption depends mainly on the voltage rise per stage∆V , the input

transition timeτ , the threshold voltageVt, and transfer capacitors(Ci, C′

i) [25]

PSC = PSC(k, Vt, ∆V, τ, f, Ci). (3.10)

Short-circuit losses are particularly significant at low output currents , when∆V is high

compared toVt, while they are negligible when

∆V ≤ 2Vt (3.11)

A limit condition on the output currentIO range where short circuit losses are signifi-

cant, can be obtained from (3.2) and (3.11)

IO ≤ 2 f Ci(VDD − 2 (1 + β) Vt) (3.12)

The problem can be alleviated by driving pMOS switches with level shifters generating

nonoverlapping control signals varying from 0 toVi [6] or by using two parallel stages

generating control signals varying fromVi−1 to Vi [8]. The problem can be solved by using

four nonoverlapping clock phases and bootstrapping the pMOS pairs [9] or by adding series

switches and using five phases [26].

Chapter 3.Design 41

Figure 3.3: Proposed bootstrapping technique applied to a voltage doubler stage.

3.4 Proposed Switch Bootstrapping Technique

The problem of the increased MOS on resistance (reduced driving capability) can be solved

by boosting the voltage driving the main CMOS switches with avoltage swing that does

not vary withIO [10], a solution that improves the driving capability at lowVDD, but does

not alleviate short circuit losses.

In order to prevent short-circuit currents and the reduced current driving capability ob-

served in the conventional voltage doubler, a new modular bootstrapping technique that

allows full control on MOS switches is proposed [27] and [28].

The circuit in Fig. 3.3, provides both control on the timing of the switch transitions

(therefore preventing short-circuit losses) and on the gate voltage swings (therefore im-

proving driving capability).

Having same pass transistors, transfer capacitors, drivers, and nonoverlapping phases as

the conventional one, the proposed circuit includes an nMOScross-coupled clock booster

Chapter 3.Design 42

(Nbi, N ′

bi, Cni, C ′

ni) driven byφ1 andφ2 and a pMOS cross-coupled clock booster (Pbi,

P ′

bi, Cpi, C ′

pi) driven byφ1 andφ2. Short-circuit losses are prevented because the volt-

ages applied between the gate and source terminals of pairsNi - N ′

i andNDi - N ′

Di have

nonoverlapping transition times with both voltages low, whereas the gate-to-source volt-

ages of pairsPi - P ′

i andPDi - P ′

Di have complementary transition times with both voltages

high.

The timing of switch transitions and the nonoverlapping slots can be adjusted by con-

trolling the main clock phases. The amplitude of the gate voltage swings does not depend

on output current or number of stages and is controlled by thelow and high levels of the

main phases, typically varying from 0 toVH = VDD. The corresponding voltage control-

ling Ni andN ′

i goes fromVi−1 (off) to Vi−1 + VH (on) and the voltage controllingPi and

P ′

i goes fromVi − VH (on) toVi (off). In steady state, the maximum voltage across any

switch isVDD and internal voltages are within the range from 0 to the maximum CP output

voltage.

3.5 Charge Reuse Technique

Since load-independent losses due to parasitic capacitances have a strong impact on con-

version efficiency. Dynamic power losses can be reduced by reusing some of the charges

wasted in charging or discharging the parasitic capacitances each cycle [11], [20]. In partic-

ular, if we consider those internal nodes of a voltage doubler that are connected to ground

through a switch at every cycle and have complementary voltage swings, the parasitic ca-

pacitances associated with them are charged to a certain voltage and then discharged to

0, therefore a part of that charge can be reused (and therefore the input conductance is

reduced). This can be accomplished if we redirect some of thecharges wasted at falling

nodes to charge parasitic capacitances at rising nodes before each switch event.

To that end, switches driven by appropriate control signalsare used to equalize the

Chapter 3.Design 43

voltages of the parasitic capacitances. The time required by this operation is much smaller

than the time needed for charging the transfer capacitors, because only a small fraction

(e.g.α, typically 1.5% to 20%) of the capacitance is involved and equalization switches

are sized to complete charge reuse within each nonoverlapping time slot. Therefore, the

time allocated for the equalization has a limited impact on the voltage doubler operation.

Furthermore, the control signal can be generated through a NOR gate directly from the

nonoverlapping control phases that are already needed to avoid short-circuit losses.

3.5.1 Charge Reuse Voltage Doubler Design

The design of a voltage doubler stage with charge reuse is shown in Fig. 3.4. The parasitic

capacitancesαCi andαC ′

i are alternately charged toVDD and discharged to 0. The equal-

ization switch controlled by a NOR circuit brings both capacitances toVDD/2 before each

switch event, therefore the amount of charges drawn from thepower supply for charging

parasitic capacitances is half the amount needed by the conventional circuit. As a conse-

quence, charge reusing can reduce the load independent losses by a factor two. Circuit

analysis confirms that the input conductance of the voltage doubler CPs with charge reuse

is half that of conventional voltage doubler CPs:

G∗

I = fCT ·α + β + αβ

2 (1 + β), (3.13)

while the voltage gainA and the output resistanceRO are unchanged.

3.6 Design Constrains

The design of efficient and high performance CPs is usually associated with several design

concerns that need to be addressed. Design considerations on MOS switches and boot-

strapping circuits play an important role in the proper operation of the charge pump.

Chapter 3.Design 44

Figure 3.4: Bootstrapped voltage doubler stage with chargereuse.

3.6.1 MOS Switches

The use of MOS transistors as switches requires that switches are designed appropriately.

MOS switches with a large aspect ratio are required mainly for three reasons. First, large

switches (i.e. with low on resistancesRON ) reduce resistive power losses. Second, to ensure

a small time constant (i.e. fast transient) of the charge transfer paths, large switches are

needed. Third, charge pumps require large switches if they have to deliver large currents.

In addition, the maximum switching frequencies at which a charge pump can operate

depend on the time constants of the individual stages. Each stage can be viewed as an

RC network, which needs MOS switches to have a relatively low onresistances so that

capacitor voltages can settle within the clock semi-period. Therefore, a number of time

constants within the half clock cycle are required for a complete charge transfer, and the

following relation must hold:

Chapter 3.Design 45

TON >> RON · Ci (3.14)

A frequency increase requires a reduction in the on-resistance of transfer switches,

which can be obtained by increasing the transistors aspect ratios(W/L), which also re-

quires larger drivers to maintain sharp transitions, and call for longer nonoverlapping time

(due to larger gate capacitance and, hence, transition times). This increases the contribu-

tions of the switches parasitic capacitances that adds to the capacitor parasitics, and, hence,

reduces the voltage gainA, increases the dynamic power losses, and reduces the efficiency.

3.6.2 Bootstrapping Circuit

A key design issue of the proposed circuit involves sizing the boosting capacitor adequately

to bootstrap the gate of the pass transistors with the required overdrive voltage. The boosted

voltage on the gate of the pass transistor is reduced becauseloading capacitanceCload

(here we refer to MOS pass transistor capacitances and otherparasitic capacitances) share

a portion of the charge. The added bootstrapping circuits are not on the primary charge

transfer path. However, these capacitors must be able to supply sufficient voltage swing to

the gate of the pass transistor and other parasitic capacitances. The boosted voltage can be

expressed as

Vg = Vi−1 + VDD

CN

CN + Cload

. (3.15)

In this design, the values of the bootstrapping capacitorsCN are approximately 10 times

Cload. This ensures that corresponding voltages controlling pass transistors are within the

required range. Furthermore, the precharge transistors (Nbi, N ′

bi,Pbi, P ′

bi) allow bootstrap-

ping capacitors to be charged to the required voltage level.The time required for such

operation (RC delay) is much less than the time required for charging transfer capacitors,

because bootstrapping capacitors are small and depend mainly on the gate size of the pass

Chapter 3.Design 46

transistor. Therefore, the area of precharge transistors is small as well.

3.6.3 Design Trade-Offs

To achieve satisfactory functional and performance results of the proposed design, several

Spectre simulations were performed in the 0.18-µm technology. Fine tuning of the voltage

doubler components such as pass transistors and bootstrapping capacitor sizes was done to

maximize efficiency and reduce area.

Fig. 3.5 demonstrates the maximum efficiency of a one-stage voltage doubler as a func-

tion of the width of the pass transistors. In this design, thewidth of pMOS pass transistors

is scaled with respect to the width of nMOS pass transistors according to the mobility ratio

µn/µp, which is about 2.5. At smaller transistors widths, the maximum efficiency is limited

by the high on resistance of the switches. On the other hand, increasing the width of the

switches gives rise to dynamic power losses due to the intrinsic parasitic capacitances of

the switches.

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0 20 40 60 80 100 120 140 160 180

Ma

xE

ffic

ien

cy

Pass transistor width ( m)m

Figure 3.5: Maximum efficiency versus transistor width for avoltage doubler whenN = 1,VDD = 1.8 V,f = 10 MHz,CT = 250 pF,α = 0.015, andβ = 0.01.

Fig. 3.6 shows the maximum efficiency of a one-stage voltage doubler as a function of

Chapter 3.Design 47

the bootstrapping capacitor size. As the bootstrapping capacitor size increases, the max-

imum efficiency increase. Further increase in the bootstrapping capacitor size will result

in an increased area occupation and reduced maximum efficiency since larger drivers are

required to drive these capacitors and the associated parasitics.

0

10

20

30

40

50

60

70

80

90

0.1 1 10 100

Ma

xE

ffic

ien

cy

Capacitance (pF)

Figure 3.6: Bootstrapping capacitor size versus the maximum efficiency.

3.7 Technology Constrains

In this section, we examine issues related to design and implementation of fully integrated

voltage doublers in standard CMOS process. While in off-chip implementations the critical

design constraints are number of discrete components and board complexity, in on-chip re-

alization the key cost constraint is silicon area occupation. The area allocated to integrated

capacitors and switches depends on technological parameters, design specifications, and

layout optimization. However, technology limitations, some of which are pointed out in

this section, determine the integrated devices characteristics.

Chapter 3.Design 48

3.7.1 Integrated Capacitors

In a digital CMOS technology, capacitors are made by superimposition of conductive and

dielectric layers such as polysilicon, metal, or diffused layers and dielectric layers of sili-

con dioxide (SiO2) or silicon nitride (Si3N4). The performance of a charge pump depends

critically on the properties of integrated capacitors, andin particular on parasitic capaci-

tances (expressed by the technological parametersα andβ), equivalent series resistance,

and capacitance per unit area.

Metal-metal capacitors can be constructed in an interleaved configuration to maximize

the capacitance utilization between available metal layers. To be more specific, capacitors

constructed with metal layers have a much smaller series resistance (hence time constant)

and can therefore operate at higher frequencies [29]. However, the specific capacitance of

metal-metal structures in standard CMOS processes is low, because metal layers for inter-

connections are separated by thick oxide layers (e.g. 1.35µm in the considered technology)

to have minimal capacitive couplings. Such constraint limits the capacitance that can be

integrated in a reasonable silicon area and ultimately limits the CP driving capability. In

addition, metal-metal capacitors have high parasitic coupling to the substrate with respect

to the specific capacitance (up to20%) and the parasitic capacitancesαCi andβCi are

particularly high when the distance between the utilized metal layers and substrate is low.

MOS capacitors are constructed between a polysilicon layerand a diffused layer. These

layers are separated by a thin oxide layer (e.g. 4.1 nm in the considered technology) and the

capacitance per unit area is very high. The capacitance value that can be built in a specific

area depends on the technological parameterCox (the capacitance per unit area of the gate

oxide) multiplied by the gate area [30]. The voltage dependence of the gate-to-channel

capacitance is limited for the considered design range. Theeffect of the gate-to-source

voltage on the gate-to-channel capacitance is shown in Fig.3.7. The stray parasitic capac-

itancesαCi (between doped silicon and substrate) andβCi (between the polysilicon layer

and the substrate) associated with capacitorCi are lower than other available structures. To

Chapter 3.Design 49

Figure 3.7: CV curve of nMOS capacitor (Spectre simulation).

Figure 3.8: Equivalent series resistance of MOS capacitor.

realize a specific capacitance value, both the lengthL and the widthW of the polysilicon

layer are scaled. As a result, the related parasitic resistance, known as equivalent series

resistance, arises from both the gate sheet resistanceRg and the channel resistanceRch.

The ESR of a MOS capacitor is shown in Fig. 3.8 and is given by [31]

ESR ≈Rch

4+ Rg. (3.16)

The polysilicon gate resistance can be expressed as

Rg = R

W

L(3.17)

Chapter 3.Design 50

whereR is the polysilicon sheet resistance. The channel resistance can be approxi-

mated with

Rch =L

µCoxW (VGS − Vth)(3.18)

To this end, any large integrated capacitor is usually constructed as a set of parallel

optimal units to minimize the related ESR. Given a specific capacitance area the number of

required parallel devices and their geometry can be found byconsidering the derivative of

(3.16) and setting it equal to zero. This procedure not only reduces resistive power losses,

but also improves the intrinsic time constant of the MOS capacitors used in this design.

3.7.2 Bulk Biasing

Beside the higher carrier mobility, nMOS switches share thesame substrate, therefore PN

junctions are always reversed biased. A problem with the pMOS switches is that lower

n-well potential results in a current loss injected into thesubstrate. The problem can be

alleviated by switching the bulk of pMOS switches to the higher voltage between source

and drain [6]. The voltage doubler shown in Fig. 3.9 includesan additional circuit to bias

the bulk of the pMOS switches. The bulk biaser circuit is constructed with the auxiliary

pMOS switchesPS, P ′

S, and the capacitorCS to keep the bulk of the main pMOS switches

at voltage levelVS ≥ VO. This is important when a small load capacitorCL is used or a

large output current is delivered, since the voltage ripplewill increase according to (2.24).

Also, it should be noted that minimum-sized devices are usedbecause the biasing capacitor

CS is not connected to the load.

Chapter 3.Design 51

C C'

P'

PN

N'VDD

CL

f1 f2

0

0

CS

PS

P’S

0

RL

VO

Figure 3.9: 2-phases cross-coupled voltage doubler stage with dynamic bulk biasing forpMOS switches [6].

3.8 Design of CP’s Auxiliary Circuits

3.8.1 Clock Generation Circuit

An external 50% duty-cycle reference clock cannot usually be utilized directly, but it is used

as an input for a clock generator, which produces the nonoverlapping clock signals. The

timing of switch transitions and the nonoverlapping slots depend on the clock generation

circuit shown in Fig. 3.10. Such circuit is simple and includes only cross-coupled NAND

gates, inverters, and even number of delay blocks. Each delay block is conceived by means

of an inverter and a voltage-controlled RC network that consists of a transmission gate and

an nMOS capacitor. Nonoverlapping time slots of the generated phases (φ1 andφ2) depend

mainly on the low to high and the high to low propagation delays through the cascaded

delay blocks. For this design, to ensure enough time to control the switches, a longer

nonoverlapping time has been favored in order to prevent short-circuit power losses in the

drivers and main pass transistors. Nonoverlapping time wasalso controlled via an external

DC voltage to control the resistance of the transmission gate in the RC network and the

corresponding nonoverlapping time.

Chapter 3.Design 52

Figure 3.10: Nonoverlapping clock generation scheme (detailed schematic is shown inAppendix A).

Figure 3.11: A CMOS inverter driver with tapering factor 4 (detailed schematic is shownin appendix A).

3.8.2 Inverter Driver Circuit

Large transfer switches and related interconnects presenta large capacitive load on the

clock phases path, therefore clock drivers are necessary tomaintain sharp transitions and

reduce short circuit losses. To increase the energy efficiency of a charge pump, drivers

are designed so that the power dissipation in the driver chain is minimized. Designers

often choose low-power tapered driver chains, which are constructed with cascaded inverter

stages whose sizes increase progressively by a scaling factor S, as an example, stages are

scaled withS = 4 to minimize the power delay product as shown in Fig. 3.11. In each

inverter stage, pMOS transistors are scaled with respect tothe nMOS transistors according

to the mobility ratio [32]. As a result, the output transitions of each inverter have equal rise

and fall time delay.

Chapter 3.Design 53

3.9 Summary

This chapter discusses the fundamental design constraintsof integrated voltage doublers.

Integrated devices capabilities and associated power losses in conventional designs are ad-

dressed with focus on resistive, dynamic, and short-circuit power losses. With all these

design aspects in mind, a new switch bootstrapping technique is proposed to overcome

these limitations and prevent short-circuit losses, improve driving capability, and enhance

the overall conversion efficiency. Furthermore, a charge reuse technique is applied with

the result of reducing the dynamic power losses. Design and technology constrains are

discussed to optimize design parameters.

Chapter 4.Results

Chapter 4

Results

4.1 Introduction

This chapter presents the simulation results, prototype implementation, and experimental

results of the integrated voltage doublers. First, key simulation results of the designed

voltage doublers are shown and discussed at nominal process(TT), supply voltage (1.8 V)

and temperature (27C). The clock signal applied is increased from 1 MHz to 10 MHz.

This frequency range indicates a design trade-off requiredto meet the design specifications

within a reasonable silicon area, operating at lower frequencies reduces the dynamic power

losses while increasing the frequency scales up the output current that the voltage doubler

can deliver. In addition, the design implementation and thetest method used to character-

ize the design are discussed in details. Finally, the performance of the fabricated voltage

doublers is presented and explained. Measured and simulated results are compared.

4.2 Simulation Results

This section presents key simulations and their results so as to provide a functional and

performance reference for the fabricated chip. To verify the improvements achieved by the

proposed switch bootstrapping technique and the charge reusing technique, voltage dou-

54

Chapter 4.Results 55

(a) One-stage latched voltage doubler.

(b) Two-stage latched voltage doubler.

Figure 4.1: Schematic diagrams of the conventional voltagedoublers.

blers with the proposed techniques (Fig. 4.2) are simulatedand compared with conventional

voltage doublers (Fig. 4.1). The simulated circuits are designed in 0.18-µm technology with

3.3 V devices and can be summarized as follows:


(a) One-stage bootstrapped voltage dou-bler.

(b) Two-stage bootstrapped voltage doubler.

(c) Two-stage bootstrapped voltage doubler with charge reuse.

Figure 4.2: Schematic diagrams of the proposed voltage doublers.


• One-stage latched voltage doubler (Fig. 4.1(a)).

• Two-stage latched voltage doubler (Fig. 4.1(b)).

• One-stage bootstrapped voltage doubler (Fig. 4.2(a)).

• Two-stage bootstrapped voltage doubler (Fig. 4.2(b)).

• Two-stage bootstrapped voltage doubler with charge reuse (Fig. 4.2(c)).

To have a fair comparison, all voltage doublers are designedunder same specifications

which include 262.5 pF stage capacitance, 1.8 V supply voltage, same clock frequency,

and the same sizes of charge transfer switches. Moreover, each voltage doubler has the

following building blocks as shown in Fig. 4.3:

Clock

GenerationDrivers

Charge

PumpGlobal

Clock

VO

VDD VDD VDD

0 0 0 0

Load

IOf1

f2

f1

f2

f1

f2

f1

f2

Figure 4.3: Charge pump block diagram.

• Non-overlapping clock generation circuit.

• Drivers.

• Charge pump core.

4.2.1 Steady-State

Conversion efficiency, output characteristics, and input power consumption are evaluated in

steady-state conditions. The conversion efficiency is calculated as the average output power

divided by the average input power including the power dissipation of the drivers and the


nonoverlapping clock generation circuits. The simulated output resistance is calculated as

the change in the average output voltage divided by the corresponding change in the output

current.

(a) Output characteristics.

(b) Conversion efficiencies.

0

2

4

6

8

10

12

14

16

18

20

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

Inp

ut

po

we

r%

Load current (mA)

Input power

(c) Improvement in input power

Figure 4.4: Output characteristics, conversion efficiencies, and input power improvementof a one stage latched and bootstrapped voltage doublers as afunction of the output currentIO, whenN = 1, VDD = 1.8 V, f = 1 MHz, CT = 262.5 pF,α = 0.015, andβ = 0.01(Spectre simulations).

4.2.1.1 One-Stage Voltage Doublers Comparison

Performance of the one-stage bootstrapped voltage doubler(Fig. 4.2(a)) and the one-stage

latched voltage doubler (Fig. 4.2(a)) is compared. Both voltage doublers are designed to

achieve a voltage gain ofA = 2 and to deliver an output currentIO from 0 A to 2 mA.




(c) Improvement in input power.

Figure 4.5: Output characteristics and conversion efficiencies of a one stage latched andbootstrapped voltage doublers, and savings in input power due to switch bootstrapping asa function of the output currentIO whenN = 1,VDD = 1.8 V,f = 10 MHz,CT = 262.5 pF,α = 0.015, andβ = 0.01 (Spectre simulations).

Fig. 4.4(a) and Fig. 4.5(a) present the simulated output characteristic at 1 MHz and 10

MHz, respectively. Simulation results show that the bootstrapped voltage doubler gives an

open-circuit output voltage of 3.58 V, as compared 3.57 V provided by the latched voltage

doubler because of the smaller top plate parasitic capacitanceβC in the bootstrapped volt-

age doubler. The simulated output resistance is nearly constant (RO = 3.81 kΩ), while the

output resistance of latched voltage doubler increases significantly (because of the surge

in on resistance of the pass transistors) when the load current is high enough to reduce

the value of∆V , with the output voltage dropping to zero when∆V < Vt. The conver-


sion efficiency as a function of the load current is shown in Fig. 4.4(b) and Fig. 4.5(b) for

both voltage doublers at 1 MHz and 10 MHz, respectively. The maximum efficiency of

the bootstrapped voltage doubler is82.02% whenIO = 90 µA at f = 1 MHz and80.67%

whenIO = 0.9 mA atf = 10 MHz, while the maximum efficiency of the latched voltage

doubler is81.84% whenIO = 90µA at f = 1 MHz and80.53% whenIO = 0.9 mA atf =

10 MHz. At any frequency, the efficiency of the bootstrapped doubler is improved at both

low and high load currents. At low output current, the maximum improvement in the input

power consumption is about17% whenIO = 0 as shown in Fig. 4.4(c) and Fig. 4.5(c) be-

cause short-circuit losses are prevented and parasitic capacitances of the pass transistors do

not increase the value ofβ at the voltage doubler internal nodes. At high load current,the

efficiency is significantly improved as well because of the nearly constant output resistance.

4.2.1.2 Two-Stage Voltage Doublers Comparison

Two-stage bootstrapped voltage doubler (Fig. 4.2(b)) and two-stage latched voltage doubler

(Fig. 4.1(b)) are designed and simulated. Both voltage doublers are designed to have a

voltage gain ofA = 3 and deliver an output currentIO from 0 A to 2 mA. Fig. 4.6(a) and Fig.

4.7(a) compare the variation of the output voltage as function of the load currentIO for the

two voltage doublers. The maximum output voltage is 3.59 V for the bootstrapped voltage

doubler and 3.54 V for the latched voltage doubler (indeed, the parasitic capacitances of the

bootstrapped voltage doubler is slightly smaller because the gate capacitance of the pass

transistors are not connected to internal nodes on the charge transfer path). It is also seen

that the bootstrapped voltage doubler is able to guarantee aconstant value ofRO (∼ 8.51

kΩ at f = 1 MHz, and∼ 831Ω at f = 10 MHz) for the whole output current range, while

the output resistance of the conventional voltage doubler significantly increases for higher

output currents as a consequence of the increasedRON of transfer switches.

The efficiency as a function of the load current is shown in Fig. 4.6(b) and Fig. 4.7(b)

for both voltage doublers at 1 MHz and 10 MHz, respectively. The maximum power effi-




(c) Input power improvement.

Figure 4.6: Output characteristics and conversion efficiencies of a two stage latched andbootstrapped voltage doublers, and savings in input power due to switch bootstrapping asa function of the output currentIO whenN = 1, VDD = 1.8 V, f = 1 MHz, CT = 525 pF,α = 0.015, andβ = 0.01 (Spectre simulations).

ciency of the bootstrapped voltage doubler is about77.36% at IO = 80µA andf = 1 MHz

and76.47% at IO = 0.8 mA andf = 10 MHz, while the maximum efficiency of the latched

voltage doubler is77.21% whenIO = 80µA at f = 1 MHz and75.57% whenIO = 0.7 mA

at f = 10 MHz. For higher values ofIO, the proposed solution guarantees a better energy

efficiency. At lowIO the input power of the proposed circuit is reduced as well, because

short-circuit losses are absent as shown in Fig. 4.6(c).




(c) Improvement in input power.

Figure 4.7: Output characteristics and conversion efficiencies of a two stage latched andbootstrapped voltage doublers, and savings in input power due to switch bootstrapping asa function of the output currentIO whenN = 1, VDD = 1.8 V,f = 10 MHz,CT = 525 pF,α = 0.015, andβ = 0.01 (Spectre simulations).

4.2.1.3 Voltage Doubler with Charge Reuse

To evaluate the impact of charge reuse technique, a two-stage bootstrapped voltage doubler

with charge reuse was designed as shown in Fig. 4.2(c) and compared to the two stage volt-

age doubler in Fig. 4.2(b). The output characteristic and efficiency comparison for different

load conditions are shown in Fig. 4.8 and Fig. 4.9 at 1 MHz and 10 MHz, respectively. The

simulated output characteristics for both voltage doublers are the same, because thef · CT

product and the number of stages are not changed.

The simulated conversion efficiency of the two-stage bootstrapped voltage doubler and




Figure 4.8: Output characteristics and conversion efficiencies of a two stage bootstrappedvoltage doubler and bootstrapped voltage doubler with charge reuse as a function of theoutput currentIO, whenN = 2, VDD = 1.8 V, CT = 525 pF,f = 1 MHz, α = 0.015, andβ = 0.01 (Spectre simulation).

of the two-stage bootstrapped voltage doubler with charge reuse as a function of the load

current is shown in and Fig. 4.8(b) and Fig. 4.9(b) for both voltage doublers at 1 MHz

and 10 MHz, respectively. The efficiency of the bootstrappedvoltage doubler with charge

reuse is improved at low and moderate load currents. The reduction of load-independent

losses for the voltage doubler with charge reuse is about 30%. Charge reusing improves

the overall conversion efficiency substantially because a significant portion of the charges

normally wasted through parasitic capacitances is reused.The maximum efficiency of

the charge reuse voltage doubler is80.77% at f = 1 MHz and79.83% at f = 10 MHz.

However, the overall reduction in load-independent lossesis less than the theoretical 50%

reduction, because there are diminishing effects caused byadditional power losses from the

charge reuse circuit. The short-circuit current occurs in the charge reuse path and the small

amount of parasitic capacitance added by the equalization switch contribute to the overall




Figure 4.9: Output characteristics and conversion efficiencies of a two bootstrapped voltagedoubler and bootstrapped voltage doubler with charge reuseas a function of the outputcurrentIO, whenN = 2,VDD = 1.8 V,CT = 525 pF,f = 10 MHz,α = 0.015, andβ = 0.01(Spectre simulation).

current consumption.

4.2.2 Transient Analysis Results

4.2.2.1 Rise Time

The start-up time of the proposed voltage doubler and the latched voltage doubler are pre-

sented with the transient analysis in Fig. 4.10, which showsthe output voltage as a function

of time. The start-up time is defined as the time taken to boostthe output terminal up to

90% of the target voltage and depends on output resistance and total capacitance of the CP,

and the load capacitance. The start-up time is evaluated by setting the initial condition of all

capacitors to 0 V. The comparison is made with a target voltage of 5.4 V, a supply voltage

of 1.8 V, and a 1 nF capacitive load. A significant advantage ofthe proposed voltage dou-

bler is the faster rise time of the output voltage at the start-up, the simulated start-up for the


Figure 4.10: Start-up transient with 1 nF capacitive load (two-stage charge pump,VDD =1.8 V, andf = 10 MHz) (Spectre simulation).

two-stage bootstrapped voltage doubler is 2.26µs against 4.26µs for the two-stage latched

voltage doubler, i.e. the rise time of the bootstrapped doubler is reduced by 47% com-

pared to the conventional one. The improvement in start-up time results from the smaller

on resistance of the bootstrapped switches, because the switches have gate voltage swings

varying from 0 toVDD.

Figure 4.11: Energy consumption versus output current (IO) of a latched and bootstrappedvoltage doublers with 1nF capacitive load (two-stage charge pump,VDD = 1.8 V, f = 1MHz) (Spectre simulation).

Energy consumption as a function of the output currentIO for the proposed and the

conventional voltage doublers is shown in Fig. 4.11. Here, the energy consumption is

calculated as the integral of the power consumed by the charge pump during the start-up


time, i.e. when capacitors are discharged and the voltage increases from 0 V to90% of the

target voltage. The energy consumption of the bootstrappedvoltage doubler is independent

of the load current because a given voltage is applied between the gate and source terminals

of the switches, thus making their on resistance constant and the corresponding start-up

time faster.

Switch bootstrapping not only improves steady-state performance of voltage doublers,

it also enhances their dynamic behaviour by reducing the start-up time which significantly

contribute in reducing the related energy consumption.

Figure 4.12: Simulated waveforms of the current drawn from the power supply of theproposed charge reuse bootstrapped charge pump and the bootstrapped charge pump (two-stage charge pump,VDD = 1.8 V,f = 10 MHz) (Spectre simulation).

4.2.2.2 Charge Reuse

Simulated supply current waveforms of the charge reuse bootstrapped voltage doubler and

the conventional voltage doubler are shown in Fig. 4.12. A current saving is achieved by

charge reuse voltage doubler, where the peak current level of the charge reuse voltage dou-

bler is about 19 mA while it is about 27 mA for the conventionalvoltage doubler (i.e. here

we refer to the bootstrapped voltage doubler shown in Fig. 4.2(b)). Furthermore, the time


Table 4.1: Devices available in the fabrication technology.

Symbol Device name Description

1.8 V nMOS transistorMinimum featurel = 0.18µm, nomi-nal threshold voltageVt ≈ 0.53 V

1.8 V pMOS transistorMinimum featurel = 0.18µm, nomi-nal threshold voltageVt ≈ -0.53

3.3 V nMOS transistorMinimum featurel = 0.35µm, nomi-nal threshold voltageVt ≈ 0.59 V

3.3 V pMOS transistorMinimum featurel = 0.3µm, nominalthreshold voltageVt ≈ -0.71 V

3.3 V nMOS capacitor Cox ≈ 5.4 fF/µm2

duration of the current peak is smaller in the charge reuse current waveform. As a result,

the area under the current waveform which represents the average current consumption is

reduced as well, therefore reducing the overall current drawn from the power supply.

4.3 Prototype Implementation

4.3.1 Fabrication Technology

The voltage doublers are designed and fabricated in a TSMC 0.18-µm CMOS process

(nominal supply voltages are 1.8 and 3.3 volts), with a single polysilicon and 6-metal layers,

including MIM capacitor and deep n-well layer options. The core area is 1.5 mm× 0.66

mm = 1 mm2, and the total area including bonding pads is 1.5 mm× 1 mm = 1.5 mm2. The

chip area is dominated by the area occupied by integrated capacitors. Since the circuit’s

target is to generate an output voltage higher than the supply voltage, high voltage devices

are needed. The technology offers a thick oxide layer that increases the breakdown voltage

limit of the transistors making this technology suitable tothe design. Devices used in the

design of the voltage doublers are described in Table 4.1.


Figure 4.13: Diagram of the analog design flow used in the design (adapted from CMC).

4.3.2 Tools and Design Flow

Mathematical functional verification is performed with Mathematica software at an early

stage of the design as explained in the analysis in Chapter 2.To achieve satisfactory func-

tional and performance results, transistor level schematics are created in Cadence Com-

poser and Spectre circuit simulator is used to simulate and optimize the design. The chip

layout is drafted using Cadence Virtuoso. After completingthe design of the layout, Men-

tor’s Calibre tool is used in coordination with the layout editor for physical verifications

purposes. Design rule check (DRC) is performed to avoid violations against all design

rules. Layout Versus Schematic (LVS) is carried out to ensure that the netlists created by

the schematic match the extracted netlist from the layout. To ensure success of the design


process, the analog design flow shown in Fig. 4.13 is followed.

4.3.3 Test Setup Realization

Test issues including packaging, test fixture, and equipment setup are considered during

the design in order to characterize and measure the integrated voltage doublers parameters

such as voltage gain, output resistance, current consumption, and energy efficiency.

Figure 4.14: Photograph of the 24-pin CFP package containing the fabricated chip.

4.3.3.1 Package

Since the designed circuits need to be connected to test equipment by placing the packaged

chip on a test board, the decision on packaging has a strong impact on the design perfor-

mance, testability, and board fixturing. The die was packaged in 24-pin CFP (Ceramic Flat

Package) from Spectrum Semiconductor, Inc as shown in Fig. 4.14. The packaging choice

was considered during the design process based on the numberof pins that are required for

the designed circuits, the area allocated for the die, and the slightly better package para-

sitics (i.e. about 2.5 nH) compared to the 44-pin CFP alternative which has the drawback

of longer leads, larger size, and therefore worse parasitics. A technical drawing of the used


package is shown in Appendix A in Fig. A.6.

Figure 4.15: Layout of the designed test board.

4.3.3.2 Test Fixture

After the selection of the appropriate package, a test fixture was developed to connect

the packaged chips to the test equipment. The test board was designed using EAGLE

PCB-Design software considering footprints of package andoff-chip components to ensure

the design testability and the input and output requirements for the designed circuits (Fig.

4.15). A one layer FR4 dielectric test board with a minimum 1.34 mil trace was fabricated

for the device under test. To maintain constant supply voltages, all input voltage supplies

were heavily decoupled by placing large through hole capacitors (e.g. 1µF). Moreover,

1 nF ceramic output capacitors were added to the board to create load capacitances for

the designed voltage doublers. The 24-pin CFP packaged device was interfaced to SMA

connectors by soldering the connectors on the test board in order to provide clock signals

for the circuits. For mechanical support purpose, the packaged chip was placed in a central

recess in the test board and clamped into place by using a translucent plastic clamp.


Figure 4.16: Block diagram of the experimental setup.

4.3.3.3 Equipment Setup

A test setup as shown in Fig. 4.16 was used. Square wave inputswere generated using

a BK Precision 4040A function generator to provide the clocksignal to the chip. The

output voltage of each voltage doubler was captured using a Tektronix DPO7104 digital

oscilloscope, capable of capturing waveforms measurements (i.e. amplitude, rise time,

mean value, etc.). An Agilent E3630A DC power supply was usedto provide a reference

voltage for the clock generation circuits in order to control the nonoverlapping time. A

Keithley 2602 source meter was utilized because it providesboth measuring and sourcing

capabilities in DC with very high accuracy and has a Test Script Processor (TSP). Channel

A was configured as a DC input voltage source and a current meter, while channel B was

configured as a DC output current source and a voltage meter. To conduct tests, a host

PC (controller), was programmed to send sequences of commands to the Keithley source

meter, which, in turn, executed the commands and returned the captured data to the host

PC.

4.3.4 Layout Considerations

Layout is very important in high performance charge pumps. The analog (voltage doublers

core) and digital (clock generation and drivers) power supplies were connected to their


Figure 4.17: Chip design layout.

own separate pads circuitry with wide metal lines. Empty areas were filled with nMOS

capacitors and connected to the closest power supply to act as decoupling capacitors. The

large MOS switches were laid out in an interdigitated fashion with multiple contacts to

reduce parasitic capacitances and resistances. To preventlatch-up, double guard rings were

placed surrounding each MOS switch. Fig. 4.17 shows the layout of the designed circuits

and their pads arrangement which can be summarized as follows:

• Two-stage bootstrapped voltage doubler without bulk biasing (circuit 1).

• One-stage bootstrapped voltage doubler (circuit 2).

• Two-stage bootstrapped voltage doubler (circuit 3).

• Two-stage bootstrapped voltage doubler with charge reuse (circuit 4).

• One-stage latched voltage doubler(circuit 5).

• Two-stage latched voltage doubler (circuit 6).

Circuit 1 to circuit 6 power supplies were fed through padsVDD1 to VDD6, clock signals

were fed through padsCLK1 to CLK6, and output voltages were connected to padsVO1


to VO6, each corresponding to one circuit. PadsCKP156 andCKP234 were connected as

power supplies for the digital blocks of circuit 1, circuit 5, and circuit 6, and of circuit

2, circuit 3, and circuit 4. Moreover,V REF156 andV REF234 were used as a reference

voltage for the clock generation blocks of circuit 1, circuit 5, and circuit 6, and of circuit 2,

circuit 3, and circuit 4.

Figure 4.18: Microphotograph of the design; the chip size is1 mm× 1.5 mm.

4.4 Experimental Results

Microphotograph of the fabricated voltage doubler is shownin Fig. 4.18. An enlarged

microphotograph of the different building blocks in the one-stage bootstrapped voltage

doubler (circuit 2 in Fig. 4.17) is also shown in Fig. 4.19. Tovalidate the design and

simulation results, the fabricated voltage doublers were characterized and the measured

results were compared with the simulation results. All measurements were carried out with

an external load capacitor of 1 nF and a clock frequency of about 1 MHz.

The measured output characteristic of the two-stage bootstrapped voltage doubler at a


Figure 4.19: A microphotograph showing circuits designed in a one stage bootstrappedvoltage doubler.

supply voltage ofVDD = 1.8 V is shown in Fig. 4.20(a). The measured output resistance

is 7.49 kΩ, which is compared with a calculated value of 7.62 kΩ. The experimental

results show that the two-stage bootstrapped voltage doubler gives an open-circuit output

voltage of 5.395 V, very close to the output voltage of 5.388 Vprovided by simulation

results. Moreover, the output voltage shows a linear decline with the load current because

of the almost constant output resistance. The measured efficiency as a function of the load

current is shown in Fig. 4.20(b), and as expected from simulations the maximum efficiency

is 78.4% at IO = 90µA.

Fig. 4.21(a) shows the measured output characteristics forthe two-stage bootstrapped

voltage doubler with charge reuse which is equivalent to theoutput characteristics of the

two-stage bootstrapped doubler. The open circuit output voltage at a supply voltage of

VDD = 1.8 V is 3.593 V. The measured output resistance forf = 1 MHz is about 7.46

kΩ. The measured efficiency is shown in Fig. 4.21(b), the maximum measured efficiency

is 80.01% at IO = 80 µA. Improvement in input power consumption of the charge reuse

bootstrapped voltage doubler with respect to the bootstrapped voltage doubler is shown in


0

1

2

3

4

5

6

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4V

O(V

)

Load current (mA)

Simulated

Measured

(a) Output characteristic.

0

10

20

30

40

50

60

70

80

90

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Eff

icie

ncy

Load current (mA)

Simulated

Measured

(b) Efficiency.

Figure 4.20: Measured and simulated output characteristicand conversion efficiency of afully integrated two stage bootstrapped voltage doubler asa function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz.

Fig. 4.22. The maximum measured power savings are found to be14% at IO = 0 A. The

difference between the measured power savings and the simulated ones (i.e. a maximum

power savings of30%) is due to the short nonoverlapping time, which, in turn, affects the

time required to equalize the voltages of the parasitic capacitances, and therefore results in

a larger average power consumption.

On the other hand, measured output characteristics and conversion efficiency of the

two-stage latched voltage doubler as a function of the output currentIO are shown in Fig.

4.23 at a supply voltage ofVDD = 1.8 V. Fig. 4.23(a) shows the output voltage as a function

of the load current. The maximum output voltage is 5.372 V, the output resistance of the

latched voltage doubler increases nonlinearly because of the increase in on resistance of

the switches whenIO is high enough to reduce the value of∆V , with the output voltage


0

1

2

3

4

5

6

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4V

O(V

)

Load current (mA)

Measured

Simulated


0

10

20

30

40

50

60

70

80

90

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Eff

icie

ncy

Load current (mA)

Simulated

Measured

(b) Efficiency.

Figure 4.21: Measured and simulated output characteristicand conversion efficiency of afully integrated two stage bootstrapped voltage doubler with charge reuse as a function ofthe output currentIO, whenVDD = 1.8 V,f = 1 MHz.

dropping to zero atIOmax = 230µA, the measured efficiency is shown in Fig. 4.23(b). The

maximum measured efficiency is 77.9% at IO = 100µA. The measured efficiency at high

load current is reduced because of the increased on resistance that influences the output

resistance.

The measured output characteristics of the one-stage bootstrapped voltage doubler at a

supply voltageVDD = 1.8 V is shown in Fig. 4.24(a). The measured output resistance is

3.67 kΩ, which is compared with a calculated value of 3.81 kΩ. The experimental results

show that the one-stage bootstrapped voltage doubler givesan output voltage 3.595 V, as

compared to an output voltage of 3.579 V provided by simulation results. The output

voltage shows a linear decay with any load current because ofthe nearly constant output

resistance. The measured efficiency as a function of the loadcurrent is shown in Fig.


0

5

10

15

20

25

30

0 0.0001 0.0002 0.0003 0.0004In

pu

tp

ow

er

imp

rov

em

en

t%

Load current (A)

Measured

Simulated

Figure 4.22: Measured and simulated improvement in input power consumption of thetwo-stages bootstrapped voltage doubler with charge reusewith respect to the two-stagesbootstrapped voltage doubler as a function of the output currentIO, whenVDD = 1.8 V,f= 1 MHz.

4.24(b). The maximum efficiency is81.76% at IO = 100µA.

Fig. 4.25 shows measured output characteristics and conversion efficiency of the one-

stage latched voltage doubler at a supply voltageVDD = 1.8 V. The measured open-circuit

output voltage is 3.584 V. The output voltage of the latched voltage doubler falls sharply

and becomes 0 V at high load currentIOmax = 240µA because∆V is reduced progressively

due to the higher output resistanceRO. The maximum measured efficiency is 81.62%, the

efficiency is reduced at high currents because of the increased switches on resistance.

As can be seen, there is a good agreement between the predicted and measured results.

However, an additional ripple component due to capacitive coupling from the clocks causes

inaccuracies in the measured output voltage. Furthermore,parasitic capacitances vary from

chip to chip and in general their value cannot be predicted toa sufficiently high accuracy

because of their nonlinear voltage dependence.

Short-circuit power consumption as a function of the outputcurrent is also examined in

the one stage voltage doublers (Fig. 4.26) and the two stage voltage doublers (Fig. 4.27).

Under no-load condition, the maximum measured improvementin the bootstrapped voltage

doubler compared to the latched voltage doubler is 6% for the one stage and 7.5% for the

two stage because short-circuit losses are prevented. The improvement in the two stage

voltage doubler is higher because short-circuit currents are prevented in four CMOS pairs


0

1

2

3

4

5

6

7

0 0.05 0.1 0.15 0.2V

O(V

)

Load current (mA)

Simulated

Measured


0

10

20

30

40

50

60

70

80

90

0 0.05 0.1 0.15 0.2 0.25

Eff

icie

ncy

Load current (mA)

Simulated

Measured

(b) Efficiency.

Figure 4.23: Measured and simulated output characteristics and conversion efficiency ofa fully integrated two stage cross-coupled (latched) voltage doubler as a function of theoutput currentIO, whenVDD = 1.8 V,f = 1 MHz.

instead of two CMOS pairs in the first stage. At higher output currents, the overdrive

voltage decreases (i.e. the voltage rise∆V is lower), and therefore the power losses due to

short-circuit currents becomes negligible.

Fig. 4.28 shows the measured load-independent power losses(PLI) as a function of the

input supply voltage for the two-stage latched voltage doubler, the two stage bootstrapped

voltage doubler, and the two stage bootstrapped voltage doubler with charge reuse. The

load-independent power losses are the total input power at no-load condition, and they

are dominated by dynamic power losses and short-circuit power losses especially at high

switching frequencies (10 MHz and higher).

As expressed in (3.10), it is obvious that short-circuit power dissipation for the latched

voltage doubler will depend on the voltage rise∆V , which, in turn, scales with the in-


0

0.5

1

1.5

2

2.5

3

3.5

4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4V

O(V

)

Load current (mA)

Simulated

Measured


0

10

20

30

40

50

60

70

80

90

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

VO

(V)

Load current (mA)

Simulated

Measured

(b) Efficiency.

Figure 4.24: Measured and simulated output characteristicand conversion efficiency of afully integrated one stage bootstrapped voltage doubler asa function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz.

put supply voltage. Due to the employment of the proposed bootstrapping technique,

load-independent losses see noticeable improvements, because short-circuit currents are

prevented. In particular, a maximum load-independent losses reduction of 11.53% is mea-

sured at 2.2 V. The bootstrapped voltage doubler with chargereuse continues to contribute

a clear reduction in load-dependent losses. In addition to the short-circuit currents block-

age, charge reuse reduces the dynamic power losses of the voltage doubler and improves

the overall power efficiency.

The measured maximum efficiencies as a function of the clock frequency of the two-

stage latched voltage doubler, the two stage bootstrapped voltage doubler, and the two-stage

bootstrapped voltage doubler with charge reuse are shown inFig. 4.29. At lower frequen-

cies (i.e. slow-switching conditions), it is obvious that the maximum power efficiency


0

0.5

1

1.5

2

2.5

3

3.5

4

0 0.05 0.1 0.15 0.2 0.25V

O(V

)

Load current (mA)

Simulated

Measured


0

10

20

30

40

50

60

70

80

90

0 0.05 0.1 0.15 0.2 0.25

Eff

icie

ncy

Load current (mA)

Simulated

Measured

(b) Efficiency.

Figure 4.25: Measured and simulated output characteristics and conversion efficiency ofa fully integrated one stage cross-coupled (latched) voltage doubler as a function of theoutput currentIO, whenVDD = 1.8 V,f = 1 MHz.

of the bootstrapped voltage doubler is higher than the latched voltage doubler because

short-circuit power losses are prevented and the parasiticcapacitances are lower. The boot-

strapped voltage with charge reuse has the best efficiency because of power saving due to

charge reuse. At faster clock frequencies, the output resistanceRO of the voltage doublers

increases when the resistances associated with switches, capacitors and interconnect dom-

inate and charges are not fully transferred due to insufficient timing while the switches are

turned on. Fig. 4.30 shows the measured output resistance ofthe two stage bootstrapped

voltage doubler as a function of the frequency. The measuredresults are in good agreement

with the model proposed recently in [7].

Overall, as can be seen, the provided experimental results successfully verify the effec-

tiveness of the proposed techniques and there is a good agreement between the predicted


Figure 4.26: Measured and simulated improvement in input power consumption of the onestage bootstrapped voltage doubler with respect to the one stage latched voltage doubler asa function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz.

Figure 4.27: Measured and simulated improvement in input power consumption of the twostages bootstrapped voltage doubler with respect to the twostages latched voltage doubleras a function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz.

simulated results and the measured results.

4.5 Discussion of the Results and Design Considerations

Switch bootstrapping improves the driving capability of voltage doublers and, at the same

time, removes short-circuit losses. Bootstrapped voltagedoublers occupy comparable sili-

con area (overhead< 2%) to that of latched voltage doublers. Each bootstrapping capacitor

is about 1 pF. This value is a compromise between a large voltage swing (≤ VDD) on the

gate of the MOS switch and silicon area. The measured output voltages of the bootstrapped


40.00

50.00

60.00

70.00

80.00

90.00

100.00

110.00

120.00

1.6 1.7 1.8 1.9 2 2.1 2.2

PLI

(mW

)

Input Voltage (V)

Charge reuse

Bootstrapped

Latched

Figure 4.28: Measured load independent power losses versusinput supply voltage of two-stage voltage doublers bootstrapped, latched, and bootstrapped with charge reuse atf = 1MHz.

voltage doublers show a linear decay for any output current indicating that the output resis-

tance is constant because each MOS switch has a given gate voltage swing, and therefore

a constant on resistance. This results in higher efficiency when the circuit needs to deliver

a higher output current, in contrast to the reduced driving capability of the latched voltage

doubler, which impacts the efficiency at high output currents, especially for low voltage ap-

plications. In addition, at low output currents unwanted short-circuit losses during switch

events reduce the efficiency and the output voltage of the latched voltage doubler, while

the efficiency of bootstrapped voltage doubler is improved because the timing of switch

events can be controlled, and therefore short-circuit currents can be prevented. The pro-

posed bootstrapping technique is suitable for building reliable voltage doublers with high

efficiency at wide range of input voltages and output currents.

The charge reuse technique effectively decreases the dynamic power losses and the

overall power consumption in the bootstrapped voltage doubler, especially for voltage dou-

blers meant to operate at higher switching frequencies. Dynamic power losses due to

charges wasted through parasitic capacitances can be reduced by means of a simple ad-

ditional circuit and control signals easily generated fromthe nonoverlapping phases with

no perceptible performance degradation for the voltage doubler operation. Since the charge


50

55

60

65

70

75

80

85

90

0 2 4 6 8 10 12 14 16 18 20

Ma

x e

ffic

ien

cy%

f (MHz)

Charge reuse

Bootstrapped

Latched

Figure 4.29: Measured maximum efficiencies versus frequency of two stage voltage dou-blers latched, bootstrapped, and bootstrapped with chargereuse at a supply voltageVDD =1.8 V.

reuse path has a finite resistance and the charge reuse circuit consumes power, the maxi-

mum power savings will be limited by the the duration of the nonoverlapping time. As an

example, atVDD = 1.8 V andf = 1 MHz, power savings are reduced to 14%. The trade-

off between charge reuse circuit complexity, and hence associated area, and the amount of

power savings should be carefully considered during the design. The charge reuse tech-

nique can be applied to voltage doublers and to any double CP with a small area overhead

added by the charge reuse circuit (overhead< 0.3%).


0

1000

2000

3000

4000

5000

6000

7000

8000

0 2 4 6 8 10 12 14 16 18 20

RO

()

f (MHz)

Calculation

Measurement

W

Figure 4.30: Measured and calculated [7] output resistanceof the two stage bootstrappedvoltage doublers at a supply voltageVDD = 1.8 V with parasitic resistance of 120Ω.

Chapter 5.Conclusion and Future Work

Chapter 5

Conclusion and Future Work

5.1 Conclusion

This dissertation presented techniques to improve performance and conversion efficiency

of integrated charge pumps. Switch bootstrapping reduces short-circuit power losses, im-

proves driving capability, and enhances the overall conversion efficiency. The proposed

technique uses conventional nonoverlapping phases and is suitable for building high-efficiency

charge pumps without high voltage stress across the MOS switches, thereby it can be scaled

to any number of stages limited only by CMOS process constrains. The application of

charge reuse is shown to be highly effective in reducing dynamic power losses and improv-

ing the overall conversion efficiency. Charge reuse can be applied to bootstrapped voltage

doublers and to any properly driven double charge pumps. A significant portion of the

charges normally wasted through parasitic capacitances can be reused by means of small

additional switches and control signals easily generated from the nonoverlapping phases

used in high-efficiency bootstrapped charge pumps. A prototype of the voltage doublers

with the proposed techniques was fabricated in a 0.18-µm CMOS process. The effective-

ness of the proposed bootstrapping and charge reusing techniques is demonstrated through

experimental results. The simulation and experimental results are in good agreement with

85

Chapter 5.Conclusion and Future Work 86

Table 5.1: Modular CP Design.

Terminal Heap Fibonacci Exponential

1 VDD Vi−1 Vi−1

2 Vi Vi Vi

3 Vi−1 Vi−2 Vi−1

the analysis.

The specific research contributions of this work include thefollowing:

1. Determination of an analysis method suitable for any integrated charge pump.

2. Modelling, optimizing, and comparing the output resistance and the conversion effi-

ciency of different charge pump circuits.

3. Development of a switch bootstrapping technique for voltage doublers. The tech-

nique improves driving capability, prevents short-circuit losses, and enables efficient

operation at low supply voltages.

4. Application of the charge reuse concept to effectively reduce the dynamic power

losses of integrated double charge pumps.

5. Prototype implementation in a 0.18-µm CMOS process and discussion of experimen-

tal results.

5.2 Future Work

An interesting development of this research will involve using ideas described in this the-

sis to design other double charge pumps. The proposed bootstrapping techniques can be


Figure 5.1: Proposed bootstrapping technique in a modular CP stage used to build genericdouble CPs (e.g. doubler-based CP, heap CP, Fibonacci CP, and exponential CP).

applied with similar considerations to the construction ofthe modular stage in Fig. 5.1. If

the terminals are connected as reported in Table 5.1 (starting values beingVi=−1 = Vi=0 =

VDD), a cascade connection of stages gives rise to a double heap charge pump [33], to a

double Fibonacci charge pump [12], or to a double exponential charge pump [15]. The

gate voltage swings and the timing of the switch transitionsare controlled as in the case

of the voltage doubler (preventing short-circuit losses and improving driving capability).

The resulting charge pumps require only the conventional nonoverlapping phases, do not

have extra parasitic capacitances affecting the efficiency, and can be scaled to any number

of stages.

The extension of the concept to a modular stage for generating any two-phase double

charge pump is shown in Fig. 5.2. As an example, the double Cockcroft-Walton con-

figuration (double ladder charge pump) is obtained with node1 connected toVi−1, node 2

connected toVi, node 3 connected toVi−1, and node 4 connected toVi−2 (the starting values

beingVi=−1 = 0, Vi=0 = VDD). This structure can operate without exceeding breakdown


Figure 5.2: Proposed bootstrapping technique in a modular CP stage used to build anytwo-phase double CP

voltages of both transfer capacitors and MOS switches [34].In general, this stage is suit-

able for building adaptive charge pumps (i.e. charge pumps that change the conversion ratio

under different input voltages and load currents to maintain high power efficiency). Future

developments of the adaptive charge pump could also includeautomatic reconfiguration of

the required voltage conversion ratio by means of adaptive control circuitry.

Appendix A.Testing

Appendix A

Testing

A.1 View of the Full Chip and the Designed Circuits

Figure A.1: Top view of the designed chip schematic.

89

Appendix A.Testing 90

Table A.1: Signal types and description.Signal Type Description

VDD1 input/output input supply voltage for circuit 1 (VDD,1V,2V)VDD2 input/output input supply voltage for circuit 2 (VDD,1V,2V)VDD3 input/output input supply voltage for circuit 3 (VDD,1V,2V)VDD4 input/output input supply voltage for circuit 4 (VDD,1V,2V)VDD5 input/output input supply voltage for circuit 5 (VDD,1V,2V)VDD6 input/output input supply voltage for circuit 6 (VDD,1V,2V)CLK1 input circuit 1 input clock (freq, 1MHz, 20MHz),

peak-to-peak = VDDCLK2 input circuit 2 input clock (freq, 1MHz, 20MHz),





peak-to-peak = VDDVO1 output circuit 1 output voltage, connected to the loadVO2 output circuit 2 output voltage, connected to the loadVO3 output circuit 3 output voltage, connected to the loadVO4 output circuit 4 output voltage, connected to the loadVO5 output circuit 5 output voltage, connected to the loadVO6 output circuit 6 output voltage, connected to the load

V ref156 input/outputclock reference (Vref, 0.8V, 2.5V); circuit 1,circuit 5, and circuit 6

V ref234 input/outputclock reference (Vref, 0.8V, 2.5V); circuit 2,circuit 3, and circuit 4

CP156 input/outputclock generation supply voltage (VDD); circuit1, circuit 5, and circuit 6

CP234 input/outputclock generation supply voltage (VDD); circuit2, circuit 3, and circuit 4


Figure A.2: Block view of the six circuits.


A.2 Circuits and Pads Arrangement for the Design

Figure A.3: Chip layout and pads arrangement.


A.3 Bonding Diagram for the Design

Figure A.4: Bonding diagram for the design.


A.4 Test Board

Figure A.5: Photograph of the fabricated test board.


A.4.1 Package Layout

Figure A.6: Technical drawing of the 24-pin CFP package (Spectrum Semiconductor, Inc).

A.4.2 Adding Off-Chip Passive Components

Through hole capacitors and resistors can be added to the board to create input and output

filters. For instance, a parallel output capacitor and resistor can be added between (vo1 and

gnd) to test for the output characteristics at certain load condition.


A.4.3 Clamping the Package to the Fixture

The clamp is fastened to the board with 4-40 machine screws. In order to ensure even

pressure on the IC package, care should be exercised when tightening the nuts on the clamp.


A.5 Schematic View of Circuits

Figure A.7: Circuit 1 schematic (2stMVD).


Figure A.8: Circuit 2 schematic (1stMVD).


Figure A.9: Circuit 3 schematic (2stMVDDBB).


Figure A.10: Circuit 4 schematic (2stCSDBB).


Figure A.11: Circuit 5 schematic (1stCCVD).


Figure A.12: Circuit 6 schematic (2stCCVD).


Figure A.13: Clock generation circuit schematic.

Appendix B.Published Papers

Appendix B

Published Papers

B.1 Refereed Publications

• Younis Allasasmehand Stefano Gregori, “Switch bootstrapping technique for volt-

age doublers and double charge pumps,” inProc. IEEE Int. Symp. Circuits Syst.

(ISCAS), 2011, pp. 494-497.

• Jingqi Liu,Younis Allasasmeh, and Stefano Gregori, “Fully-integrated charge pumps

without oxide breakdown limitation,” inProc. IEEE Canadian Conf. Electrical and

Computer Engineering (CCECE), 2011, pp. 1474-1477.

• Younis Allasasmehand Stefano Gregori, “Charge reusing in switched-capacitor

voltage multipliers with reduced dynamic losses,” inProc. IEEE Midwest Symp. Cir-

cuits Syst. (MWSCAS), 2010, pp.1169-1172.

• Younis Allasasmehand Stefano Gregori, “A performance comparison of Dickson

and Fibonacci charge pumps,” inProc. European Conf. Circuit Theory Design (EC-

CTD), 2009, pp. 89-92.

104

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ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED CHARGE PUMPS … · 2017-10-27 · ABSTRACT...

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