Analog VLSI Circuit Design Individual Assignment Page 1 of 4

KEEE 4469 University of Malaya 2015

ASSIGNMENT TOPIC:

Design and Analysis of Transimpedance Amplifier (TIA) in 0.13 µm Standard CMOS

Technology

Instructions:

This assignment is to be carried out individually.

Course Outcomes

UPON COMPLETION OF THE MODULE YOU SHOULD BE ABLE TO DEMONSTRATE

THE FOLLOWING COURSE OUTCOMES:

Analyze the theoretical concepts of analog CMOS VLSI circuits. Integrate basic analog CMOS VLSI circuits.

Evaluate the performance of integrated CMOS analog circuits adapting

standardized state of the art tools.

The objective of this assignment is being devoted to the design and analysis of low voltage

CMOS amplifier.

Theory:

Transimpedance amplifier play a critical role in optical receivers. Trade-offs between noise,

speed, gain and supply voltage present many challenges in TIA design. The TIA bandwidth is

typically chosen to be equal 0.7 times the bit rate – a reasonable compromise between total

integrated noise and the intersymbol interference (ISI) resulting from limited bandwidth. Fig. 1

shows a common gate topology is a candidate for TIAs as it provides a relatively low input

impedance, a broad band, and a well behaved time response. However, its input referred noise

current is relatively high.

A TIA configuration that achieves more relaxed noise headroom trade-offs is the shunt-shunt

feedback topology. Actual implementations of feedback TIA suffer from voltage headroom,

stability and overshoot problem. Fig. 2 suggests a modification which allow a greater drop

across RD.

Analog VLSI Circuit Design Individual Assignment Page 2 of 4

KEEE 4469 University of Malaya 2015

VDD

Iin

Vb1

M2CD

M1

Vb2

RD

Vout

Fig. 1 . Common gate TIA

Iin

M2

CD

M1

RD

Vout

VDD

VDD

RF

CL

Fig. 2. Feedback TIA

Work Programme:

Design, verify and analyze a shunt-shunt feedback CMOS Transimpedance Amplifier (TIA) as

in Fig. 2

1) Design and simulate a low voltage CMOS Transimpedance Amplifier in 0.13 µm

standard CMOS technology adapting Cadence-Spectre Platform. The amplifier is

targeted in the application 2.5Gb/s optoelectronic transceiver for optical

communication.

Analog VLSI Circuit Design Individual Assignment Page 3 of 4

KEEE 4469 University of Malaya 2015

2) A individual technical report and presentation is to be submitted adhering to the below

mentioned requirements :

a) Clear Technical Theory details related to the Assignment.

[30 % ]

b) Achievement of the correct circuit design for the TIA.

[20 % ]

c) Proper explanation for the working of individual components in the designed

circuit.

[15 % ]

d) Able to verify the full in the class simulation, also able to answer the questions

related to the designed circuit.

[15 % ]

e) Discussion and conclusion

[20 % ]

3) The grading criteria of the report are based on :

Grading Criteria:

A: 80% +

Clear and well presented theory details related to your Assignment.

Able to achieve the correct circuit design.

Able to explain the working of individual components in the designed circuit.

Able to perform the full test in the laboratory, also able to answer the questions

related to the designed circuit.

B: 70-79%

Clear and well presented theory details related to your Assignment.

Able to achieve the correct circuit design.

Able to explain the working of individual components in the designed circuit.

Not able to perform the full test in the laboratory, but able to answer the questions

related to the designed circuit.

Analog VLSI Circuit Design Individual Assignment Page 4 of 4

KEEE 4469 University of Malaya 2015

C: 60-69%

Clear and well presented theory details related to your Assignment.

Able to achieve the correct circuit design.

Able to explain the working of individual components in the designed circuit.

Not able to perform the full test in the laboratory, also not able to answer the

questions related to the designed circuit.

D: 50-59%

Clear and well presented theory details related to your Assignment.

Able to achieve the correct circuit design.

Not able to explain the working of individual components in the designed

circuit.

Not able to perform the full test in the laboratory, also not able to answer the

questions related to the designed circuit.

E: 40-49%

Clear and well presented theory details related to your Assignment.

Not able to achieve the correct circuit design.

Not able to explain the working of individual components in the designed

circuit.

Not able to perform the full test in the laboratory, also not able to answer the

questions related to the designed circuit.

F: 0-39%

Not clear and well presented theory details related to your Assignment.

Not able to achieve the correct circuit design.

Not able to explain the working of individual components in the designed

circuit.

Not able to perform the full test in the laboratory, also not able to answer the

questions related to the designed circuit.