Analogic algorithms for optical detection of breaks and short circuits on the layouts of printed...

*Correspondence to: Peter Szolgay, Analogic and Neural Computing Systems Laboratory, Computer and Automation Institute,Hungarian Academy of Sciences, P.O.B. 63, H-1502, Budapest, Hungary. Email: [email protected]

Contract grant sponsor: OTKA; contract grant number: T019063

CCC 0098—9886/99/010103—14$17.50 Received 15 May 1997Copyright ( 1999 John Wiley & Sons, Ltd. Revised 14 November 1997

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. ¹heor. Appl., 27, 103—116 (1999)

ANALOGIC ALGORITHMS FOR OPTICAL DETECTION OFBREAKS AND SHORT CIRCUITS ON THE LAYOUTS OF PRINTED

CIRCUIT BOARDS USING CNN

PETER SZOLGAY*,1 AND KATALIN TO® MO® RDI2

1Analogic and Neural Computing Systems Laboratory, Computer and Automation Institute, Hungarian Academy of Sciences,P.O.B. 63, H-1502, Budapest, Hungary

2Image Processing and Neurocomputing Department, Faculty of Engineering, University of Veszprem, Egyetem u. 10, H-8201Veszprem, Hungary

SUMMARY

Printed circuit board layout inspection methods are mostly based on local geometric information, therefore they are wellsuited to the CNN paradigm. Here the detection of two layout errors is considered namely, the breaks in the wires andsome kind of short circuits. The designed analogic algorithms to solve the problems above were tested on real-lifeexamples using an experimental system based on our CNN-HAB digital multiprocessor add-in-board with 1 million cellspace and at a speed of 2.0 ls/cell/iteration. The break detection algorithm was tested on a 20*22 CNN UniversalMachine (CNNUM) chip and the results were compared to other automatic optical inspection systems as well. Copyright( 1999 John Wiley & Sons, Ltd.

KEY WORDS: layout error detection; automatic optical inspection; analogic algorithms

1. INTRODUCTION

There is an increasing demand to reach 100% quality assurance at the PCB production. The faulty samplesshould be selected and repaired or removed before each critical technological step of production. Anautomatic optical inspection (AOI) is necessary to avoid the human faults and to meet the requirements ofhigh-production rate and of tight tolerances. In addition to these a high speed, high detection accuracy anda low false-alarm rate are required. The main types of AOI techniques are as follows:1,2

(i) reference based methods,3 where the PCB samples are compared to a stored correct one,(ii) non-referential methods,4 where the technological rules are checked on the PCB samples,(iii) hybrid methods2 are combination of the two previous methods.

To avoid the alignment and lighting problems a hybrid method was used where the technological ruleshave to be checked. The layout rule checking of a printed circuit board documentation or a manufacturedboard is time consuming. The design and manufacturing rule checking of a layout needs mostly localgeometric information, it is well suited to the CNN paradigm.5~7 The typical layout errors on a PCB artworkfilm or on a manufactured PCB are as follows: (i) the wire width is smaller than a given value, a wire may evenbe broken, (ii) the isolation on the layout is smaller than a given value, a short circuit may even be generated,(iii) the break of a pad, (iv) fleck or pinhole on a wire and (v) the misalignment of the pads to the holes.

The detection of the minimal line width violations is a key problem. It can be shown that a lot of layouterror detection rules can be transformed to this problem.8

Figure 1. Breaks of wires on a layout

In the paper two new types of layout errors are considered: breaks and short circuits. For detecting breaks,the basic idea of the algorithm is that a wire has to be terminated in a pad, in a via hole or in another wire.9The short-circuit detection in a layout is based on global properties. To solve this problem the wholeinterconnection of a circuit has to be known. CNN is especially efficient in detecting local properties. Ananalogic algorithm is given to detect some types of short circuits.9 The places of the ‘H shape-type’interconnections will be detected on the layout. Hence, the most frequently occurring short circuits can bedetected.

Our experimental system consists of our CNN-HAB10 digital multiprocessor add-in-board with its1 million cell space and at about a speed of 2)0 ls/cell/iteration, and the input images of a printed circuitboard or an artwork film are scanned in by using an HP ScanJet Plus scanner.11 The point here is to havea scanned grey-scale image where the layout figures can be easily identified on the background isolation area.

The brake detection algorithm was tested on a 20*22 CNNUM chip12 by using the CNN ChipPrototyping System (CCPS),13 the results were compared to professional AOI systems.2

In Section 2 the details of the break detection analogic algorithm, in Section 3, the details of theshort-circuit detection analogic algorithm are given. In Section 4 some experimental results are given withcomplex real life examples running on the CNN-HAB and some simple test examples running on a CNNUMchip.

2. AN ANALOGIC ALGORITHM TO DETECT BREAKS OF WIRES ON THE LAYOUT OFPRINTED CIRCUIT BOARDS

2.1. Problem formulation and pre-processing

The first question is how to define a ‘break’ on a wire. Places, where a wire is not terminated in a pad, ina via hole or in another wire segment (see Figure 1) have to be found. The flowchart of the analogic algorithmis given in Figure 2 to detect the breaks of wires.

The first step is to convert the grey-scale picture into a black and white one. To solve this problem theaverage, the threshold, or some non-linear filtering templates14 can be used. This step is common in everyCNN based layout error detection algorithm.8

104 P. SZOLGAY AND K. TO® MO® RDI

Copyright ( 1999 John Wiley & Sons, Ltd. Int. J. Circ. ¹heor. Appl., 27, 103—116 (1999)

Figure 2. The analogic algorithm of the break detection on a layout with w wire width

The next step is to skeletonize the layout image to make the detection phase wire size independent. For ourpurpose the black-and-white skeletonization [5] is not good enough, firstly because this method peels alsothe endings of the wire, and we do not find the exact positions of errors, secondly because the endings of thewires after the skeletonization have many different strange shapes.

So we tried to find similar templates which, we call ‘horizontal skeleton’ (‘horskel’) templates, which peelthe black pixels only from right or form left of a wire, and so the algorithm finds the horizontal ‘skeleton’ ofthe objects. This can be seen in Figure 3 for 3-pixel-wide vertical wires.

There are two horskel templates. They should be applied sequentially, always feeding the output back tothe input before using the next template.

ALGORITHMS FOR DETECTION OF CIRCUIT ERRORS FOR CNN 105


Figure 3(a), (b) Skeletonized elements (b) of typical wire segments (a)

The skeletonizing templates are:

A1"[3], B

1"C

0)125 0 0)5

!0)5 0)5 0)5

0)125 0 0)5 D , z1"!1

A2"[3], B

2"C

0)5 0 0)125

0)5 0)5 !0)5

0)5 0 0)125 D , z2"!1

The different enlarged wire endings of Figure 3(a) after the skeletonization can be seen in Figure 4.For horizontal wires we use the vertical skeleton, ‘‘verskel’’ templates, which are the same as the horskel

ones, rotating the templates with 90°. The possible endings are the same as in the vertical case after rotatingwith 90°.

2.2. How to find the endings on the horizontal and vertical skeletonized layout

The next template finds the wire endings on the horizontal skeletonized layout, shown in Figure 4, and thesingle black pixel objects too. These small objects are to be removed by the ‘small object removal’ template.14

A"[3], B"C!0)25 !0)25 !0)25

!0)5 0)5 !0)5

!0)25 !0)25 !0)25 D , z"!5)8

To find the endings of horizontal wires after vertical skeletonization, this template must be rotatedwith 90°.

2.3. ¹he results and the limitations of the break detection algorithm

To get the final result an OR function was used to collect the errors found on horizontal and verticalskeletonized layout. The pad size should be larger than the maximal line width (this condition is met inpractical cases), which means that the pads are larger than one pixel after the skeletonization step. In our wirebreak detection algorithm the skeletonization step is making the rest of the algorithms independent from the



Figure 4. The different wire endings Figure 5. ‘H’-type short circuits

current wire size. The actual wire width is a known value, which is used as an input data in our analogicalgorithm determining the number of skeletonizing steps.

All the A templates (the feed-back templates) used in the break detection analogic algorithm are centrallysymmetric which is a sufficient condition of the stability of the corresponding operations. The templatevalues were computed from the desired steady state of the CNN defined by local rules.

3. AN ANALOGIC ALGORITHM TO DETECT SHORT CIRCUITS OF WIRES ON THE LAYOUTOF PRINTED CIRCUIT BOARDS

The first question is how to define a ‘short circuit’ between wires. Places where two wires are connectedhave to be found (originally they must not be connected). The ‘H’-type short circuits of wires (see Figure 5)can be detected by the following analogic algorithm. The flowchart of the algorithm can be seen in Figure 6.

3.1. Pre-processing

The first step is to convert the grey-scale picture into a black and white one.14The next step is to decide whether there are holes in the picture or not. In the affirmative, first of all we have

to fill them in. We use a two-step algorithm, which is much faster than the hole filler template.14 In the firststep we fill in the local concavities with the Hollow template (see Figure 7(b)).14 (This template brings thosewhite pixels into black, which are surrounded by black pixels from at least four directions.) This is a templateof diffusion type, so the transient must be stopped after a while. The running time depends on the sizes of theholes. Downloading the original image on the input, and the processed one on the initial state, the followingtemplate erases the newly appeared black pixels, which have at least one white neighbour (namely, none ofthem is in hole) see Figure 7c.

The template is the following:

A"C1)1 1)1 1)1

1)1 1)1 1)1

1)1 1)1 1)1D , B"C0 0 0

0 8)8 0

0 0 0 D , z"0

The algorithm branches here into two parts, the part of the method for ‘standing H’ shapes betweenvertical lines is considered in details next and for ‘lying H’ shapes between horizontal lines all the templatesmust be rotated by 90°. At the end the two results must be logically OR-ed.

3.2. Peeling

When we have the hole-free (filled in) layout image, we can start a peeling algorithm. This consists of twotypes of peelings. First, we peel some pixels from the top and from the bottom. The next template peels black



Figure 6. The analogic algorithm of the short-circuit detection



Figure 8. Cutting the wires where they change direction

Figure 7. The Hole Filling’s steps: a, b, c

pixels, having black pixels below, and white pixels above them, so it peels from the top till the wire is of onepixel wide:

A"C0 0 0

0 2 0

0 0 0 D , B"C0 0)5 0

0 2)5 0

0 !0)5 0D , z"!3

Rotating it by 180°, it peels the pixels from the bottom.We need this template to cut the wires where they change direction (elbow or junction), and peel the

short-circuit connections, see Figure 8.After some cycles of peeling, we use a one-pixel connecting template, because the vertical lines of the

scanned images are not really vertical (see e.g. in Figure 9(a)), and so after these cycles the connection can becut (Figure 9(b)). The connecting template is enough here, to eliminate this fault (Figure 9(c)).

A"C0 0 0

0 2 0

0 0 0D , B"C0 0 0

1 1 1

0 0 0D , z"1



Figure 11. Wire endings with different shapes and the smoothedimage

Figure 12. Removing the two-pixel wide wire segments

Figure 9. Operation of the one-pixel connecting template Figure 10. Sometimes there are two-pixel wide wire places afterthe peeling

But if the short circuit is on a big area, then we have to peel many times, and then if the short circuit is closeto the wire endings or elbow, with this template we cut the short-circuit wires too, and so we can not find theplaces of errors. Therefore, in the second peeling phase we use a different peeling template, which does not cutthe connections anywhere, only peels the pixels from the top and from the bottom, till the horizontal lines areonly one-pixel wide (or sometimes two pixel wide if the wire is not really horizontal, see Figure 10).

The next template peels from the top, and rotating it by 180°, it peels from the bottom:

A"C0 0 0

0 2)5 0

0 0 0D , B"C0 1)5 0

0)5 2)8 0)5

!0)6 !1)5 !0)6D , z"!1)2

Using these peeling templates, the question is how many times this template has to be used. It depends onthe wire width (the first peeling cycles) and the admissible short-circuit width (the second peeling cycles). Thenumber of iterations in our examples can be seen in Figure 6.

3.3. Smoothing

After the peeling phases, we have to smooth the image, since it consists of parts due to the second peeling,which are to be removed. If the wire endings with different shapes are removed in some cycles (see Figure 11),then only the shapes to be detected remain in the picture. The next four templates do this function. They must



Figure 13. The shapes of the wires for the error detection templates

be used cyclically and the output must be fed back to the input after each iteration.

A1"C

0 0 0

0 4 0

0 0 0D , B1"C

0)5 1)1 1)1

0)5 4 1)1

0)5 1)1 1)1D , z1"!3)1

The other three templates can be generated by rotating this template by 90°, 180° and 270°.Another problem is that the horizontal lines after the peeling can have places where they are two-pixel

wide (see Figure 12) (when the wires or short-circuit lines are wide, not really horizontal, and so only thesecond peeling algorithm peels at last) and this disturbs the detection. The next templates make these linesegments thinner:

A1"[14], B

1"C

0 0 0 0 0

0 1)1 1)1 1)1 0

0 1)1 !1)1 !1)1 0

0 !1)1 !1)1 1)1 0

0 1)1 1)1 1)1 0D , z1"!1)9

A2"[14], B

2"C

0 0 0 0 0

0 1)1 1)1 1)1 0

0 !1)1 !1)1 1)1 0

0 1)1 !1)1 !1)1 0

0 1)1 1)1 1)1 0D , z2"!1)9

3.4. Detection of possible error points

The next step is to detect the possible error points. The shapes in Figure 13 can be detected with thefollowing templates:

Template 1

A1"C

0 0 0

0 2 0

0 0 0D , B1"C

1)1 !2)2 0

2)2 0)2 0

1)1 !2)2 0 D , z1"!7)7



Figure 14. The detected points

Template 2

A2"C

0 0 0

0 2 0

0 0 0 D , B2"C

0 !2)2 1)1

0 0)2 2)2

0 !2)2 1)1D , z2"!7)7

The detected points must be logically OR-ed to get all the error points. See Figures 13 and 14.These templates find junctions and sometimes the elbows of wide wires (see Figure 14).In Figure 14, it can be seen that the points signed with ‘a’, ‘b’ and ‘c’ are usually not real error points, only if

they are close enough to each other.

3.5. Selection of real error points with distance classification

The short-circuits detector algorithm may do false alarms due to the fact no node identifiers can beassigned to the different layout objects. It can be seen in Figure 14 that there are detected places which arenot short circuits. These detected places are points. We have to classify them, and choose only the pointswhich are real short circuits with high probability. For this purpose, we use distance classification, namely ifthere are two detected points within a certain distance, then they form short circuit with high probability.Otherwise, they have to be removed. The steps are as follows.

First, we increase the size of these points with the Increase template14 till the desired patches reach eachother, and then feeding the result to the input with the following diffusion-type template which peels thepatches from the left and the right.

A"C0 0 0

1)5 1 1)5

0 0 0 D , B"C0 0 0

0 2 0

0 0 0D , z"!4)5

Then, after certain number of iterations, the patches which were generated by single points (they have noneighbour points in the given distance) will disappear. So now with the Recall template14 we can ‘recall’ thereal error points’ patches, and they can be logically AND-ed with the possible error points and in this way,we get the result, the real error points on the PCB. Snapshot of this method can be seen in Figure 15.



Figure 15. Distance classification. (a) the possible error points (b) the patches generated around a point (c) the patches after peeling (d)after recalling (e) the result

3.6. ¹he results and the limitations of the short-circuit detector analogic algorithm

If we run this algorithm for the ‘lying H’-s too by using the rotated templates, and using logical ORfunction we can get all the H-type short circuits on a PCB. In our short-circuit detection algorithm thepeeling steps are making the rest of the algorithms independent from the current wire size. The actual wirewidth is a known value, which is used as an input data in our analogic algorithm determining the number ofthe peeling steps.

Using the proposed short-circuit detection algorithm, that short circuits can be detected only which aregenerated between the layout objects on the same layer. This means the following case cannot be detected byour short-circuit detector algorithm if a via hole with node A runs into a wire with a node B. Ourshort-circuits detector algorithm may do false alarms as well due to the fact that the suspicious points areselected by a distance classification.

All the templates used in short-circuit detection algorithm have centrally symmetric A templates providinga sufficient condition for the stability of the corresponding analogic operations. The template values werecomputed from the desired steady state of the CNN defined by local rules.

4. CURRENT EXPERIMENTS ON THE EXPERIMENTAL SYSTEM

4.1. Black and white image generation

After the scanning process, we get a grey-scale picture of the printed circuit board. The layout errordetection algorithms work on black and white images, so we have to generate black and white pictures wherethe interconnections are black and the isolation areas are white or opposite. We used the average andthreshold templates shown in Table I. To get the best results for different types of PCB-s we have to usedifferent templates. The threshold level of the threshold template can be set by the constant bias current z.The used time step was 1.

4.2. Current experiments with analogic layout error detection algorithms by usingthe CNN-HAB accelerator board

Having the black and white picture, we can start the error detection algorithms.The first experience was to find the breaks in the wire. (This algorithm finds the breaks in the horizontal

and vertical wires.) The algorithm worked well, only the repeat parameters of skeleton algorithm had to beset. Table II contains these settings, and the processing times on an Intel Pentium PC with 75MHz by usingthe CNN-HAB accelerator board.10

An artwork film input of F1 and the result of the error detection are in Figure 16.



Table I. Black and white image generation

PCB types The iteration numbers using the templates:code number Size in pixels Average Threshold z"... Remarks

P1 784*601 4P2 320*397 3 0)5P3 332*374 3 0)5 The scanned image was

not well processableP4 784*255 3 0)5

Table II. Current experiments with CNN-HAB

Finding breaks Finding short circuitsPCB types Skeleton repeat Processing Peeling 1 Peeling 2 Distance Processingcode number number time repeat number repeat number settings time

(min) (min)

P1 2 2)5 5 3 2*4 12P2 4 1)5 5 3 2*7 4)5P3 2 2 3 2 2*4 3P4 3 2 5 3 2*4 7)5F1 (Artwork) 2 1)5 5 3 2*4 6)5

Figure 16. Detecting breaks in the wires (F1)

The second experience was to find the ‘H’-type short circuits on a printed circuit board. Here also therepeat parameters had to be set, and in the distance classification the possible maximum distance have to bedefined between the two farthest points of the short circuit. The input of the P1 and the results of the errordetection are in Figure 17. The critical parameters and the processing times are shown in Table II for somereal-life examples. The primary aim of these experiments were to test our analogic algorithms in complexreal-life examples.



Figure 18. The input layout image and the detected wire breaks by using a 20*22 CNNUM chip

Figure 17. Detecting short circuits (P1)

4.3. Current experiments by using a 20*22 CNN universal machine (CNNºM) chip

A 20*22 CNNUM chip,12 designed 0)8 l CMOS technology with on-chip optical input, was used. Theinput and the output are binary ($1). Four binary images and eight different templates can be stored on thechip. The time constant of the chip is 250 ns. In order to achieve the available maximum speed of the chip, allthe used templates and intermediate results were stored on the chip. Due to the on-chip memory limitations,the number of the templates and internally stored images should not exceed 8 or 4, respectively. Themeasured accuracy of the chip12 was about 6—7 bits.

The CNN Chip Prototyping System (CCPS)13 provided an easy-to-use analogic algorithm developmentenvironment to the 20*22 CNNUM chip. The break detection algorithm was written in C`` using the ACLlibrary and also on analogic machine code (AMC). In our test example black and white input image was used.The algorithm was run 5000 times and the whole time was measured. The time requirement of thealgorithm—including the image and template downloading to the chip and saving the results ina file—supposing one skeletonization step, was 7)6 ms by using the AMC code. The processing speed value57,895 pixels/s on the 20*22 CNNUM chip and it is close to the best published processing speed values ofprofessional AOI systems.2



The templates of the break detection analogic algorithm were robust enough to be implemented on theCNNUM chip with six bit accuracy. The CCPS system has an automatic template conversion procedure tocompute the template values down loaded on the chip from the templates values stored in the CNN SoftwareLibrary.14

The CNNUM chip can use templates of the nearest neighbourhood. The allowed range of bias value andof other template values are $6 and $3, respectively. Due to these limitations, some templates of theshort—circuit detector algorithm have to be scaled to run it on this chip.

5. CONCLUSIONS

Analogic CNN algorithms were given to detect layout errors on printed circuit boards. The algorithmswere tested on real-life examples by using the CNN-HAB, a digitally emulated CNN and the results werepromising.

The time requirements of all the layout error detection algorithms using digital image processing methodsare proportional to the area of the layout to be tested. The time dependence of the analog VLSIimplementation of the analogic algorithms proposed here are independent of the area to be checked,providing a very high processing speed. To check this property the break detection algorithm was imple-mented on a 20*22 CNNUM chip. The processing speed value of break detection algorithm running ona relatively small CNNUM chip is close to the best published processing speed values of professional AOIsystems.2 The processing speed is increasing linearly with the number of the pixels (CNN cells) ona CNNUM chip. A CNNUM based test system using larger and more powerful chips can be a low cost partof a computer-integrated manufacturing system of PCBs.

ACKNOWLEDGEMENTS

This work has been supported by Research Grant No. T019063 National Research Fund of Hungary(OTKA)

REFERENCES

1. R. T. Chin and C. A. Harlow, Automated visual inspection: a survey’, IEEE ¹rans Pattern Anal. Mach. Intell., PAMI-4 (6),pp. 557—573 (1982).

2. M. Maganti, F. Ercal, C. H. Dagli and S. Tsunekawa, ‘Automatic PCB inspection algorithms: a survey’, Comput. »ision Imageºnderstanding, 63 (2), 287—313 (1996).

3. Y. Hara, H. Doi, K. Karasaki, T. Iida, ‘A system for PCB automated inspection using fluorescent light’, IEEE ¹rans. Pattern Anal.and Machi. Intell., PAMI-10, (1), 69—78 (1988).

4. A. M. Darwish and A. K. Jain, ‘A rule based approach for visual pattern inspection’, IEEE ¹rans. Pattern Anal. Mach. Intell.,PAMI-10, (1), 56—68 (1988).

5. L. O. Chua and L. Yang, ‘Cellular neural networks: theory’, IEEE ¹rans. on Circuits Systems, 35, 1257—1272 (1988).6. L. O. Chua and L. Yang, ‘Cellular neural networks: applications, IEEE ¹rans. Circuits Systems, 35, 1273—1290 (1988).7. T. Roska and L. O. Chua, ‘The CNN universal machine: an analogic array computer, IEEE ¹rans. Circuits Systems—II, 40,

163—173 (1993).8. P. Szolgay, I. Kispal and T. Kozek, ‘An experimental system for optical detection of layout errors of printed circuit boards using

learned CNN templates’, Proc. of CNNA’92, Munich, 1992, pp. 203—209.9. P. Szolgay and K. Tomordi, ‘Optical detection of breaks and short circuits on the layouts of printed circuit boards using CNN’ Proc.

CNNA ’96, Seville, 1996, pp. 87—91.10. T. Roska, G. Bartfai, P. Szolgay, T. Sziranyi, A. Radvanyi, T. Kozek, Zs. Ugray and A. Zarandy, ‘A digital multiprocessor hardware

accelerator board for cellular neural networks: CNN-HAC’, Int. J. Circuit ¹heory Appl., 20 (5), 589—599 (1992).11. HP ScanJet Plus User’s Manual, 1989.12. R. Dominguez-Castro, S. Espejo, A. Rodriguez Vazques, R. Carmona, P. Foldesy, A. Zarandy, P. Szolgay, T. Sziranyi and T. Roska,

‘A 0.8 lm CMOS 2-D programmable mixed-signal focal-plane array-processor with on-chip binary imaging and instructionsstorage’, »ision Chip with ¸ocal ¸ogic and Image Memory, IEEE J. Solid State Circuits, 32 (7), pp. 1013—1026 (1997).

13. T. Roska, P. Szolgay, A. Zarandy, P. Venetianer, A. Radvanyi and T. Sziranyi, ‘On a CNN chip-prototyping system’ Proc. CNNA ’94,Rome, 1994, pp. 375—380.

14. T. Roska and L. Kek (eds), ‘Analogic CNN program library,’ DNS-5-1994. MTA-SZTAKI Budapest, 1994.15. G. A. W. West, ‘A system for the automatic visual inspection of bare-printed circuit boards’, IEEE ¹rans. on Systems, Man

Cybernetics, SMC-114 (5), 1984, 767—773.



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