Analog-to-Digital Converters Lecture L10.5 Lab 11.

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Analog-to-Digital Converters Lecture L10.5 Lab 11
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Transcript of Analog-to-Digital Converters Lecture L10.5 Lab 11.

Page 1: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Analog-to-Digital Converters

Lecture L10.5

Lab 11

Page 2: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Analog-to-Digital Converters

• Converts analog signals to digital signals– 8-bit: 0 – 255– 10-bit: 0 – 1023– 12-bit: 0 – 4095

• Successive Approximation

• Flash

Page 3: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Method of Successive Approximation

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V

5V

2.5V

3.75V

3.125V3.4375V Vin = 3.5V

step 1 step 2 step 3 step 4

voltage

Page 4: Analog-to-Digital Converters Lecture L10.5 Lab 11.

1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 00000V

5V

2.5V

3.75V

3.125V3.4375V Vin = 3.5V

step 1 step 2 step 3 step 4

voltage

Control

D/A Converter

V

V

in

DA

Binary OutputC+

-

Implementing Successive Approximation

Page 5: Analog-to-Digital Converters Lecture L10.5 Lab 11.

ADC08318-Bit Serial I/O A/D

Converter

Page 6: Analog-to-Digital Converters Lecture L10.5 Lab 11.
Page 7: Analog-to-Digital Converters Lecture L10.5 Lab 11.
Page 8: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Analog-to-Digital

Converter ADC0831

VCC CLK DO VREF

VIN (+) VIN (-)

GND

CS

Voltage Input +5 VDC

Xilinx XC95108 Interface

4.7 K

220 K

Figure 1. Analog-to-Digital Converter Circuit

1

2

4

3

8

7

5

6

Page 9: Analog-to-Digital Converters Lecture L10.5 Lab 11.

      

  CLK

CS

DOTRI-

STATE 7 6 5 4 3 2 1 0TRI-

STATE(MSB) (LSB)

ADC0831 Timing

Page 10: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Xilinx XC95108 PC84 CPLD Clock Divider

Counter Q7..Q0

Shift RegisterS7..S0

Display RegisterD7..D0

Binary-to-BCDConverter

Hundreds Tens Units

0

Clock

Clock

Data

Load

Count Detect Logic

(Q7..Q4 = 10102)

7-SegmentDecoder

7-SegmentDecoder

0

4 MHz Clock

Q3

Q7Q6

Q3

Capture

7 7

VoltageDisplay

a..g a..g

dpt

1

CLK

CS

DO

ADC0831Interface

!Q3

Voltmeter Logic Block Diagram

Page 11: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Binary input: 101100101 shift left 1 01100101 shift left 10 1100101 shift left 101 100101 add 3 +11 : 1000 100101 shift left 1 0001 00101 shift left 10 0010 0101 shift left 100 0100 101 shift left 1000 1001 01 add 3 +11 : : 1011 1100 01 shift left 1 0111 1000 1 add 3 : +11 +11 : 1 1010 1011 1 shift left 011 0101 0111

hundreds tens units BCD: 3 5 7 Figure 4. Binary-to-BCD Conversion

C1

C2

C3

C7 C4

C8 C5

C9 C6

0 B8 B7 B6 B5 B4 B3 B2 B1 B0

P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

0

P10

9-bit Binary Input

Hundreds Tens Units

BCD Output

Figure 5. 9-bit Binary-to-BCD Converter

Page 12: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Flash A/D Converter

• Uses analog comparators to convert an analog signal to a digital signal in a single clock cycle

• n-bit converter requires 2n – 1 comparators– 4-bit converter requires 15 comparators– 8-bit converter requires 255 comparators

• Or two 4-bit converters plus a D/A converter

Page 13: Analog-to-Digital Converters Lecture L10.5 Lab 11.

MAX118

Page 14: Analog-to-Digital Converters Lecture L10.5 Lab 11.

Flash A/D Converter

Page 15: Analog-to-Digital Converters Lecture L10.5 Lab 11.

MAX118